hw/ppce500_mpc8544ds.c

   1 /*
   2  * QEMU PowerPC MPC8544DS board emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "net.h"
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "pci.h"
  23 #include "boards.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_ppc.h"
  27 #include "device_tree.h"
  28 #include "openpic.h"
  29 #include "ppc.h"
  30 #include "loader.h"
  31 #include "elf.h"
  32 #include "sysbus.h"
  33 #include "exec-memory.h"
  34
  35 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  36 #define UIMAGE_LOAD_BASE           0
  37 #define DTC_LOAD_PAD               0x500000
  38 #define DTC_PAD_MASK               0xFFFFF
  39 #define INITRD_LOAD_PAD            0x2000000
  40 #define INITRD_PAD_MASK            0xFFFFFF
  41
  42 #define RAM_SIZES_ALIGN            (64UL << 20)
  43
  44 #define MPC8544_CCSRBAR_BASE       0xE0000000
  45 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000)
  46 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500)
  47 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600)
  48 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000)
  49 #define MPC8544_PCI_REGS_SIZE      0x1000
  50 #define MPC8544_PCI_IO             0xE1000000
  51 #define MPC8544_PCI_IOLEN          0x10000
  52 #define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000)
  53 #define MPC8544_SPIN_BASE          0xEF000000
  54
  55 struct boot_info
  56 {
  57     uint32_t dt_base;
  58     uint32_t entry;
  59 };
  60
  61 static int mpc8544_load_device_tree(CPUPPCState *env,
  62                                     target_phys_addr_t addr,
  63                                     uint32_t ramsize,
  64                                     target_phys_addr_t initrd_base,
  65                                     target_phys_addr_t initrd_size,
  66                                     const char *kernel_cmdline)
  67 {
  68     int ret = -1;
  69 #ifdef CONFIG_FDT
  70     uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
  71     char *filename;
  72     int fdt_size;
  73     void *fdt;
  74     uint8_t hypercall[16];
  75     uint32_t clock_freq = 400000000;
  76     uint32_t tb_freq = 400000000;
  77     int i;
  78
  79     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  80     if (!filename) {
  81         goto out;
  82     }
  83     fdt = load_device_tree(filename, &fdt_size);
  84     g_free(filename);
  85     if (fdt == NULL) {
  86         goto out;
  87     }
  88
  89     /* Manipulate device tree in memory. */
  90     ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
  91                                sizeof(mem_reg_property));
  92     if (ret < 0)
  93         fprintf(stderr, "couldn't set /memory/reg\n");
  94
  95     if (initrd_size) {
  96         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  97                                         initrd_base);
  98         if (ret < 0) {
  99             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 100         }
 101
 102         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 103                                         (initrd_base + initrd_size));
 104         if (ret < 0) {
 105             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 106         }
 107     }
 108
 109     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 110                                       kernel_cmdline);
 111     if (ret < 0)
 112         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 113
 114     if (kvm_enabled()) {
 115         /* Read out host's frequencies */
 116         clock_freq = kvmppc_get_clockfreq();
 117         tb_freq = kvmppc_get_tbfreq();
 118
 119         /* indicate KVM hypercall interface */
 120         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 121                                     "linux,kvm");
 122         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 123         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 124                              hypercall, sizeof(hypercall));
 125     }
 126
 127     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 128        the first node as boot node and be happy */
 129     for (i = smp_cpus - 1; i >= 0; i--) {
 130         char cpu_name[128];
 131         uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
 132
 133         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 134             if (env->cpu_index == i) {
 135                 break;
 136             }
 137         }
 138
 139         if (!env) {
 140             continue;
 141         }
 142
 143         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 144         qemu_devtree_add_subnode(fdt, cpu_name);
 145         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 146         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 147         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 148         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 149         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 150                                   env->dcache_line_size);
 151         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 152                                   env->icache_line_size);
 153         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 154         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 155         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 156         if (env->cpu_index) {
 157             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 158             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 159             qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
 160                                  &cpu_release_addr, sizeof(cpu_release_addr));
 161         } else {
 162             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 163         }
 164     }
 165
 166     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 167     g_free(fdt);
 168
 169 out:
 170 #endif
 171
 172     return ret;
 173 }
 174
 175 /* Create -kernel TLB entries for BookE, linearly spanning 256MB.  */
 176 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 177 {
 178     return ffs(size >> 10) - 1;
 179 }
 180
 181 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 182                                      target_ulong va,
 183                                      target_phys_addr_t pa)
 184 {
 185     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 186     target_phys_addr_t size;
 187
 188     size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT);
 189     tlb->mas1 = MAS1_VALID | size;
 190     tlb->mas2 = va & TARGET_PAGE_MASK;
 191     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
 192     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 193
 194     env->tlb_dirty = true;
 195 }
 196
 197 static void mpc8544ds_cpu_reset_sec(void *opaque)
 198 {
 199     PowerPCCPU *cpu = opaque;
 200     CPUPPCState *env = &cpu->env;
 201
 202     cpu_reset(CPU(cpu));
 203
 204     /* Secondary CPU starts in halted state for now. Needs to change when
 205        implementing non-kernel boot. */
 206     env->halted = 1;
 207     env->exception_index = EXCP_HLT;
 208 }
 209
 210 static void mpc8544ds_cpu_reset(void *opaque)
 211 {
 212     PowerPCCPU *cpu = opaque;
 213     CPUPPCState *env = &cpu->env;
 214     struct boot_info *bi = env->load_info;
 215
 216     cpu_reset(CPU(cpu));
 217
 218     /* Set initial guest state. */
 219     env->halted = 0;
 220     env->gpr[1] = (16<<20) - 8;
 221     env->gpr[3] = bi->dt_base;
 222     env->nip = bi->entry;
 223     mmubooke_create_initial_mapping(env, 0, 0);
 224 }
 225
 226 static void mpc8544ds_init(ram_addr_t ram_size,
 227                          const char *boot_device,
 228                          const char *kernel_filename,
 229                          const char *kernel_cmdline,
 230                          const char *initrd_filename,
 231                          const char *cpu_model)
 232 {
 233     MemoryRegion *address_space_mem = get_system_memory();
 234     MemoryRegion *ram = g_new(MemoryRegion, 1);
 235     PCIBus *pci_bus;
 236     CPUPPCState *env = NULL;
 237     uint64_t elf_entry;
 238     uint64_t elf_lowaddr;
 239     target_phys_addr_t entry=0;
 240     target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
 241     target_long kernel_size=0;
 242     target_ulong dt_base = 0;
 243     target_ulong initrd_base = 0;
 244     target_long initrd_size=0;
 245     int i=0;
 246     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 247     qemu_irq **irqs, *mpic;
 248     DeviceState *dev;
 249     CPUPPCState *firstenv = NULL;
 250
 251     /* Setup CPUs */
 252     if (cpu_model == NULL) {
 253         cpu_model = "e500v2_v30";
 254     }
 255
 256     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 257     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 258     for (i = 0; i < smp_cpus; i++) {
 259         PowerPCCPU *cpu;
 260         qemu_irq *input;
 261
 262         cpu = cpu_ppc_init(cpu_model);
 263         if (cpu == NULL) {
 264             fprintf(stderr, "Unable to initialize CPU!\n");
 265             exit(1);
 266         }
 267         env = &cpu->env;
 268
 269         if (!firstenv) {
 270             firstenv = env;
 271         }
 272
 273         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 274         input = (qemu_irq *)env->irq_inputs;
 275         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 276         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 277         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 278
 279         ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
 280
 281         /* Register reset handler */
 282         if (!i) {
 283             /* Primary CPU */
 284             struct boot_info *boot_info;
 285             boot_info = g_malloc0(sizeof(struct boot_info));
 286             qemu_register_reset(mpc8544ds_cpu_reset, cpu);
 287             env->load_info = boot_info;
 288         } else {
 289             /* Secondary CPUs */
 290             qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
 291         }
 292     }
 293
 294     env = firstenv;
 295
 296     /* Fixup Memory size on a alignment boundary */
 297     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 298
 299     /* Register Memory */
 300     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 301     vmstate_register_ram_global(ram);
 302     memory_region_add_subregion(address_space_mem, 0, ram);
 303
 304     /* MPIC */
 305     mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
 306                      smp_cpus, irqs, NULL);
 307
 308     if (!mpic) {
 309         cpu_abort(env, "MPIC failed to initialize\n");
 310     }
 311
 312     /* Serial */
 313     if (serial_hds[0]) {
 314         serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
 315                        0, mpic[12+26], 399193,
 316                        serial_hds[0], DEVICE_BIG_ENDIAN);
 317     }
 318
 319     if (serial_hds[1]) {
 320         serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
 321                        0, mpic[12+26], 399193,
 322                        serial_hds[0], DEVICE_BIG_ENDIAN);
 323     }
 324
 325     /* General Utility device */
 326     sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
 327
 328     /* PCI */
 329     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
 330                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
 331                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
 332                                 NULL);
 333     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 334     if (!pci_bus)
 335         printf("couldn't create PCI controller!\n");
 336
 337     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
 338
 339     if (pci_bus) {
 340         /* Register network interfaces. */
 341         for (i = 0; i < nb_nics; i++) {
 342             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 343         }
 344     }
 345
 346     /* Register spinning region */
 347     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 348
 349     /* Load kernel. */
 350     if (kernel_filename) {
 351         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
 352         if (kernel_size < 0) {
 353             kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 354                                    &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
 355             entry = elf_entry;
 356             loadaddr = elf_lowaddr;
 357         }
 358         /* XXX try again as binary */
 359         if (kernel_size < 0) {
 360             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 361                     kernel_filename);
 362             exit(1);
 363         }
 364     }
 365
 366     /* Load initrd. */
 367     if (initrd_filename) {
 368         initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 369         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 370                                           ram_size - initrd_base);
 371
 372         if (initrd_size < 0) {
 373             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 374                     initrd_filename);
 375             exit(1);
 376         }
 377     }
 378
 379     /* If we're loading a kernel directly, we must load the device tree too. */
 380     if (kernel_filename) {
 381         struct boot_info *boot_info;
 382
 383 #ifndef CONFIG_FDT
 384         cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
 385 #endif
 386         dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 387         if (mpc8544_load_device_tree(env, dt_base, ram_size,
 388                     initrd_base, initrd_size, kernel_cmdline) < 0) {
 389             fprintf(stderr, "couldn't load device tree\n");
 390             exit(1);
 391         }
 392
 393         boot_info = env->load_info;
 394         boot_info->entry = entry;
 395         boot_info->dt_base = dt_base;
 396     }
 397
 398     if (kvm_enabled()) {
 399         kvmppc_init();
 400     }
 401 }
 402
 403 static QEMUMachine mpc8544ds_machine = {
 404     .name = "mpc8544ds",
 405     .desc = "mpc8544ds",
 406     .init = mpc8544ds_init,
 407     .max_cpus = 15,
 408 };
 409
 410 static void mpc8544ds_machine_init(void)
 411 {
 412     qemu_register_machine(&mpc8544ds_machine);
 413 }
 414
 415 machine_init(mpc8544ds_machine_init);