2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "sysemu/kvm.h"
24 #include "mmu-hash64.h"
30 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
31 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
33 # define LOG_MMU(...) do { } while (0)
34 # define LOG_MMU_STATE(...) do { } while (0)
38 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
40 # define LOG_SLB(...) do { } while (0)
43 struct mmu_ctx_hash64
{
44 hwaddr raddr
; /* Real address */
45 int prot
; /* Protection bits */
46 int key
; /* Access key */
53 static ppc_slb_t
*slb_lookup(CPUPPCState
*env
, target_ulong eaddr
)
55 uint64_t esid_256M
, esid_1T
;
58 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
60 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
61 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
63 for (n
= 0; n
< env
->slb_nr
; n
++) {
64 ppc_slb_t
*slb
= &env
->slb
[n
];
66 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
67 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
68 /* We check for 1T matches on all MMUs here - if the MMU
69 * doesn't have 1T segment support, we will have prevented 1T
70 * entries from being inserted in the slbmte code. */
71 if (((slb
->esid
== esid_256M
) &&
72 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
73 || ((slb
->esid
== esid_1T
) &&
74 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
82 void dump_slb(FILE *f
, fprintf_function cpu_fprintf
, CPUPPCState
*env
)
87 cpu_synchronize_state(env
);
89 cpu_fprintf(f
, "SLB\tESID\t\t\tVSID\n");
90 for (i
= 0; i
< env
->slb_nr
; i
++) {
91 slbe
= env
->slb
[i
].esid
;
92 slbv
= env
->slb
[i
].vsid
;
93 if (slbe
== 0 && slbv
== 0) {
96 cpu_fprintf(f
, "%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
101 void helper_slbia(CPUPPCState
*env
)
103 int n
, do_invalidate
;
106 /* XXX: Warning: slbia never invalidates the first segment */
107 for (n
= 1; n
< env
->slb_nr
; n
++) {
108 ppc_slb_t
*slb
= &env
->slb
[n
];
110 if (slb
->esid
& SLB_ESID_V
) {
111 slb
->esid
&= ~SLB_ESID_V
;
112 /* XXX: given the fact that segment size is 256 MB or 1TB,
113 * and we still don't have a tlb_flush_mask(env, n, mask)
114 * in QEMU, we just invalidate all TLBs
124 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
128 slb
= slb_lookup(env
, addr
);
133 if (slb
->esid
& SLB_ESID_V
) {
134 slb
->esid
&= ~SLB_ESID_V
;
136 /* XXX: given the fact that segment size is 256 MB or 1TB,
137 * and we still don't have a tlb_flush_mask(env, n, mask)
138 * in QEMU, we just invalidate all TLBs
144 int ppc_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
146 int slot
= rb
& 0xfff;
147 ppc_slb_t
*slb
= &env
->slb
[slot
];
149 if (rb
& (0x1000 - env
->slb_nr
)) {
150 return -1; /* Reserved bits set or slot too high */
152 if (rs
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
153 return -1; /* Bad segment size */
155 if ((rs
& SLB_VSID_B
) && !(env
->mmu_model
& POWERPC_MMU_1TSEG
)) {
156 return -1; /* 1T segment on MMU that doesn't support it */
159 /* Mask out the slot number as we store the entry */
160 slb
->esid
= rb
& (SLB_ESID_ESID
| SLB_ESID_V
);
163 LOG_SLB("%s: %d " TARGET_FMT_lx
" - " TARGET_FMT_lx
" => %016" PRIx64
164 " %016" PRIx64
"\n", __func__
, slot
, rb
, rs
,
165 slb
->esid
, slb
->vsid
);
170 static int ppc_load_slb_esid(CPUPPCState
*env
, target_ulong rb
,
173 int slot
= rb
& 0xfff;
174 ppc_slb_t
*slb
= &env
->slb
[slot
];
176 if (slot
>= env
->slb_nr
) {
184 static int ppc_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
,
187 int slot
= rb
& 0xfff;
188 ppc_slb_t
*slb
= &env
->slb
[slot
];
190 if (slot
>= env
->slb_nr
) {
198 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
200 if (ppc_store_slb(env
, rb
, rs
) < 0) {
201 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
206 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
210 if (ppc_load_slb_esid(env
, rb
, &rt
) < 0) {
211 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
217 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
221 if (ppc_load_slb_vsid(env
, rb
, &rt
) < 0) {
222 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
229 * 64-bit hash table MMU handling
232 static int ppc_hash64_pp_check(int key
, int pp
, bool nx
)
236 /* Compute access rights */
237 /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
244 access
|= PAGE_WRITE
;
262 access
= PAGE_READ
| PAGE_WRITE
;
273 static int ppc_hash64_check_prot(int prot
, int rwx
)
278 if (prot
& PAGE_EXEC
) {
283 } else if (rwx
== 1) {
284 if (prot
& PAGE_WRITE
) {
290 if (prot
& PAGE_READ
) {
300 static int pte64_check(struct mmu_ctx_hash64
*ctx
, target_ulong pte0
,
301 target_ulong pte1
, int rwx
)
306 pp
= (pte1
& HPTE64_R_PP
) | ((pte1
& HPTE64_R_PP0
) >> 61);
307 /* No execute if either noexec or guarded bits set */
308 nx
= (pte1
& HPTE64_R_N
) || (pte1
& HPTE64_R_G
);
309 /* Compute access rights */
310 access
= ppc_hash64_pp_check(ctx
->key
, pp
, nx
);
311 /* Keep the matching PTE informations */
314 ret
= ppc_hash64_check_prot(ctx
->prot
, rwx
);
317 LOG_MMU("PTE access granted !\n");
319 /* Access right violation */
320 LOG_MMU("PTE access rejected\n");
326 static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64
*ctx
,
327 uint64_t *pte1p
, int ret
, int rw
)
331 /* Update page flags */
332 if (!(*pte1p
& HPTE64_R_R
)) {
333 /* Update accessed flag */
334 *pte1p
|= HPTE64_R_R
;
337 if (!(*pte1p
& HPTE64_R_C
)) {
338 if (rw
== 1 && ret
== 0) {
339 /* Update changed flag */
340 *pte1p
|= HPTE64_R_C
;
343 /* Force page fault for first write access */
344 ctx
->prot
&= ~PAGE_WRITE
;
351 static hwaddr
ppc_hash64_pteg_search(CPUPPCState
*env
, hwaddr pteg_off
,
352 bool secondary
, target_ulong ptem
,
353 ppc_hash_pte64_t
*pte
)
355 hwaddr pte_offset
= pteg_off
;
356 target_ulong pte0
, pte1
;
359 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
360 pte0
= ppc_hash64_load_hpte0(env
, pte_offset
);
361 pte1
= ppc_hash64_load_hpte1(env
, pte_offset
);
363 if ((pte0
& HPTE64_V_VALID
)
364 && (secondary
== !!(pte0
& HPTE64_V_SECONDARY
))
365 && HPTE64_V_COMPARE(pte0
, ptem
)) {
371 pte_offset
+= HASH_PTE_SIZE_64
;
377 static hwaddr
ppc_hash64_htab_lookup(CPUPPCState
*env
,
378 ppc_slb_t
*slb
, target_ulong eaddr
,
379 ppc_hash_pte64_t
*pte
)
381 hwaddr pteg_off
, pte_offset
;
382 uint64_t vsid
, pageaddr
, ptem
;
384 int segment_bits
, target_page_bits
;
386 if (slb
->vsid
& SLB_VSID_B
) {
387 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
390 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
394 target_page_bits
= (slb
->vsid
& SLB_VSID_L
)
395 ? TARGET_PAGE_BITS_16M
: TARGET_PAGE_BITS
;
397 pageaddr
= eaddr
& ((1ULL << segment_bits
)
398 - (1ULL << target_page_bits
));
399 if (slb
->vsid
& SLB_VSID_B
) {
400 hash
= vsid
^ (vsid
<< 25) ^ (pageaddr
>> target_page_bits
);
402 hash
= vsid
^ (pageaddr
>> target_page_bits
);
404 /* Only 5 bits of the page index are used in the AVPN */
405 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) |
406 ((pageaddr
>> 16) & ((1ULL << segment_bits
) - 0x80));
408 /* Page address translation */
409 LOG_MMU("htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
410 " hash " TARGET_FMT_plx
"\n",
411 env
->htab_base
, env
->htab_mask
, hash
);
413 /* Primary PTEG lookup */
414 LOG_MMU("0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
415 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
416 " hash=" TARGET_FMT_plx
"\n",
417 env
->htab_base
, env
->htab_mask
, vsid
, ptem
, hash
);
418 pteg_off
= (hash
* HASH_PTEG_SIZE_64
) & env
->htab_mask
;
419 pte_offset
= ppc_hash64_pteg_search(env
, pteg_off
, 0, ptem
, pte
);
421 if (pte_offset
== -1) {
422 /* Secondary PTEG lookup */
423 LOG_MMU("1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
424 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
425 " hash=" TARGET_FMT_plx
"\n", env
->htab_base
,
426 env
->htab_mask
, vsid
, ptem
, ~hash
);
428 pteg_off
= (~hash
* HASH_PTEG_SIZE_64
) & env
->htab_mask
;
429 pte_offset
= ppc_hash64_pteg_search(env
, pteg_off
, 1, ptem
, pte
);
435 static int ppc_hash64_translate(CPUPPCState
*env
, struct mmu_ctx_hash64
*ctx
,
436 target_ulong eaddr
, int rwx
)
441 ppc_hash_pte64_t pte
;
442 int target_page_bits
;
444 /* 1. Handle real mode accesses */
445 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
446 /* Translation is off */
447 /* In real mode the top 4 effective address bits are ignored */
448 ctx
->raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
449 ctx
->prot
= PAGE_READ
| PAGE_EXEC
| PAGE_WRITE
;
453 /* 2. Translation is on, so look up the SLB */
454 slb
= slb_lookup(env
, eaddr
);
460 /* 3. Check for segment level no-execute violation */
461 if ((rwx
== 2) && (slb
->vsid
& SLB_VSID_N
)) {
465 /* 4. Locate the PTE in the hash table */
466 pte_offset
= ppc_hash64_htab_lookup(env
, slb
, eaddr
, &pte
);
467 if (pte_offset
== -1) {
470 LOG_MMU("found PTE at offset %08" HWADDR_PRIx
"\n", pte_offset
);
472 /* 5. Check access permissions */
473 ctx
->key
= !!(msr_pr
? (slb
->vsid
& SLB_VSID_KP
)
474 : (slb
->vsid
& SLB_VSID_KS
));
476 ret
= pte64_check(ctx
, pte
.pte0
, pte
.pte1
, rwx
);
477 /* Update page flags */
478 if (ppc_hash64_pte_update_flags(ctx
, &pte
.pte1
, ret
, rwx
) == 1) {
479 ppc_hash64_store_hpte1(env
, pte_offset
, pte
.pte1
);
482 /* We have a TLB that saves 4K pages, so let's
483 * split a huge page to 4k chunks */
484 target_page_bits
= (slb
->vsid
& SLB_VSID_L
)
485 ? TARGET_PAGE_BITS_16M
: TARGET_PAGE_BITS
;
486 if (target_page_bits
!= TARGET_PAGE_BITS
) {
487 ctx
->raddr
|= (eaddr
& ((1 << target_page_bits
) - 1))
493 hwaddr
ppc_hash64_get_phys_page_debug(CPUPPCState
*env
, target_ulong addr
)
495 struct mmu_ctx_hash64 ctx
;
497 if (unlikely(ppc_hash64_translate(env
, &ctx
, addr
, 0) != 0)) {
501 return ctx
.raddr
& TARGET_PAGE_MASK
;
504 int ppc_hash64_handle_mmu_fault(CPUPPCState
*env
, target_ulong address
, int rwx
,
507 struct mmu_ctx_hash64 ctx
;
510 ret
= ppc_hash64_translate(env
, &ctx
, address
, rwx
);
512 tlb_set_page(env
, address
& TARGET_PAGE_MASK
,
513 ctx
.raddr
& TARGET_PAGE_MASK
, ctx
.prot
,
514 mmu_idx
, TARGET_PAGE_SIZE
);
516 } else if (ret
< 0) {
521 env
->exception_index
= POWERPC_EXCP_ISI
;
522 env
->error_code
= 0x40000000;
525 /* Access rights violation */
526 env
->exception_index
= POWERPC_EXCP_ISI
;
527 env
->error_code
= 0x08000000;
530 /* No execute protection violation */
531 env
->exception_index
= POWERPC_EXCP_ISI
;
532 env
->error_code
= 0x10000000;
535 /* No match in segment table */
536 env
->exception_index
= POWERPC_EXCP_ISEG
;
543 /* No matches in page tables or TLB */
544 env
->exception_index
= POWERPC_EXCP_DSI
;
546 env
->spr
[SPR_DAR
] = address
;
548 env
->spr
[SPR_DSISR
] = 0x42000000;
550 env
->spr
[SPR_DSISR
] = 0x40000000;
554 /* Access rights violation */
555 env
->exception_index
= POWERPC_EXCP_DSI
;
557 env
->spr
[SPR_DAR
] = address
;
559 env
->spr
[SPR_DSISR
] = 0x0A000000;
561 env
->spr
[SPR_DSISR
] = 0x08000000;
565 /* No match in segment table */
566 env
->exception_index
= POWERPC_EXCP_DSEG
;
568 env
->spr
[SPR_DAR
] = address
;
573 printf("%s: set exception to %d %02x\n", __func__
,
574 env
->exception
, env
->error_code
);