4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "qemu-common.h"
31 //#define DEBUG_FEATURES
33 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
);
35 /* Sparc MMU emulation */
39 static spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
43 spin_lock(&global_cpu_lock
);
48 spin_unlock(&global_cpu_lock
);
51 #if defined(CONFIG_USER_ONLY)
53 int cpu_sparc_handle_mmu_fault(CPUState
*env1
, target_ulong address
, int rw
,
54 int mmu_idx
, int is_softmmu
)
57 env1
->exception_index
= TT_TFAULT
;
59 env1
->exception_index
= TT_DFAULT
;
65 #ifndef TARGET_SPARC64
67 * Sparc V8 Reference MMU (SRMMU)
69 static const int access_table
[8][8] = {
70 { 0, 0, 0, 0, 8, 0, 12, 12 },
71 { 0, 0, 0, 0, 8, 0, 0, 0 },
72 { 8, 8, 0, 0, 0, 8, 12, 12 },
73 { 8, 8, 0, 0, 0, 8, 0, 0 },
74 { 8, 0, 8, 0, 8, 8, 12, 12 },
75 { 8, 0, 8, 0, 8, 0, 8, 0 },
76 { 8, 8, 8, 0, 8, 8, 12, 12 },
77 { 8, 8, 8, 0, 8, 8, 8, 0 }
80 static const int perm_table
[2][8] = {
83 PAGE_READ
| PAGE_WRITE
,
84 PAGE_READ
| PAGE_EXEC
,
85 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
87 PAGE_READ
| PAGE_WRITE
,
88 PAGE_READ
| PAGE_EXEC
,
89 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
93 PAGE_READ
| PAGE_WRITE
,
94 PAGE_READ
| PAGE_EXEC
,
95 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
103 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
104 int *prot
, int *access_index
,
105 target_ulong address
, int rw
, int mmu_idx
,
106 target_ulong
*page_size
)
108 int access_perms
= 0;
109 target_phys_addr_t pde_ptr
;
111 int error_code
= 0, is_dirty
, is_user
;
112 unsigned long page_offset
;
114 is_user
= mmu_idx
== MMU_USER_IDX
;
116 if ((env
->mmuregs
[0] & MMU_E
) == 0) { /* MMU disabled */
117 *page_size
= TARGET_PAGE_SIZE
;
118 // Boot mode: instruction fetches are taken from PROM
119 if (rw
== 2 && (env
->mmuregs
[0] & env
->def
->mmu_bm
)) {
120 *physical
= env
->prom_addr
| (address
& 0x7ffffULL
);
121 *prot
= PAGE_READ
| PAGE_EXEC
;
125 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
129 *access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
130 *physical
= 0xffffffffffff0000ULL
;
132 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
133 /* Context base + context number */
134 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
135 pde
= ldl_phys(pde_ptr
);
138 switch (pde
& PTE_ENTRYTYPE_MASK
) {
140 case 0: /* Invalid */
142 case 2: /* L0 PTE, maybe should not happen? */
143 case 3: /* Reserved */
146 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
147 pde
= ldl_phys(pde_ptr
);
149 switch (pde
& PTE_ENTRYTYPE_MASK
) {
151 case 0: /* Invalid */
152 return (1 << 8) | (1 << 2);
153 case 3: /* Reserved */
154 return (1 << 8) | (4 << 2);
156 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
157 pde
= ldl_phys(pde_ptr
);
159 switch (pde
& PTE_ENTRYTYPE_MASK
) {
161 case 0: /* Invalid */
162 return (2 << 8) | (1 << 2);
163 case 3: /* Reserved */
164 return (2 << 8) | (4 << 2);
166 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
167 pde
= ldl_phys(pde_ptr
);
169 switch (pde
& PTE_ENTRYTYPE_MASK
) {
171 case 0: /* Invalid */
172 return (3 << 8) | (1 << 2);
173 case 1: /* PDE, should not happen */
174 case 3: /* Reserved */
175 return (3 << 8) | (4 << 2);
177 page_offset
= (address
& TARGET_PAGE_MASK
) &
178 (TARGET_PAGE_SIZE
- 1);
180 *page_size
= TARGET_PAGE_SIZE
;
183 page_offset
= address
& 0x3ffff;
184 *page_size
= 0x40000;
188 page_offset
= address
& 0xffffff;
189 *page_size
= 0x1000000;
194 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
195 error_code
= access_table
[*access_index
][access_perms
];
196 if (error_code
&& !((env
->mmuregs
[0] & MMU_NF
) && is_user
))
199 /* update page modified and dirty bits */
200 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
201 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
202 pde
|= PG_ACCESSED_MASK
;
204 pde
|= PG_MODIFIED_MASK
;
205 stl_phys_notdirty(pde_ptr
, pde
);
208 /* the page can be put in the TLB */
209 *prot
= perm_table
[is_user
][access_perms
];
210 if (!(pde
& PG_MODIFIED_MASK
)) {
211 /* only set write access if already dirty... otherwise wait
213 *prot
&= ~PAGE_WRITE
;
216 /* Even if large ptes, we map only one 4KB page in the cache to
217 avoid filling it too fast */
218 *physical
= ((target_phys_addr_t
)(pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
222 /* Perform address translation */
223 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
224 int mmu_idx
, int is_softmmu
)
226 target_phys_addr_t paddr
;
228 target_ulong page_size
;
229 int error_code
= 0, prot
, access_index
;
231 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
232 address
, rw
, mmu_idx
, &page_size
);
233 if (error_code
== 0) {
234 vaddr
= address
& TARGET_PAGE_MASK
;
235 paddr
&= TARGET_PAGE_MASK
;
237 printf("Translate at " TARGET_FMT_lx
" -> " TARGET_FMT_plx
", vaddr "
238 TARGET_FMT_lx
"\n", address
, paddr
, vaddr
);
240 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
244 if (env
->mmuregs
[3]) /* Fault status register */
245 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
246 env
->mmuregs
[3] |= (access_index
<< 5) | error_code
| 2;
247 env
->mmuregs
[4] = address
; /* Fault address register */
249 if ((env
->mmuregs
[0] & MMU_NF
) || env
->psret
== 0) {
250 // No fault mode: if a mapping is available, just override
251 // permissions. If no mapping is available, redirect accesses to
252 // neverland. Fake/overridden mappings will be flushed when
253 // switching to normal mode.
254 vaddr
= address
& TARGET_PAGE_MASK
;
255 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
256 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
260 env
->exception_index
= TT_TFAULT
;
262 env
->exception_index
= TT_DFAULT
;
267 target_ulong
mmu_probe(CPUState
*env
, target_ulong address
, int mmulev
)
269 target_phys_addr_t pde_ptr
;
272 /* Context base + context number */
273 pde_ptr
= (target_phys_addr_t
)(env
->mmuregs
[1] << 4) +
274 (env
->mmuregs
[2] << 2);
275 pde
= ldl_phys(pde_ptr
);
277 switch (pde
& PTE_ENTRYTYPE_MASK
) {
279 case 0: /* Invalid */
280 case 2: /* PTE, maybe should not happen? */
281 case 3: /* Reserved */
286 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
287 pde
= ldl_phys(pde_ptr
);
289 switch (pde
& PTE_ENTRYTYPE_MASK
) {
291 case 0: /* Invalid */
292 case 3: /* Reserved */
299 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
300 pde
= ldl_phys(pde_ptr
);
302 switch (pde
& PTE_ENTRYTYPE_MASK
) {
304 case 0: /* Invalid */
305 case 3: /* Reserved */
312 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
313 pde
= ldl_phys(pde_ptr
);
315 switch (pde
& PTE_ENTRYTYPE_MASK
) {
317 case 0: /* Invalid */
318 case 1: /* PDE, should not happen */
319 case 3: /* Reserved */
331 void dump_mmu(CPUState
*env
)
333 target_ulong va
, va1
, va2
;
334 unsigned int n
, m
, o
;
335 target_phys_addr_t pde_ptr
, pa
;
338 printf("MMU dump:\n");
339 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
340 pde
= ldl_phys(pde_ptr
);
341 printf("Root ptr: " TARGET_FMT_plx
", ctx: %d\n",
342 (target_phys_addr_t
)env
->mmuregs
[1] << 4, env
->mmuregs
[2]);
343 for (n
= 0, va
= 0; n
< 256; n
++, va
+= 16 * 1024 * 1024) {
344 pde
= mmu_probe(env
, va
, 2);
346 pa
= cpu_get_phys_page_debug(env
, va
);
347 printf("VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
348 " PDE: " TARGET_FMT_lx
"\n", va
, pa
, pde
);
349 for (m
= 0, va1
= va
; m
< 64; m
++, va1
+= 256 * 1024) {
350 pde
= mmu_probe(env
, va1
, 1);
352 pa
= cpu_get_phys_page_debug(env
, va1
);
353 printf(" VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
354 " PDE: " TARGET_FMT_lx
"\n", va1
, pa
, pde
);
355 for (o
= 0, va2
= va1
; o
< 64; o
++, va2
+= 4 * 1024) {
356 pde
= mmu_probe(env
, va2
, 0);
358 pa
= cpu_get_phys_page_debug(env
, va2
);
359 printf(" VA: " TARGET_FMT_lx
", PA: "
360 TARGET_FMT_plx
" PTE: " TARGET_FMT_lx
"\n",
368 printf("MMU dump ends\n");
370 #endif /* DEBUG_MMU */
372 #else /* !TARGET_SPARC64 */
374 // 41 bit physical address space
375 static inline target_phys_addr_t
ultrasparc_truncate_physical(uint64_t x
)
377 return x
& 0x1ffffffffffULL
;
381 * UltraSparc IIi I/DMMUs
384 static inline int compare_masked(uint64_t x
, uint64_t y
, uint64_t mask
)
386 return (x
& mask
) == (y
& mask
);
389 // Returns true if TTE tag is valid and matches virtual address value in context
390 // requires virtual address mask value calculated from TTE entry size
391 static inline int ultrasparc_tag_match(SparcTLBEntry
*tlb
,
392 uint64_t address
, uint64_t context
,
393 target_phys_addr_t
*physical
,
398 switch ((tlb
->tte
>> 61) & 3) {
401 mask
= 0xffffffffffffe000ULL
;
404 mask
= 0xffffffffffff0000ULL
;
407 mask
= 0xfffffffffff80000ULL
;
410 mask
= 0xffffffffffc00000ULL
;
414 // valid, context match, virtual address match?
415 if (TTE_IS_VALID(tlb
->tte
) &&
416 ((is_nucleus
&& compare_masked(0, tlb
->tag
, 0x1fff))
417 || TTE_IS_GLOBAL(tlb
->tte
) || compare_masked(context
, tlb
->tag
, 0x1fff))
418 && compare_masked(address
, tlb
->tag
, mask
))
420 // decode physical address
421 *physical
= ((tlb
->tte
& mask
) | (address
& ~mask
)) & 0x1ffffffe000ULL
;
428 static int get_physical_address_data(CPUState
*env
,
429 target_phys_addr_t
*physical
, int *prot
,
430 target_ulong address
, int rw
, int is_user
)
436 if ((env
->lsu
& DMMU_E
) == 0) { /* DMMU disabled */
437 *physical
= ultrasparc_truncate_physical(address
);
438 *prot
= PAGE_READ
| PAGE_WRITE
;
442 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
443 is_nucleus
= env
->tl
> 0;
445 for (i
= 0; i
< 64; i
++) {
446 // ctx match, vaddr match, valid?
447 if (ultrasparc_tag_match(&env
->dtlb
[i
],
448 address
, context
, physical
,
451 if (((env
->dtlb
[i
].tte
& 0x4) && is_user
) ||
452 (!(env
->dtlb
[i
].tte
& 0x2) && (rw
== 1))) {
453 uint8_t fault_type
= 0;
455 if ((env
->dtlb
[i
].tte
& 0x4) && is_user
) {
456 fault_type
|= 1; /* privilege violation */
459 if (env
->dmmu
.sfsr
& 1) /* Fault status register */
460 env
->dmmu
.sfsr
= 2; /* overflow (not read before
463 env
->dmmu
.sfsr
|= (is_user
<< 3) | ((rw
== 1) << 2) | 1;
465 env
->dmmu
.sfsr
|= (fault_type
<< 7);
467 env
->dmmu
.sfar
= address
; /* Fault address register */
468 env
->exception_index
= TT_DFAULT
;
470 printf("DFAULT at 0x%" PRIx64
"\n", address
);
475 if (env
->dtlb
[i
].tte
& 0x2)
477 TTE_SET_USED(env
->dtlb
[i
].tte
);
482 printf("DMISS at 0x%" PRIx64
"\n", address
);
484 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
485 env
->exception_index
= TT_DMISS
;
489 static int get_physical_address_code(CPUState
*env
,
490 target_phys_addr_t
*physical
, int *prot
,
491 target_ulong address
, int is_user
)
497 if ((env
->lsu
& IMMU_E
) == 0 || (env
->pstate
& PS_RED
) != 0) {
499 *physical
= ultrasparc_truncate_physical(address
);
504 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
505 is_nucleus
= env
->tl
> 0;
507 for (i
= 0; i
< 64; i
++) {
508 // ctx match, vaddr match, valid?
509 if (ultrasparc_tag_match(&env
->itlb
[i
],
510 address
, context
, physical
,
513 if ((env
->itlb
[i
].tte
& 0x4) && is_user
) {
514 if (env
->immu
.sfsr
) /* Fault status register */
515 env
->immu
.sfsr
= 2; /* overflow (not read before
517 env
->immu
.sfsr
|= (is_user
<< 3) | 1;
518 env
->exception_index
= TT_TFAULT
;
520 printf("TFAULT at 0x%" PRIx64
"\n", address
);
525 TTE_SET_USED(env
->itlb
[i
].tte
);
530 printf("TMISS at 0x%" PRIx64
"\n", address
);
532 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
533 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
534 env
->exception_index
= TT_TMISS
;
538 static int get_physical_address(CPUState
*env
, target_phys_addr_t
*physical
,
539 int *prot
, int *access_index
,
540 target_ulong address
, int rw
, int mmu_idx
,
541 target_ulong
*page_size
)
543 int is_user
= mmu_idx
== MMU_USER_IDX
;
545 /* ??? We treat everything as a small page, then explicitly flush
546 everything when an entry is evicted. */
547 *page_size
= TARGET_PAGE_SIZE
;
549 return get_physical_address_code(env
, physical
, prot
, address
,
552 return get_physical_address_data(env
, physical
, prot
, address
, rw
,
556 /* Perform address translation */
557 int cpu_sparc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
558 int mmu_idx
, int is_softmmu
)
560 target_ulong virt_addr
, vaddr
;
561 target_phys_addr_t paddr
;
562 target_ulong page_size
;
563 int error_code
= 0, prot
, access_index
;
565 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
,
566 address
, rw
, mmu_idx
, &page_size
);
567 if (error_code
== 0) {
568 virt_addr
= address
& TARGET_PAGE_MASK
;
569 vaddr
= virt_addr
+ ((address
& TARGET_PAGE_MASK
) &
570 (TARGET_PAGE_SIZE
- 1));
572 printf("Translate at 0x%" PRIx64
" -> 0x%" PRIx64
", vaddr 0x%" PRIx64
573 "\n", address
, paddr
, vaddr
);
575 tlb_set_page(env
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
583 void dump_mmu(CPUState
*env
)
588 printf("MMU contexts: Primary: %" PRId64
", Secondary: %" PRId64
"\n",
589 env
->dmmu
.mmu_primary_context
, env
->dmmu
.mmu_secondary_context
);
590 if ((env
->lsu
& DMMU_E
) == 0) {
591 printf("DMMU disabled\n");
593 printf("DMMU dump:\n");
594 for (i
= 0; i
< 64; i
++) {
595 switch ((env
->dtlb
[i
].tte
>> 61) & 3) {
610 if ((env
->dtlb
[i
].tte
& 0x8000000000000000ULL
) != 0) {
611 printf("[%02u] VA: %" PRIx64
", PA: %" PRIx64
612 ", %s, %s, %s, %s, ctx %" PRId64
" %s\n",
614 env
->dtlb
[i
].tag
& (uint64_t)~0x1fffULL
,
615 env
->dtlb
[i
].tte
& (uint64_t)0x1ffffffe000ULL
,
617 env
->dtlb
[i
].tte
& 0x4? "priv": "user",
618 env
->dtlb
[i
].tte
& 0x2? "RW": "RO",
619 env
->dtlb
[i
].tte
& 0x40? "locked": "unlocked",
620 env
->dtlb
[i
].tag
& (uint64_t)0x1fffULL
,
621 TTE_IS_GLOBAL(env
->dtlb
[i
].tag
)? "global" : "local");
625 if ((env
->lsu
& IMMU_E
) == 0) {
626 printf("IMMU disabled\n");
628 printf("IMMU dump:\n");
629 for (i
= 0; i
< 64; i
++) {
630 switch ((env
->itlb
[i
].tte
>> 61) & 3) {
645 if ((env
->itlb
[i
].tte
& 0x8000000000000000ULL
) != 0) {
646 printf("[%02u] VA: %" PRIx64
", PA: %" PRIx64
647 ", %s, %s, %s, ctx %" PRId64
" %s\n",
649 env
->itlb
[i
].tag
& (uint64_t)~0x1fffULL
,
650 env
->itlb
[i
].tte
& (uint64_t)0x1ffffffe000ULL
,
652 env
->itlb
[i
].tte
& 0x4? "priv": "user",
653 env
->itlb
[i
].tte
& 0x40? "locked": "unlocked",
654 env
->itlb
[i
].tag
& (uint64_t)0x1fffULL
,
655 TTE_IS_GLOBAL(env
->itlb
[i
].tag
)? "global" : "local");
660 #endif /* DEBUG_MMU */
662 #endif /* TARGET_SPARC64 */
663 #endif /* !CONFIG_USER_ONLY */
666 #if !defined(CONFIG_USER_ONLY)
667 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
669 target_phys_addr_t phys_addr
;
670 target_ulong page_size
;
671 int prot
, access_index
;
673 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
, 2,
674 MMU_KERNEL_IDX
, &page_size
) != 0)
675 if (get_physical_address(env
, &phys_addr
, &prot
, &access_index
, addr
,
676 0, MMU_KERNEL_IDX
, &page_size
) != 0)
678 if (cpu_get_physical_page_desc(phys_addr
) == IO_MEM_UNASSIGNED
)
684 void cpu_reset(CPUSPARCState
*env
)
686 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
687 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
688 log_cpu_state(env
, 0);
693 #ifndef TARGET_SPARC64
696 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
698 #if defined(CONFIG_USER_ONLY)
699 #ifdef TARGET_SPARC64
700 env
->cleanwin
= env
->nwindows
- 2;
701 env
->cansave
= env
->nwindows
- 2;
702 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
703 env
->asi
= 0x82; // Primary no-fault
706 #if !defined(TARGET_SPARC64)
711 #ifdef TARGET_SPARC64
712 env
->pstate
= PS_PRIV
|PS_RED
|PS_PEF
|PS_AG
;
713 env
->hpstate
= HS_PRIV
;
714 env
->tl
= env
->maxtl
;
715 cpu_tsptr(env
)->tt
= TT_POWER_ON_RESET
;
718 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
719 env
->mmuregs
[0] |= env
->def
->mmu_bm
;
722 env
->npc
= env
->pc
+ 4;
726 static int cpu_sparc_register(CPUSPARCState
*env
, const char *cpu_model
)
728 sparc_def_t def1
, *def
= &def1
;
730 if (cpu_sparc_find_by_name(def
, cpu_model
) < 0)
733 env
->def
= qemu_mallocz(sizeof(*def
));
734 memcpy(env
->def
, def
, sizeof(*def
));
735 #if defined(CONFIG_USER_ONLY)
736 if ((env
->def
->features
& CPU_FEATURE_FLOAT
))
737 env
->def
->features
|= CPU_FEATURE_FLOAT128
;
739 env
->cpu_model_str
= cpu_model
;
740 env
->version
= def
->iu_version
;
741 env
->fsr
= def
->fpu_version
;
742 env
->nwindows
= def
->nwindows
;
743 #if !defined(TARGET_SPARC64)
744 env
->mmuregs
[0] |= def
->mmu_version
;
745 cpu_sparc_set_id(env
, 0);
746 env
->mxccregs
[7] |= def
->mxcc_version
;
748 env
->mmu_version
= def
->mmu_version
;
749 env
->maxtl
= def
->maxtl
;
750 env
->version
|= def
->maxtl
<< 8;
751 env
->version
|= def
->nwindows
- 1;
756 static void cpu_sparc_close(CPUSPARCState
*env
)
762 CPUSPARCState
*cpu_sparc_init(const char *cpu_model
)
766 env
= qemu_mallocz(sizeof(CPUSPARCState
));
769 gen_intermediate_code_init(env
);
771 if (cpu_sparc_register(env
, cpu_model
) < 0) {
772 cpu_sparc_close(env
);
780 void cpu_sparc_set_id(CPUSPARCState
*env
, unsigned int cpu
)
782 #if !defined(TARGET_SPARC64)
783 env
->mxccregs
[7] = ((cpu
+ 8) & 0xf) << 24;
787 static const sparc_def_t sparc_defs
[] = {
788 #ifdef TARGET_SPARC64
790 .name
= "Fujitsu Sparc64",
791 .iu_version
= ((0x04ULL
<< 48) | (0x02ULL
<< 32) | (0ULL << 24)),
792 .fpu_version
= 0x00000000,
793 .mmu_version
= mmu_us_12
,
796 .features
= CPU_DEFAULT_FEATURES
,
799 .name
= "Fujitsu Sparc64 III",
800 .iu_version
= ((0x04ULL
<< 48) | (0x03ULL
<< 32) | (0ULL << 24)),
801 .fpu_version
= 0x00000000,
802 .mmu_version
= mmu_us_12
,
805 .features
= CPU_DEFAULT_FEATURES
,
808 .name
= "Fujitsu Sparc64 IV",
809 .iu_version
= ((0x04ULL
<< 48) | (0x04ULL
<< 32) | (0ULL << 24)),
810 .fpu_version
= 0x00000000,
811 .mmu_version
= mmu_us_12
,
814 .features
= CPU_DEFAULT_FEATURES
,
817 .name
= "Fujitsu Sparc64 V",
818 .iu_version
= ((0x04ULL
<< 48) | (0x05ULL
<< 32) | (0x51ULL
<< 24)),
819 .fpu_version
= 0x00000000,
820 .mmu_version
= mmu_us_12
,
823 .features
= CPU_DEFAULT_FEATURES
,
826 .name
= "TI UltraSparc I",
827 .iu_version
= ((0x17ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
828 .fpu_version
= 0x00000000,
829 .mmu_version
= mmu_us_12
,
832 .features
= CPU_DEFAULT_FEATURES
,
835 .name
= "TI UltraSparc II",
836 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0x20ULL
<< 24)),
837 .fpu_version
= 0x00000000,
838 .mmu_version
= mmu_us_12
,
841 .features
= CPU_DEFAULT_FEATURES
,
844 .name
= "TI UltraSparc IIi",
845 .iu_version
= ((0x17ULL
<< 48) | (0x12ULL
<< 32) | (0x91ULL
<< 24)),
846 .fpu_version
= 0x00000000,
847 .mmu_version
= mmu_us_12
,
850 .features
= CPU_DEFAULT_FEATURES
,
853 .name
= "TI UltraSparc IIe",
854 .iu_version
= ((0x17ULL
<< 48) | (0x13ULL
<< 32) | (0x14ULL
<< 24)),
855 .fpu_version
= 0x00000000,
856 .mmu_version
= mmu_us_12
,
859 .features
= CPU_DEFAULT_FEATURES
,
862 .name
= "Sun UltraSparc III",
863 .iu_version
= ((0x3eULL
<< 48) | (0x14ULL
<< 32) | (0x34ULL
<< 24)),
864 .fpu_version
= 0x00000000,
865 .mmu_version
= mmu_us_12
,
868 .features
= CPU_DEFAULT_FEATURES
,
871 .name
= "Sun UltraSparc III Cu",
872 .iu_version
= ((0x3eULL
<< 48) | (0x15ULL
<< 32) | (0x41ULL
<< 24)),
873 .fpu_version
= 0x00000000,
874 .mmu_version
= mmu_us_3
,
877 .features
= CPU_DEFAULT_FEATURES
,
880 .name
= "Sun UltraSparc IIIi",
881 .iu_version
= ((0x3eULL
<< 48) | (0x16ULL
<< 32) | (0x34ULL
<< 24)),
882 .fpu_version
= 0x00000000,
883 .mmu_version
= mmu_us_12
,
886 .features
= CPU_DEFAULT_FEATURES
,
889 .name
= "Sun UltraSparc IV",
890 .iu_version
= ((0x3eULL
<< 48) | (0x18ULL
<< 32) | (0x31ULL
<< 24)),
891 .fpu_version
= 0x00000000,
892 .mmu_version
= mmu_us_4
,
895 .features
= CPU_DEFAULT_FEATURES
,
898 .name
= "Sun UltraSparc IV+",
899 .iu_version
= ((0x3eULL
<< 48) | (0x19ULL
<< 32) | (0x22ULL
<< 24)),
900 .fpu_version
= 0x00000000,
901 .mmu_version
= mmu_us_12
,
904 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_CMT
,
907 .name
= "Sun UltraSparc IIIi+",
908 .iu_version
= ((0x3eULL
<< 48) | (0x22ULL
<< 32) | (0ULL << 24)),
909 .fpu_version
= 0x00000000,
910 .mmu_version
= mmu_us_3
,
913 .features
= CPU_DEFAULT_FEATURES
,
916 .name
= "Sun UltraSparc T1",
917 // defined in sparc_ifu_fdp.v and ctu.h
918 .iu_version
= ((0x3eULL
<< 48) | (0x23ULL
<< 32) | (0x02ULL
<< 24)),
919 .fpu_version
= 0x00000000,
920 .mmu_version
= mmu_sun4v
,
923 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
927 .name
= "Sun UltraSparc T2",
928 // defined in tlu_asi_ctl.v and n2_revid_cust.v
929 .iu_version
= ((0x3eULL
<< 48) | (0x24ULL
<< 32) | (0x02ULL
<< 24)),
930 .fpu_version
= 0x00000000,
931 .mmu_version
= mmu_sun4v
,
934 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
938 .name
= "NEC UltraSparc I",
939 .iu_version
= ((0x22ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
940 .fpu_version
= 0x00000000,
941 .mmu_version
= mmu_us_12
,
944 .features
= CPU_DEFAULT_FEATURES
,
948 .name
= "Fujitsu MB86900",
949 .iu_version
= 0x00 << 24, /* Impl 0, ver 0 */
950 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
951 .mmu_version
= 0x00 << 24, /* Impl 0, ver 0 */
952 .mmu_bm
= 0x00004000,
953 .mmu_ctpr_mask
= 0x007ffff0,
954 .mmu_cxr_mask
= 0x0000003f,
955 .mmu_sfsr_mask
= 0xffffffff,
956 .mmu_trcr_mask
= 0xffffffff,
958 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_FSMULD
,
961 .name
= "Fujitsu MB86904",
962 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
963 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
964 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
965 .mmu_bm
= 0x00004000,
966 .mmu_ctpr_mask
= 0x00ffffc0,
967 .mmu_cxr_mask
= 0x000000ff,
968 .mmu_sfsr_mask
= 0x00016fff,
969 .mmu_trcr_mask
= 0x00ffffff,
971 .features
= CPU_DEFAULT_FEATURES
,
974 .name
= "Fujitsu MB86907",
975 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
976 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
977 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
978 .mmu_bm
= 0x00004000,
979 .mmu_ctpr_mask
= 0xffffffc0,
980 .mmu_cxr_mask
= 0x000000ff,
981 .mmu_sfsr_mask
= 0x00016fff,
982 .mmu_trcr_mask
= 0xffffffff,
984 .features
= CPU_DEFAULT_FEATURES
,
987 .name
= "LSI L64811",
988 .iu_version
= 0x10 << 24, /* Impl 1, ver 0 */
989 .fpu_version
= 1 << 17, /* FPU version 1 (LSI L64814) */
990 .mmu_version
= 0x10 << 24,
991 .mmu_bm
= 0x00004000,
992 .mmu_ctpr_mask
= 0x007ffff0,
993 .mmu_cxr_mask
= 0x0000003f,
994 .mmu_sfsr_mask
= 0xffffffff,
995 .mmu_trcr_mask
= 0xffffffff,
997 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1001 .name
= "Cypress CY7C601",
1002 .iu_version
= 0x11 << 24, /* Impl 1, ver 1 */
1003 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1004 .mmu_version
= 0x10 << 24,
1005 .mmu_bm
= 0x00004000,
1006 .mmu_ctpr_mask
= 0x007ffff0,
1007 .mmu_cxr_mask
= 0x0000003f,
1008 .mmu_sfsr_mask
= 0xffffffff,
1009 .mmu_trcr_mask
= 0xffffffff,
1011 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1015 .name
= "Cypress CY7C611",
1016 .iu_version
= 0x13 << 24, /* Impl 1, ver 3 */
1017 .fpu_version
= 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1018 .mmu_version
= 0x10 << 24,
1019 .mmu_bm
= 0x00004000,
1020 .mmu_ctpr_mask
= 0x007ffff0,
1021 .mmu_cxr_mask
= 0x0000003f,
1022 .mmu_sfsr_mask
= 0xffffffff,
1023 .mmu_trcr_mask
= 0xffffffff,
1025 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1029 .name
= "TI MicroSparc I",
1030 .iu_version
= 0x41000000,
1031 .fpu_version
= 4 << 17,
1032 .mmu_version
= 0x41000000,
1033 .mmu_bm
= 0x00004000,
1034 .mmu_ctpr_mask
= 0x007ffff0,
1035 .mmu_cxr_mask
= 0x0000003f,
1036 .mmu_sfsr_mask
= 0x00016fff,
1037 .mmu_trcr_mask
= 0x0000003f,
1039 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_MUL
|
1040 CPU_FEATURE_DIV
| CPU_FEATURE_FLUSH
| CPU_FEATURE_FSQRT
|
1044 .name
= "TI MicroSparc II",
1045 .iu_version
= 0x42000000,
1046 .fpu_version
= 4 << 17,
1047 .mmu_version
= 0x02000000,
1048 .mmu_bm
= 0x00004000,
1049 .mmu_ctpr_mask
= 0x00ffffc0,
1050 .mmu_cxr_mask
= 0x000000ff,
1051 .mmu_sfsr_mask
= 0x00016fff,
1052 .mmu_trcr_mask
= 0x00ffffff,
1054 .features
= CPU_DEFAULT_FEATURES
,
1057 .name
= "TI MicroSparc IIep",
1058 .iu_version
= 0x42000000,
1059 .fpu_version
= 4 << 17,
1060 .mmu_version
= 0x04000000,
1061 .mmu_bm
= 0x00004000,
1062 .mmu_ctpr_mask
= 0x00ffffc0,
1063 .mmu_cxr_mask
= 0x000000ff,
1064 .mmu_sfsr_mask
= 0x00016bff,
1065 .mmu_trcr_mask
= 0x00ffffff,
1067 .features
= CPU_DEFAULT_FEATURES
,
1070 .name
= "TI SuperSparc 40", // STP1020NPGA
1071 .iu_version
= 0x41000000, // SuperSPARC 2.x
1072 .fpu_version
= 0 << 17,
1073 .mmu_version
= 0x00000800, // SuperSPARC 2.x, no MXCC
1074 .mmu_bm
= 0x00002000,
1075 .mmu_ctpr_mask
= 0xffffffc0,
1076 .mmu_cxr_mask
= 0x0000ffff,
1077 .mmu_sfsr_mask
= 0xffffffff,
1078 .mmu_trcr_mask
= 0xffffffff,
1080 .features
= CPU_DEFAULT_FEATURES
,
1083 .name
= "TI SuperSparc 50", // STP1020PGA
1084 .iu_version
= 0x40000000, // SuperSPARC 3.x
1085 .fpu_version
= 0 << 17,
1086 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1087 .mmu_bm
= 0x00002000,
1088 .mmu_ctpr_mask
= 0xffffffc0,
1089 .mmu_cxr_mask
= 0x0000ffff,
1090 .mmu_sfsr_mask
= 0xffffffff,
1091 .mmu_trcr_mask
= 0xffffffff,
1093 .features
= CPU_DEFAULT_FEATURES
,
1096 .name
= "TI SuperSparc 51",
1097 .iu_version
= 0x40000000, // SuperSPARC 3.x
1098 .fpu_version
= 0 << 17,
1099 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1100 .mmu_bm
= 0x00002000,
1101 .mmu_ctpr_mask
= 0xffffffc0,
1102 .mmu_cxr_mask
= 0x0000ffff,
1103 .mmu_sfsr_mask
= 0xffffffff,
1104 .mmu_trcr_mask
= 0xffffffff,
1105 .mxcc_version
= 0x00000104,
1107 .features
= CPU_DEFAULT_FEATURES
,
1110 .name
= "TI SuperSparc 60", // STP1020APGA
1111 .iu_version
= 0x40000000, // SuperSPARC 3.x
1112 .fpu_version
= 0 << 17,
1113 .mmu_version
= 0x01000800, // SuperSPARC 3.x, no MXCC
1114 .mmu_bm
= 0x00002000,
1115 .mmu_ctpr_mask
= 0xffffffc0,
1116 .mmu_cxr_mask
= 0x0000ffff,
1117 .mmu_sfsr_mask
= 0xffffffff,
1118 .mmu_trcr_mask
= 0xffffffff,
1120 .features
= CPU_DEFAULT_FEATURES
,
1123 .name
= "TI SuperSparc 61",
1124 .iu_version
= 0x44000000, // SuperSPARC 3.x
1125 .fpu_version
= 0 << 17,
1126 .mmu_version
= 0x01000000, // SuperSPARC 3.x, MXCC
1127 .mmu_bm
= 0x00002000,
1128 .mmu_ctpr_mask
= 0xffffffc0,
1129 .mmu_cxr_mask
= 0x0000ffff,
1130 .mmu_sfsr_mask
= 0xffffffff,
1131 .mmu_trcr_mask
= 0xffffffff,
1132 .mxcc_version
= 0x00000104,
1134 .features
= CPU_DEFAULT_FEATURES
,
1137 .name
= "TI SuperSparc II",
1138 .iu_version
= 0x40000000, // SuperSPARC II 1.x
1139 .fpu_version
= 0 << 17,
1140 .mmu_version
= 0x08000000, // SuperSPARC II 1.x, MXCC
1141 .mmu_bm
= 0x00002000,
1142 .mmu_ctpr_mask
= 0xffffffc0,
1143 .mmu_cxr_mask
= 0x0000ffff,
1144 .mmu_sfsr_mask
= 0xffffffff,
1145 .mmu_trcr_mask
= 0xffffffff,
1146 .mxcc_version
= 0x00000104,
1148 .features
= CPU_DEFAULT_FEATURES
,
1151 .name
= "Ross RT625",
1152 .iu_version
= 0x1e000000,
1153 .fpu_version
= 1 << 17,
1154 .mmu_version
= 0x1e000000,
1155 .mmu_bm
= 0x00004000,
1156 .mmu_ctpr_mask
= 0x007ffff0,
1157 .mmu_cxr_mask
= 0x0000003f,
1158 .mmu_sfsr_mask
= 0xffffffff,
1159 .mmu_trcr_mask
= 0xffffffff,
1161 .features
= CPU_DEFAULT_FEATURES
,
1164 .name
= "Ross RT620",
1165 .iu_version
= 0x1f000000,
1166 .fpu_version
= 1 << 17,
1167 .mmu_version
= 0x1f000000,
1168 .mmu_bm
= 0x00004000,
1169 .mmu_ctpr_mask
= 0x007ffff0,
1170 .mmu_cxr_mask
= 0x0000003f,
1171 .mmu_sfsr_mask
= 0xffffffff,
1172 .mmu_trcr_mask
= 0xffffffff,
1174 .features
= CPU_DEFAULT_FEATURES
,
1177 .name
= "BIT B5010",
1178 .iu_version
= 0x20000000,
1179 .fpu_version
= 0 << 17, /* B5010/B5110/B5120/B5210 */
1180 .mmu_version
= 0x20000000,
1181 .mmu_bm
= 0x00004000,
1182 .mmu_ctpr_mask
= 0x007ffff0,
1183 .mmu_cxr_mask
= 0x0000003f,
1184 .mmu_sfsr_mask
= 0xffffffff,
1185 .mmu_trcr_mask
= 0xffffffff,
1187 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_SWAP
| CPU_FEATURE_FSQRT
|
1191 .name
= "Matsushita MN10501",
1192 .iu_version
= 0x50000000,
1193 .fpu_version
= 0 << 17,
1194 .mmu_version
= 0x50000000,
1195 .mmu_bm
= 0x00004000,
1196 .mmu_ctpr_mask
= 0x007ffff0,
1197 .mmu_cxr_mask
= 0x0000003f,
1198 .mmu_sfsr_mask
= 0xffffffff,
1199 .mmu_trcr_mask
= 0xffffffff,
1201 .features
= CPU_FEATURE_FLOAT
| CPU_FEATURE_MUL
| CPU_FEATURE_FSQRT
|
1205 .name
= "Weitek W8601",
1206 .iu_version
= 0x90 << 24, /* Impl 9, ver 0 */
1207 .fpu_version
= 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1208 .mmu_version
= 0x10 << 24,
1209 .mmu_bm
= 0x00004000,
1210 .mmu_ctpr_mask
= 0x007ffff0,
1211 .mmu_cxr_mask
= 0x0000003f,
1212 .mmu_sfsr_mask
= 0xffffffff,
1213 .mmu_trcr_mask
= 0xffffffff,
1215 .features
= CPU_DEFAULT_FEATURES
,
1219 .iu_version
= 0xf2000000,
1220 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1221 .mmu_version
= 0xf2000000,
1222 .mmu_bm
= 0x00004000,
1223 .mmu_ctpr_mask
= 0x007ffff0,
1224 .mmu_cxr_mask
= 0x0000003f,
1225 .mmu_sfsr_mask
= 0xffffffff,
1226 .mmu_trcr_mask
= 0xffffffff,
1228 .features
= CPU_DEFAULT_FEATURES
,
1232 .iu_version
= 0xf3000000,
1233 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
1234 .mmu_version
= 0xf3000000,
1235 .mmu_bm
= 0x00004000,
1236 .mmu_ctpr_mask
= 0x007ffff0,
1237 .mmu_cxr_mask
= 0x0000003f,
1238 .mmu_sfsr_mask
= 0xffffffff,
1239 .mmu_trcr_mask
= 0xffffffff,
1241 .features
= CPU_DEFAULT_FEATURES
,
1246 static const char * const feature_name
[] = {
1263 static void print_features(FILE *f
,
1264 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1265 uint32_t features
, const char *prefix
)
1269 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1270 if (feature_name
[i
] && (features
& (1 << i
))) {
1272 (*cpu_fprintf
)(f
, "%s", prefix
);
1273 (*cpu_fprintf
)(f
, "%s ", feature_name
[i
]);
1277 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
)
1281 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++)
1282 if (feature_name
[i
] && !strcmp(flagname
, feature_name
[i
])) {
1283 *features
|= 1 << i
;
1286 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
1289 static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def
, const char *cpu_model
)
1292 const sparc_def_t
*def
= NULL
;
1293 char *s
= strdup(cpu_model
);
1294 char *featurestr
, *name
= strtok(s
, ",");
1295 uint32_t plus_features
= 0;
1296 uint32_t minus_features
= 0;
1297 long long iu_version
;
1298 uint32_t fpu_version
, mmu_version
, nwindows
;
1300 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1301 if (strcasecmp(name
, sparc_defs
[i
].name
) == 0) {
1302 def
= &sparc_defs
[i
];
1307 memcpy(cpu_def
, def
, sizeof(*def
));
1309 featurestr
= strtok(NULL
, ",");
1310 while (featurestr
) {
1313 if (featurestr
[0] == '+') {
1314 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
);
1315 } else if (featurestr
[0] == '-') {
1316 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
);
1317 } else if ((val
= strchr(featurestr
, '='))) {
1319 if (!strcmp(featurestr
, "iu_version")) {
1322 iu_version
= strtoll(val
, &err
, 0);
1323 if (!*val
|| *err
) {
1324 fprintf(stderr
, "bad numerical value %s\n", val
);
1327 cpu_def
->iu_version
= iu_version
;
1328 #ifdef DEBUG_FEATURES
1329 fprintf(stderr
, "iu_version %llx\n", iu_version
);
1331 } else if (!strcmp(featurestr
, "fpu_version")) {
1334 fpu_version
= strtol(val
, &err
, 0);
1335 if (!*val
|| *err
) {
1336 fprintf(stderr
, "bad numerical value %s\n", val
);
1339 cpu_def
->fpu_version
= fpu_version
;
1340 #ifdef DEBUG_FEATURES
1341 fprintf(stderr
, "fpu_version %x\n", fpu_version
);
1343 } else if (!strcmp(featurestr
, "mmu_version")) {
1346 mmu_version
= strtol(val
, &err
, 0);
1347 if (!*val
|| *err
) {
1348 fprintf(stderr
, "bad numerical value %s\n", val
);
1351 cpu_def
->mmu_version
= mmu_version
;
1352 #ifdef DEBUG_FEATURES
1353 fprintf(stderr
, "mmu_version %x\n", mmu_version
);
1355 } else if (!strcmp(featurestr
, "nwindows")) {
1358 nwindows
= strtol(val
, &err
, 0);
1359 if (!*val
|| *err
|| nwindows
> MAX_NWINDOWS
||
1360 nwindows
< MIN_NWINDOWS
) {
1361 fprintf(stderr
, "bad numerical value %s\n", val
);
1364 cpu_def
->nwindows
= nwindows
;
1365 #ifdef DEBUG_FEATURES
1366 fprintf(stderr
, "nwindows %d\n", nwindows
);
1369 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1373 fprintf(stderr
, "feature string `%s' not in format "
1374 "(+feature|-feature|feature=xyz)\n", featurestr
);
1377 featurestr
= strtok(NULL
, ",");
1379 cpu_def
->features
|= plus_features
;
1380 cpu_def
->features
&= ~minus_features
;
1381 #ifdef DEBUG_FEATURES
1382 print_features(stderr
, fprintf
, cpu_def
->features
, NULL
);
1392 void sparc_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
1396 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
1397 (*cpu_fprintf
)(f
, "Sparc %16s IU " TARGET_FMT_lx
" FPU %08x MMU %08x NWINS %d ",
1399 sparc_defs
[i
].iu_version
,
1400 sparc_defs
[i
].fpu_version
,
1401 sparc_defs
[i
].mmu_version
,
1402 sparc_defs
[i
].nwindows
);
1403 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
&
1404 ~sparc_defs
[i
].features
, "-");
1405 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
&
1406 sparc_defs
[i
].features
, "+");
1407 (*cpu_fprintf
)(f
, "\n");
1409 (*cpu_fprintf
)(f
, "Default CPU feature flags (use '-' to remove): ");
1410 print_features(f
, cpu_fprintf
, CPU_DEFAULT_FEATURES
, NULL
);
1411 (*cpu_fprintf
)(f
, "\n");
1412 (*cpu_fprintf
)(f
, "Available CPU feature flags (use '+' to add): ");
1413 print_features(f
, cpu_fprintf
, ~CPU_DEFAULT_FEATURES
, NULL
);
1414 (*cpu_fprintf
)(f
, "\n");
1415 (*cpu_fprintf
)(f
, "Numerical features (use '=' to set): iu_version "
1416 "fpu_version mmu_version nwindows\n");
1419 static void cpu_print_cc(FILE *f
,
1420 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1423 cpu_fprintf(f
, "%c%c%c%c", cc
& PSR_NEG
? 'N' : '-',
1424 cc
& PSR_ZERO
? 'Z' : '-', cc
& PSR_OVF
? 'V' : '-',
1425 cc
& PSR_CARRY
? 'C' : '-');
1428 #ifdef TARGET_SPARC64
1429 #define REGS_PER_LINE 4
1431 #define REGS_PER_LINE 8
1434 void cpu_dump_state(CPUState
*env
, FILE *f
,
1435 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
1440 cpu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
,
1442 cpu_fprintf(f
, "General Registers:\n");
1444 for (i
= 0; i
< 8; i
++) {
1445 if (i
% REGS_PER_LINE
== 0) {
1446 cpu_fprintf(f
, "%%g%d-%d:", i
, i
+ REGS_PER_LINE
- 1);
1448 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gregs
[i
]);
1449 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
1450 cpu_fprintf(f
, "\n");
1453 cpu_fprintf(f
, "\nCurrent Register Window:\n");
1454 for (x
= 0; x
< 3; x
++) {
1455 for (i
= 0; i
< 8; i
++) {
1456 if (i
% REGS_PER_LINE
== 0) {
1457 cpu_fprintf(f
, "%%%c%d-%d: ",
1458 x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i'),
1459 i
, i
+ REGS_PER_LINE
- 1);
1461 cpu_fprintf(f
, TARGET_FMT_lx
" ", env
->regwptr
[i
+ x
* 8]);
1462 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
1463 cpu_fprintf(f
, "\n");
1467 cpu_fprintf(f
, "\nFloating Point Registers:\n");
1468 for (i
= 0; i
< TARGET_FPREGS
; i
++) {
1470 cpu_fprintf(f
, "%%f%02d:", i
);
1471 cpu_fprintf(f
, " %016f", *(float *)&env
->fpr
[i
]);
1473 cpu_fprintf(f
, "\n");
1475 #ifdef TARGET_SPARC64
1476 cpu_fprintf(f
, "pstate: %08x ccr: %02x (icc: ", env
->pstate
,
1478 cpu_print_cc(f
, cpu_fprintf
, GET_CCR(env
) << PSR_CARRY_SHIFT
);
1479 cpu_fprintf(f
, " xcc: ");
1480 cpu_print_cc(f
, cpu_fprintf
, GET_CCR(env
) << (PSR_CARRY_SHIFT
- 4));
1481 cpu_fprintf(f
, ") asi: %02x tl: %d pil: %x\n", env
->asi
, env
->tl
,
1483 cpu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
1484 "cleanwin: %d cwp: %d\n",
1485 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
1486 env
->cleanwin
, env
->nwindows
- 1 - env
->cwp
);
1487 cpu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
" fprs: "
1488 TARGET_FMT_lx
"\n", env
->fsr
, env
->y
, env
->fprs
);
1490 cpu_fprintf(f
, "psr: %08x (icc: ", GET_PSR(env
));
1491 cpu_print_cc(f
, cpu_fprintf
, GET_PSR(env
));
1492 cpu_fprintf(f
, " SPE: %c%c%c) wim: %08x\n", env
->psrs
? 'S' : '-',
1493 env
->psrps
? 'P' : '-', env
->psret
? 'E' : '-',
1495 cpu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
"\n",