4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 /* Eventually those constants should go to Linux pci_regs.h */
25 #define PCI_MSI_PENDING_32 0x10
26 #define PCI_MSI_PENDING_64 0x14
28 /* PCI_MSI_ADDRESS_LO */
29 #define PCI_MSI_ADDRESS_LO_MASK (~0x3)
31 /* If we get rid of cap allocator, we won't need those. */
32 #define PCI_MSI_32_SIZEOF 0x0a
33 #define PCI_MSI_64_SIZEOF 0x0e
34 #define PCI_MSI_32M_SIZEOF 0x14
35 #define PCI_MSI_64M_SIZEOF 0x18
37 #define PCI_MSI_VECTORS_MAX 32
39 /* Flag for interrupt controller to declare MSI/MSI-X support */
42 /* If we get rid of cap allocator, we won't need this. */
43 static inline uint8_t msi_cap_sizeof(uint16_t flags
)
45 switch (flags
& (PCI_MSI_FLAGS_MASKBIT
| PCI_MSI_FLAGS_64BIT
)) {
46 case PCI_MSI_FLAGS_MASKBIT
| PCI_MSI_FLAGS_64BIT
:
47 return PCI_MSI_64M_SIZEOF
;
48 case PCI_MSI_FLAGS_64BIT
:
49 return PCI_MSI_64_SIZEOF
;
50 case PCI_MSI_FLAGS_MASKBIT
:
51 return PCI_MSI_32M_SIZEOF
;
53 return PCI_MSI_32_SIZEOF
;
64 # define MSI_DPRINTF(fmt, ...) \
65 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
67 # define MSI_DPRINTF(fmt, ...) do { } while (0)
69 #define MSI_DEV_PRINTF(dev, fmt, ...) \
70 MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
72 static inline unsigned int msi_nr_vectors(uint16_t flags
)
75 ((flags
& PCI_MSI_FLAGS_QSIZE
) >> (ffs(PCI_MSI_FLAGS_QSIZE
) - 1));
78 static inline uint8_t msi_flags_off(const PCIDevice
* dev
)
80 return dev
->msi_cap
+ PCI_MSI_FLAGS
;
83 static inline uint8_t msi_address_lo_off(const PCIDevice
* dev
)
85 return dev
->msi_cap
+ PCI_MSI_ADDRESS_LO
;
88 static inline uint8_t msi_address_hi_off(const PCIDevice
* dev
)
90 return dev
->msi_cap
+ PCI_MSI_ADDRESS_HI
;
93 static inline uint8_t msi_data_off(const PCIDevice
* dev
, bool msi64bit
)
95 return dev
->msi_cap
+ (msi64bit
? PCI_MSI_DATA_64
: PCI_MSI_DATA_32
);
98 static inline uint8_t msi_mask_off(const PCIDevice
* dev
, bool msi64bit
)
100 return dev
->msi_cap
+ (msi64bit
? PCI_MSI_MASK_64
: PCI_MSI_MASK_32
);
103 static inline uint8_t msi_pending_off(const PCIDevice
* dev
, bool msi64bit
)
105 return dev
->msi_cap
+ (msi64bit
? PCI_MSI_PENDING_64
: PCI_MSI_PENDING_32
);
108 bool msi_enabled(const PCIDevice
*dev
)
110 return msi_present(dev
) &&
111 (pci_get_word(dev
->config
+ msi_flags_off(dev
)) &
112 PCI_MSI_FLAGS_ENABLE
);
115 int msi_init(struct PCIDevice
*dev
, uint8_t offset
,
116 unsigned int nr_vectors
, bool msi64bit
, bool msi_per_vector_mask
)
118 unsigned int vectors_order
;
123 if (!msi_supported
) {
128 "init offset: 0x%"PRIx8
" vector: %"PRId8
129 " 64bit %d mask %d\n",
130 offset
, nr_vectors
, msi64bit
, msi_per_vector_mask
);
132 assert(!(nr_vectors
& (nr_vectors
- 1))); /* power of 2 */
133 assert(nr_vectors
> 0);
134 assert(nr_vectors
<= PCI_MSI_VECTORS_MAX
);
135 /* the nr of MSI vectors is up to 32 */
136 vectors_order
= ffs(nr_vectors
) - 1;
138 flags
= vectors_order
<< (ffs(PCI_MSI_FLAGS_QMASK
) - 1);
140 flags
|= PCI_MSI_FLAGS_64BIT
;
142 if (msi_per_vector_mask
) {
143 flags
|= PCI_MSI_FLAGS_MASKBIT
;
146 cap_size
= msi_cap_sizeof(flags
);
147 config_offset
= pci_add_capability(dev
, PCI_CAP_ID_MSI
, offset
, cap_size
);
148 if (config_offset
< 0) {
149 return config_offset
;
152 dev
->msi_cap
= config_offset
;
153 dev
->cap_present
|= QEMU_PCI_CAP_MSI
;
155 pci_set_word(dev
->config
+ msi_flags_off(dev
), flags
);
156 pci_set_word(dev
->wmask
+ msi_flags_off(dev
),
157 PCI_MSI_FLAGS_QSIZE
| PCI_MSI_FLAGS_ENABLE
);
158 pci_set_long(dev
->wmask
+ msi_address_lo_off(dev
),
159 PCI_MSI_ADDRESS_LO_MASK
);
161 pci_set_long(dev
->wmask
+ msi_address_hi_off(dev
), 0xffffffff);
163 pci_set_word(dev
->wmask
+ msi_data_off(dev
, msi64bit
), 0xffff);
165 if (msi_per_vector_mask
) {
166 /* Make mask bits 0 to nr_vectors - 1 writable. */
167 pci_set_long(dev
->wmask
+ msi_mask_off(dev
, msi64bit
),
168 0xffffffff >> (PCI_MSI_VECTORS_MAX
- nr_vectors
));
170 return config_offset
;
173 void msi_uninit(struct PCIDevice
*dev
)
178 if (!(dev
->cap_present
& QEMU_PCI_CAP_MSI
)) {
181 flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
182 cap_size
= msi_cap_sizeof(flags
);
183 pci_del_capability(dev
, PCI_CAP_ID_MSI
, cap_size
);
184 dev
->cap_present
&= ~QEMU_PCI_CAP_MSI
;
186 MSI_DEV_PRINTF(dev
, "uninit\n");
189 void msi_reset(PCIDevice
*dev
)
194 if (!msi_present(dev
)) {
198 flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
199 flags
&= ~(PCI_MSI_FLAGS_QSIZE
| PCI_MSI_FLAGS_ENABLE
);
200 msi64bit
= flags
& PCI_MSI_FLAGS_64BIT
;
202 pci_set_word(dev
->config
+ msi_flags_off(dev
), flags
);
203 pci_set_long(dev
->config
+ msi_address_lo_off(dev
), 0);
205 pci_set_long(dev
->config
+ msi_address_hi_off(dev
), 0);
207 pci_set_word(dev
->config
+ msi_data_off(dev
, msi64bit
), 0);
208 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
209 pci_set_long(dev
->config
+ msi_mask_off(dev
, msi64bit
), 0);
210 pci_set_long(dev
->config
+ msi_pending_off(dev
, msi64bit
), 0);
212 MSI_DEV_PRINTF(dev
, "reset\n");
215 static bool msi_is_masked(const PCIDevice
*dev
, unsigned int vector
)
217 uint16_t flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
219 assert(vector
< PCI_MSI_VECTORS_MAX
);
221 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
225 mask
= pci_get_long(dev
->config
+
226 msi_mask_off(dev
, flags
& PCI_MSI_FLAGS_64BIT
));
227 return mask
& (1U << vector
);
230 void msi_notify(PCIDevice
*dev
, unsigned int vector
)
232 uint16_t flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
233 bool msi64bit
= flags
& PCI_MSI_FLAGS_64BIT
;
234 unsigned int nr_vectors
= msi_nr_vectors(flags
);
238 assert(vector
< nr_vectors
);
239 if (msi_is_masked(dev
, vector
)) {
240 assert(flags
& PCI_MSI_FLAGS_MASKBIT
);
241 pci_long_test_and_set_mask(
242 dev
->config
+ msi_pending_off(dev
, msi64bit
), 1U << vector
);
243 MSI_DEV_PRINTF(dev
, "pending vector 0x%x\n", vector
);
248 address
= pci_get_quad(dev
->config
+ msi_address_lo_off(dev
));
250 address
= pci_get_long(dev
->config
+ msi_address_lo_off(dev
));
253 /* upper bit 31:16 is zero */
254 data
= pci_get_word(dev
->config
+ msi_data_off(dev
, msi64bit
));
255 if (nr_vectors
> 1) {
256 data
&= ~(nr_vectors
- 1);
262 " address: 0x%"PRIx64
" data: 0x%"PRIx32
"\n",
263 vector
, address
, data
);
264 stl_le_phys(address
, data
);
267 /* call this function after updating configs by pci_default_write_config(). */
268 void msi_write_config(PCIDevice
*dev
, uint32_t addr
, uint32_t val
, int len
)
270 uint16_t flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
271 bool msi64bit
= flags
& PCI_MSI_FLAGS_64BIT
;
272 bool msi_per_vector_mask
= flags
& PCI_MSI_FLAGS_MASKBIT
;
273 unsigned int nr_vectors
;
274 uint8_t log_num_vecs
;
275 uint8_t log_max_vecs
;
279 if (!msi_present(dev
) ||
280 !ranges_overlap(addr
, len
, dev
->msi_cap
, msi_cap_sizeof(flags
))) {
285 MSI_DEV_PRINTF(dev
, "addr 0x%"PRIx32
" val 0x%"PRIx32
" len %d\n",
287 MSI_DEV_PRINTF(dev
, "ctrl: 0x%"PRIx16
" address: 0x%"PRIx32
,
289 pci_get_long(dev
->config
+ msi_address_lo_off(dev
)));
291 fprintf(stderr
, " address-hi: 0x%"PRIx32
,
292 pci_get_long(dev
->config
+ msi_address_hi_off(dev
)));
294 fprintf(stderr
, " data: 0x%"PRIx16
,
295 pci_get_word(dev
->config
+ msi_data_off(dev
, msi64bit
)));
296 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
297 fprintf(stderr
, " mask 0x%"PRIx32
" pending 0x%"PRIx32
,
298 pci_get_long(dev
->config
+ msi_mask_off(dev
, msi64bit
)),
299 pci_get_long(dev
->config
+ msi_pending_off(dev
, msi64bit
)));
301 fprintf(stderr
, "\n");
304 if (!(flags
& PCI_MSI_FLAGS_ENABLE
)) {
309 * Now MSI is enabled, clear INTx# interrupts.
310 * the driver is prohibited from writing enable bit to mask
311 * a service request. But the guest OS could do this.
312 * So we just discard the interrupts as moderate fallback.
314 * 6.8.3.3. Enabling Operation
315 * While enabled for MSI or MSI-X operation, a function is prohibited
316 * from using its INTx# pin (if implemented) to request
317 * service (MSI, MSI-X, and INTx# are mutually exclusive).
319 pci_device_deassert_intx(dev
);
322 * nr_vectors might be set bigger than capable. So clamp it.
323 * This is not legal by spec, so we can do anything we like,
324 * just don't crash the host
327 (flags
& PCI_MSI_FLAGS_QSIZE
) >> (ffs(PCI_MSI_FLAGS_QSIZE
) - 1);
329 (flags
& PCI_MSI_FLAGS_QMASK
) >> (ffs(PCI_MSI_FLAGS_QMASK
) - 1);
330 if (log_num_vecs
> log_max_vecs
) {
331 flags
&= ~PCI_MSI_FLAGS_QSIZE
;
332 flags
|= log_max_vecs
<< (ffs(PCI_MSI_FLAGS_QSIZE
) - 1);
333 pci_set_word(dev
->config
+ msi_flags_off(dev
), flags
);
336 if (!msi_per_vector_mask
) {
337 /* if per vector masking isn't supported,
338 there is no pending interrupt. */
342 nr_vectors
= msi_nr_vectors(flags
);
344 /* This will discard pending interrupts, if any. */
345 pending
= pci_get_long(dev
->config
+ msi_pending_off(dev
, msi64bit
));
346 pending
&= 0xffffffff >> (PCI_MSI_VECTORS_MAX
- nr_vectors
);
347 pci_set_long(dev
->config
+ msi_pending_off(dev
, msi64bit
), pending
);
349 /* deliver pending interrupts which are unmasked */
350 for (vector
= 0; vector
< nr_vectors
; ++vector
) {
351 if (msi_is_masked(dev
, vector
) || !(pending
& (1U << vector
))) {
355 pci_long_test_and_clear_mask(
356 dev
->config
+ msi_pending_off(dev
, msi64bit
), 1U << vector
);
357 msi_notify(dev
, vector
);
361 unsigned int msi_nr_vectors_allocated(const PCIDevice
*dev
)
363 uint16_t flags
= pci_get_word(dev
->config
+ msi_flags_off(dev
));
364 return msi_nr_vectors(flags
);