2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 * Data structures for storing PCI state
20 * Adapted to kvm by Qumranet
22 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
23 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
24 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
25 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
28 #ifndef __DEVICE_ASSIGNMENT_H__
29 #define __DEVICE_ASSIGNMENT_H__
32 #include "qemu-common.h"
33 #include "qemu-queue.h"
36 /* From include/linux/pci.h in the kernel sources */
37 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
39 typedef struct PCIHostDevice
{
47 int type
; /* Memory or port I/O */
50 uint32_t size
; /* size of the region */
55 uint8_t bus
, dev
, func
; /* Bus inside domain, device and function */
56 int irq
; /* IRQ number */
57 uint16_t region_number
; /* number of active regions */
59 /* Port I/O or MMIO Regions */
60 PCIRegion regions
[PCI_NUM_REGIONS
- 1];
65 MemoryRegion container
;
66 MemoryRegion real_iomem
;
68 void *r_virtbase
; /* mmapped access address for memory regions */
69 uint32_t r_baseport
; /* the base guest port for I/O regions */
71 int num
; /* our index within v_addrs[] */
72 pcibus_t e_size
; /* emulated size of region in bytes */
73 pcibus_t r_size
; /* real size of region in bytes */
77 #define ASSIGNED_DEVICE_USE_IOMMU_BIT 0
78 #define ASSIGNED_DEVICE_PREFER_MSI_BIT 1
80 #define ASSIGNED_DEVICE_USE_IOMMU_MASK (1 << ASSIGNED_DEVICE_USE_IOMMU_BIT)
81 #define ASSIGNED_DEVICE_PREFER_MSI_MASK (1 << ASSIGNED_DEVICE_PREFER_MSI_BIT)
83 typedef struct AssignedDevice
{
89 AssignedDevRegion v_addrs
[PCI_NUM_REGIONS
- 1];
90 PCIDevRegions real_device
;
96 int irq_requested_type
;
99 #define ASSIGNED_DEVICE_CAP_MSI (1 << 0)
100 #define ASSIGNED_DEVICE_CAP_MSIX (1 << 1)
102 #define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0)
103 #define ASSIGNED_DEVICE_MSIX_ENABLED (1 << 1)
104 #define ASSIGNED_DEVICE_MSIX_MASKED (1 << 2)
107 uint8_t emulate_config_read
[PCI_CONFIG_SPACE_SIZE
];
108 uint8_t emulate_config_write
[PCI_CONFIG_SPACE_SIZE
];
110 struct kvm_irq_routing_entry
*entry
;
111 void *msix_table_page
;
112 target_phys_addr_t msix_table_addr
;
116 QLIST_ENTRY(AssignedDevice
) next
;
119 void assigned_dev_update_irqs(void);
121 #endif /* __DEVICE_ASSIGNMENT_H__ */