target-alpha/cpu.h

   1 /*
   2  *  Alpha emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #if !defined (__CPU_ALPHA_H__)
  21 #define __CPU_ALPHA_H__
  22
  23 #include "config.h"
  24 #include "qemu-common.h"
  25
  26 #define TARGET_LONG_BITS 64
  27
  28 #define CPUArchState struct CPUAlphaState
  29
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define ELF_MACHINE     EM_ALPHA
  37
  38 #define ICACHE_LINE_SIZE 32
  39 #define DCACHE_LINE_SIZE 32
  40
  41 #define TARGET_PAGE_BITS 13
  42
  43 #ifdef CONFIG_USER_ONLY
  44 /* ??? The kernel likes to give addresses in high memory.  If the host has
  45    more virtual address space than the guest, this can lead to impossible
  46    allocations.  Honor the long-standing assumption that only kernel addrs
  47    are negative, but otherwise allow allocations anywhere.  This could lead
  48    to tricky emulation problems for programs doing tagged addressing, but
  49    that's far fewer than encounter the impossible allocation problem.  */
  50 #define TARGET_PHYS_ADDR_SPACE_BITS  63
  51 #define TARGET_VIRT_ADDR_SPACE_BITS  63
  52 #else
  53 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
  54 #define TARGET_PHYS_ADDR_SPACE_BITS  44
  55 #define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
  56 #endif
  57
  58 /* Alpha major type */
  59 enum {
  60     ALPHA_EV3  = 1,
  61     ALPHA_EV4  = 2,
  62     ALPHA_SIM  = 3,
  63     ALPHA_LCA  = 4,
  64     ALPHA_EV5  = 5, /* 21164 */
  65     ALPHA_EV45 = 6, /* 21064A */
  66     ALPHA_EV56 = 7, /* 21164A */
  67 };
  68
  69 /* EV4 minor type */
  70 enum {
  71     ALPHA_EV4_2 = 0,
  72     ALPHA_EV4_3 = 1,
  73 };
  74
  75 /* LCA minor type */
  76 enum {
  77     ALPHA_LCA_1 = 1, /* 21066 */
  78     ALPHA_LCA_2 = 2, /* 20166 */
  79     ALPHA_LCA_3 = 3, /* 21068 */
  80     ALPHA_LCA_4 = 4, /* 21068 */
  81     ALPHA_LCA_5 = 5, /* 21066A */
  82     ALPHA_LCA_6 = 6, /* 21068A */
  83 };
  84
  85 /* EV5 minor type */
  86 enum {
  87     ALPHA_EV5_1 = 1, /* Rev BA, CA */
  88     ALPHA_EV5_2 = 2, /* Rev DA, EA */
  89     ALPHA_EV5_3 = 3, /* Pass 3 */
  90     ALPHA_EV5_4 = 4, /* Pass 3.2 */
  91     ALPHA_EV5_5 = 5, /* Pass 4 */
  92 };
  93
  94 /* EV45 minor type */
  95 enum {
  96     ALPHA_EV45_1 = 1, /* Pass 1 */
  97     ALPHA_EV45_2 = 2, /* Pass 1.1 */
  98     ALPHA_EV45_3 = 3, /* Pass 2 */
  99 };
 100
 101 /* EV56 minor type */
 102 enum {
 103     ALPHA_EV56_1 = 1, /* Pass 1 */
 104     ALPHA_EV56_2 = 2, /* Pass 2 */
 105 };
 106
 107 enum {
 108     IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
 109     IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
 110     IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
 111     IMPLVER_21364 = 3, /* EV7 & EV79 */
 112 };
 113
 114 enum {
 115     AMASK_BWX      = 0x00000001,
 116     AMASK_FIX      = 0x00000002,
 117     AMASK_CIX      = 0x00000004,
 118     AMASK_MVI      = 0x00000100,
 119     AMASK_TRAP     = 0x00000200,
 120     AMASK_PREFETCH = 0x00001000,
 121 };
 122
 123 enum {
 124     VAX_ROUND_NORMAL = 0,
 125     VAX_ROUND_CHOPPED,
 126 };
 127
 128 enum {
 129     IEEE_ROUND_NORMAL = 0,
 130     IEEE_ROUND_DYNAMIC,
 131     IEEE_ROUND_PLUS,
 132     IEEE_ROUND_MINUS,
 133     IEEE_ROUND_CHOPPED,
 134 };
 135
 136 /* IEEE floating-point operations encoding */
 137 /* Trap mode */
 138 enum {
 139     FP_TRAP_I   = 0x0,
 140     FP_TRAP_U   = 0x1,
 141     FP_TRAP_S  = 0x4,
 142     FP_TRAP_SU  = 0x5,
 143     FP_TRAP_SUI = 0x7,
 144 };
 145
 146 /* Rounding mode */
 147 enum {
 148     FP_ROUND_CHOPPED = 0x0,
 149     FP_ROUND_MINUS   = 0x1,
 150     FP_ROUND_NORMAL  = 0x2,
 151     FP_ROUND_DYNAMIC = 0x3,
 152 };
 153
 154 /* FPCR bits */
 155 #define FPCR_SUM                (1ULL << 63)
 156 #define FPCR_INED               (1ULL << 62)
 157 #define FPCR_UNFD               (1ULL << 61)
 158 #define FPCR_UNDZ               (1ULL << 60)
 159 #define FPCR_DYN_SHIFT          58
 160 #define FPCR_DYN_CHOPPED        (0ULL << FPCR_DYN_SHIFT)
 161 #define FPCR_DYN_MINUS          (1ULL << FPCR_DYN_SHIFT)
 162 #define FPCR_DYN_NORMAL         (2ULL << FPCR_DYN_SHIFT)
 163 #define FPCR_DYN_PLUS           (3ULL << FPCR_DYN_SHIFT)
 164 #define FPCR_DYN_MASK           (3ULL << FPCR_DYN_SHIFT)
 165 #define FPCR_IOV                (1ULL << 57)
 166 #define FPCR_INE                (1ULL << 56)
 167 #define FPCR_UNF                (1ULL << 55)
 168 #define FPCR_OVF                (1ULL << 54)
 169 #define FPCR_DZE                (1ULL << 53)
 170 #define FPCR_INV                (1ULL << 52)
 171 #define FPCR_OVFD               (1ULL << 51)
 172 #define FPCR_DZED               (1ULL << 50)
 173 #define FPCR_INVD               (1ULL << 49)
 174 #define FPCR_DNZ                (1ULL << 48)
 175 #define FPCR_DNOD               (1ULL << 47)
 176 #define FPCR_STATUS_MASK        (FPCR_IOV | FPCR_INE | FPCR_UNF \
 177                                  | FPCR_OVF | FPCR_DZE | FPCR_INV)
 178
 179 /* The silly software trap enables implemented by the kernel emulation.
 180    These are more or less architecturally required, since the real hardware
 181    has read-as-zero bits in the FPCR when the features aren't implemented.
 182    For the purposes of QEMU, we pretend the FPCR can hold everything.  */
 183 #define SWCR_TRAP_ENABLE_INV    (1ULL << 1)
 184 #define SWCR_TRAP_ENABLE_DZE    (1ULL << 2)
 185 #define SWCR_TRAP_ENABLE_OVF    (1ULL << 3)
 186 #define SWCR_TRAP_ENABLE_UNF    (1ULL << 4)
 187 #define SWCR_TRAP_ENABLE_INE    (1ULL << 5)
 188 #define SWCR_TRAP_ENABLE_DNO    (1ULL << 6)
 189 #define SWCR_TRAP_ENABLE_MASK   ((1ULL << 7) - (1ULL << 1))
 190
 191 #define SWCR_MAP_DMZ            (1ULL << 12)
 192 #define SWCR_MAP_UMZ            (1ULL << 13)
 193 #define SWCR_MAP_MASK           (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
 194
 195 #define SWCR_STATUS_INV         (1ULL << 17)
 196 #define SWCR_STATUS_DZE         (1ULL << 18)
 197 #define SWCR_STATUS_OVF         (1ULL << 19)
 198 #define SWCR_STATUS_UNF         (1ULL << 20)
 199 #define SWCR_STATUS_INE         (1ULL << 21)
 200 #define SWCR_STATUS_DNO         (1ULL << 22)
 201 #define SWCR_STATUS_MASK        ((1ULL << 23) - (1ULL << 17))
 202
 203 #define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
 204
 205 /* MMU modes definitions */
 206
 207 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
 208    The Unix PALcode only exposes the kernel and user modes; presumably
 209    executive and supervisor are used by VMS.
 210
 211    PALcode itself uses physical mode for code and kernel mode for data;
 212    there are PALmode instructions that can access data via physical mode
 213    or via an os-installed "alternate mode", which is one of the 4 above.
 214
 215    QEMU does not currently properly distinguish between code/data when
 216    looking up addresses.  To avoid having to address this issue, our
 217    emulated PALcode will cheat and use the KSEG mapping for its code+data
 218    rather than physical addresses.
 219
 220    Moreover, we're only emulating Unix PALcode, and not attempting VMS.
 221
 222    All of which allows us to drop all but kernel and user modes.
 223    Elide the unused MMU modes to save space.  */
 224
 225 #define NB_MMU_MODES 2
 226
 227 #define MMU_MODE0_SUFFIX _kernel
 228 #define MMU_MODE1_SUFFIX _user
 229 #define MMU_KERNEL_IDX   0
 230 #define MMU_USER_IDX     1
 231
 232 typedef struct CPUAlphaState CPUAlphaState;
 233
 234 struct CPUAlphaState {
 235     uint64_t ir[31];
 236     float64 fir[31];
 237     uint64_t pc;
 238     uint64_t unique;
 239     uint64_t lock_addr;
 240     uint64_t lock_st_addr;
 241     uint64_t lock_value;
 242     float_status fp_status;
 243     /* The following fields make up the FPCR, but in FP_STATUS format.  */
 244     uint8_t fpcr_exc_status;
 245     uint8_t fpcr_exc_mask;
 246     uint8_t fpcr_dyn_round;
 247     uint8_t fpcr_flush_to_zero;
 248     uint8_t fpcr_dnod;
 249     uint8_t fpcr_undz;
 250
 251     /* The Internal Processor Registers.  Some of these we assume always
 252        exist for use in user-mode.  */
 253     uint8_t ps;
 254     uint8_t intr_flag;
 255     uint8_t pal_mode;
 256     uint8_t fen;
 257
 258     uint32_t pcc_ofs;
 259
 260     /* These pass data from the exception logic in the translator and
 261        helpers to the OS entry point.  This is used for both system
 262        emulation and user-mode.  */
 263     uint64_t trap_arg0;
 264     uint64_t trap_arg1;
 265     uint64_t trap_arg2;
 266
 267 #if !defined(CONFIG_USER_ONLY)
 268     /* The internal data required by our emulation of the Unix PALcode.  */
 269     uint64_t exc_addr;
 270     uint64_t palbr;
 271     uint64_t ptbr;
 272     uint64_t vptptr;
 273     uint64_t sysval;
 274     uint64_t usp;
 275     uint64_t shadow[8];
 276     uint64_t scratch[24];
 277 #endif
 278
 279     /* This alarm doesn't exist in real hardware; we wish it did.  */
 280     struct QEMUTimer *alarm_timer;
 281     uint64_t alarm_expire;
 282
 283 #if TARGET_LONG_BITS > HOST_LONG_BITS
 284     /* temporary fixed-point registers
 285      * used to emulate 64 bits target on 32 bits hosts
 286      */
 287     target_ulong t0, t1;
 288 #endif
 289
 290     /* Those resources are used only in QEMU core */
 291     CPU_COMMON
 292
 293     int error_code;
 294
 295     uint32_t features;
 296     uint32_t amask;
 297     int implver;
 298 };
 299
 300 #define cpu_init cpu_alpha_init
 301 #define cpu_exec cpu_alpha_exec
 302 #define cpu_gen_code cpu_alpha_gen_code
 303 #define cpu_signal_handler cpu_alpha_signal_handler
 304
 305 #include "cpu-all.h"
 306 #include "cpu-qom.h"
 307
 308 enum {
 309     FEATURE_ASN    = 0x00000001,
 310     FEATURE_SPS    = 0x00000002,
 311     FEATURE_VIRBND = 0x00000004,
 312     FEATURE_TBCHK  = 0x00000008,
 313 };
 314
 315 enum {
 316     EXCP_RESET,
 317     EXCP_MCHK,
 318     EXCP_SMP_INTERRUPT,
 319     EXCP_CLK_INTERRUPT,
 320     EXCP_DEV_INTERRUPT,
 321     EXCP_MMFAULT,
 322     EXCP_UNALIGN,
 323     EXCP_OPCDEC,
 324     EXCP_ARITH,
 325     EXCP_FEN,
 326     EXCP_CALL_PAL,
 327     /* For Usermode emulation.  */
 328     EXCP_STL_C,
 329     EXCP_STQ_C,
 330 };
 331
 332 /* Alpha-specific interrupt pending bits.  */
 333 #define CPU_INTERRUPT_TIMER     CPU_INTERRUPT_TGT_EXT_0
 334 #define CPU_INTERRUPT_SMP       CPU_INTERRUPT_TGT_EXT_1
 335 #define CPU_INTERRUPT_MCHK      CPU_INTERRUPT_TGT_EXT_2
 336
 337 /* OSF/1 Page table bits.  */
 338 enum {
 339     PTE_VALID = 0x0001,
 340     PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
 341     PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
 342     PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
 343     PTE_ASM   = 0x0010,
 344     PTE_KRE   = 0x0100,
 345     PTE_URE   = 0x0200,
 346     PTE_KWE   = 0x1000,
 347     PTE_UWE   = 0x2000
 348 };
 349
 350 /* Hardware interrupt (entInt) constants.  */
 351 enum {
 352     INT_K_IP,
 353     INT_K_CLK,
 354     INT_K_MCHK,
 355     INT_K_DEV,
 356     INT_K_PERF,
 357 };
 358
 359 /* Memory management (entMM) constants.  */
 360 enum {
 361     MM_K_TNV,
 362     MM_K_ACV,
 363     MM_K_FOR,
 364     MM_K_FOE,
 365     MM_K_FOW
 366 };
 367
 368 /* Arithmetic exception (entArith) constants.  */
 369 enum {
 370     EXC_M_SWC = 1,      /* Software completion */
 371     EXC_M_INV = 2,      /* Invalid operation */
 372     EXC_M_DZE = 4,      /* Division by zero */
 373     EXC_M_FOV = 8,      /* Overflow */
 374     EXC_M_UNF = 16,     /* Underflow */
 375     EXC_M_INE = 32,     /* Inexact result */
 376     EXC_M_IOV = 64      /* Integer Overflow */
 377 };
 378
 379 /* Processor status constants.  */
 380 enum {
 381     /* Low 3 bits are interrupt mask level.  */
 382     PS_INT_MASK = 7,
 383
 384     /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
 385        The Unix PALcode only uses bit 4.  */
 386     PS_USER_MODE = 8
 387 };
 388
 389 static inline int cpu_mmu_index(CPUAlphaState *env)
 390 {
 391     if (env->pal_mode) {
 392         return MMU_KERNEL_IDX;
 393     } else if (env->ps & PS_USER_MODE) {
 394         return MMU_USER_IDX;
 395     } else {
 396         return MMU_KERNEL_IDX;
 397     }
 398 }
 399
 400 enum {
 401     IR_V0   = 0,
 402     IR_T0   = 1,
 403     IR_T1   = 2,
 404     IR_T2   = 3,
 405     IR_T3   = 4,
 406     IR_T4   = 5,
 407     IR_T5   = 6,
 408     IR_T6   = 7,
 409     IR_T7   = 8,
 410     IR_S0   = 9,
 411     IR_S1   = 10,
 412     IR_S2   = 11,
 413     IR_S3   = 12,
 414     IR_S4   = 13,
 415     IR_S5   = 14,
 416     IR_S6   = 15,
 417     IR_FP   = IR_S6,
 418     IR_A0   = 16,
 419     IR_A1   = 17,
 420     IR_A2   = 18,
 421     IR_A3   = 19,
 422     IR_A4   = 20,
 423     IR_A5   = 21,
 424     IR_T8   = 22,
 425     IR_T9   = 23,
 426     IR_T10  = 24,
 427     IR_T11  = 25,
 428     IR_RA   = 26,
 429     IR_T12  = 27,
 430     IR_PV   = IR_T12,
 431     IR_AT   = 28,
 432     IR_GP   = 29,
 433     IR_SP   = 30,
 434     IR_ZERO = 31,
 435 };
 436
 437 CPUAlphaState * cpu_alpha_init (const char *cpu_model);
 438 int cpu_alpha_exec(CPUAlphaState *s);
 439 /* you can call this signal handler from your SIGBUS and SIGSEGV
 440    signal handlers to inform the virtual CPU of exceptions. non zero
 441    is returned if the signal was handled by the virtual CPU.  */
 442 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
 443                              void *puc);
 444 int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
 445                                 int mmu_idx);
 446 #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
 447 void do_interrupt (CPUAlphaState *env);
 448 void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
 449 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
 450 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
 451
 452 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
 453 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
 454 #ifndef CONFIG_USER_ONLY
 455 void swap_shadow_regs(CPUAlphaState *env);
 456 QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
 457                                          target_phys_addr_t addr, int is_write,
 458                                          int is_exec, int unused, int size);
 459 #endif
 460
 461 /* Bits in TB->FLAGS that control how translation is processed.  */
 462 enum {
 463     TB_FLAGS_PAL_MODE = 1,
 464     TB_FLAGS_FEN = 2,
 465     TB_FLAGS_USER_MODE = 8,
 466
 467     TB_FLAGS_AMASK_SHIFT = 4,
 468     TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
 469     TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
 470     TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
 471     TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
 472     TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
 473     TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
 474 };
 475
 476 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
 477                                         target_ulong *cs_base, int *pflags)
 478 {
 479     int flags = 0;
 480
 481     *pc = env->pc;
 482     *cs_base = 0;
 483
 484     if (env->pal_mode) {
 485         flags = TB_FLAGS_PAL_MODE;
 486     } else {
 487         flags = env->ps & PS_USER_MODE;
 488     }
 489     if (env->fen) {
 490         flags |= TB_FLAGS_FEN;
 491     }
 492     flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
 493
 494     *pflags = flags;
 495 }
 496
 497 #if defined(CONFIG_USER_ONLY)
 498 static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
 499 {
 500     if (newsp) {
 501         env->ir[IR_SP] = newsp;
 502     }
 503     env->ir[IR_V0] = 0;
 504     env->ir[IR_A3] = 0;
 505 }
 506
 507 static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
 508 {
 509     env->unique = newtls;
 510 }
 511 #endif
 512
 513 static inline bool cpu_has_work(CPUAlphaState *env)
 514 {
 515     /* Here we are checking to see if the CPU should wake up from HALT.
 516        We will have gotten into this state only for WTINT from PALmode.  */
 517     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
 518        asleep even if (some) interrupts have been asserted.  For now,
 519        assume that if a CPU really wants to stay asleep, it will mask
 520        interrupts at the chipset level, which will prevent these bits
 521        from being set in the first place.  */
 522     return env->interrupt_request & (CPU_INTERRUPT_HARD
 523                                      | CPU_INTERRUPT_TIMER
 524                                      | CPU_INTERRUPT_SMP
 525                                      | CPU_INTERRUPT_MCHK);
 526 }
 527
 528 #include "exec-all.h"
 529
 530 static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
 531 {
 532     env->pc = tb->pc;
 533 }
 534
 535 #endif /* !defined (__CPU_ALPHA_H__) */