hw/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "boards.h"
  25 #include "sysemu.h"
  26 #include "sysbus.h"
  27 #include "arm-misc.h"
  28 #include "loader.h"
  29 #include "exynos4210.h"
  30
  31 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  32
  33 /* PWM */
  34 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  35
  36 /* MCT */
  37 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  38
  39 /* UART's definitions */
  40 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  41 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  42 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  43 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  44 #define EXYNOS4210_UART0_FIFO_SIZE     256
  45 #define EXYNOS4210_UART1_FIFO_SIZE     64
  46 #define EXYNOS4210_UART2_FIFO_SIZE     16
  47 #define EXYNOS4210_UART3_FIFO_SIZE     16
  48 /* Interrupt Group of External Interrupt Combiner for UART */
  49 #define EXYNOS4210_UART_INT_GRP        26
  50
  51 /* External GIC */
  52 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  53 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  54
  55 /* Combiner */
  56 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  57 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  58
  59 /* PMU SFR base address */
  60 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  61
  62 /* Display controllers (FIMD) */
  63 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  64
  65 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  66                                     0x09, 0x00, 0x00, 0x00 };
  67
  68 void exynos4210_write_secondary(ARMCPU *cpu,
  69         const struct arm_boot_info *info)
  70 {
  71     int n;
  72     uint32_t smpboot[] = {
  73         0xe59f3024, /* ldr r3, External gic_cpu_if */
  74         0xe59f2024, /* ldr r2, Internal gic_cpu_if */
  75         0xe59f0024, /* ldr r0, startaddr */
  76         0xe3a01001, /* mov r1, #1 */
  77         0xe5821000, /* str r1, [r2] */
  78         0xe5831000, /* str r1, [r3] */
  79         0xe320f003, /* wfi */
  80         0xe5901000, /* ldr     r1, [r0] */
  81         0xe1110001, /* tst     r1, r1 */
  82         0x0afffffb, /* beq     <wfi> */
  83         0xe12fff11, /* bx      r1 */
  84         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
  85         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
  86         0           /* bootreg: Boot register address is held here */
  87     };
  88     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
  89     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
  90     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  91         smpboot[n] = tswap32(smpboot[n]);
  92     }
  93     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
  94                        info->smp_loader_start);
  95 }
  96
  97 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
  98         unsigned long ram_size)
  99 {
 100     qemu_irq cpu_irq[EXYNOS4210_NCPUS];
 101     int i, n;
 102     Exynos4210State *s = g_new(Exynos4210State, 1);
 103     qemu_irq *irqp;
 104     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
 105     unsigned long mem_size;
 106     DeviceState *dev;
 107     SysBusDevice *busdev;
 108
 109     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 110         s->cpu[n] = cpu_arm_init("cortex-a9");
 111         if (!s->cpu[n]) {
 112             fprintf(stderr, "Unable to find CPU %d definition\n", n);
 113             exit(1);
 114         }
 115
 116         /* Create PIC controller for each processor instance */
 117         irqp = arm_pic_init_cpu(s->cpu[n]);
 118
 119         /*
 120          * Get GICs gpio_in cpu_irq to connect a combiner to them later.
 121          * Use only IRQ for a while.
 122          */
 123         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 124     }
 125
 126     /*** IRQs ***/
 127
 128     s->irq_table = exynos4210_init_irq(&s->irqs);
 129
 130     /* IRQ Gate */
 131     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 132         dev = qdev_create(NULL, "exynos4210.irq_gate");
 133         qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
 134         qdev_init_nofail(dev);
 135         /* Get IRQ Gate input in gate_irq */
 136         for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 137             gate_irq[i][n] = qdev_get_gpio_in(dev, n);
 138         }
 139         busdev = sysbus_from_qdev(dev);
 140
 141         /* Connect IRQ Gate output to cpu_irq */
 142         sysbus_connect_irq(busdev, 0, cpu_irq[i]);
 143     }
 144
 145     /* Private memory region and Internal GIC */
 146     dev = qdev_create(NULL, "a9mpcore_priv");
 147     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 148     qdev_init_nofail(dev);
 149     busdev = sysbus_from_qdev(dev);
 150     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 151     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 152         sysbus_connect_irq(busdev, n, gate_irq[n][0]);
 153     }
 154     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 155         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 156     }
 157
 158     /* Cache controller */
 159     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 160
 161     /* External GIC */
 162     dev = qdev_create(NULL, "exynos4210.gic");
 163     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 164     qdev_init_nofail(dev);
 165     busdev = sysbus_from_qdev(dev);
 166     /* Map CPU interface */
 167     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 168     /* Map Distributer interface */
 169     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 170     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 171         sysbus_connect_irq(busdev, n, gate_irq[n][1]);
 172     }
 173     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 174         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 175     }
 176
 177     /* Internal Interrupt Combiner */
 178     dev = qdev_create(NULL, "exynos4210.combiner");
 179     qdev_init_nofail(dev);
 180     busdev = sysbus_from_qdev(dev);
 181     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 182         sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 183     }
 184     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 185     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 186
 187     /* External Interrupt Combiner */
 188     dev = qdev_create(NULL, "exynos4210.combiner");
 189     qdev_prop_set_uint32(dev, "external", 1);
 190     qdev_init_nofail(dev);
 191     busdev = sysbus_from_qdev(dev);
 192     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 193         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 194     }
 195     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 196     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 197
 198     /* Initialize board IRQs. */
 199     exynos4210_init_board_irqs(&s->irqs);
 200
 201     /*** Memory ***/
 202
 203     /* Chip-ID and OMR */
 204     memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
 205             sizeof(chipid_and_omr), chipid_and_omr);
 206     memory_region_set_readonly(&s->chipid_mem, true);
 207     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 208                                 &s->chipid_mem);
 209
 210     /* Internal ROM */
 211     memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
 212                            EXYNOS4210_IROM_SIZE);
 213     memory_region_set_readonly(&s->irom_mem, true);
 214     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 215                                 &s->irom_mem);
 216     /* mirror of iROM */
 217     memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
 218                              &s->irom_mem,
 219                              EXYNOS4210_IROM_BASE_ADDR,
 220                              EXYNOS4210_IROM_SIZE);
 221     memory_region_set_readonly(&s->irom_alias_mem, true);
 222     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 223                                 &s->irom_alias_mem);
 224
 225     /* Internal RAM */
 226     memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
 227                            EXYNOS4210_IRAM_SIZE);
 228     vmstate_register_ram_global(&s->iram_mem);
 229     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 230                                 &s->iram_mem);
 231
 232     /* DRAM */
 233     mem_size = ram_size;
 234     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 235         memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
 236                 mem_size - EXYNOS4210_DRAM_MAX_SIZE);
 237         vmstate_register_ram_global(&s->dram1_mem);
 238         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 239                 &s->dram1_mem);
 240         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 241     }
 242     memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
 243     vmstate_register_ram_global(&s->dram0_mem);
 244     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 245             &s->dram0_mem);
 246
 247    /* PMU.
 248     * The only reason of existence at the moment is that secondary CPU boot
 249     * loader uses PMU INFORM5 register as a holding pen.
 250     */
 251     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 252
 253     /* PWM */
 254     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 255                           s->irq_table[exynos4210_get_irq(22, 0)],
 256                           s->irq_table[exynos4210_get_irq(22, 1)],
 257                           s->irq_table[exynos4210_get_irq(22, 2)],
 258                           s->irq_table[exynos4210_get_irq(22, 3)],
 259                           s->irq_table[exynos4210_get_irq(22, 4)],
 260                           NULL);
 261
 262     /* Multi Core Timer */
 263     dev = qdev_create(NULL, "exynos4210.mct");
 264     qdev_init_nofail(dev);
 265     busdev = sysbus_from_qdev(dev);
 266     for (n = 0; n < 4; n++) {
 267         /* Connect global timer interrupts to Combiner gpio_in */
 268         sysbus_connect_irq(busdev, n,
 269                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 270     }
 271     /* Connect local timer interrupts to Combiner gpio_in */
 272     sysbus_connect_irq(busdev, 4,
 273             s->irq_table[exynos4210_get_irq(51, 0)]);
 274     sysbus_connect_irq(busdev, 5,
 275             s->irq_table[exynos4210_get_irq(35, 3)]);
 276     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 277
 278     /*** UARTs ***/
 279     exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 280                            EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 281                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 282
 283     exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 284                            EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 285                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 286
 287     exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 288                            EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 289                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 290
 291     exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 292                            EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 293                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 294
 295     /*** Display controller (FIMD) ***/
 296     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 297             s->irq_table[exynos4210_get_irq(11, 0)],
 298             s->irq_table[exynos4210_get_irq(11, 1)],
 299             s->irq_table[exynos4210_get_irq(11, 2)],
 300             NULL);
 301
 302     return s;
 303 }