target-ppc/fpu_helper.c

   1 /*
   2  *  PowerPC floating point and SPE emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "exec/helper-proto.h"
  21
  22 /*****************************************************************************/
  23 /* Floating point operations helpers */
  24 uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
  25 {
  26     CPU_FloatU f;
  27     CPU_DoubleU d;
  28
  29     f.l = arg;
  30     d.d = float32_to_float64(f.f, &env->fp_status);
  31     return d.ll;
  32 }
  33
  34 uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
  35 {
  36     CPU_FloatU f;
  37     CPU_DoubleU d;
  38
  39     d.ll = arg;
  40     f.f = float64_to_float32(d.d, &env->fp_status);
  41     return f.l;
  42 }
  43
  44 static inline int isden(float64 d)
  45 {
  46     CPU_DoubleU u;
  47
  48     u.d = d;
  49
  50     return ((u.ll >> 52) & 0x7FF) == 0;
  51 }
  52
  53 static inline int ppc_float32_get_unbiased_exp(float32 f)
  54 {
  55     return ((f >> 23) & 0xFF) - 127;
  56 }
  57
  58 static inline int ppc_float64_get_unbiased_exp(float64 f)
  59 {
  60     return ((f >> 52) & 0x7FF) - 1023;
  61 }
  62
  63 uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
  64 {
  65     CPU_DoubleU farg;
  66     int isneg;
  67     int ret;
  68
  69     farg.ll = arg;
  70     isneg = float64_is_neg(farg.d);
  71     if (unlikely(float64_is_any_nan(farg.d))) {
  72         if (float64_is_signaling_nan(farg.d)) {
  73             /* Signaling NaN: flags are undefined */
  74             ret = 0x00;
  75         } else {
  76             /* Quiet NaN */
  77             ret = 0x11;
  78         }
  79     } else if (unlikely(float64_is_infinity(farg.d))) {
  80         /* +/- infinity */
  81         if (isneg) {
  82             ret = 0x09;
  83         } else {
  84             ret = 0x05;
  85         }
  86     } else {
  87         if (float64_is_zero(farg.d)) {
  88             /* +/- zero */
  89             if (isneg) {
  90                 ret = 0x12;
  91             } else {
  92                 ret = 0x02;
  93             }
  94         } else {
  95             if (isden(farg.d)) {
  96                 /* Denormalized numbers */
  97                 ret = 0x10;
  98             } else {
  99                 /* Normalized numbers */
 100                 ret = 0x00;
 101             }
 102             if (isneg) {
 103                 ret |= 0x08;
 104             } else {
 105                 ret |= 0x04;
 106             }
 107         }
 108     }
 109     if (set_fprf) {
 110         /* We update FPSCR_FPRF */
 111         env->fpscr &= ~(0x1F << FPSCR_FPRF);
 112         env->fpscr |= ret << FPSCR_FPRF;
 113     }
 114     /* We just need fpcc to update Rc1 */
 115     return ret & 0xF;
 116 }
 117
 118 /* Floating-point invalid operations exception */
 119 static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
 120                                              int set_fpcc)
 121 {
 122     CPUState *cs = CPU(ppc_env_get_cpu(env));
 123     uint64_t ret = 0;
 124     int ve;
 125
 126     ve = fpscr_ve;
 127     switch (op) {
 128     case POWERPC_EXCP_FP_VXSNAN:
 129         env->fpscr |= 1 << FPSCR_VXSNAN;
 130         break;
 131     case POWERPC_EXCP_FP_VXSOFT:
 132         env->fpscr |= 1 << FPSCR_VXSOFT;
 133         break;
 134     case POWERPC_EXCP_FP_VXISI:
 135         /* Magnitude subtraction of infinities */
 136         env->fpscr |= 1 << FPSCR_VXISI;
 137         goto update_arith;
 138     case POWERPC_EXCP_FP_VXIDI:
 139         /* Division of infinity by infinity */
 140         env->fpscr |= 1 << FPSCR_VXIDI;
 141         goto update_arith;
 142     case POWERPC_EXCP_FP_VXZDZ:
 143         /* Division of zero by zero */
 144         env->fpscr |= 1 << FPSCR_VXZDZ;
 145         goto update_arith;
 146     case POWERPC_EXCP_FP_VXIMZ:
 147         /* Multiplication of zero by infinity */
 148         env->fpscr |= 1 << FPSCR_VXIMZ;
 149         goto update_arith;
 150     case POWERPC_EXCP_FP_VXVC:
 151         /* Ordered comparison of NaN */
 152         env->fpscr |= 1 << FPSCR_VXVC;
 153         if (set_fpcc) {
 154             env->fpscr &= ~(0xF << FPSCR_FPCC);
 155             env->fpscr |= 0x11 << FPSCR_FPCC;
 156         }
 157         /* We must update the target FPR before raising the exception */
 158         if (ve != 0) {
 159             cs->exception_index = POWERPC_EXCP_PROGRAM;
 160             env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
 161             /* Update the floating-point enabled exception summary */
 162             env->fpscr |= 1 << FPSCR_FEX;
 163             /* Exception is differed */
 164             ve = 0;
 165         }
 166         break;
 167     case POWERPC_EXCP_FP_VXSQRT:
 168         /* Square root of a negative number */
 169         env->fpscr |= 1 << FPSCR_VXSQRT;
 170     update_arith:
 171         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 172         if (ve == 0) {
 173             /* Set the result to quiet NaN */
 174             ret = 0x7FF8000000000000ULL;
 175             if (set_fpcc) {
 176                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 177                 env->fpscr |= 0x11 << FPSCR_FPCC;
 178             }
 179         }
 180         break;
 181     case POWERPC_EXCP_FP_VXCVI:
 182         /* Invalid conversion */
 183         env->fpscr |= 1 << FPSCR_VXCVI;
 184         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 185         if (ve == 0) {
 186             /* Set the result to quiet NaN */
 187             ret = 0x7FF8000000000000ULL;
 188             if (set_fpcc) {
 189                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 190                 env->fpscr |= 0x11 << FPSCR_FPCC;
 191             }
 192         }
 193         break;
 194     }
 195     /* Update the floating-point invalid operation summary */
 196     env->fpscr |= 1 << FPSCR_VX;
 197     /* Update the floating-point exception summary */
 198     env->fpscr |= 1 << FPSCR_FX;
 199     if (ve != 0) {
 200         /* Update the floating-point enabled exception summary */
 201         env->fpscr |= 1 << FPSCR_FEX;
 202         if (msr_fe0 != 0 || msr_fe1 != 0) {
 203             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 204                                        POWERPC_EXCP_FP | op);
 205         }
 206     }
 207     return ret;
 208 }
 209
 210 static inline void float_zero_divide_excp(CPUPPCState *env)
 211 {
 212     env->fpscr |= 1 << FPSCR_ZX;
 213     env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 214     /* Update the floating-point exception summary */
 215     env->fpscr |= 1 << FPSCR_FX;
 216     if (fpscr_ze != 0) {
 217         /* Update the floating-point enabled exception summary */
 218         env->fpscr |= 1 << FPSCR_FEX;
 219         if (msr_fe0 != 0 || msr_fe1 != 0) {
 220             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 221                                        POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
 222         }
 223     }
 224 }
 225
 226 static inline void float_overflow_excp(CPUPPCState *env)
 227 {
 228     CPUState *cs = CPU(ppc_env_get_cpu(env));
 229
 230     env->fpscr |= 1 << FPSCR_OX;
 231     /* Update the floating-point exception summary */
 232     env->fpscr |= 1 << FPSCR_FX;
 233     if (fpscr_oe != 0) {
 234         /* XXX: should adjust the result */
 235         /* Update the floating-point enabled exception summary */
 236         env->fpscr |= 1 << FPSCR_FEX;
 237         /* We must update the target FPR before raising the exception */
 238         cs->exception_index = POWERPC_EXCP_PROGRAM;
 239         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 240     } else {
 241         env->fpscr |= 1 << FPSCR_XX;
 242         env->fpscr |= 1 << FPSCR_FI;
 243     }
 244 }
 245
 246 static inline void float_underflow_excp(CPUPPCState *env)
 247 {
 248     CPUState *cs = CPU(ppc_env_get_cpu(env));
 249
 250     env->fpscr |= 1 << FPSCR_UX;
 251     /* Update the floating-point exception summary */
 252     env->fpscr |= 1 << FPSCR_FX;
 253     if (fpscr_ue != 0) {
 254         /* XXX: should adjust the result */
 255         /* Update the floating-point enabled exception summary */
 256         env->fpscr |= 1 << FPSCR_FEX;
 257         /* We must update the target FPR before raising the exception */
 258         cs->exception_index = POWERPC_EXCP_PROGRAM;
 259         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 260     }
 261 }
 262
 263 static inline void float_inexact_excp(CPUPPCState *env)
 264 {
 265     CPUState *cs = CPU(ppc_env_get_cpu(env));
 266
 267     env->fpscr |= 1 << FPSCR_XX;
 268     /* Update the floating-point exception summary */
 269     env->fpscr |= 1 << FPSCR_FX;
 270     if (fpscr_xe != 0) {
 271         /* Update the floating-point enabled exception summary */
 272         env->fpscr |= 1 << FPSCR_FEX;
 273         /* We must update the target FPR before raising the exception */
 274         cs->exception_index = POWERPC_EXCP_PROGRAM;
 275         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 276     }
 277 }
 278
 279 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
 280 {
 281     int rnd_type;
 282
 283     /* Set rounding mode */
 284     switch (fpscr_rn) {
 285     case 0:
 286         /* Best approximation (round to nearest) */
 287         rnd_type = float_round_nearest_even;
 288         break;
 289     case 1:
 290         /* Smaller magnitude (round toward zero) */
 291         rnd_type = float_round_to_zero;
 292         break;
 293     case 2:
 294         /* Round toward +infinite */
 295         rnd_type = float_round_up;
 296         break;
 297     default:
 298     case 3:
 299         /* Round toward -infinite */
 300         rnd_type = float_round_down;
 301         break;
 302     }
 303     set_float_rounding_mode(rnd_type, &env->fp_status);
 304 }
 305
 306 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
 307 {
 308     int prev;
 309
 310     prev = (env->fpscr >> bit) & 1;
 311     env->fpscr &= ~(1 << bit);
 312     if (prev == 1) {
 313         switch (bit) {
 314         case FPSCR_RN1:
 315         case FPSCR_RN:
 316             fpscr_set_rounding_mode(env);
 317             break;
 318         default:
 319             break;
 320         }
 321     }
 322 }
 323
 324 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 325 {
 326     CPUState *cs = CPU(ppc_env_get_cpu(env));
 327     int prev;
 328
 329     prev = (env->fpscr >> bit) & 1;
 330     env->fpscr |= 1 << bit;
 331     if (prev == 0) {
 332         switch (bit) {
 333         case FPSCR_VX:
 334             env->fpscr |= 1 << FPSCR_FX;
 335             if (fpscr_ve) {
 336                 goto raise_ve;
 337             }
 338             break;
 339         case FPSCR_OX:
 340             env->fpscr |= 1 << FPSCR_FX;
 341             if (fpscr_oe) {
 342                 goto raise_oe;
 343             }
 344             break;
 345         case FPSCR_UX:
 346             env->fpscr |= 1 << FPSCR_FX;
 347             if (fpscr_ue) {
 348                 goto raise_ue;
 349             }
 350             break;
 351         case FPSCR_ZX:
 352             env->fpscr |= 1 << FPSCR_FX;
 353             if (fpscr_ze) {
 354                 goto raise_ze;
 355             }
 356             break;
 357         case FPSCR_XX:
 358             env->fpscr |= 1 << FPSCR_FX;
 359             if (fpscr_xe) {
 360                 goto raise_xe;
 361             }
 362             break;
 363         case FPSCR_VXSNAN:
 364         case FPSCR_VXISI:
 365         case FPSCR_VXIDI:
 366         case FPSCR_VXZDZ:
 367         case FPSCR_VXIMZ:
 368         case FPSCR_VXVC:
 369         case FPSCR_VXSOFT:
 370         case FPSCR_VXSQRT:
 371         case FPSCR_VXCVI:
 372             env->fpscr |= 1 << FPSCR_VX;
 373             env->fpscr |= 1 << FPSCR_FX;
 374             if (fpscr_ve != 0) {
 375                 goto raise_ve;
 376             }
 377             break;
 378         case FPSCR_VE:
 379             if (fpscr_vx != 0) {
 380             raise_ve:
 381                 env->error_code = POWERPC_EXCP_FP;
 382                 if (fpscr_vxsnan) {
 383                     env->error_code |= POWERPC_EXCP_FP_VXSNAN;
 384                 }
 385                 if (fpscr_vxisi) {
 386                     env->error_code |= POWERPC_EXCP_FP_VXISI;
 387                 }
 388                 if (fpscr_vxidi) {
 389                     env->error_code |= POWERPC_EXCP_FP_VXIDI;
 390                 }
 391                 if (fpscr_vxzdz) {
 392                     env->error_code |= POWERPC_EXCP_FP_VXZDZ;
 393                 }
 394                 if (fpscr_vximz) {
 395                     env->error_code |= POWERPC_EXCP_FP_VXIMZ;
 396                 }
 397                 if (fpscr_vxvc) {
 398                     env->error_code |= POWERPC_EXCP_FP_VXVC;
 399                 }
 400                 if (fpscr_vxsoft) {
 401                     env->error_code |= POWERPC_EXCP_FP_VXSOFT;
 402                 }
 403                 if (fpscr_vxsqrt) {
 404                     env->error_code |= POWERPC_EXCP_FP_VXSQRT;
 405                 }
 406                 if (fpscr_vxcvi) {
 407                     env->error_code |= POWERPC_EXCP_FP_VXCVI;
 408                 }
 409                 goto raise_excp;
 410             }
 411             break;
 412         case FPSCR_OE:
 413             if (fpscr_ox != 0) {
 414             raise_oe:
 415                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 416                 goto raise_excp;
 417             }
 418             break;
 419         case FPSCR_UE:
 420             if (fpscr_ux != 0) {
 421             raise_ue:
 422                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 423                 goto raise_excp;
 424             }
 425             break;
 426         case FPSCR_ZE:
 427             if (fpscr_zx != 0) {
 428             raise_ze:
 429                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
 430                 goto raise_excp;
 431             }
 432             break;
 433         case FPSCR_XE:
 434             if (fpscr_xx != 0) {
 435             raise_xe:
 436                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 437                 goto raise_excp;
 438             }
 439             break;
 440         case FPSCR_RN1:
 441         case FPSCR_RN:
 442             fpscr_set_rounding_mode(env);
 443             break;
 444         default:
 445             break;
 446         raise_excp:
 447             /* Update the floating-point enabled exception summary */
 448             env->fpscr |= 1 << FPSCR_FEX;
 449             /* We have to update Rc1 before raising the exception */
 450             cs->exception_index = POWERPC_EXCP_PROGRAM;
 451             break;
 452         }
 453     }
 454 }
 455
 456 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 457 {
 458     CPUState *cs = CPU(ppc_env_get_cpu(env));
 459     target_ulong prev, new;
 460     int i;
 461
 462     prev = env->fpscr;
 463     new = (target_ulong)arg;
 464     new &= ~0x60000000LL;
 465     new |= prev & 0x60000000LL;
 466     for (i = 0; i < sizeof(target_ulong) * 2; i++) {
 467         if (mask & (1 << i)) {
 468             env->fpscr &= ~(0xFLL << (4 * i));
 469             env->fpscr |= new & (0xFLL << (4 * i));
 470         }
 471     }
 472     /* Update VX and FEX */
 473     if (fpscr_ix != 0) {
 474         env->fpscr |= 1 << FPSCR_VX;
 475     } else {
 476         env->fpscr &= ~(1 << FPSCR_VX);
 477     }
 478     if ((fpscr_ex & fpscr_eex) != 0) {
 479         env->fpscr |= 1 << FPSCR_FEX;
 480         cs->exception_index = POWERPC_EXCP_PROGRAM;
 481         /* XXX: we should compute it properly */
 482         env->error_code = POWERPC_EXCP_FP;
 483     } else {
 484         env->fpscr &= ~(1 << FPSCR_FEX);
 485     }
 486     fpscr_set_rounding_mode(env);
 487 }
 488
 489 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 490 {
 491     helper_store_fpscr(env, arg, mask);
 492 }
 493
 494 void helper_float_check_status(CPUPPCState *env)
 495 {
 496     CPUState *cs = CPU(ppc_env_get_cpu(env));
 497     int status = get_float_exception_flags(&env->fp_status);
 498
 499     if (status & float_flag_divbyzero) {
 500         float_zero_divide_excp(env);
 501     } else if (status & float_flag_overflow) {
 502         float_overflow_excp(env);
 503     } else if (status & float_flag_underflow) {
 504         float_underflow_excp(env);
 505     } else if (status & float_flag_inexact) {
 506         float_inexact_excp(env);
 507     }
 508
 509     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
 510         (env->error_code & POWERPC_EXCP_FP)) {
 511         /* Differred floating-point exception after target FPR update */
 512         if (msr_fe0 != 0 || msr_fe1 != 0) {
 513             helper_raise_exception_err(env, cs->exception_index,
 514                                        env->error_code);
 515         }
 516     }
 517 }
 518
 519 void helper_reset_fpstatus(CPUPPCState *env)
 520 {
 521     set_float_exception_flags(0, &env->fp_status);
 522 }
 523
 524 /* fadd - fadd. */
 525 uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 526 {
 527     CPU_DoubleU farg1, farg2;
 528
 529     farg1.ll = arg1;
 530     farg2.ll = arg2;
 531
 532     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 533                  float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
 534         /* Magnitude subtraction of infinities */
 535         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 536     } else {
 537         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 538                      float64_is_signaling_nan(farg2.d))) {
 539             /* sNaN addition */
 540             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 541         }
 542         farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
 543     }
 544
 545     return farg1.ll;
 546 }
 547
 548 /* fsub - fsub. */
 549 uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 550 {
 551     CPU_DoubleU farg1, farg2;
 552
 553     farg1.ll = arg1;
 554     farg2.ll = arg2;
 555
 556     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 557                  float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
 558         /* Magnitude subtraction of infinities */
 559         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 560     } else {
 561         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 562                      float64_is_signaling_nan(farg2.d))) {
 563             /* sNaN subtraction */
 564             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 565         }
 566         farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
 567     }
 568
 569     return farg1.ll;
 570 }
 571
 572 /* fmul - fmul. */
 573 uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 574 {
 575     CPU_DoubleU farg1, farg2;
 576
 577     farg1.ll = arg1;
 578     farg2.ll = arg2;
 579
 580     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 581                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 582         /* Multiplication of zero by infinity */
 583         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 584     } else {
 585         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 586                      float64_is_signaling_nan(farg2.d))) {
 587             /* sNaN multiplication */
 588             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 589         }
 590         farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
 591     }
 592
 593     return farg1.ll;
 594 }
 595
 596 /* fdiv - fdiv. */
 597 uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 598 {
 599     CPU_DoubleU farg1, farg2;
 600
 601     farg1.ll = arg1;
 602     farg2.ll = arg2;
 603
 604     if (unlikely(float64_is_infinity(farg1.d) &&
 605                  float64_is_infinity(farg2.d))) {
 606         /* Division of infinity by infinity */
 607         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
 608     } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
 609         /* Division of zero by zero */
 610         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
 611     } else {
 612         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 613                      float64_is_signaling_nan(farg2.d))) {
 614             /* sNaN division */
 615             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 616         }
 617         farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
 618     }
 619
 620     return farg1.ll;
 621 }
 622
 623
 624 #define FPU_FCTI(op, cvt, nanval)                                      \
 625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)                   \
 626 {                                                                      \
 627     CPU_DoubleU farg;                                                  \
 628                                                                        \
 629     farg.ll = arg;                                                     \
 630     farg.ll = float64_to_##cvt(farg.d, &env->fp_status);               \
 631                                                                        \
 632     if (unlikely(env->fp_status.float_exception_flags)) {              \
 633         if (float64_is_any_nan(arg)) {                                 \
 634             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 635             if (float64_is_signaling_nan(arg)) {                       \
 636                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
 637             }                                                          \
 638             farg.ll = nanval;                                          \
 639         } else if (env->fp_status.float_exception_flags &              \
 640                    float_flag_invalid) {                               \
 641             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 642         }                                                              \
 643         helper_float_check_status(env);                                \
 644     }                                                                  \
 645     return farg.ll;                                                    \
 646  }
 647
 648 FPU_FCTI(fctiw, int32, 0x80000000U)
 649 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
 650 FPU_FCTI(fctiwu, uint32, 0x00000000U)
 651 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
 652 #if defined(TARGET_PPC64)
 653 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
 654 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
 655 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
 656 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
 657 #endif
 658
 659 #if defined(TARGET_PPC64)
 660
 661 #define FPU_FCFI(op, cvtr, is_single)                      \
 662 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
 663 {                                                          \
 664     CPU_DoubleU farg;                                      \
 665                                                            \
 666     if (is_single) {                                       \
 667         float32 tmp = cvtr(arg, &env->fp_status);          \
 668         farg.d = float32_to_float64(tmp, &env->fp_status); \
 669     } else {                                               \
 670         farg.d = cvtr(arg, &env->fp_status);               \
 671     }                                                      \
 672     helper_float_check_status(env);                        \
 673     return farg.ll;                                        \
 674 }
 675
 676 FPU_FCFI(fcfid, int64_to_float64, 0)
 677 FPU_FCFI(fcfids, int64_to_float32, 1)
 678 FPU_FCFI(fcfidu, uint64_to_float64, 0)
 679 FPU_FCFI(fcfidus, uint64_to_float32, 1)
 680
 681 #endif
 682
 683 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
 684                               int rounding_mode)
 685 {
 686     CPU_DoubleU farg;
 687
 688     farg.ll = arg;
 689
 690     if (unlikely(float64_is_signaling_nan(farg.d))) {
 691         /* sNaN round */
 692         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 693         farg.ll = arg | 0x0008000000000000ULL;
 694     } else {
 695         int inexact = get_float_exception_flags(&env->fp_status) &
 696                       float_flag_inexact;
 697         set_float_rounding_mode(rounding_mode, &env->fp_status);
 698         farg.ll = float64_round_to_int(farg.d, &env->fp_status);
 699         /* Restore rounding mode from FPSCR */
 700         fpscr_set_rounding_mode(env);
 701
 702         /* fri* does not set FPSCR[XX] */
 703         if (!inexact) {
 704             env->fp_status.float_exception_flags &= ~float_flag_inexact;
 705         }
 706     }
 707     helper_float_check_status(env);
 708     return farg.ll;
 709 }
 710
 711 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
 712 {
 713     return do_fri(env, arg, float_round_ties_away);
 714 }
 715
 716 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
 717 {
 718     return do_fri(env, arg, float_round_to_zero);
 719 }
 720
 721 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
 722 {
 723     return do_fri(env, arg, float_round_up);
 724 }
 725
 726 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
 727 {
 728     return do_fri(env, arg, float_round_down);
 729 }
 730
 731 /* fmadd - fmadd. */
 732 uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 733                       uint64_t arg3)
 734 {
 735     CPU_DoubleU farg1, farg2, farg3;
 736
 737     farg1.ll = arg1;
 738     farg2.ll = arg2;
 739     farg3.ll = arg3;
 740
 741     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 742                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 743         /* Multiplication of zero by infinity */
 744         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 745     } else {
 746         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 747                      float64_is_signaling_nan(farg2.d) ||
 748                      float64_is_signaling_nan(farg3.d))) {
 749             /* sNaN operation */
 750             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 751         }
 752         /* This is the way the PowerPC specification defines it */
 753         float128 ft0_128, ft1_128;
 754
 755         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 756         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 757         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 758         if (unlikely(float128_is_infinity(ft0_128) &&
 759                      float64_is_infinity(farg3.d) &&
 760                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 761             /* Magnitude subtraction of infinities */
 762             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 763         } else {
 764             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 765             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 766             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 767         }
 768     }
 769
 770     return farg1.ll;
 771 }
 772
 773 /* fmsub - fmsub. */
 774 uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 775                       uint64_t arg3)
 776 {
 777     CPU_DoubleU farg1, farg2, farg3;
 778
 779     farg1.ll = arg1;
 780     farg2.ll = arg2;
 781     farg3.ll = arg3;
 782
 783     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 784                  (float64_is_zero(farg1.d) &&
 785                   float64_is_infinity(farg2.d)))) {
 786         /* Multiplication of zero by infinity */
 787         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 788     } else {
 789         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 790                      float64_is_signaling_nan(farg2.d) ||
 791                      float64_is_signaling_nan(farg3.d))) {
 792             /* sNaN operation */
 793             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 794         }
 795         /* This is the way the PowerPC specification defines it */
 796         float128 ft0_128, ft1_128;
 797
 798         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 799         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 800         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 801         if (unlikely(float128_is_infinity(ft0_128) &&
 802                      float64_is_infinity(farg3.d) &&
 803                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 804             /* Magnitude subtraction of infinities */
 805             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 806         } else {
 807             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 808             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 809             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 810         }
 811     }
 812     return farg1.ll;
 813 }
 814
 815 /* fnmadd - fnmadd. */
 816 uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 817                        uint64_t arg3)
 818 {
 819     CPU_DoubleU farg1, farg2, farg3;
 820
 821     farg1.ll = arg1;
 822     farg2.ll = arg2;
 823     farg3.ll = arg3;
 824
 825     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 826                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 827         /* Multiplication of zero by infinity */
 828         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 829     } else {
 830         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 831                      float64_is_signaling_nan(farg2.d) ||
 832                      float64_is_signaling_nan(farg3.d))) {
 833             /* sNaN operation */
 834             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 835         }
 836         /* This is the way the PowerPC specification defines it */
 837         float128 ft0_128, ft1_128;
 838
 839         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 840         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 841         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 842         if (unlikely(float128_is_infinity(ft0_128) &&
 843                      float64_is_infinity(farg3.d) &&
 844                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 845             /* Magnitude subtraction of infinities */
 846             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 847         } else {
 848             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 849             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 850             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 851         }
 852         if (likely(!float64_is_any_nan(farg1.d))) {
 853             farg1.d = float64_chs(farg1.d);
 854         }
 855     }
 856     return farg1.ll;
 857 }
 858
 859 /* fnmsub - fnmsub. */
 860 uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 861                        uint64_t arg3)
 862 {
 863     CPU_DoubleU farg1, farg2, farg3;
 864
 865     farg1.ll = arg1;
 866     farg2.ll = arg2;
 867     farg3.ll = arg3;
 868
 869     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 870                  (float64_is_zero(farg1.d) &&
 871                   float64_is_infinity(farg2.d)))) {
 872         /* Multiplication of zero by infinity */
 873         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 874     } else {
 875         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 876                      float64_is_signaling_nan(farg2.d) ||
 877                      float64_is_signaling_nan(farg3.d))) {
 878             /* sNaN operation */
 879             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 880         }
 881         /* This is the way the PowerPC specification defines it */
 882         float128 ft0_128, ft1_128;
 883
 884         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 885         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 886         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 887         if (unlikely(float128_is_infinity(ft0_128) &&
 888                      float64_is_infinity(farg3.d) &&
 889                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 890             /* Magnitude subtraction of infinities */
 891             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 892         } else {
 893             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 894             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 895             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 896         }
 897         if (likely(!float64_is_any_nan(farg1.d))) {
 898             farg1.d = float64_chs(farg1.d);
 899         }
 900     }
 901     return farg1.ll;
 902 }
 903
 904 /* frsp - frsp. */
 905 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
 906 {
 907     CPU_DoubleU farg;
 908     float32 f32;
 909
 910     farg.ll = arg;
 911
 912     if (unlikely(float64_is_signaling_nan(farg.d))) {
 913         /* sNaN square root */
 914         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 915     }
 916     f32 = float64_to_float32(farg.d, &env->fp_status);
 917     farg.d = float32_to_float64(f32, &env->fp_status);
 918
 919     return farg.ll;
 920 }
 921
 922 /* fsqrt - fsqrt. */
 923 uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
 924 {
 925     CPU_DoubleU farg;
 926
 927     farg.ll = arg;
 928
 929     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 930         /* Square root of a negative nonzero number */
 931         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 932     } else {
 933         if (unlikely(float64_is_signaling_nan(farg.d))) {
 934             /* sNaN square root */
 935             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 936         }
 937         farg.d = float64_sqrt(farg.d, &env->fp_status);
 938     }
 939     return farg.ll;
 940 }
 941
 942 /* fre - fre. */
 943 uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
 944 {
 945     CPU_DoubleU farg;
 946
 947     farg.ll = arg;
 948
 949     if (unlikely(float64_is_signaling_nan(farg.d))) {
 950         /* sNaN reciprocal */
 951         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 952     }
 953     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 954     return farg.d;
 955 }
 956
 957 /* fres - fres. */
 958 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
 959 {
 960     CPU_DoubleU farg;
 961     float32 f32;
 962
 963     farg.ll = arg;
 964
 965     if (unlikely(float64_is_signaling_nan(farg.d))) {
 966         /* sNaN reciprocal */
 967         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 968     }
 969     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 970     f32 = float64_to_float32(farg.d, &env->fp_status);
 971     farg.d = float32_to_float64(f32, &env->fp_status);
 972
 973     return farg.ll;
 974 }
 975
 976 /* frsqrte  - frsqrte. */
 977 uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
 978 {
 979     CPU_DoubleU farg;
 980
 981     farg.ll = arg;
 982
 983     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 984         /* Reciprocal square root of a negative nonzero number */
 985         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 986     } else {
 987         if (unlikely(float64_is_signaling_nan(farg.d))) {
 988             /* sNaN reciprocal square root */
 989             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 990         }
 991         farg.d = float64_sqrt(farg.d, &env->fp_status);
 992         farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 993     }
 994     return farg.ll;
 995 }
 996
 997 /* fsel - fsel. */
 998 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 999                      uint64_t arg3)
1000 {
1001     CPU_DoubleU farg1;
1002
1003     farg1.ll = arg1;
1004
1005     if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1006         !float64_is_any_nan(farg1.d)) {
1007         return arg2;
1008     } else {
1009         return arg3;
1010     }
1011 }
1012
1013 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1014 {
1015     int fe_flag = 0;
1016     int fg_flag = 0;
1017
1018     if (unlikely(float64_is_infinity(fra) ||
1019                  float64_is_infinity(frb) ||
1020                  float64_is_zero(frb))) {
1021         fe_flag = 1;
1022         fg_flag = 1;
1023     } else {
1024         int e_a = ppc_float64_get_unbiased_exp(fra);
1025         int e_b = ppc_float64_get_unbiased_exp(frb);
1026
1027         if (unlikely(float64_is_any_nan(fra) ||
1028                      float64_is_any_nan(frb))) {
1029             fe_flag = 1;
1030         } else if ((e_b <= -1022) || (e_b >= 1021)) {
1031             fe_flag = 1;
1032         } else if (!float64_is_zero(fra) &&
1033                    (((e_a - e_b) >= 1023) ||
1034                     ((e_a - e_b) <= -1021) ||
1035                     (e_a <= -970))) {
1036             fe_flag = 1;
1037         }
1038
1039         if (unlikely(float64_is_zero_or_denormal(frb))) {
1040             /* XB is not zero because of the above check and */
1041             /* so must be denormalized.                      */
1042             fg_flag = 1;
1043         }
1044     }
1045
1046     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1047 }
1048
1049 uint32_t helper_ftsqrt(uint64_t frb)
1050 {
1051     int fe_flag = 0;
1052     int fg_flag = 0;
1053
1054     if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1055         fe_flag = 1;
1056         fg_flag = 1;
1057     } else {
1058         int e_b = ppc_float64_get_unbiased_exp(frb);
1059
1060         if (unlikely(float64_is_any_nan(frb))) {
1061             fe_flag = 1;
1062         } else if (unlikely(float64_is_zero(frb))) {
1063             fe_flag = 1;
1064         } else if (unlikely(float64_is_neg(frb))) {
1065             fe_flag = 1;
1066         } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
1067             fe_flag = 1;
1068         }
1069
1070         if (unlikely(float64_is_zero_or_denormal(frb))) {
1071             /* XB is not zero because of the above check and */
1072             /* therefore must be denormalized.               */
1073             fg_flag = 1;
1074         }
1075     }
1076
1077     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1078 }
1079
1080 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1081                   uint32_t crfD)
1082 {
1083     CPU_DoubleU farg1, farg2;
1084     uint32_t ret = 0;
1085
1086     farg1.ll = arg1;
1087     farg2.ll = arg2;
1088
1089     if (unlikely(float64_is_any_nan(farg1.d) ||
1090                  float64_is_any_nan(farg2.d))) {
1091         ret = 0x01UL;
1092     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1093         ret = 0x08UL;
1094     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1095         ret = 0x04UL;
1096     } else {
1097         ret = 0x02UL;
1098     }
1099
1100     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1101     env->fpscr |= ret << FPSCR_FPRF;
1102     env->crf[crfD] = ret;
1103     if (unlikely(ret == 0x01UL
1104                  && (float64_is_signaling_nan(farg1.d) ||
1105                      float64_is_signaling_nan(farg2.d)))) {
1106         /* sNaN comparison */
1107         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1108     }
1109 }
1110
1111 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1112                   uint32_t crfD)
1113 {
1114     CPU_DoubleU farg1, farg2;
1115     uint32_t ret = 0;
1116
1117     farg1.ll = arg1;
1118     farg2.ll = arg2;
1119
1120     if (unlikely(float64_is_any_nan(farg1.d) ||
1121                  float64_is_any_nan(farg2.d))) {
1122         ret = 0x01UL;
1123     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1124         ret = 0x08UL;
1125     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1126         ret = 0x04UL;
1127     } else {
1128         ret = 0x02UL;
1129     }
1130
1131     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1132     env->fpscr |= ret << FPSCR_FPRF;
1133     env->crf[crfD] = ret;
1134     if (unlikely(ret == 0x01UL)) {
1135         if (float64_is_signaling_nan(farg1.d) ||
1136             float64_is_signaling_nan(farg2.d)) {
1137             /* sNaN comparison */
1138             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
1139                                   POWERPC_EXCP_FP_VXVC, 1);
1140         } else {
1141             /* qNaN comparison */
1142             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1);
1143         }
1144     }
1145 }
1146
1147 /* Single-precision floating-point conversions */
1148 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1149 {
1150     CPU_FloatU u;
1151
1152     u.f = int32_to_float32(val, &env->vec_status);
1153
1154     return u.l;
1155 }
1156
1157 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1158 {
1159     CPU_FloatU u;
1160
1161     u.f = uint32_to_float32(val, &env->vec_status);
1162
1163     return u.l;
1164 }
1165
1166 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1167 {
1168     CPU_FloatU u;
1169
1170     u.l = val;
1171     /* NaN are not treated the same way IEEE 754 does */
1172     if (unlikely(float32_is_quiet_nan(u.f))) {
1173         return 0;
1174     }
1175
1176     return float32_to_int32(u.f, &env->vec_status);
1177 }
1178
1179 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1180 {
1181     CPU_FloatU u;
1182
1183     u.l = val;
1184     /* NaN are not treated the same way IEEE 754 does */
1185     if (unlikely(float32_is_quiet_nan(u.f))) {
1186         return 0;
1187     }
1188
1189     return float32_to_uint32(u.f, &env->vec_status);
1190 }
1191
1192 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1193 {
1194     CPU_FloatU u;
1195
1196     u.l = val;
1197     /* NaN are not treated the same way IEEE 754 does */
1198     if (unlikely(float32_is_quiet_nan(u.f))) {
1199         return 0;
1200     }
1201
1202     return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1203 }
1204
1205 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1206 {
1207     CPU_FloatU u;
1208
1209     u.l = val;
1210     /* NaN are not treated the same way IEEE 754 does */
1211     if (unlikely(float32_is_quiet_nan(u.f))) {
1212         return 0;
1213     }
1214
1215     return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1216 }
1217
1218 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1219 {
1220     CPU_FloatU u;
1221     float32 tmp;
1222
1223     u.f = int32_to_float32(val, &env->vec_status);
1224     tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1225     u.f = float32_div(u.f, tmp, &env->vec_status);
1226
1227     return u.l;
1228 }
1229
1230 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1231 {
1232     CPU_FloatU u;
1233     float32 tmp;
1234
1235     u.f = uint32_to_float32(val, &env->vec_status);
1236     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1237     u.f = float32_div(u.f, tmp, &env->vec_status);
1238
1239     return u.l;
1240 }
1241
1242 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1243 {
1244     CPU_FloatU u;
1245     float32 tmp;
1246
1247     u.l = val;
1248     /* NaN are not treated the same way IEEE 754 does */
1249     if (unlikely(float32_is_quiet_nan(u.f))) {
1250         return 0;
1251     }
1252     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1253     u.f = float32_mul(u.f, tmp, &env->vec_status);
1254
1255     return float32_to_int32(u.f, &env->vec_status);
1256 }
1257
1258 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1259 {
1260     CPU_FloatU u;
1261     float32 tmp;
1262
1263     u.l = val;
1264     /* NaN are not treated the same way IEEE 754 does */
1265     if (unlikely(float32_is_quiet_nan(u.f))) {
1266         return 0;
1267     }
1268     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1269     u.f = float32_mul(u.f, tmp, &env->vec_status);
1270
1271     return float32_to_uint32(u.f, &env->vec_status);
1272 }
1273
1274 #define HELPER_SPE_SINGLE_CONV(name)                              \
1275     uint32_t helper_e##name(CPUPPCState *env, uint32_t val)       \
1276     {                                                             \
1277         return e##name(env, val);                                 \
1278     }
1279 /* efscfsi */
1280 HELPER_SPE_SINGLE_CONV(fscfsi);
1281 /* efscfui */
1282 HELPER_SPE_SINGLE_CONV(fscfui);
1283 /* efscfuf */
1284 HELPER_SPE_SINGLE_CONV(fscfuf);
1285 /* efscfsf */
1286 HELPER_SPE_SINGLE_CONV(fscfsf);
1287 /* efsctsi */
1288 HELPER_SPE_SINGLE_CONV(fsctsi);
1289 /* efsctui */
1290 HELPER_SPE_SINGLE_CONV(fsctui);
1291 /* efsctsiz */
1292 HELPER_SPE_SINGLE_CONV(fsctsiz);
1293 /* efsctuiz */
1294 HELPER_SPE_SINGLE_CONV(fsctuiz);
1295 /* efsctsf */
1296 HELPER_SPE_SINGLE_CONV(fsctsf);
1297 /* efsctuf */
1298 HELPER_SPE_SINGLE_CONV(fsctuf);
1299
1300 #define HELPER_SPE_VECTOR_CONV(name)                            \
1301     uint64_t helper_ev##name(CPUPPCState *env, uint64_t val)    \
1302     {                                                           \
1303         return ((uint64_t)e##name(env, val >> 32) << 32) |      \
1304             (uint64_t)e##name(env, val);                        \
1305     }
1306 /* evfscfsi */
1307 HELPER_SPE_VECTOR_CONV(fscfsi);
1308 /* evfscfui */
1309 HELPER_SPE_VECTOR_CONV(fscfui);
1310 /* evfscfuf */
1311 HELPER_SPE_VECTOR_CONV(fscfuf);
1312 /* evfscfsf */
1313 HELPER_SPE_VECTOR_CONV(fscfsf);
1314 /* evfsctsi */
1315 HELPER_SPE_VECTOR_CONV(fsctsi);
1316 /* evfsctui */
1317 HELPER_SPE_VECTOR_CONV(fsctui);
1318 /* evfsctsiz */
1319 HELPER_SPE_VECTOR_CONV(fsctsiz);
1320 /* evfsctuiz */
1321 HELPER_SPE_VECTOR_CONV(fsctuiz);
1322 /* evfsctsf */
1323 HELPER_SPE_VECTOR_CONV(fsctsf);
1324 /* evfsctuf */
1325 HELPER_SPE_VECTOR_CONV(fsctuf);
1326
1327 /* Single-precision floating-point arithmetic */
1328 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1329 {
1330     CPU_FloatU u1, u2;
1331
1332     u1.l = op1;
1333     u2.l = op2;
1334     u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1335     return u1.l;
1336 }
1337
1338 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1339 {
1340     CPU_FloatU u1, u2;
1341
1342     u1.l = op1;
1343     u2.l = op2;
1344     u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1345     return u1.l;
1346 }
1347
1348 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1349 {
1350     CPU_FloatU u1, u2;
1351
1352     u1.l = op1;
1353     u2.l = op2;
1354     u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1355     return u1.l;
1356 }
1357
1358 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1359 {
1360     CPU_FloatU u1, u2;
1361
1362     u1.l = op1;
1363     u2.l = op2;
1364     u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1365     return u1.l;
1366 }
1367
1368 #define HELPER_SPE_SINGLE_ARITH(name)                                   \
1369     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1370     {                                                                   \
1371         return e##name(env, op1, op2);                                  \
1372     }
1373 /* efsadd */
1374 HELPER_SPE_SINGLE_ARITH(fsadd);
1375 /* efssub */
1376 HELPER_SPE_SINGLE_ARITH(fssub);
1377 /* efsmul */
1378 HELPER_SPE_SINGLE_ARITH(fsmul);
1379 /* efsdiv */
1380 HELPER_SPE_SINGLE_ARITH(fsdiv);
1381
1382 #define HELPER_SPE_VECTOR_ARITH(name)                                   \
1383     uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1384     {                                                                   \
1385         return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) |   \
1386             (uint64_t)e##name(env, op1, op2);                           \
1387     }
1388 /* evfsadd */
1389 HELPER_SPE_VECTOR_ARITH(fsadd);
1390 /* evfssub */
1391 HELPER_SPE_VECTOR_ARITH(fssub);
1392 /* evfsmul */
1393 HELPER_SPE_VECTOR_ARITH(fsmul);
1394 /* evfsdiv */
1395 HELPER_SPE_VECTOR_ARITH(fsdiv);
1396
1397 /* Single-precision floating-point comparisons */
1398 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1399 {
1400     CPU_FloatU u1, u2;
1401
1402     u1.l = op1;
1403     u2.l = op2;
1404     return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1405 }
1406
1407 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1408 {
1409     CPU_FloatU u1, u2;
1410
1411     u1.l = op1;
1412     u2.l = op2;
1413     return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1414 }
1415
1416 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1417 {
1418     CPU_FloatU u1, u2;
1419
1420     u1.l = op1;
1421     u2.l = op2;
1422     return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1423 }
1424
1425 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1426 {
1427     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1428     return efscmplt(env, op1, op2);
1429 }
1430
1431 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1432 {
1433     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1434     return efscmpgt(env, op1, op2);
1435 }
1436
1437 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1438 {
1439     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1440     return efscmpeq(env, op1, op2);
1441 }
1442
1443 #define HELPER_SINGLE_SPE_CMP(name)                                     \
1444     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1445     {                                                                   \
1446         return e##name(env, op1, op2) << 2;                             \
1447     }
1448 /* efststlt */
1449 HELPER_SINGLE_SPE_CMP(fststlt);
1450 /* efststgt */
1451 HELPER_SINGLE_SPE_CMP(fststgt);
1452 /* efststeq */
1453 HELPER_SINGLE_SPE_CMP(fststeq);
1454 /* efscmplt */
1455 HELPER_SINGLE_SPE_CMP(fscmplt);
1456 /* efscmpgt */
1457 HELPER_SINGLE_SPE_CMP(fscmpgt);
1458 /* efscmpeq */
1459 HELPER_SINGLE_SPE_CMP(fscmpeq);
1460
1461 static inline uint32_t evcmp_merge(int t0, int t1)
1462 {
1463     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1464 }
1465
1466 #define HELPER_VECTOR_SPE_CMP(name)                                     \
1467     uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1468     {                                                                   \
1469         return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32),          \
1470                            e##name(env, op1, op2));                     \
1471     }
1472 /* evfststlt */
1473 HELPER_VECTOR_SPE_CMP(fststlt);
1474 /* evfststgt */
1475 HELPER_VECTOR_SPE_CMP(fststgt);
1476 /* evfststeq */
1477 HELPER_VECTOR_SPE_CMP(fststeq);
1478 /* evfscmplt */
1479 HELPER_VECTOR_SPE_CMP(fscmplt);
1480 /* evfscmpgt */
1481 HELPER_VECTOR_SPE_CMP(fscmpgt);
1482 /* evfscmpeq */
1483 HELPER_VECTOR_SPE_CMP(fscmpeq);
1484
1485 /* Double-precision floating-point conversion */
1486 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1487 {
1488     CPU_DoubleU u;
1489
1490     u.d = int32_to_float64(val, &env->vec_status);
1491
1492     return u.ll;
1493 }
1494
1495 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1496 {
1497     CPU_DoubleU u;
1498
1499     u.d = int64_to_float64(val, &env->vec_status);
1500
1501     return u.ll;
1502 }
1503
1504 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1505 {
1506     CPU_DoubleU u;
1507
1508     u.d = uint32_to_float64(val, &env->vec_status);
1509
1510     return u.ll;
1511 }
1512
1513 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1514 {
1515     CPU_DoubleU u;
1516
1517     u.d = uint64_to_float64(val, &env->vec_status);
1518
1519     return u.ll;
1520 }
1521
1522 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1523 {
1524     CPU_DoubleU u;
1525
1526     u.ll = val;
1527     /* NaN are not treated the same way IEEE 754 does */
1528     if (unlikely(float64_is_any_nan(u.d))) {
1529         return 0;
1530     }
1531
1532     return float64_to_int32(u.d, &env->vec_status);
1533 }
1534
1535 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1536 {
1537     CPU_DoubleU u;
1538
1539     u.ll = val;
1540     /* NaN are not treated the same way IEEE 754 does */
1541     if (unlikely(float64_is_any_nan(u.d))) {
1542         return 0;
1543     }
1544
1545     return float64_to_uint32(u.d, &env->vec_status);
1546 }
1547
1548 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1549 {
1550     CPU_DoubleU u;
1551
1552     u.ll = val;
1553     /* NaN are not treated the same way IEEE 754 does */
1554     if (unlikely(float64_is_any_nan(u.d))) {
1555         return 0;
1556     }
1557
1558     return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1559 }
1560
1561 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1562 {
1563     CPU_DoubleU u;
1564
1565     u.ll = val;
1566     /* NaN are not treated the same way IEEE 754 does */
1567     if (unlikely(float64_is_any_nan(u.d))) {
1568         return 0;
1569     }
1570
1571     return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1572 }
1573
1574 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1575 {
1576     CPU_DoubleU u;
1577
1578     u.ll = val;
1579     /* NaN are not treated the same way IEEE 754 does */
1580     if (unlikely(float64_is_any_nan(u.d))) {
1581         return 0;
1582     }
1583
1584     return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1585 }
1586
1587 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1588 {
1589     CPU_DoubleU u;
1590
1591     u.ll = val;
1592     /* NaN are not treated the same way IEEE 754 does */
1593     if (unlikely(float64_is_any_nan(u.d))) {
1594         return 0;
1595     }
1596
1597     return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1598 }
1599
1600 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1601 {
1602     CPU_DoubleU u;
1603     float64 tmp;
1604
1605     u.d = int32_to_float64(val, &env->vec_status);
1606     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1607     u.d = float64_div(u.d, tmp, &env->vec_status);
1608
1609     return u.ll;
1610 }
1611
1612 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1613 {
1614     CPU_DoubleU u;
1615     float64 tmp;
1616
1617     u.d = uint32_to_float64(val, &env->vec_status);
1618     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1619     u.d = float64_div(u.d, tmp, &env->vec_status);
1620
1621     return u.ll;
1622 }
1623
1624 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1625 {
1626     CPU_DoubleU u;
1627     float64 tmp;
1628
1629     u.ll = val;
1630     /* NaN are not treated the same way IEEE 754 does */
1631     if (unlikely(float64_is_any_nan(u.d))) {
1632         return 0;
1633     }
1634     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1635     u.d = float64_mul(u.d, tmp, &env->vec_status);
1636
1637     return float64_to_int32(u.d, &env->vec_status);
1638 }
1639
1640 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1641 {
1642     CPU_DoubleU u;
1643     float64 tmp;
1644
1645     u.ll = val;
1646     /* NaN are not treated the same way IEEE 754 does */
1647     if (unlikely(float64_is_any_nan(u.d))) {
1648         return 0;
1649     }
1650     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1651     u.d = float64_mul(u.d, tmp, &env->vec_status);
1652
1653     return float64_to_uint32(u.d, &env->vec_status);
1654 }
1655
1656 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1657 {
1658     CPU_DoubleU u1;
1659     CPU_FloatU u2;
1660
1661     u1.ll = val;
1662     u2.f = float64_to_float32(u1.d, &env->vec_status);
1663
1664     return u2.l;
1665 }
1666
1667 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1668 {
1669     CPU_DoubleU u2;
1670     CPU_FloatU u1;
1671
1672     u1.l = val;
1673     u2.d = float32_to_float64(u1.f, &env->vec_status);
1674
1675     return u2.ll;
1676 }
1677
1678 /* Double precision fixed-point arithmetic */
1679 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1680 {
1681     CPU_DoubleU u1, u2;
1682
1683     u1.ll = op1;
1684     u2.ll = op2;
1685     u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1686     return u1.ll;
1687 }
1688
1689 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1690 {
1691     CPU_DoubleU u1, u2;
1692
1693     u1.ll = op1;
1694     u2.ll = op2;
1695     u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1696     return u1.ll;
1697 }
1698
1699 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1700 {
1701     CPU_DoubleU u1, u2;
1702
1703     u1.ll = op1;
1704     u2.ll = op2;
1705     u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1706     return u1.ll;
1707 }
1708
1709 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1710 {
1711     CPU_DoubleU u1, u2;
1712
1713     u1.ll = op1;
1714     u2.ll = op2;
1715     u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1716     return u1.ll;
1717 }
1718
1719 /* Double precision floating point helpers */
1720 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1721 {
1722     CPU_DoubleU u1, u2;
1723
1724     u1.ll = op1;
1725     u2.ll = op2;
1726     return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1727 }
1728
1729 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1730 {
1731     CPU_DoubleU u1, u2;
1732
1733     u1.ll = op1;
1734     u2.ll = op2;
1735     return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1736 }
1737
1738 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1739 {
1740     CPU_DoubleU u1, u2;
1741
1742     u1.ll = op1;
1743     u2.ll = op2;
1744     return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1745 }
1746
1747 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1748 {
1749     /* XXX: TODO: test special values (NaN, infinites, ...) */
1750     return helper_efdtstlt(env, op1, op2);
1751 }
1752
1753 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1754 {
1755     /* XXX: TODO: test special values (NaN, infinites, ...) */
1756     return helper_efdtstgt(env, op1, op2);
1757 }
1758
1759 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1760 {
1761     /* XXX: TODO: test special values (NaN, infinites, ...) */
1762     return helper_efdtsteq(env, op1, op2);
1763 }
1764
1765 #define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
1766     (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |    \
1767      (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
1768
1769 #define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
1770 #define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
1771 #define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
1772 #define xC(opcode) DECODE_SPLIT(opcode, 3, 1,  6, 5)
1773 #define BF(opcode) (((opcode) >> (31-8)) & 7)
1774
1775 typedef union _ppc_vsr_t {
1776     uint64_t u64[2];
1777     uint32_t u32[4];
1778     float32 f32[4];
1779     float64 f64[2];
1780 } ppc_vsr_t;
1781
1782 #if defined(HOST_WORDS_BIGENDIAN)
1783 #define VsrW(i) u32[i]
1784 #define VsrD(i) u64[i]
1785 #else
1786 #define VsrW(i) u32[3-(i)]
1787 #define VsrD(i) u64[1-(i)]
1788 #endif
1789
1790 static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1791 {
1792     if (n < 32) {
1793         vsr->VsrD(0) = env->fpr[n];
1794         vsr->VsrD(1) = env->vsr[n];
1795     } else {
1796         vsr->u64[0] = env->avr[n-32].u64[0];
1797         vsr->u64[1] = env->avr[n-32].u64[1];
1798     }
1799 }
1800
1801 static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1802 {
1803     if (n < 32) {
1804         env->fpr[n] = vsr->VsrD(0);
1805         env->vsr[n] = vsr->VsrD(1);
1806     } else {
1807         env->avr[n-32].u64[0] = vsr->u64[0];
1808         env->avr[n-32].u64[1] = vsr->u64[1];
1809     }
1810 }
1811
1812 #define float64_to_float64(x, env) x
1813
1814
1815 /* VSX_ADD_SUB - VSX floating point add/subract
1816  *   name  - instruction mnemonic
1817  *   op    - operation (add or sub)
1818  *   nels  - number of elements (1, 2 or 4)
1819  *   tp    - type (float32 or float64)
1820  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1821  *   sfprf - set FPRF
1822  */
1823 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp)                    \
1824 void helper_##name(CPUPPCState *env, uint32_t opcode)                        \
1825 {                                                                            \
1826     ppc_vsr_t xt, xa, xb;                                                    \
1827     int i;                                                                   \
1828                                                                              \
1829     getVSR(xA(opcode), &xa, env);                                            \
1830     getVSR(xB(opcode), &xb, env);                                            \
1831     getVSR(xT(opcode), &xt, env);                                            \
1832     helper_reset_fpstatus(env);                                              \
1833                                                                              \
1834     for (i = 0; i < nels; i++) {                                             \
1835         float_status tstat = env->fp_status;                                 \
1836         set_float_exception_flags(0, &tstat);                                \
1837         xt.fld = tp##_##op(xa.fld, xb.fld, &tstat);                          \
1838         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1839                                                                              \
1840         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1841             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {      \
1842                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);    \
1843             } else if (tp##_is_signaling_nan(xa.fld) ||                      \
1844                        tp##_is_signaling_nan(xb.fld)) {                      \
1845                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1846             }                                                                \
1847         }                                                                    \
1848                                                                              \
1849         if (r2sp) {                                                          \
1850             xt.fld = helper_frsp(env, xt.fld);                               \
1851         }                                                                    \
1852                                                                              \
1853         if (sfprf) {                                                         \
1854             helper_compute_fprf(env, xt.fld, sfprf);                         \
1855         }                                                                    \
1856     }                                                                        \
1857     putVSR(xT(opcode), &xt, env);                                            \
1858     helper_float_check_status(env);                                          \
1859 }
1860
1861 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1862 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1863 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1864 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1865 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1866 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1867 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1868 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1869
1870 /* VSX_MUL - VSX floating point multiply
1871  *   op    - instruction mnemonic
1872  *   nels  - number of elements (1, 2 or 4)
1873  *   tp    - type (float32 or float64)
1874  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1875  *   sfprf - set FPRF
1876  */
1877 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp)                              \
1878 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
1879 {                                                                            \
1880     ppc_vsr_t xt, xa, xb;                                                    \
1881     int i;                                                                   \
1882                                                                              \
1883     getVSR(xA(opcode), &xa, env);                                            \
1884     getVSR(xB(opcode), &xb, env);                                            \
1885     getVSR(xT(opcode), &xt, env);                                            \
1886     helper_reset_fpstatus(env);                                              \
1887                                                                              \
1888     for (i = 0; i < nels; i++) {                                             \
1889         float_status tstat = env->fp_status;                                 \
1890         set_float_exception_flags(0, &tstat);                                \
1891         xt.fld = tp##_mul(xa.fld, xb.fld, &tstat);                           \
1892         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1893                                                                              \
1894         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1895             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) ||        \
1896                 (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) {        \
1897                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf);    \
1898             } else if (tp##_is_signaling_nan(xa.fld) ||                      \
1899                        tp##_is_signaling_nan(xb.fld)) {                      \
1900                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1901             }                                                                \
1902         }                                                                    \
1903                                                                              \
1904         if (r2sp) {                                                          \
1905             xt.fld = helper_frsp(env, xt.fld);                               \
1906         }                                                                    \
1907                                                                              \
1908         if (sfprf) {                                                         \
1909             helper_compute_fprf(env, xt.fld, sfprf);                         \
1910         }                                                                    \
1911     }                                                                        \
1912                                                                              \
1913     putVSR(xT(opcode), &xt, env);                                            \
1914     helper_float_check_status(env);                                          \
1915 }
1916
1917 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1918 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1919 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1920 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1921
1922 /* VSX_DIV - VSX floating point divide
1923  *   op    - instruction mnemonic
1924  *   nels  - number of elements (1, 2 or 4)
1925  *   tp    - type (float32 or float64)
1926  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1927  *   sfprf - set FPRF
1928  */
1929 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp)                               \
1930 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1931 {                                                                             \
1932     ppc_vsr_t xt, xa, xb;                                                     \
1933     int i;                                                                    \
1934                                                                               \
1935     getVSR(xA(opcode), &xa, env);                                             \
1936     getVSR(xB(opcode), &xb, env);                                             \
1937     getVSR(xT(opcode), &xt, env);                                             \
1938     helper_reset_fpstatus(env);                                               \
1939                                                                               \
1940     for (i = 0; i < nels; i++) {                                              \
1941         float_status tstat = env->fp_status;                                  \
1942         set_float_exception_flags(0, &tstat);                                 \
1943         xt.fld = tp##_div(xa.fld, xb.fld, &tstat);                            \
1944         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
1945                                                                               \
1946         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
1947             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {       \
1948                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf);     \
1949             } else if (tp##_is_zero(xa.fld) &&                                \
1950                 tp##_is_zero(xb.fld)) {                                       \
1951                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf);     \
1952             } else if (tp##_is_signaling_nan(xa.fld) ||                       \
1953                 tp##_is_signaling_nan(xb.fld)) {                              \
1954                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1955             }                                                                 \
1956         }                                                                     \
1957                                                                               \
1958         if (r2sp) {                                                           \
1959             xt.fld = helper_frsp(env, xt.fld);                                \
1960         }                                                                     \
1961                                                                               \
1962         if (sfprf) {                                                          \
1963             helper_compute_fprf(env, xt.fld, sfprf);                          \
1964         }                                                                     \
1965     }                                                                         \
1966                                                                               \
1967     putVSR(xT(opcode), &xt, env);                                             \
1968     helper_float_check_status(env);                                           \
1969 }
1970
1971 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1972 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1973 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1974 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1975
1976 /* VSX_RE  - VSX floating point reciprocal estimate
1977  *   op    - instruction mnemonic
1978  *   nels  - number of elements (1, 2 or 4)
1979  *   tp    - type (float32 or float64)
1980  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1981  *   sfprf - set FPRF
1982  */
1983 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp)                                \
1984 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1985 {                                                                             \
1986     ppc_vsr_t xt, xb;                                                         \
1987     int i;                                                                    \
1988                                                                               \
1989     getVSR(xB(opcode), &xb, env);                                             \
1990     getVSR(xT(opcode), &xt, env);                                             \
1991     helper_reset_fpstatus(env);                                               \
1992                                                                               \
1993     for (i = 0; i < nels; i++) {                                              \
1994         if (unlikely(tp##_is_signaling_nan(xb.fld))) {                        \
1995                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1996         }                                                                     \
1997         xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status);                 \
1998                                                                               \
1999         if (r2sp) {                                                           \
2000             xt.fld = helper_frsp(env, xt.fld);                                \
2001         }                                                                     \
2002                                                                               \
2003         if (sfprf) {                                                          \
2004             helper_compute_fprf(env, xt.fld, sfprf);                          \
2005         }                                                                     \
2006     }                                                                         \
2007                                                                               \
2008     putVSR(xT(opcode), &xt, env);                                             \
2009     helper_float_check_status(env);                                           \
2010 }
2011
2012 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
2013 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
2014 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
2015 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
2016
2017 /* VSX_SQRT - VSX floating point square root
2018  *   op    - instruction mnemonic
2019  *   nels  - number of elements (1, 2 or 4)
2020  *   tp    - type (float32 or float64)
2021  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2022  *   sfprf - set FPRF
2023  */
2024 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp)                             \
2025 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2026 {                                                                            \
2027     ppc_vsr_t xt, xb;                                                        \
2028     int i;                                                                   \
2029                                                                              \
2030     getVSR(xB(opcode), &xb, env);                                            \
2031     getVSR(xT(opcode), &xt, env);                                            \
2032     helper_reset_fpstatus(env);                                              \
2033                                                                              \
2034     for (i = 0; i < nels; i++) {                                             \
2035         float_status tstat = env->fp_status;                                 \
2036         set_float_exception_flags(0, &tstat);                                \
2037         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2038         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2039                                                                              \
2040         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2041             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2042                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2043             } else if (tp##_is_signaling_nan(xb.fld)) {                      \
2044                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2045             }                                                                \
2046         }                                                                    \
2047                                                                              \
2048         if (r2sp) {                                                          \
2049             xt.fld = helper_frsp(env, xt.fld);                               \
2050         }                                                                    \
2051                                                                              \
2052         if (sfprf) {                                                         \
2053             helper_compute_fprf(env, xt.fld, sfprf);                         \
2054         }                                                                    \
2055     }                                                                        \
2056                                                                              \
2057     putVSR(xT(opcode), &xt, env);                                            \
2058     helper_float_check_status(env);                                          \
2059 }
2060
2061 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2062 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2063 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2064 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2065
2066 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2067  *   op    - instruction mnemonic
2068  *   nels  - number of elements (1, 2 or 4)
2069  *   tp    - type (float32 or float64)
2070  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2071  *   sfprf - set FPRF
2072  */
2073 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp)                           \
2074 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2075 {                                                                            \
2076     ppc_vsr_t xt, xb;                                                        \
2077     int i;                                                                   \
2078                                                                              \
2079     getVSR(xB(opcode), &xb, env);                                            \
2080     getVSR(xT(opcode), &xt, env);                                            \
2081     helper_reset_fpstatus(env);                                              \
2082                                                                              \
2083     for (i = 0; i < nels; i++) {                                             \
2084         float_status tstat = env->fp_status;                                 \
2085         set_float_exception_flags(0, &tstat);                                \
2086         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2087         xt.fld = tp##_div(tp##_one, xt.fld, &tstat);                         \
2088         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2089                                                                              \
2090         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2091             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2092                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2093             } else if (tp##_is_signaling_nan(xb.fld)) {                      \
2094                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2095             }                                                                \
2096         }                                                                    \
2097                                                                              \
2098         if (r2sp) {                                                          \
2099             xt.fld = helper_frsp(env, xt.fld);                               \
2100         }                                                                    \
2101                                                                              \
2102         if (sfprf) {                                                         \
2103             helper_compute_fprf(env, xt.fld, sfprf);                         \
2104         }                                                                    \
2105     }                                                                        \
2106                                                                              \
2107     putVSR(xT(opcode), &xt, env);                                            \
2108     helper_float_check_status(env);                                          \
2109 }
2110
2111 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2112 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2113 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2114 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2115
2116 /* VSX_TDIV - VSX floating point test for divide
2117  *   op    - instruction mnemonic
2118  *   nels  - number of elements (1, 2 or 4)
2119  *   tp    - type (float32 or float64)
2120  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2121  *   emin  - minimum unbiased exponent
2122  *   emax  - maximum unbiased exponent
2123  *   nbits - number of fraction bits
2124  */
2125 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits)                  \
2126 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2127 {                                                                       \
2128     ppc_vsr_t xa, xb;                                                   \
2129     int i;                                                              \
2130     int fe_flag = 0;                                                    \
2131     int fg_flag = 0;                                                    \
2132                                                                         \
2133     getVSR(xA(opcode), &xa, env);                                       \
2134     getVSR(xB(opcode), &xb, env);                                       \
2135                                                                         \
2136     for (i = 0; i < nels; i++) {                                        \
2137         if (unlikely(tp##_is_infinity(xa.fld) ||                        \
2138                      tp##_is_infinity(xb.fld) ||                        \
2139                      tp##_is_zero(xb.fld))) {                           \
2140             fe_flag = 1;                                                \
2141             fg_flag = 1;                                                \
2142         } else {                                                        \
2143             int e_a = ppc_##tp##_get_unbiased_exp(xa.fld);              \
2144             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2145                                                                         \
2146             if (unlikely(tp##_is_any_nan(xa.fld) ||                     \
2147                          tp##_is_any_nan(xb.fld))) {                    \
2148                 fe_flag = 1;                                            \
2149             } else if ((e_b <= emin) || (e_b >= (emax-2))) {            \
2150                 fe_flag = 1;                                            \
2151             } else if (!tp##_is_zero(xa.fld) &&                         \
2152                        (((e_a - e_b) >= emax) ||                        \
2153                         ((e_a - e_b) <= (emin+1)) ||                    \
2154                          (e_a <= (emin+nbits)))) {                      \
2155                 fe_flag = 1;                                            \
2156             }                                                           \
2157                                                                         \
2158             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2159                 /* XB is not zero because of the above check and */     \
2160                 /* so must be denormalized.                      */     \
2161                 fg_flag = 1;                                            \
2162             }                                                           \
2163         }                                                               \
2164     }                                                                   \
2165                                                                         \
2166     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2167 }
2168
2169 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2170 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2171 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2172
2173 /* VSX_TSQRT - VSX floating point test for square root
2174  *   op    - instruction mnemonic
2175  *   nels  - number of elements (1, 2 or 4)
2176  *   tp    - type (float32 or float64)
2177  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2178  *   emin  - minimum unbiased exponent
2179  *   emax  - maximum unbiased exponent
2180  *   nbits - number of fraction bits
2181  */
2182 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits)                       \
2183 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2184 {                                                                       \
2185     ppc_vsr_t xa, xb;                                                   \
2186     int i;                                                              \
2187     int fe_flag = 0;                                                    \
2188     int fg_flag = 0;                                                    \
2189                                                                         \
2190     getVSR(xA(opcode), &xa, env);                                       \
2191     getVSR(xB(opcode), &xb, env);                                       \
2192                                                                         \
2193     for (i = 0; i < nels; i++) {                                        \
2194         if (unlikely(tp##_is_infinity(xb.fld) ||                        \
2195                      tp##_is_zero(xb.fld))) {                           \
2196             fe_flag = 1;                                                \
2197             fg_flag = 1;                                                \
2198         } else {                                                        \
2199             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2200                                                                         \
2201             if (unlikely(tp##_is_any_nan(xb.fld))) {                    \
2202                 fe_flag = 1;                                            \
2203             } else if (unlikely(tp##_is_zero(xb.fld))) {                \
2204                 fe_flag = 1;                                            \
2205             } else if (unlikely(tp##_is_neg(xb.fld))) {                 \
2206                 fe_flag = 1;                                            \
2207             } else if (!tp##_is_zero(xb.fld) &&                         \
2208                       (e_b <= (emin+nbits))) {                          \
2209                 fe_flag = 1;                                            \
2210             }                                                           \
2211                                                                         \
2212             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2213                 /* XB is not zero because of the above check and */     \
2214                 /* therefore must be denormalized.               */     \
2215                 fg_flag = 1;                                            \
2216             }                                                           \
2217         }                                                               \
2218     }                                                                   \
2219                                                                         \
2220     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2221 }
2222
2223 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2224 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2225 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2226
2227 /* VSX_MADD - VSX floating point muliply/add variations
2228  *   op    - instruction mnemonic
2229  *   nels  - number of elements (1, 2 or 4)
2230  *   tp    - type (float32 or float64)
2231  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2232  *   maddflgs - flags for the float*muladd routine that control the
2233  *           various forms (madd, msub, nmadd, nmsub)
2234  *   afrm  - A form (1=A, 0=M)
2235  *   sfprf - set FPRF
2236  */
2237 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp)              \
2238 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
2239 {                                                                             \
2240     ppc_vsr_t xt_in, xa, xb, xt_out;                                          \
2241     ppc_vsr_t *b, *c;                                                         \
2242     int i;                                                                    \
2243                                                                               \
2244     if (afrm) { /* AxB + T */                                                 \
2245         b = &xb;                                                              \
2246         c = &xt_in;                                                           \
2247     } else { /* AxT + B */                                                    \
2248         b = &xt_in;                                                           \
2249         c = &xb;                                                              \
2250     }                                                                         \
2251                                                                               \
2252     getVSR(xA(opcode), &xa, env);                                             \
2253     getVSR(xB(opcode), &xb, env);                                             \
2254     getVSR(xT(opcode), &xt_in, env);                                          \
2255                                                                               \
2256     xt_out = xt_in;                                                           \
2257                                                                               \
2258     helper_reset_fpstatus(env);                                               \
2259                                                                               \
2260     for (i = 0; i < nels; i++) {                                              \
2261         float_status tstat = env->fp_status;                                  \
2262         set_float_exception_flags(0, &tstat);                                 \
2263         if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2264             /* Avoid double rounding errors by rounding the intermediate */   \
2265             /* result to odd.                                            */   \
2266             set_float_rounding_mode(float_round_to_zero, &tstat);             \
2267             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2268                                        maddflgs, &tstat);                     \
2269             xt_out.fld |= (get_float_exception_flags(&tstat) &                \
2270                               float_flag_inexact) != 0;                       \
2271         } else {                                                              \
2272             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2273                                         maddflgs, &tstat);                    \
2274         }                                                                     \
2275         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
2276                                                                               \
2277         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
2278             if (tp##_is_signaling_nan(xa.fld) ||                              \
2279                 tp##_is_signaling_nan(b->fld) ||                              \
2280                 tp##_is_signaling_nan(c->fld)) {                              \
2281                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
2282                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2283             }                                                                 \
2284             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) ||         \
2285                 (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) {         \
2286                 xt_out.fld = float64_to_##tp(fload_invalid_op_excp(env,       \
2287                     POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status);          \
2288                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2289             }                                                                 \
2290             if ((tstat.float_exception_flags & float_flag_invalid) &&         \
2291                 ((tp##_is_infinity(xa.fld) ||                                 \
2292                   tp##_is_infinity(b->fld)) &&                                \
2293                   tp##_is_infinity(c->fld))) {                                \
2294                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);     \
2295             }                                                                 \
2296         }                                                                     \
2297                                                                               \
2298         if (r2sp) {                                                           \
2299             xt_out.fld = helper_frsp(env, xt_out.fld);                        \
2300         }                                                                     \
2301                                                                               \
2302         if (sfprf) {                                                          \
2303             helper_compute_fprf(env, xt_out.fld, sfprf);                      \
2304         }                                                                     \
2305     }                                                                         \
2306     putVSR(xT(opcode), &xt_out, env);                                         \
2307     helper_float_check_status(env);                                           \
2308 }
2309
2310 #define MADD_FLGS 0
2311 #define MSUB_FLGS float_muladd_negate_c
2312 #define NMADD_FLGS float_muladd_negate_result
2313 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
2314
2315 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
2316 VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
2317 VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
2318 VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0)
2319 VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0)
2320 VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0)
2321 VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0)
2322 VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0)
2323
2324 VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1)
2325 VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1)
2326 VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1)
2327 VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1)
2328 VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1)
2329 VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1)
2330 VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1)
2331 VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1)
2332
2333 VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0)
2334 VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0)
2335 VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0)
2336 VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0)
2337 VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0)
2338 VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0)
2339 VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0)
2340 VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0)
2341
2342 VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0)
2343 VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0)
2344 VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0)
2345 VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0)
2346 VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0)
2347 VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
2348 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
2349 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
2350
2351 #define VSX_SCALAR_CMP(op, ordered)                                      \
2352 void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
2353 {                                                                        \
2354     ppc_vsr_t xa, xb;                                                    \
2355     uint32_t cc = 0;                                                     \
2356                                                                          \
2357     getVSR(xA(opcode), &xa, env);                                        \
2358     getVSR(xB(opcode), &xb, env);                                        \
2359                                                                          \
2360     if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                       \
2361                  float64_is_any_nan(xb.VsrD(0)))) {                      \
2362         if (float64_is_signaling_nan(xa.VsrD(0)) ||                      \
2363             float64_is_signaling_nan(xb.VsrD(0))) {                      \
2364             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);       \
2365         }                                                                \
2366         if (ordered) {                                                   \
2367             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);         \
2368         }                                                                \
2369         cc = 1;                                                          \
2370     } else {                                                             \
2371         if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) {       \
2372             cc = 8;                                                      \
2373         } else if (!float64_le(xa.VsrD(0), xb.VsrD(0),                   \
2374                                &env->fp_status)) { \
2375             cc = 4;                                                      \
2376         } else {                                                         \
2377             cc = 2;                                                      \
2378         }                                                                \
2379     }                                                                    \
2380                                                                          \
2381     env->fpscr &= ~(0x0F << FPSCR_FPRF);                                 \
2382     env->fpscr |= cc << FPSCR_FPRF;                                      \
2383     env->crf[BF(opcode)] = cc;                                           \
2384                                                                          \
2385     helper_float_check_status(env);                                      \
2386 }
2387
2388 VSX_SCALAR_CMP(xscmpodp, 1)
2389 VSX_SCALAR_CMP(xscmpudp, 0)
2390
2391 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
2392 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
2393
2394 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2395  *   name  - instruction mnemonic
2396  *   op    - operation (max or min)
2397  *   nels  - number of elements (1, 2 or 4)
2398  *   tp    - type (float32 or float64)
2399  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2400  */
2401 #define VSX_MAX_MIN(name, op, nels, tp, fld)                                  \
2402 void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
2403 {                                                                             \
2404     ppc_vsr_t xt, xa, xb;                                                     \
2405     int i;                                                                    \
2406                                                                               \
2407     getVSR(xA(opcode), &xa, env);                                             \
2408     getVSR(xB(opcode), &xb, env);                                             \
2409     getVSR(xT(opcode), &xt, env);                                             \
2410                                                                               \
2411     for (i = 0; i < nels; i++) {                                              \
2412         xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status);                  \
2413         if (unlikely(tp##_is_signaling_nan(xa.fld) ||                         \
2414                      tp##_is_signaling_nan(xb.fld))) {                        \
2415             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
2416         }                                                                     \
2417     }                                                                         \
2418                                                                               \
2419     putVSR(xT(opcode), &xt, env);                                             \
2420     helper_float_check_status(env);                                           \
2421 }
2422
2423 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2424 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2425 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2426 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2427 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2428 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2429
2430 /* VSX_CMP - VSX floating point compare
2431  *   op    - instruction mnemonic
2432  *   nels  - number of elements (1, 2 or 4)
2433  *   tp    - type (float32 or float64)
2434  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2435  *   cmp   - comparison operation
2436  *   svxvc - set VXVC bit
2437  */
2438 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc)                            \
2439 void helper_##op(CPUPPCState *env, uint32_t opcode)                       \
2440 {                                                                         \
2441     ppc_vsr_t xt, xa, xb;                                                 \
2442     int i;                                                                \
2443     int all_true = 1;                                                     \
2444     int all_false = 1;                                                    \
2445                                                                           \
2446     getVSR(xA(opcode), &xa, env);                                         \
2447     getVSR(xB(opcode), &xb, env);                                         \
2448     getVSR(xT(opcode), &xt, env);                                         \
2449                                                                           \
2450     for (i = 0; i < nels; i++) {                                          \
2451         if (unlikely(tp##_is_any_nan(xa.fld) ||                           \
2452                      tp##_is_any_nan(xb.fld))) {                          \
2453             if (tp##_is_signaling_nan(xa.fld) ||                          \
2454                 tp##_is_signaling_nan(xb.fld)) {                          \
2455                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);    \
2456             }                                                             \
2457             if (svxvc) {                                                  \
2458                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);      \
2459             }                                                             \
2460             xt.fld = 0;                                                   \
2461             all_true = 0;                                                 \
2462         } else {                                                          \
2463             if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == 1) {       \
2464                 xt.fld = -1;                                              \
2465                 all_false = 0;                                            \
2466             } else {                                                      \
2467                 xt.fld = 0;                                               \
2468                 all_true = 0;                                             \
2469             }                                                             \
2470         }                                                                 \
2471     }                                                                     \
2472                                                                           \
2473     putVSR(xT(opcode), &xt, env);                                         \
2474     if ((opcode >> (31-21)) & 1) {                                        \
2475         env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0);       \
2476     }                                                                     \
2477     helper_float_check_status(env);                                       \
2478  }
2479
2480 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0)
2481 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1)
2482 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1)
2483 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0)
2484 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1)
2485 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1)
2486
2487 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2488  *   op    - instruction mnemonic
2489  *   nels  - number of elements (1, 2 or 4)
2490  *   stp   - source type (float32 or float64)
2491  *   ttp   - target type (float32 or float64)
2492  *   sfld  - source vsr_t field
2493  *   tfld  - target vsr_t field (f32 or f64)
2494  *   sfprf - set FPRF
2495  */
2496 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf)    \
2497 void helper_##op(CPUPPCState *env, uint32_t opcode)                \
2498 {                                                                  \
2499     ppc_vsr_t xt, xb;                                              \
2500     int i;                                                         \
2501                                                                    \
2502     getVSR(xB(opcode), &xb, env);                                  \
2503     getVSR(xT(opcode), &xt, env);                                  \
2504                                                                    \
2505     for (i = 0; i < nels; i++) {                                   \
2506         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);        \
2507         if (unlikely(stp##_is_signaling_nan(xb.sfld))) {           \
2508             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2509             xt.tfld = ttp##_snan_to_qnan(xt.tfld);                 \
2510         }                                                          \
2511         if (sfprf) {                                               \
2512             helper_compute_fprf(env, ttp##_to_float64(xt.tfld,     \
2513                                 &env->fp_status), sfprf);          \
2514         }                                                          \
2515     }                                                              \
2516                                                                    \
2517     putVSR(xT(opcode), &xt, env);                                  \
2518     helper_float_check_status(env);                                \
2519 }
2520
2521 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2522 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2523 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
2524 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
2525
2526 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2527 {
2528     float_status tstat = env->fp_status;
2529     set_float_exception_flags(0, &tstat);
2530
2531     return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2532 }
2533
2534 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2535 {
2536     float_status tstat = env->fp_status;
2537     set_float_exception_flags(0, &tstat);
2538
2539     return float32_to_float64(xb >> 32, &tstat);
2540 }
2541
2542 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2543  *   op    - instruction mnemonic
2544  *   nels  - number of elements (1, 2 or 4)
2545  *   stp   - source type (float32 or float64)
2546  *   ttp   - target type (int32, uint32, int64 or uint64)
2547  *   sfld  - source vsr_t field
2548  *   tfld  - target vsr_t field
2549  *   rnan  - resulting NaN
2550  */
2551 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan)              \
2552 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2553 {                                                                            \
2554     ppc_vsr_t xt, xb;                                                        \
2555     int i;                                                                   \
2556                                                                              \
2557     getVSR(xB(opcode), &xb, env);                                            \
2558     getVSR(xT(opcode), &xt, env);                                            \
2559                                                                              \
2560     for (i = 0; i < nels; i++) {                                             \
2561         if (unlikely(stp##_is_any_nan(xb.sfld))) {                           \
2562             if (stp##_is_signaling_nan(xb.sfld)) {                           \
2563                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);       \
2564             }                                                                \
2565             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);            \
2566             xt.tfld = rnan;                                                  \
2567         } else {                                                             \
2568             xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld,                \
2569                           &env->fp_status);                                  \
2570             if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2571                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);        \
2572             }                                                                \
2573         }                                                                    \
2574     }                                                                        \
2575                                                                              \
2576     putVSR(xT(opcode), &xt, env);                                            \
2577     helper_float_check_status(env);                                          \
2578 }
2579
2580 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2581                   0x8000000000000000ULL)
2582 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2583                   0x80000000U)
2584 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2585 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2586 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2587                   0x8000000000000000ULL)
2588 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \
2589                   0x80000000U)
2590 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2591 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U)
2592 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \
2593                   0x8000000000000000ULL)
2594 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2595 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
2596 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2597
2598 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2599  *   op    - instruction mnemonic
2600  *   nels  - number of elements (1, 2 or 4)
2601  *   stp   - source type (int32, uint32, int64 or uint64)
2602  *   ttp   - target type (float32 or float64)
2603  *   sfld  - source vsr_t field
2604  *   tfld  - target vsr_t field
2605  *   jdef  - definition of the j index (i or 2*i)
2606  *   sfprf - set FPRF
2607  */
2608 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp)  \
2609 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2610 {                                                                       \
2611     ppc_vsr_t xt, xb;                                                   \
2612     int i;                                                              \
2613                                                                         \
2614     getVSR(xB(opcode), &xb, env);                                       \
2615     getVSR(xT(opcode), &xt, env);                                       \
2616                                                                         \
2617     for (i = 0; i < nels; i++) {                                        \
2618         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);             \
2619         if (r2sp) {                                                     \
2620             xt.tfld = helper_frsp(env, xt.tfld);                        \
2621         }                                                               \
2622         if (sfprf) {                                                    \
2623             helper_compute_fprf(env, xt.tfld, sfprf);                   \
2624         }                                                               \
2625     }                                                                   \
2626                                                                         \
2627     putVSR(xT(opcode), &xt, env);                                       \
2628     helper_float_check_status(env);                                     \
2629 }
2630
2631 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2632 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2633 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2634 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2635 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2636 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2637 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
2638 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
2639 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
2640 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
2641 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2642 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2643
2644 /* For "use current rounding mode", define a value that will not be one of
2645  * the existing rounding model enums.
2646  */
2647 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2648   float_round_up + float_round_to_zero)
2649
2650 /* VSX_ROUND - VSX floating point round
2651  *   op    - instruction mnemonic
2652  *   nels  - number of elements (1, 2 or 4)
2653  *   tp    - type (float32 or float64)
2654  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2655  *   rmode - rounding mode
2656  *   sfprf - set FPRF
2657  */
2658 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf)                     \
2659 void helper_##op(CPUPPCState *env, uint32_t opcode)                    \
2660 {                                                                      \
2661     ppc_vsr_t xt, xb;                                                  \
2662     int i;                                                             \
2663     getVSR(xB(opcode), &xb, env);                                      \
2664     getVSR(xT(opcode), &xt, env);                                      \
2665                                                                        \
2666     if (rmode != FLOAT_ROUND_CURRENT) {                                \
2667         set_float_rounding_mode(rmode, &env->fp_status);               \
2668     }                                                                  \
2669                                                                        \
2670     for (i = 0; i < nels; i++) {                                       \
2671         if (unlikely(tp##_is_signaling_nan(xb.fld))) {                 \
2672             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);     \
2673             xt.fld = tp##_snan_to_qnan(xb.fld);                        \
2674         } else {                                                       \
2675             xt.fld = tp##_round_to_int(xb.fld, &env->fp_status);       \
2676         }                                                              \
2677         if (sfprf) {                                                   \
2678             helper_compute_fprf(env, xt.fld, sfprf);                   \
2679         }                                                              \
2680     }                                                                  \
2681                                                                        \
2682     /* If this is not a "use current rounding mode" instruction,       \
2683      * then inhibit setting of the XX bit and restore rounding         \
2684      * mode from FPSCR */                                              \
2685     if (rmode != FLOAT_ROUND_CURRENT) {                                \
2686         fpscr_set_rounding_mode(env);                                  \
2687         env->fp_status.float_exception_flags &= ~float_flag_inexact;   \
2688     }                                                                  \
2689                                                                        \
2690     putVSR(xT(opcode), &xt, env);                                      \
2691     helper_float_check_status(env);                                    \
2692 }
2693
2694 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_nearest_even, 1)
2695 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2696 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2697 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2698 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2699
2700 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_nearest_even, 0)
2701 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2702 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2703 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2704 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2705
2706 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_nearest_even, 0)
2707 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2708 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2709 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2710 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2711
2712 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2713 {
2714     helper_reset_fpstatus(env);
2715
2716     uint64_t xt = helper_frsp(env, xb);
2717
2718     helper_compute_fprf(env, xt, 1);
2719     helper_float_check_status(env);
2720     return xt;
2721 }