target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 void cpu_save(QEMUFile *f, void *opaque)
   5 {
   6     int i;
   7     CPUARMState *env = (CPUARMState *)opaque;
   8
   9     for (i = 0; i < 16; i++) {
  10         qemu_put_be32(f, env->regs[i]);
  11     }
  12     qemu_put_be32(f, cpsr_read(env));
  13     qemu_put_be32(f, env->spsr);
  14     for (i = 0; i < 6; i++) {
  15         qemu_put_be32(f, env->banked_spsr[i]);
  16         qemu_put_be32(f, env->banked_r13[i]);
  17         qemu_put_be32(f, env->banked_r14[i]);
  18     }
  19     for (i = 0; i < 5; i++) {
  20         qemu_put_be32(f, env->usr_regs[i]);
  21         qemu_put_be32(f, env->fiq_regs[i]);
  22     }
  23     qemu_put_be32(f, env->cp15.c0_cpuid);
  24     qemu_put_be32(f, env->cp15.c0_cssel);
  25     qemu_put_be32(f, env->cp15.c1_sys);
  26     qemu_put_be32(f, env->cp15.c1_coproc);
  27     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  28     qemu_put_be32(f, env->cp15.c1_scr);
  29     qemu_put_be32(f, env->cp15.c2_base0);
  30     qemu_put_be32(f, env->cp15.c2_base1);
  31     qemu_put_be32(f, env->cp15.c2_control);
  32     qemu_put_be32(f, env->cp15.c2_mask);
  33     qemu_put_be32(f, env->cp15.c2_base_mask);
  34     qemu_put_be32(f, env->cp15.c2_data);
  35     qemu_put_be32(f, env->cp15.c2_insn);
  36     qemu_put_be32(f, env->cp15.c3);
  37     qemu_put_be32(f, env->cp15.c5_insn);
  38     qemu_put_be32(f, env->cp15.c5_data);
  39     for (i = 0; i < 8; i++) {
  40         qemu_put_be32(f, env->cp15.c6_region[i]);
  41     }
  42     qemu_put_be32(f, env->cp15.c6_insn);
  43     qemu_put_be32(f, env->cp15.c6_data);
  44     qemu_put_be32(f, env->cp15.c7_par);
  45     qemu_put_be32(f, env->cp15.c9_insn);
  46     qemu_put_be32(f, env->cp15.c9_data);
  47     qemu_put_be32(f, env->cp15.c9_pmcr);
  48     qemu_put_be32(f, env->cp15.c9_pmcnten);
  49     qemu_put_be32(f, env->cp15.c9_pmovsr);
  50     qemu_put_be32(f, env->cp15.c9_pmxevtyper);
  51     qemu_put_be32(f, env->cp15.c9_pmuserenr);
  52     qemu_put_be32(f, env->cp15.c9_pminten);
  53     qemu_put_be32(f, env->cp15.c13_fcse);
  54     qemu_put_be32(f, env->cp15.c13_context);
  55     qemu_put_be32(f, env->cp15.c13_tls1);
  56     qemu_put_be32(f, env->cp15.c13_tls2);
  57     qemu_put_be32(f, env->cp15.c13_tls3);
  58     qemu_put_be32(f, env->cp15.c15_cpar);
  59     qemu_put_be32(f, env->cp15.c15_power_control);
  60     qemu_put_be32(f, env->cp15.c15_diagnostic);
  61     qemu_put_be32(f, env->cp15.c15_power_diagnostic);
  62
  63     qemu_put_be32(f, env->features);
  64
  65     if (arm_feature(env, ARM_FEATURE_VFP)) {
  66         for (i = 0;  i < 16; i++) {
  67             CPU_DoubleU u;
  68             u.d = env->vfp.regs[i];
  69             qemu_put_be32(f, u.l.upper);
  70             qemu_put_be32(f, u.l.lower);
  71         }
  72         for (i = 0; i < 16; i++) {
  73             qemu_put_be32(f, env->vfp.xregs[i]);
  74         }
  75
  76         /* TODO: Should use proper FPSCR access functions.  */
  77         qemu_put_be32(f, env->vfp.vec_len);
  78         qemu_put_be32(f, env->vfp.vec_stride);
  79
  80         if (arm_feature(env, ARM_FEATURE_VFP3)) {
  81             for (i = 16;  i < 32; i++) {
  82                 CPU_DoubleU u;
  83                 u.d = env->vfp.regs[i];
  84                 qemu_put_be32(f, u.l.upper);
  85                 qemu_put_be32(f, u.l.lower);
  86             }
  87         }
  88     }
  89
  90     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  91         for (i = 0; i < 16; i++) {
  92             qemu_put_be64(f, env->iwmmxt.regs[i]);
  93         }
  94         for (i = 0; i < 16; i++) {
  95             qemu_put_be32(f, env->iwmmxt.cregs[i]);
  96         }
  97     }
  98
  99     if (arm_feature(env, ARM_FEATURE_M)) {
 100         qemu_put_be32(f, env->v7m.other_sp);
 101         qemu_put_be32(f, env->v7m.vecbase);
 102         qemu_put_be32(f, env->v7m.basepri);
 103         qemu_put_be32(f, env->v7m.control);
 104         qemu_put_be32(f, env->v7m.current_sp);
 105         qemu_put_be32(f, env->v7m.exception);
 106     }
 107
 108     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 109         qemu_put_be32(f, env->teecr);
 110         qemu_put_be32(f, env->teehbr);
 111     }
 112 }
 113
 114 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 115 {
 116     CPUARMState *env = (CPUARMState *)opaque;
 117     int i;
 118     uint32_t val;
 119
 120     if (version_id != CPU_SAVE_VERSION)
 121         return -EINVAL;
 122
 123     for (i = 0; i < 16; i++) {
 124         env->regs[i] = qemu_get_be32(f);
 125     }
 126     val = qemu_get_be32(f);
 127     /* Avoid mode switch when restoring CPSR.  */
 128     env->uncached_cpsr = val & CPSR_M;
 129     cpsr_write(env, val, 0xffffffff);
 130     env->spsr = qemu_get_be32(f);
 131     for (i = 0; i < 6; i++) {
 132         env->banked_spsr[i] = qemu_get_be32(f);
 133         env->banked_r13[i] = qemu_get_be32(f);
 134         env->banked_r14[i] = qemu_get_be32(f);
 135     }
 136     for (i = 0; i < 5; i++) {
 137         env->usr_regs[i] = qemu_get_be32(f);
 138         env->fiq_regs[i] = qemu_get_be32(f);
 139     }
 140     env->cp15.c0_cpuid = qemu_get_be32(f);
 141     env->cp15.c0_cssel = qemu_get_be32(f);
 142     env->cp15.c1_sys = qemu_get_be32(f);
 143     env->cp15.c1_coproc = qemu_get_be32(f);
 144     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
 145     env->cp15.c1_scr = qemu_get_be32(f);
 146     env->cp15.c2_base0 = qemu_get_be32(f);
 147     env->cp15.c2_base1 = qemu_get_be32(f);
 148     env->cp15.c2_control = qemu_get_be32(f);
 149     env->cp15.c2_mask = qemu_get_be32(f);
 150     env->cp15.c2_base_mask = qemu_get_be32(f);
 151     env->cp15.c2_data = qemu_get_be32(f);
 152     env->cp15.c2_insn = qemu_get_be32(f);
 153     env->cp15.c3 = qemu_get_be32(f);
 154     env->cp15.c5_insn = qemu_get_be32(f);
 155     env->cp15.c5_data = qemu_get_be32(f);
 156     for (i = 0; i < 8; i++) {
 157         env->cp15.c6_region[i] = qemu_get_be32(f);
 158     }
 159     env->cp15.c6_insn = qemu_get_be32(f);
 160     env->cp15.c6_data = qemu_get_be32(f);
 161     env->cp15.c7_par = qemu_get_be32(f);
 162     env->cp15.c9_insn = qemu_get_be32(f);
 163     env->cp15.c9_data = qemu_get_be32(f);
 164     env->cp15.c9_pmcr = qemu_get_be32(f);
 165     env->cp15.c9_pmcnten = qemu_get_be32(f);
 166     env->cp15.c9_pmovsr = qemu_get_be32(f);
 167     env->cp15.c9_pmxevtyper = qemu_get_be32(f);
 168     env->cp15.c9_pmuserenr = qemu_get_be32(f);
 169     env->cp15.c9_pminten = qemu_get_be32(f);
 170     env->cp15.c13_fcse = qemu_get_be32(f);
 171     env->cp15.c13_context = qemu_get_be32(f);
 172     env->cp15.c13_tls1 = qemu_get_be32(f);
 173     env->cp15.c13_tls2 = qemu_get_be32(f);
 174     env->cp15.c13_tls3 = qemu_get_be32(f);
 175     env->cp15.c15_cpar = qemu_get_be32(f);
 176     env->cp15.c15_power_control = qemu_get_be32(f);
 177     env->cp15.c15_diagnostic = qemu_get_be32(f);
 178     env->cp15.c15_power_diagnostic = qemu_get_be32(f);
 179
 180     env->features = qemu_get_be32(f);
 181
 182     if (arm_feature(env, ARM_FEATURE_VFP)) {
 183         for (i = 0;  i < 16; i++) {
 184             CPU_DoubleU u;
 185             u.l.upper = qemu_get_be32(f);
 186             u.l.lower = qemu_get_be32(f);
 187             env->vfp.regs[i] = u.d;
 188         }
 189         for (i = 0; i < 16; i++) {
 190             env->vfp.xregs[i] = qemu_get_be32(f);
 191         }
 192
 193         /* TODO: Should use proper FPSCR access functions.  */
 194         env->vfp.vec_len = qemu_get_be32(f);
 195         env->vfp.vec_stride = qemu_get_be32(f);
 196
 197         if (arm_feature(env, ARM_FEATURE_VFP3)) {
 198             for (i = 16;  i < 32; i++) {
 199                 CPU_DoubleU u;
 200                 u.l.upper = qemu_get_be32(f);
 201                 u.l.lower = qemu_get_be32(f);
 202                 env->vfp.regs[i] = u.d;
 203             }
 204         }
 205     }
 206
 207     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 208         for (i = 0; i < 16; i++) {
 209             env->iwmmxt.regs[i] = qemu_get_be64(f);
 210         }
 211         for (i = 0; i < 16; i++) {
 212             env->iwmmxt.cregs[i] = qemu_get_be32(f);
 213         }
 214     }
 215
 216     if (arm_feature(env, ARM_FEATURE_M)) {
 217         env->v7m.other_sp = qemu_get_be32(f);
 218         env->v7m.vecbase = qemu_get_be32(f);
 219         env->v7m.basepri = qemu_get_be32(f);
 220         env->v7m.control = qemu_get_be32(f);
 221         env->v7m.current_sp = qemu_get_be32(f);
 222         env->v7m.exception = qemu_get_be32(f);
 223     }
 224
 225     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 226         env->teecr = qemu_get_be32(f);
 227         env->teehbr = qemu_get_be32(f);
 228     }
 229
 230     return 0;
 231 }