xilinx_zynq: Added SPI controllers + flashes
[qemu-kvm.git] / target-sparc / int64_helper.c
blob5d0bc6c6d28c345f6df1c601d13a92887537b785
1 /*
2 * Sparc64 interrupt helpers
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "cpu.h"
21 #include "helper.h"
22 #include "trace.h"
24 #define DEBUG_PCALL
26 #ifdef DEBUG_PCALL
27 static const char * const excp_names[0x80] = {
28 [TT_TFAULT] = "Instruction Access Fault",
29 [TT_TMISS] = "Instruction Access MMU Miss",
30 [TT_CODE_ACCESS] = "Instruction Access Error",
31 [TT_ILL_INSN] = "Illegal Instruction",
32 [TT_PRIV_INSN] = "Privileged Instruction",
33 [TT_NFPU_INSN] = "FPU Disabled",
34 [TT_FP_EXCP] = "FPU Exception",
35 [TT_TOVF] = "Tag Overflow",
36 [TT_CLRWIN] = "Clean Windows",
37 [TT_DIV_ZERO] = "Division By Zero",
38 [TT_DFAULT] = "Data Access Fault",
39 [TT_DMISS] = "Data Access MMU Miss",
40 [TT_DATA_ACCESS] = "Data Access Error",
41 [TT_DPROT] = "Data Protection Error",
42 [TT_UNALIGNED] = "Unaligned Memory Access",
43 [TT_PRIV_ACT] = "Privileged Action",
44 [TT_EXTINT | 0x1] = "External Interrupt 1",
45 [TT_EXTINT | 0x2] = "External Interrupt 2",
46 [TT_EXTINT | 0x3] = "External Interrupt 3",
47 [TT_EXTINT | 0x4] = "External Interrupt 4",
48 [TT_EXTINT | 0x5] = "External Interrupt 5",
49 [TT_EXTINT | 0x6] = "External Interrupt 6",
50 [TT_EXTINT | 0x7] = "External Interrupt 7",
51 [TT_EXTINT | 0x8] = "External Interrupt 8",
52 [TT_EXTINT | 0x9] = "External Interrupt 9",
53 [TT_EXTINT | 0xa] = "External Interrupt 10",
54 [TT_EXTINT | 0xb] = "External Interrupt 11",
55 [TT_EXTINT | 0xc] = "External Interrupt 12",
56 [TT_EXTINT | 0xd] = "External Interrupt 13",
57 [TT_EXTINT | 0xe] = "External Interrupt 14",
58 [TT_EXTINT | 0xf] = "External Interrupt 15",
60 #endif
62 void do_interrupt(CPUSPARCState *env)
64 int intno = env->exception_index;
65 trap_state *tsptr;
67 #ifdef DEBUG_PCALL
68 if (qemu_loglevel_mask(CPU_LOG_INT)) {
69 static int count;
70 const char *name;
72 if (intno < 0 || intno >= 0x180) {
73 name = "Unknown";
74 } else if (intno >= 0x100) {
75 name = "Trap Instruction";
76 } else if (intno >= 0xc0) {
77 name = "Window Fill";
78 } else if (intno >= 0x80) {
79 name = "Window Spill";
80 } else {
81 name = excp_names[intno];
82 if (!name) {
83 name = "Unknown";
87 qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
88 log_cpu_state(env, 0);
89 #if 0
91 int i;
92 uint8_t *ptr;
94 qemu_log(" code=");
95 ptr = (uint8_t *)env->pc;
96 for (i = 0; i < 16; i++) {
97 qemu_log(" %02x", ldub(ptr + i));
99 qemu_log("\n");
101 #endif
102 count++;
104 #endif
105 #if !defined(CONFIG_USER_ONLY)
106 if (env->tl >= env->maxtl) {
107 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
108 " Error state", env->exception_index, env->tl, env->maxtl);
109 return;
111 #endif
112 if (env->tl < env->maxtl - 1) {
113 env->tl++;
114 } else {
115 env->pstate |= PS_RED;
116 if (env->tl < env->maxtl) {
117 env->tl++;
120 tsptr = cpu_tsptr(env);
122 tsptr->tstate = (cpu_get_ccr(env) << 32) |
123 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
124 cpu_get_cwp64(env);
125 tsptr->tpc = env->pc;
126 tsptr->tnpc = env->npc;
127 tsptr->tt = intno;
129 switch (intno) {
130 case TT_IVEC:
131 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
132 break;
133 case TT_TFAULT:
134 case TT_DFAULT:
135 case TT_TMISS ... TT_TMISS + 3:
136 case TT_DMISS ... TT_DMISS + 3:
137 case TT_DPROT ... TT_DPROT + 3:
138 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
139 break;
140 default:
141 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
142 break;
145 if (intno == TT_CLRWIN) {
146 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
147 } else if ((intno & 0x1c0) == TT_SPILL) {
148 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
149 } else if ((intno & 0x1c0) == TT_FILL) {
150 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
152 env->tbr &= ~0x7fffULL;
153 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
154 env->pc = env->tbr;
155 env->npc = env->pc + 4;
156 env->exception_index = -1;
159 trap_state *cpu_tsptr(CPUSPARCState* env)
161 return &env->ts[env->tl & MAXTL_MASK];
164 static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
166 if (env->softint != value) {
167 env->softint = value;
168 #if !defined(CONFIG_USER_ONLY)
169 if (cpu_interrupts_enabled(env)) {
170 cpu_check_irqs(env);
172 #endif
173 return true;
175 return false;
178 void helper_set_softint(CPUSPARCState *env, uint64_t value)
180 if (do_modify_softint(env, env->softint | (uint32_t)value)) {
181 trace_int_helper_set_softint(env->softint);
185 void helper_clear_softint(CPUSPARCState *env, uint64_t value)
187 if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
188 trace_int_helper_clear_softint(env->softint);
192 void helper_write_softint(CPUSPARCState *env, uint64_t value)
194 if (do_modify_softint(env, (uint32_t)value)) {
195 trace_int_helper_write_softint(env->softint);