target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/gdbstub.h"
  31 #include "qemu/host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 static struct XtensaConfigList *xtensa_cores;
  37
  38 static void xtensa_core_class_init(ObjectClass *oc, void *data)
  39 {
  40     CPUClass *cc = CPU_CLASS(oc);
  41     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
  42     const XtensaConfig *config = data;
  43
  44     xcc->config = config;
  45
  46     /* Use num_core_regs to see only non-privileged registers in an unmodified
  47      * gdb. Use num_regs to see all registers. gdb modification is required
  48      * for that: reset bit 0 in the 'flags' field of the registers definitions
  49      * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
  50      */
  51     cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
  52 }
  53
  54 void xtensa_register_core(XtensaConfigList *node)
  55 {
  56     TypeInfo type = {
  57         .parent = TYPE_XTENSA_CPU,
  58         .class_init = xtensa_core_class_init,
  59         .class_data = (void *)node->config,
  60     };
  61
  62     node->next = xtensa_cores;
  63     xtensa_cores = node;
  64     type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
  65     type_register(&type);
  66     g_free((gpointer)type.name);
  67 }
  68
  69 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  70 {
  71     unsigned i;
  72
  73     for (i = 0; i < env->config->ndbreak; ++i) {
  74         if (env->cpu_watchpoint[i] &&
  75                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  76             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  77         }
  78     }
  79     return 0;
  80 }
  81
  82 void xtensa_breakpoint_handler(CPUXtensaState *env)
  83 {
  84     CPUState *cs = CPU(xtensa_env_get_cpu(env));
  85
  86     if (cs->watchpoint_hit) {
  87         if (cs->watchpoint_hit->flags & BP_CPU) {
  88             uint32_t cause;
  89
  90             cs->watchpoint_hit = NULL;
  91             cause = check_hw_breakpoints(env);
  92             if (cause) {
  93                 debug_exception_env(env, cause);
  94             }
  95             cpu_resume_from_signal(cs, NULL);
  96         }
  97     }
  98 }
  99
 100 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
 101 {
 102     ObjectClass *oc;
 103     XtensaCPU *cpu;
 104     CPUXtensaState *env;
 105
 106     oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
 107     if (oc == NULL) {
 108         return NULL;
 109     }
 110
 111     cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
 112     env = &cpu->env;
 113
 114     xtensa_irq_init(env);
 115
 116     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 117
 118     return cpu;
 119 }
 120
 121
 122 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 123 {
 124     XtensaConfigList *core = xtensa_cores;
 125     cpu_fprintf(f, "Available CPUs:\n");
 126     for (; core; core = core->next) {
 127         cpu_fprintf(f, "  %s\n", core->config->name);
 128     }
 129 }
 130
 131 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 132 {
 133     XtensaCPU *cpu = XTENSA_CPU(cs);
 134     uint32_t paddr;
 135     uint32_t page_size;
 136     unsigned access;
 137
 138     if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
 139                 &paddr, &page_size, &access) == 0) {
 140         return paddr;
 141     }
 142     if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
 143                 &paddr, &page_size, &access) == 0) {
 144         return paddr;
 145     }
 146     return ~0;
 147 }
 148
 149 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 150 {
 151     if (xtensa_option_enabled(env->config,
 152                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 153         return vector - env->config->vecbase + env->sregs[VECBASE];
 154     } else {
 155         return vector;
 156     }
 157 }
 158
 159 /*!
 160  * Handle penging IRQ.
 161  * For the high priority interrupt jump to the corresponding interrupt vector.
 162  * For the level-1 interrupt convert it to either user, kernel or double
 163  * exception with the 'level-1 interrupt' exception cause.
 164  */
 165 static void handle_interrupt(CPUXtensaState *env)
 166 {
 167     int level = env->pending_irq_level;
 168
 169     if (level > xtensa_get_cintlevel(env) &&
 170             level <= env->config->nlevel &&
 171             (env->config->level_mask[level] &
 172              env->sregs[INTSET] &
 173              env->sregs[INTENABLE])) {
 174         CPUState *cs = CPU(xtensa_env_get_cpu(env));
 175
 176         if (level > 1) {
 177             env->sregs[EPC1 + level - 1] = env->pc;
 178             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 179             env->sregs[PS] =
 180                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 181             env->pc = relocated_vector(env,
 182                     env->config->interrupt_vector[level]);
 183         } else {
 184             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 185
 186             if (env->sregs[PS] & PS_EXCM) {
 187                 if (env->config->ndepc) {
 188                     env->sregs[DEPC] = env->pc;
 189                 } else {
 190                     env->sregs[EPC1] = env->pc;
 191                 }
 192                 cs->exception_index = EXC_DOUBLE;
 193             } else {
 194                 env->sregs[EPC1] = env->pc;
 195                 cs->exception_index =
 196                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 197             }
 198             env->sregs[PS] |= PS_EXCM;
 199         }
 200         env->exception_taken = 1;
 201     }
 202 }
 203
 204 void xtensa_cpu_do_interrupt(CPUState *cs)
 205 {
 206     XtensaCPU *cpu = XTENSA_CPU(cs);
 207     CPUXtensaState *env = &cpu->env;
 208
 209     if (cs->exception_index == EXC_IRQ) {
 210         qemu_log_mask(CPU_LOG_INT,
 211                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 212                 "pc = %08x, a0 = %08x, ps = %08x, "
 213                 "intset = %08x, intenable = %08x, "
 214                 "ccount = %08x\n",
 215                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 216                 env->pc, env->regs[0], env->sregs[PS],
 217                 env->sregs[INTSET], env->sregs[INTENABLE],
 218                 env->sregs[CCOUNT]);
 219         handle_interrupt(env);
 220     }
 221
 222     switch (cs->exception_index) {
 223     case EXC_WINDOW_OVERFLOW4:
 224     case EXC_WINDOW_UNDERFLOW4:
 225     case EXC_WINDOW_OVERFLOW8:
 226     case EXC_WINDOW_UNDERFLOW8:
 227     case EXC_WINDOW_OVERFLOW12:
 228     case EXC_WINDOW_UNDERFLOW12:
 229     case EXC_KERNEL:
 230     case EXC_USER:
 231     case EXC_DOUBLE:
 232     case EXC_DEBUG:
 233         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 234                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 235                 __func__, cs->exception_index,
 236                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 237         if (env->config->exception_vector[cs->exception_index]) {
 238             env->pc = relocated_vector(env,
 239                     env->config->exception_vector[cs->exception_index]);
 240             env->exception_taken = 1;
 241         } else {
 242             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 243                     __func__, env->pc, cs->exception_index);
 244         }
 245         break;
 246
 247     case EXC_IRQ:
 248         break;
 249
 250     default:
 251         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 252                 __func__, env->pc, cs->exception_index);
 253         break;
 254     }
 255     check_interrupts(env);
 256 }
 257
 258 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 259         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 260 {
 261     unsigned wi, ei;
 262
 263     for (wi = 0; wi < tlb->nways; ++wi) {
 264         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 265             entry[wi][ei].asid = 0;
 266             entry[wi][ei].variable = true;
 267         }
 268     }
 269 }
 270
 271 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 272         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 273 {
 274     if (!tlb->varway56) {
 275         static const xtensa_tlb_entry way5[] = {
 276             {
 277                 .vaddr = 0xd0000000,
 278                 .paddr = 0,
 279                 .asid = 1,
 280                 .attr = 7,
 281                 .variable = false,
 282             }, {
 283                 .vaddr = 0xd8000000,
 284                 .paddr = 0,
 285                 .asid = 1,
 286                 .attr = 3,
 287                 .variable = false,
 288             }
 289         };
 290         static const xtensa_tlb_entry way6[] = {
 291             {
 292                 .vaddr = 0xe0000000,
 293                 .paddr = 0xf0000000,
 294                 .asid = 1,
 295                 .attr = 7,
 296                 .variable = false,
 297             }, {
 298                 .vaddr = 0xf0000000,
 299                 .paddr = 0xf0000000,
 300                 .asid = 1,
 301                 .attr = 3,
 302                 .variable = false,
 303             }
 304         };
 305         memcpy(entry[5], way5, sizeof(way5));
 306         memcpy(entry[6], way6, sizeof(way6));
 307     } else {
 308         uint32_t ei;
 309         for (ei = 0; ei < 8; ++ei) {
 310             entry[6][ei].vaddr = ei << 29;
 311             entry[6][ei].paddr = ei << 29;
 312             entry[6][ei].asid = 1;
 313             entry[6][ei].attr = 3;
 314         }
 315     }
 316 }
 317
 318 static void reset_tlb_region_way0(CPUXtensaState *env,
 319         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 320 {
 321     unsigned ei;
 322
 323     for (ei = 0; ei < 8; ++ei) {
 324         entry[0][ei].vaddr = ei << 29;
 325         entry[0][ei].paddr = ei << 29;
 326         entry[0][ei].asid = 1;
 327         entry[0][ei].attr = 2;
 328         entry[0][ei].variable = true;
 329     }
 330 }
 331
 332 void reset_mmu(CPUXtensaState *env)
 333 {
 334     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 335         env->sregs[RASID] = 0x04030201;
 336         env->sregs[ITLBCFG] = 0;
 337         env->sregs[DTLBCFG] = 0;
 338         env->autorefill_idx = 0;
 339         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 340         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 341         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 342         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 343     } else {
 344         reset_tlb_region_way0(env, env->itlb);
 345         reset_tlb_region_way0(env, env->dtlb);
 346     }
 347 }
 348
 349 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 350 {
 351     unsigned i;
 352     for (i = 0; i < 4; ++i) {
 353         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 354             return i;
 355         }
 356     }
 357     return 0xff;
 358 }
 359
 360 /*!
 361  * Lookup xtensa TLB for the given virtual address.
 362  * See ISA, 4.6.2.2
 363  *
 364  * \param pwi: [out] way index
 365  * \param pei: [out] entry index
 366  * \param pring: [out] access ring
 367  * \return 0 if ok, exception cause code otherwise
 368  */
 369 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 370         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 371 {
 372     const xtensa_tlb *tlb = dtlb ?
 373         &env->config->dtlb : &env->config->itlb;
 374     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 375         env->dtlb : env->itlb;
 376
 377     int nhits = 0;
 378     unsigned wi;
 379
 380     for (wi = 0; wi < tlb->nways; ++wi) {
 381         uint32_t vpn;
 382         uint32_t ei;
 383         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 384         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 385             unsigned ring = get_ring(env, entry[wi][ei].asid);
 386             if (ring < 4) {
 387                 if (++nhits > 1) {
 388                     return dtlb ?
 389                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 390                         INST_TLB_MULTI_HIT_CAUSE;
 391                 }
 392                 *pwi = wi;
 393                 *pei = ei;
 394                 *pring = ring;
 395             }
 396         }
 397     }
 398     return nhits ? 0 :
 399         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 400 }
 401
 402 /*!
 403  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 404  * See ISA, 4.6.5.10
 405  */
 406 static unsigned mmu_attr_to_access(uint32_t attr)
 407 {
 408     unsigned access = 0;
 409
 410     if (attr < 12) {
 411         access |= PAGE_READ;
 412         if (attr & 0x1) {
 413             access |= PAGE_EXEC;
 414         }
 415         if (attr & 0x2) {
 416             access |= PAGE_WRITE;
 417         }
 418
 419         switch (attr & 0xc) {
 420         case 0:
 421             access |= PAGE_CACHE_BYPASS;
 422             break;
 423
 424         case 4:
 425             access |= PAGE_CACHE_WB;
 426             break;
 427
 428         case 8:
 429             access |= PAGE_CACHE_WT;
 430             break;
 431         }
 432     } else if (attr == 13) {
 433         access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
 434     }
 435     return access;
 436 }
 437
 438 /*!
 439  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 440  * See ISA, 4.6.3.3
 441  */
 442 static unsigned region_attr_to_access(uint32_t attr)
 443 {
 444     static const unsigned access[16] = {
 445          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 446          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 447          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 448          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 449          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 450          [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 451         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 452     };
 453
 454     return access[attr & 0xf];
 455 }
 456
 457 /*!
 458  * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
 459  * See ISA, A.2.14 The Cache Attribute Register
 460  */
 461 static unsigned cacheattr_attr_to_access(uint32_t attr)
 462 {
 463     static const unsigned access[16] = {
 464          [0] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_WT,
 465          [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
 466          [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
 467          [3] =                          PAGE_EXEC | PAGE_CACHE_WB,
 468          [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
 469         [14] = PAGE_READ | PAGE_WRITE             | PAGE_CACHE_ISOLATE,
 470     };
 471
 472     return access[attr & 0xf];
 473 }
 474
 475 static bool is_access_granted(unsigned access, int is_write)
 476 {
 477     switch (is_write) {
 478     case 0:
 479         return access & PAGE_READ;
 480
 481     case 1:
 482         return access & PAGE_WRITE;
 483
 484     case 2:
 485         return access & PAGE_EXEC;
 486
 487     default:
 488         return 0;
 489     }
 490 }
 491
 492 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
 493
 494 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
 495         uint32_t vaddr, int is_write, int mmu_idx,
 496         uint32_t *paddr, uint32_t *page_size, unsigned *access,
 497         bool may_lookup_pt)
 498 {
 499     bool dtlb = is_write != 2;
 500     uint32_t wi;
 501     uint32_t ei;
 502     uint8_t ring;
 503     uint32_t vpn;
 504     uint32_t pte;
 505     const xtensa_tlb_entry *entry = NULL;
 506     xtensa_tlb_entry tmp_entry;
 507     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 508
 509     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 510             may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
 511         ring = (pte >> 4) & 0x3;
 512         wi = 0;
 513         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
 514
 515         if (update_tlb) {
 516             wi = ++env->autorefill_idx & 0x3;
 517             xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
 518             env->sregs[EXCVADDR] = vaddr;
 519             qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
 520                     __func__, vaddr, vpn, pte);
 521         } else {
 522             xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
 523             entry = &tmp_entry;
 524         }
 525         ret = 0;
 526     }
 527     if (ret != 0) {
 528         return ret;
 529     }
 530
 531     if (entry == NULL) {
 532         entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 533     }
 534
 535     if (ring < mmu_idx) {
 536         return dtlb ?
 537             LOAD_STORE_PRIVILEGE_CAUSE :
 538             INST_FETCH_PRIVILEGE_CAUSE;
 539     }
 540
 541     *access = mmu_attr_to_access(entry->attr) &
 542         ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
 543     if (!is_access_granted(*access, is_write)) {
 544         return dtlb ?
 545             (is_write ?
 546              STORE_PROHIBITED_CAUSE :
 547              LOAD_PROHIBITED_CAUSE) :
 548             INST_FETCH_PROHIBITED_CAUSE;
 549     }
 550
 551     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 552     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 553
 554     return 0;
 555 }
 556
 557 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
 558 {
 559     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 560     uint32_t paddr;
 561     uint32_t page_size;
 562     unsigned access;
 563     uint32_t pt_vaddr =
 564         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 565     int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
 566             &paddr, &page_size, &access, false);
 567
 568     qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
 569             vaddr, ret ? ~0 : paddr);
 570
 571     if (ret == 0) {
 572         *pte = ldl_phys(cs->as, paddr);
 573     }
 574     return ret;
 575 }
 576
 577 static int get_physical_addr_region(CPUXtensaState *env,
 578         uint32_t vaddr, int is_write, int mmu_idx,
 579         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 580 {
 581     bool dtlb = is_write != 2;
 582     uint32_t wi = 0;
 583     uint32_t ei = (vaddr >> 29) & 0x7;
 584     const xtensa_tlb_entry *entry =
 585         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 586
 587     *access = region_attr_to_access(entry->attr);
 588     if (!is_access_granted(*access, is_write)) {
 589         return dtlb ?
 590             (is_write ?
 591              STORE_PROHIBITED_CAUSE :
 592              LOAD_PROHIBITED_CAUSE) :
 593             INST_FETCH_PROHIBITED_CAUSE;
 594     }
 595
 596     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 597     *page_size = ~REGION_PAGE_MASK + 1;
 598
 599     return 0;
 600 }
 601
 602 /*!
 603  * Convert virtual address to physical addr.
 604  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 605  *
 606  * \return 0 if ok, exception cause code otherwise
 607  */
 608 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 609         uint32_t vaddr, int is_write, int mmu_idx,
 610         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 611 {
 612     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 613         return get_physical_addr_mmu(env, update_tlb,
 614                 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
 615     } else if (xtensa_option_bits_enabled(env->config,
 616                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 617                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 618         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 619                 paddr, page_size, access);
 620     } else {
 621         *paddr = vaddr;
 622         *page_size = TARGET_PAGE_SIZE;
 623         *access = cacheattr_attr_to_access(
 624                 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
 625         return 0;
 626     }
 627 }
 628
 629 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 630         CPUXtensaState *env, bool dtlb)
 631 {
 632     unsigned wi, ei;
 633     const xtensa_tlb *conf =
 634         dtlb ? &env->config->dtlb : &env->config->itlb;
 635     unsigned (*attr_to_access)(uint32_t) =
 636         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 637         mmu_attr_to_access : region_attr_to_access;
 638
 639     for (wi = 0; wi < conf->nways; ++wi) {
 640         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 641         const char *sz_text;
 642         bool print_header = true;
 643
 644         if (sz >= 0x100000) {
 645             sz >>= 20;
 646             sz_text = "MB";
 647         } else {
 648             sz >>= 10;
 649             sz_text = "KB";
 650         }
 651
 652         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 653             const xtensa_tlb_entry *entry =
 654                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 655
 656             if (entry->asid) {
 657                 static const char * const cache_text[8] = {
 658                     [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
 659                     [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
 660                     [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
 661                     [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
 662                 };
 663                 unsigned access = attr_to_access(entry->attr);
 664                 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
 665                     PAGE_CACHE_SHIFT;
 666
 667                 if (print_header) {
 668                     print_header = false;
 669                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 670                     cpu_fprintf(f,
 671                             "\tVaddr       Paddr       ASID  Attr RWX Cache\n"
 672                             "\t----------  ----------  ----  ---- --- -------\n");
 673                 }
 674                 cpu_fprintf(f,
 675                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c %-7s\n",
 676                         entry->vaddr,
 677                         entry->paddr,
 678                         entry->asid,
 679                         entry->attr,
 680                         (access & PAGE_READ) ? 'R' : '-',
 681                         (access & PAGE_WRITE) ? 'W' : '-',
 682                         (access & PAGE_EXEC) ? 'X' : '-',
 683                         cache_text[cache_idx] ? cache_text[cache_idx] :
 684                             "Invalid");
 685             }
 686         }
 687     }
 688 }
 689
 690 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 691 {
 692     if (xtensa_option_bits_enabled(env->config,
 693                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 694                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 695                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 696
 697         cpu_fprintf(f, "ITLB:\n");
 698         dump_tlb(f, cpu_fprintf, env, false);
 699         cpu_fprintf(f, "\nDTLB:\n");
 700         dump_tlb(f, cpu_fprintf, env, true);
 701     } else {
 702         cpu_fprintf(f, "No TLB for this CPU core\n");
 703     }
 704 }