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Call kvm_cpu_synchronize_state() on target vcpu
[qemu-kvm.git] / qemu-kvm-x86.c
blobf80d82bf8725b5b96582ff67f8469141893593f9
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
44 if (r < 0) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return r;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfeffd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, uint64_t addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfeffc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 return 0;
161 }
162
163 #ifdef KVM_EXIT_TPR_ACCESS
164
165 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
166 {
167 struct kvm_run *run = vcpu->run;
168 kvm_tpr_access_report(cpu_single_env,
169 run->tpr_access.rip,
170 run->tpr_access.is_write);
171 return 0;
172 }
173
174
175 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
176 {
177 int r;
178 struct kvm_vapic_addr va = {
179 .vapic_addr = vapic,
180 };
181
182 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
183 if (r == -1) {
184 r = -errno;
185 perror("kvm_enable_vapic");
186 return r;
187 }
188 return 0;
189 }
190
191 #endif
192
193 int kvm_arch_run(kvm_vcpu_context_t vcpu)
194 {
195 int r = 0;
196 struct kvm_run *run = vcpu->run;
197
198
199 switch (run->exit_reason) {
200 #ifdef KVM_EXIT_SET_TPR
201 case KVM_EXIT_SET_TPR:
202 break;
203 #endif
204 #ifdef KVM_EXIT_TPR_ACCESS
205 case KVM_EXIT_TPR_ACCESS:
206 r = kvm_handle_tpr_access(vcpu);
207 break;
208 #endif
209 default:
210 r = 1;
211 break;
212 }
213
214 return r;
215 }
216
217 #define MAX_ALIAS_SLOTS 4
218 static struct {
219 uint64_t start;
220 uint64_t len;
221 } kvm_aliases[MAX_ALIAS_SLOTS];
222
223 static int get_alias_slot(uint64_t start)
224 {
225 int i;
226
227 for (i=0; i<MAX_ALIAS_SLOTS; i++)
228 if (kvm_aliases[i].start == start)
229 return i;
230 return -1;
231 }
232 static int get_free_alias_slot(void)
233 {
234 int i;
235
236 for (i=0; i<MAX_ALIAS_SLOTS; i++)
237 if (kvm_aliases[i].len == 0)
238 return i;
239 return -1;
240 }
241
242 static void register_alias(int slot, uint64_t start, uint64_t len)
243 {
244 kvm_aliases[slot].start = start;
245 kvm_aliases[slot].len = len;
246 }
247
248 int kvm_create_memory_alias(kvm_context_t kvm,
249 uint64_t phys_start,
250 uint64_t len,
251 uint64_t target_phys)
252 {
253 struct kvm_memory_alias alias = {
254 .flags = 0,
255 .guest_phys_addr = phys_start,
256 .memory_size = len,
257 .target_phys_addr = target_phys,
258 };
259 int r;
260 int slot;
261
262 slot = get_alias_slot(phys_start);
263 if (slot < 0)
264 slot = get_free_alias_slot();
265 if (slot < 0)
266 return -EBUSY;
267 alias.slot = slot;
268
269 r = kvm_vm_ioctl(kvm_state, KVM_SET_MEMORY_ALIAS, &alias);
270 if (r == -1)
271 return -errno;
272
273 register_alias(slot, phys_start, len);
274 return 0;
275 }
276
277 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
278 {
279 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
280 }
281
282 #ifdef KVM_CAP_IRQCHIP
283
284 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
285 {
286 int r;
287 if (!kvm_irqchip_in_kernel(vcpu->kvm))
288 return 0;
289 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
290 if (r == -1) {
291 r = -errno;
292 perror("kvm_get_lapic");
293 }
294 return r;
295 }
296
297 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
298 {
299 int r;
300 if (!kvm_irqchip_in_kernel(vcpu->kvm))
301 return 0;
302 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
303 if (r == -1) {
304 r = -errno;
305 perror("kvm_set_lapic");
306 }
307 return r;
308 }
309
310 #endif
311
312 #ifdef KVM_CAP_PIT
313
314 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
315 {
316 if (!kvm->pit_in_kernel)
317 return 0;
318 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
319 }
320
321 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
322 {
323 if (!kvm->pit_in_kernel)
324 return 0;
325 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
326 }
327
328 #ifdef KVM_CAP_PIT_STATE2
329 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
330 {
331 if (!kvm->pit_in_kernel)
332 return 0;
333 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
334 }
335
336 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
337 {
338 if (!kvm->pit_in_kernel)
339 return 0;
340 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
341 }
342
343 #endif
344 #endif
345
346 int kvm_has_pit_state2(kvm_context_t kvm)
347 {
348 int r = 0;
349
350 #ifdef KVM_CAP_PIT_STATE2
351 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
352 #endif
353 return r;
354 }
355
356 void kvm_show_code(kvm_vcpu_context_t vcpu)
357 {
358 #define SHOW_CODE_LEN 50
359 int fd = vcpu->fd;
360 struct kvm_regs regs;
361 struct kvm_sregs sregs;
362 int r, n;
363 int back_offset;
364 unsigned char code;
365 char code_str[SHOW_CODE_LEN * 3 + 1];
366 unsigned long rip;
367 kvm_context_t kvm = vcpu->kvm;
368
369 r = ioctl(fd, KVM_GET_SREGS, &sregs);
370 if (r == -1) {
371 perror("KVM_GET_SREGS");
372 return;
373 }
374 r = ioctl(fd, KVM_GET_REGS, &regs);
375 if (r == -1) {
376 perror("KVM_GET_REGS");
377 return;
378 }
379 rip = sregs.cs.base + regs.rip;
380 back_offset = regs.rip;
381 if (back_offset > 20)
382 back_offset = 20;
383 *code_str = 0;
384 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
385 if (n == 0)
386 strcat(code_str, " -->");
387 r = kvm_mmio_read(kvm->opaque, rip + n, &code, 1);
388 if (r < 0) {
389 strcat(code_str, " xx");
390 continue;
391 }
392 sprintf(code_str + strlen(code_str), " %02x", code);
393 }
394 fprintf(stderr, "code:%s\n", code_str);
395 }
396
397
398 /*
399 * Returns available msr list. User must free.
400 */
401 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
402 {
403 struct kvm_msr_list sizer, *msrs;
404 int r;
405
406 sizer.nmsrs = 0;
407 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
408 if (r < 0 && r != -E2BIG)
409 return NULL;
410 /* Old kernel modules had a bug and could write beyond the provided
411 memory. Allocate at least a safe amount of 1K. */
412 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
413 sizer.nmsrs * sizeof(*msrs->indices)));
414
415 msrs->nmsrs = sizer.nmsrs;
416 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
417 if (r < 0) {
418 free(msrs);
419 errno = r;
420 return NULL;
421 }
422 return msrs;
423 }
424
425 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
426 {
427 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
428 int r, e;
429
430 kmsrs->nmsrs = n;
431 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
432 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
433 e = errno;
434 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
435 free(kmsrs);
436 errno = e;
437 return r;
438 }
439
440 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
441 {
442 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
443 int r, e;
444
445 kmsrs->nmsrs = n;
446 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
447 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
448 e = errno;
449 free(kmsrs);
450 errno = e;
451 return r;
452 }
453
454 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
455 int *max_banks)
456 {
457 #ifdef KVM_CAP_MCE
458 int r;
459
460 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
461 if (r > 0) {
462 *max_banks = r;
463 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
464 }
465 #endif
466 return -ENOSYS;
467 }
468
469 int kvm_setup_mce(kvm_vcpu_context_t vcpu, uint64_t *mcg_cap)
470 {
471 #ifdef KVM_CAP_MCE
472 return ioctl(vcpu->fd, KVM_X86_SETUP_MCE, mcg_cap);
473 #else
474 return -ENOSYS;
475 #endif
476 }
477
478 int kvm_set_mce(kvm_vcpu_context_t vcpu, struct kvm_x86_mce *m)
479 {
480 #ifdef KVM_CAP_MCE
481 return ioctl(vcpu->fd, KVM_X86_SET_MCE, m);
482 #else
483 return -ENOSYS;
484 #endif
485 }
486
487 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
488 {
489 fprintf(stderr,
490 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
491 " g %d avl %d)\n",
492 name, seg->selector, seg->base, seg->limit, seg->present,
493 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
494 seg->avl);
495 }
496
497 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
498 {
499 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
500 }
501
502 void kvm_show_regs(kvm_vcpu_context_t vcpu)
503 {
504 int fd = vcpu->fd;
505 struct kvm_regs regs;
506 struct kvm_sregs sregs;
507 int r;
508
509 r = ioctl(fd, KVM_GET_REGS, &regs);
510 if (r == -1) {
511 perror("KVM_GET_REGS");
512 return;
513 }
514 fprintf(stderr,
515 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
516 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
517 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
518 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
519 "rip %016llx rflags %08llx\n",
520 regs.rax, regs.rbx, regs.rcx, regs.rdx,
521 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
522 regs.r8, regs.r9, regs.r10, regs.r11,
523 regs.r12, regs.r13, regs.r14, regs.r15,
524 regs.rip, regs.rflags);
525 r = ioctl(fd, KVM_GET_SREGS, &sregs);
526 if (r == -1) {
527 perror("KVM_GET_SREGS");
528 return;
529 }
530 print_seg(stderr, "cs", &sregs.cs);
531 print_seg(stderr, "ds", &sregs.ds);
532 print_seg(stderr, "es", &sregs.es);
533 print_seg(stderr, "ss", &sregs.ss);
534 print_seg(stderr, "fs", &sregs.fs);
535 print_seg(stderr, "gs", &sregs.gs);
536 print_seg(stderr, "tr", &sregs.tr);
537 print_seg(stderr, "ldt", &sregs.ldt);
538 print_dt(stderr, "gdt", &sregs.gdt);
539 print_dt(stderr, "idt", &sregs.idt);
540 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
541 " efer %llx\n",
542 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
543 sregs.efer);
544 }
545
546 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
547 {
548 return vcpu->run->apic_base;
549 }
550
551 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
552 {
553 vcpu->run->cr8 = cr8;
554 }
555
556 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
557 {
558 return vcpu->run->cr8;
559 }
560
561 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
562 struct kvm_cpuid_entry *entries)
563 {
564 struct kvm_cpuid *cpuid;
565 int r;
566
567 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
568
569 cpuid->nent = nent;
570 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
571 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
572
573 free(cpuid);
574 return r;
575 }
576
577 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
578 struct kvm_cpuid_entry2 *entries)
579 {
580 struct kvm_cpuid2 *cpuid;
581 int r;
582
583 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
584
585 cpuid->nent = nent;
586 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
587 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
588 if (r == -1) {
589 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
590 r = -errno;
591 }
592 free(cpuid);
593 return r;
594 }
595
596 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
597 {
598 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
599 int r;
600
601 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
602 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
603 if (r > 0) {
604 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
605 if (r < 0) {
606 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
607 return r;
608 }
609 return 0;
610 }
611 #endif
612 return -1;
613 }
614
615 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
616 {
617 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
618 int r;
619
620 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
621 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
622 if (r > 0) {
623 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
624 return 0;
625 }
626 #endif
627 return -1;
628 }
629
630 #ifdef KVM_CAP_VAPIC
631
632 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
633 {
634 int r;
635 struct kvm_tpr_access_ctl tac = {
636 .enabled = enabled,
637 };
638
639 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
640 if (r <= 0)
641 return -ENOSYS;
642 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
643 if (r == -1) {
644 r = -errno;
645 perror("KVM_TPR_ACCESS_REPORTING");
646 return r;
647 }
648 return 0;
649 }
650
651 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
652 {
653 return tpr_access_reporting(vcpu, 1);
654 }
655
656 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
657 {
658 return tpr_access_reporting(vcpu, 0);
659 }
660
661 #endif
662
663 #ifdef KVM_CAP_EXT_CPUID
664
665 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
666 {
667 struct kvm_cpuid2 *cpuid;
668 int r, size;
669
670 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
671 cpuid = qemu_malloc(size);
672 cpuid->nent = max;
673 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_CPUID, cpuid);
674 if (r == 0 && cpuid->nent >= max)
675 r = -E2BIG;
676 if (r < 0) {
677 if (r == -E2BIG) {
678 free(cpuid);
679 return NULL;
680 } else {
681 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
682 strerror(-r));
683 exit(1);
684 }
685 }
686 return cpuid;
687 }
688
689 #define R_EAX 0
690 #define R_ECX 1
691 #define R_EDX 2
692 #define R_EBX 3
693 #define R_ESP 4
694 #define R_EBP 5
695 #define R_ESI 6
696 #define R_EDI 7
697
698 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
699 {
700 struct kvm_cpuid2 *cpuid;
701 int i, max;
702 uint32_t ret = 0;
703 uint32_t cpuid_1_edx;
704
705 if (!kvm_check_extension(kvm_state, KVM_CAP_EXT_CPUID)) {
706 return -1U;
707 }
708
709 max = 1;
710 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
711 max *= 2;
712 }
713
714 for (i = 0; i < cpuid->nent; ++i) {
715 if (cpuid->entries[i].function == function) {
716 switch (reg) {
717 case R_EAX:
718 ret = cpuid->entries[i].eax;
719 break;
720 case R_EBX:
721 ret = cpuid->entries[i].ebx;
722 break;
723 case R_ECX:
724 ret = cpuid->entries[i].ecx;
725 break;
726 case R_EDX:
727 ret = cpuid->entries[i].edx;
728 if (function == 1) {
729 /* kvm misreports the following features
730 */
731 ret |= 1 << 12; /* MTRR */
732 ret |= 1 << 16; /* PAT */
733 ret |= 1 << 7; /* MCE */
734 ret |= 1 << 14; /* MCA */
735 }
736
737 /* On Intel, kvm returns cpuid according to
738 * the Intel spec, so add missing bits
739 * according to the AMD spec:
740 */
741 if (function == 0x80000001) {
742 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
743 ret |= cpuid_1_edx & 0xdfeff7ff;
744 }
745 break;
746 }
747 }
748 }
749
750 free(cpuid);
751
752 return ret;
753 }
754
755 #else
756
757 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
758 {
759 return -1U;
760 }
761
762 #endif
763 int kvm_qemu_create_memory_alias(uint64_t phys_start,
764 uint64_t len,
765 uint64_t target_phys)
766 {
767 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
768 }
769
770 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
771 {
772 return kvm_destroy_memory_alias(kvm_context, phys_start);
773 }
774
775 int kvm_arch_qemu_create_context(void)
776 {
777 int i;
778 struct utsname utsname;
779
780 uname(&utsname);
781 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
782
783 if (kvm_shadow_memory)
784 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
785
786 kvm_msr_list = kvm_get_msr_list(kvm_context);
787 if (!kvm_msr_list)
788 return -1;
789 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
790 if (kvm_msr_list->indices[i] == MSR_STAR)
791 kvm_has_msr_star = 1;
792 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
793 kvm_has_vm_hsave_pa = 1;
794 }
795
796 return 0;
797 }
798
799 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
800 uint64_t data)
801 {
802 entry->index = index;
803 entry->data = data;
804 }
805
806 /* returns 0 on success, non-0 on failure */
807 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
808 {
809 switch (entry->index) {
810 case MSR_IA32_SYSENTER_CS:
811 env->sysenter_cs = entry->data;
812 break;
813 case MSR_IA32_SYSENTER_ESP:
814 env->sysenter_esp = entry->data;
815 break;
816 case MSR_IA32_SYSENTER_EIP:
817 env->sysenter_eip = entry->data;
818 break;
819 case MSR_STAR:
820 env->star = entry->data;
821 break;
822 #ifdef TARGET_X86_64
823 case MSR_CSTAR:
824 env->cstar = entry->data;
825 break;
826 case MSR_KERNELGSBASE:
827 env->kernelgsbase = entry->data;
828 break;
829 case MSR_FMASK:
830 env->fmask = entry->data;
831 break;
832 case MSR_LSTAR:
833 env->lstar = entry->data;
834 break;
835 #endif
836 case MSR_IA32_TSC:
837 env->tsc = entry->data;
838 break;
839 case MSR_VM_HSAVE_PA:
840 env->vm_hsave = entry->data;
841 break;
842 default:
843 printf("Warning unknown msr index 0x%x\n", entry->index);
844 return 1;
845 }
846 return 0;
847 }
848
849 #ifdef TARGET_X86_64
850 #define MSR_COUNT 9
851 #else
852 #define MSR_COUNT 5
853 #endif
854
855 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
856 {
857 lhs->selector = rhs->selector;
858 lhs->base = rhs->base;
859 lhs->limit = rhs->limit;
860 lhs->type = 3;
861 lhs->present = 1;
862 lhs->dpl = 3;
863 lhs->db = 0;
864 lhs->s = 1;
865 lhs->l = 0;
866 lhs->g = 0;
867 lhs->avl = 0;
868 lhs->unusable = 0;
869 }
870
871 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
872 {
873 unsigned flags = rhs->flags;
874 lhs->selector = rhs->selector;
875 lhs->base = rhs->base;
876 lhs->limit = rhs->limit;
877 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
878 lhs->present = (flags & DESC_P_MASK) != 0;
879 lhs->dpl = rhs->selector & 3;
880 lhs->db = (flags >> DESC_B_SHIFT) & 1;
881 lhs->s = (flags & DESC_S_MASK) != 0;
882 lhs->l = (flags >> DESC_L_SHIFT) & 1;
883 lhs->g = (flags & DESC_G_MASK) != 0;
884 lhs->avl = (flags & DESC_AVL_MASK) != 0;
885 lhs->unusable = 0;
886 }
887
888 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
889 {
890 lhs->selector = rhs->selector;
891 lhs->base = rhs->base;
892 lhs->limit = rhs->limit;
893 lhs->flags =
894 (rhs->type << DESC_TYPE_SHIFT)
895 | (rhs->present * DESC_P_MASK)
896 | (rhs->dpl << DESC_DPL_SHIFT)
897 | (rhs->db << DESC_B_SHIFT)
898 | (rhs->s * DESC_S_MASK)
899 | (rhs->l << DESC_L_SHIFT)
900 | (rhs->g * DESC_G_MASK)
901 | (rhs->avl * DESC_AVL_MASK);
902 }
903
904 void kvm_arch_load_regs(CPUState *env)
905 {
906 struct kvm_regs regs;
907 struct kvm_fpu fpu;
908 struct kvm_sregs sregs;
909 struct kvm_msr_entry msrs[MSR_COUNT];
910 int rc, n, i;
911
912 regs.rax = env->regs[R_EAX];
913 regs.rbx = env->regs[R_EBX];
914 regs.rcx = env->regs[R_ECX];
915 regs.rdx = env->regs[R_EDX];
916 regs.rsi = env->regs[R_ESI];
917 regs.rdi = env->regs[R_EDI];
918 regs.rsp = env->regs[R_ESP];
919 regs.rbp = env->regs[R_EBP];
920 #ifdef TARGET_X86_64
921 regs.r8 = env->regs[8];
922 regs.r9 = env->regs[9];
923 regs.r10 = env->regs[10];
924 regs.r11 = env->regs[11];
925 regs.r12 = env->regs[12];
926 regs.r13 = env->regs[13];
927 regs.r14 = env->regs[14];
928 regs.r15 = env->regs[15];
929 #endif
930
931 regs.rflags = env->eflags;
932 regs.rip = env->eip;
933
934 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
935
936 memset(&fpu, 0, sizeof fpu);
937 fpu.fsw = env->fpus & ~(7 << 11);
938 fpu.fsw |= (env->fpstt & 7) << 11;
939 fpu.fcw = env->fpuc;
940 for (i = 0; i < 8; ++i)
941 fpu.ftwx |= (!env->fptags[i]) << i;
942 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
943 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
944 fpu.mxcsr = env->mxcsr;
945 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
946
947 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
948
949 if ((env->eflags & VM_MASK)) {
950 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
951 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
952 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
953 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
954 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
955 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
956 } else {
957 set_seg(&sregs.cs, &env->segs[R_CS]);
958 set_seg(&sregs.ds, &env->segs[R_DS]);
959 set_seg(&sregs.es, &env->segs[R_ES]);
960 set_seg(&sregs.fs, &env->segs[R_FS]);
961 set_seg(&sregs.gs, &env->segs[R_GS]);
962 set_seg(&sregs.ss, &env->segs[R_SS]);
963
964 if (env->cr[0] & CR0_PE_MASK) {
965 /* force ss cpl to cs cpl */
966 sregs.ss.selector = (sregs.ss.selector & ~3) |
967 (sregs.cs.selector & 3);
968 sregs.ss.dpl = sregs.ss.selector & 3;
969 }
970 }
971
972 set_seg(&sregs.tr, &env->tr);
973 set_seg(&sregs.ldt, &env->ldt);
974
975 sregs.idt.limit = env->idt.limit;
976 sregs.idt.base = env->idt.base;
977 sregs.gdt.limit = env->gdt.limit;
978 sregs.gdt.base = env->gdt.base;
979
980 sregs.cr0 = env->cr[0];
981 sregs.cr2 = env->cr[2];
982 sregs.cr3 = env->cr[3];
983 sregs.cr4 = env->cr[4];
984
985 sregs.cr8 = cpu_get_apic_tpr(env);
986 sregs.apic_base = cpu_get_apic_base(env);
987
988 sregs.efer = env->efer;
989
990 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
991
992 /* msrs */
993 n = 0;
994 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
995 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
996 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
997 if (kvm_has_msr_star)
998 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
999 if (kvm_has_vm_hsave_pa)
1000 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1001 #ifdef TARGET_X86_64
1002 if (lm_capable_kernel) {
1003 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
1004 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1005 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
1006 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
1007 }
1008 #endif
1009
1010 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1011 if (rc == -1)
1012 perror("kvm_set_msrs FAILED");
1013 }
1014
1015 void kvm_load_tsc(CPUState *env)
1016 {
1017 int rc;
1018 struct kvm_msr_entry msr;
1019
1020 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
1021
1022 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
1023 if (rc == -1)
1024 perror("kvm_set_tsc FAILED.\n");
1025 }
1026
1027 void kvm_arch_save_mpstate(CPUState *env)
1028 {
1029 #ifdef KVM_CAP_MP_STATE
1030 int r;
1031 struct kvm_mp_state mp_state;
1032
1033 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1034 if (r < 0)
1035 env->mp_state = -1;
1036 else
1037 env->mp_state = mp_state.mp_state;
1038 #else
1039 env->mp_state = -1;
1040 #endif
1041 }
1042
1043 void kvm_arch_load_mpstate(CPUState *env)
1044 {
1045 #ifdef KVM_CAP_MP_STATE
1046 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1047
1048 /*
1049 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1050 * so don't touch it.
1051 */
1052 if (env->mp_state != -1)
1053 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1054 #endif
1055 }
1056
1057 void kvm_arch_save_regs(CPUState *env)
1058 {
1059 struct kvm_regs regs;
1060 struct kvm_fpu fpu;
1061 struct kvm_sregs sregs;
1062 struct kvm_msr_entry msrs[MSR_COUNT];
1063 uint32_t hflags;
1064 uint32_t i, n, rc;
1065
1066 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
1067
1068 env->regs[R_EAX] = regs.rax;
1069 env->regs[R_EBX] = regs.rbx;
1070 env->regs[R_ECX] = regs.rcx;
1071 env->regs[R_EDX] = regs.rdx;
1072 env->regs[R_ESI] = regs.rsi;
1073 env->regs[R_EDI] = regs.rdi;
1074 env->regs[R_ESP] = regs.rsp;
1075 env->regs[R_EBP] = regs.rbp;
1076 #ifdef TARGET_X86_64
1077 env->regs[8] = regs.r8;
1078 env->regs[9] = regs.r9;
1079 env->regs[10] = regs.r10;
1080 env->regs[11] = regs.r11;
1081 env->regs[12] = regs.r12;
1082 env->regs[13] = regs.r13;
1083 env->regs[14] = regs.r14;
1084 env->regs[15] = regs.r15;
1085 #endif
1086
1087 env->eflags = regs.rflags;
1088 env->eip = regs.rip;
1089
1090 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1091 env->fpstt = (fpu.fsw >> 11) & 7;
1092 env->fpus = fpu.fsw;
1093 env->fpuc = fpu.fcw;
1094 for (i = 0; i < 8; ++i)
1095 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1096 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1097 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1098 env->mxcsr = fpu.mxcsr;
1099
1100 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1101
1102 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1103
1104 get_seg(&env->segs[R_CS], &sregs.cs);
1105 get_seg(&env->segs[R_DS], &sregs.ds);
1106 get_seg(&env->segs[R_ES], &sregs.es);
1107 get_seg(&env->segs[R_FS], &sregs.fs);
1108 get_seg(&env->segs[R_GS], &sregs.gs);
1109 get_seg(&env->segs[R_SS], &sregs.ss);
1110
1111 get_seg(&env->tr, &sregs.tr);
1112 get_seg(&env->ldt, &sregs.ldt);
1113
1114 env->idt.limit = sregs.idt.limit;
1115 env->idt.base = sregs.idt.base;
1116 env->gdt.limit = sregs.gdt.limit;
1117 env->gdt.base = sregs.gdt.base;
1118
1119 env->cr[0] = sregs.cr0;
1120 env->cr[2] = sregs.cr2;
1121 env->cr[3] = sregs.cr3;
1122 env->cr[4] = sregs.cr4;
1123
1124 cpu_set_apic_base(env, sregs.apic_base);
1125
1126 env->efer = sregs.efer;
1127 //cpu_set_apic_tpr(env, sregs.cr8);
1128
1129 #define HFLAG_COPY_MASK ~( \
1130 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1131 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1132 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1133 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1134
1135
1136
1137 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1138 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1139 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1140 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1141 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1142 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1143 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1144
1145 if (env->efer & MSR_EFER_LMA) {
1146 hflags |= HF_LMA_MASK;
1147 }
1148
1149 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1150 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1151 } else {
1152 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1153 (DESC_B_SHIFT - HF_CS32_SHIFT);
1154 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1155 (DESC_B_SHIFT - HF_SS32_SHIFT);
1156 if (!(env->cr[0] & CR0_PE_MASK) ||
1157 (env->eflags & VM_MASK) ||
1158 !(hflags & HF_CS32_MASK)) {
1159 hflags |= HF_ADDSEG_MASK;
1160 } else {
1161 hflags |= ((env->segs[R_DS].base |
1162 env->segs[R_ES].base |
1163 env->segs[R_SS].base) != 0) <<
1164 HF_ADDSEG_SHIFT;
1165 }
1166 }
1167 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1168
1169 /* msrs */
1170 n = 0;
1171 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1172 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1173 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1174 if (kvm_has_msr_star)
1175 msrs[n++].index = MSR_STAR;
1176 msrs[n++].index = MSR_IA32_TSC;
1177 if (kvm_has_vm_hsave_pa)
1178 msrs[n++].index = MSR_VM_HSAVE_PA;
1179 #ifdef TARGET_X86_64
1180 if (lm_capable_kernel) {
1181 msrs[n++].index = MSR_CSTAR;
1182 msrs[n++].index = MSR_KERNELGSBASE;
1183 msrs[n++].index = MSR_FMASK;
1184 msrs[n++].index = MSR_LSTAR;
1185 }
1186 #endif
1187 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1188 if (rc == -1) {
1189 perror("kvm_get_msrs FAILED");
1190 }
1191 else {
1192 n = rc; /* actual number of MSRs */
1193 for (i=0 ; i<n; i++) {
1194 if (get_msr_entry(&msrs[i], env))
1195 return;
1196 }
1197 }
1198 }
1199
1200 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1201 uint32_t count, CPUState *env)
1202 {
1203 env->regs[R_EAX] = function;
1204 env->regs[R_ECX] = count;
1205 qemu_kvm_cpuid_on_env(env);
1206 e->function = function;
1207 e->flags = 0;
1208 e->index = 0;
1209 e->eax = env->regs[R_EAX];
1210 e->ebx = env->regs[R_EBX];
1211 e->ecx = env->regs[R_ECX];
1212 e->edx = env->regs[R_EDX];
1213 }
1214
1215 struct kvm_para_features {
1216 int cap;
1217 int feature;
1218 } para_features[] = {
1219 #ifdef KVM_CAP_CLOCKSOURCE
1220 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1221 #endif
1222 #ifdef KVM_CAP_NOP_IO_DELAY
1223 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1224 #endif
1225 #ifdef KVM_CAP_PV_MMU
1226 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1227 #endif
1228 #ifdef KVM_CAP_CR3_CACHE
1229 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1230 #endif
1231 { -1, -1 }
1232 };
1233
1234 static int get_para_features(kvm_context_t kvm_context)
1235 {
1236 int i, features = 0;
1237
1238 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1239 if (kvm_check_extension(kvm_state, para_features[i].cap))
1240 features |= (1 << para_features[i].feature);
1241 }
1242
1243 return features;
1244 }
1245
1246 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1247 {
1248 int i;
1249 uint32_t mask;
1250
1251 for (i = 0; i < 32; ++i) {
1252 mask = 1U << i;
1253 if ((*features & mask) && !(supported & mask)) {
1254 *features &= ~mask;
1255 }
1256 }
1257 }
1258
1259 int kvm_arch_init_vcpu(CPUState *cenv)
1260 {
1261 struct kvm_cpuid_entry2 cpuid_ent[100];
1262 #ifdef KVM_CPUID_SIGNATURE
1263 struct kvm_cpuid_entry2 *pv_ent;
1264 uint32_t signature[3];
1265 #endif
1266 int cpuid_nent = 0;
1267 CPUState copy;
1268 uint32_t i, j, limit;
1269
1270 qemu_kvm_load_lapic(cenv);
1271
1272
1273 #ifdef KVM_CPUID_SIGNATURE
1274 /* Paravirtualization CPUIDs */
1275 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1276 pv_ent = &cpuid_ent[cpuid_nent++];
1277 memset(pv_ent, 0, sizeof(*pv_ent));
1278 pv_ent->function = KVM_CPUID_SIGNATURE;
1279 pv_ent->eax = 0;
1280 pv_ent->ebx = signature[0];
1281 pv_ent->ecx = signature[1];
1282 pv_ent->edx = signature[2];
1283
1284 pv_ent = &cpuid_ent[cpuid_nent++];
1285 memset(pv_ent, 0, sizeof(*pv_ent));
1286 pv_ent->function = KVM_CPUID_FEATURES;
1287 pv_ent->eax = get_para_features(kvm_context);
1288 #endif
1289
1290 kvm_trim_features(&cenv->cpuid_features,
1291 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1292
1293 /* prevent the hypervisor bit from being cleared by the kernel */
1294 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1295 kvm_trim_features(&cenv->cpuid_ext_features,
1296 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1297 cenv->cpuid_ext_features |= i;
1298
1299 kvm_trim_features(&cenv->cpuid_ext2_features,
1300 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1301 kvm_trim_features(&cenv->cpuid_ext3_features,
1302 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1303
1304 copy = *cenv;
1305
1306 copy.regs[R_EAX] = 0;
1307 qemu_kvm_cpuid_on_env(&copy);
1308 limit = copy.regs[R_EAX];
1309
1310 for (i = 0; i <= limit; ++i) {
1311 if (i == 4 || i == 0xb || i == 0xd) {
1312 for (j = 0; ; ++j) {
1313 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1314
1315 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1316 cpuid_ent[cpuid_nent].index = j;
1317
1318 cpuid_nent++;
1319
1320 if (i == 4 && copy.regs[R_EAX] == 0)
1321 break;
1322 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1323 break;
1324 if (i == 0xd && copy.regs[R_EAX] == 0)
1325 break;
1326 }
1327 } else
1328 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1329 }
1330
1331 copy.regs[R_EAX] = 0x80000000;
1332 qemu_kvm_cpuid_on_env(&copy);
1333 limit = copy.regs[R_EAX];
1334
1335 for (i = 0x80000000; i <= limit; ++i)
1336 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1337
1338 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1339
1340 #ifdef KVM_CAP_MCE
1341 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1342 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1343 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1344 uint64_t mcg_cap;
1345 int banks;
1346
1347 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1348 perror("kvm_get_mce_cap_supported FAILED");
1349 else {
1350 if (banks > MCE_BANKS_DEF)
1351 banks = MCE_BANKS_DEF;
1352 mcg_cap &= MCE_CAP_DEF;
1353 mcg_cap |= banks;
1354 if (kvm_setup_mce(cenv->kvm_cpu_state.vcpu_ctx, &mcg_cap))
1355 perror("kvm_setup_mce FAILED");
1356 else
1357 cenv->mcg_cap = mcg_cap;
1358 }
1359 }
1360 #endif
1361
1362 return 0;
1363 }
1364
1365 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1366 {
1367 CPUState *env = cpu_single_env;
1368
1369 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1370 (env->eflags & IF_MASK)) &&
1371 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1372 env->halted = 1;
1373 }
1374 return 1;
1375 }
1376
1377 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1378 {
1379 if (!kvm_irqchip_in_kernel(kvm_context))
1380 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1381 }
1382
1383 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1384 {
1385 cpu_single_env = env;
1386
1387 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1388 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1389
1390 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1391 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1392 }
1393
1394 int kvm_arch_has_work(CPUState *env)
1395 {
1396 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1397 (env->eflags & IF_MASK)) ||
1398 (env->interrupt_request & CPU_INTERRUPT_NMI))
1399 return 1;
1400 return 0;
1401 }
1402
1403 int kvm_arch_try_push_interrupts(void *opaque)
1404 {
1405 CPUState *env = cpu_single_env;
1406 int r, irq;
1407
1408 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1409 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1410 (env->eflags & IF_MASK)) {
1411 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1412 irq = cpu_get_pic_interrupt(env);
1413 if (irq >= 0) {
1414 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1415 if (r < 0)
1416 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1417 }
1418 }
1419
1420 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1421 }
1422
1423 #ifdef KVM_CAP_USER_NMI
1424 void kvm_arch_push_nmi(void *opaque)
1425 {
1426 CPUState *env = cpu_single_env;
1427 int r;
1428
1429 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1430 return;
1431
1432 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1433 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1434 if (r < 0)
1435 printf("cpu %d fail inject NMI\n", env->cpu_index);
1436 }
1437 #endif /* KVM_CAP_USER_NMI */
1438
1439 void kvm_arch_update_regs_for_sipi(CPUState *env)
1440 {
1441 SegmentCache cs = env->segs[R_CS];
1442
1443 kvm_arch_save_regs(env);
1444 env->segs[R_CS] = cs;
1445 env->eip = 0;
1446 kvm_arch_load_regs(env);
1447 }
1448
1449 void kvm_arch_cpu_reset(CPUState *env)
1450 {
1451 kvm_arch_load_regs(env);
1452 if (!cpu_is_bsp(env)) {
1453 if (kvm_irqchip_in_kernel(kvm_context)) {
1454 #ifdef KVM_CAP_MP_STATE
1455 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1456 #endif
1457 } else {
1458 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1459 env->halted = 1;
1460 }
1461 }
1462 }
1463
1464 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1465 {
1466 uint8_t int3 = 0xcc;
1467
1468 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1469 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1470 return -EINVAL;
1471 return 0;
1472 }
1473
1474 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1475 {
1476 uint8_t int3;
1477
1478 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1479 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1480 return -EINVAL;
1481 return 0;
1482 }
1483
1484 #ifdef KVM_CAP_SET_GUEST_DEBUG
1485 static struct {
1486 target_ulong addr;
1487 int len;
1488 int type;
1489 } hw_breakpoint[4];
1490
1491 static int nb_hw_breakpoint;
1492
1493 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1494 {
1495 int n;
1496
1497 for (n = 0; n < nb_hw_breakpoint; n++)
1498 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1499 (hw_breakpoint[n].len == len || len == -1))
1500 return n;
1501 return -1;
1502 }
1503
1504 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1505 target_ulong len, int type)
1506 {
1507 switch (type) {
1508 case GDB_BREAKPOINT_HW:
1509 len = 1;
1510 break;
1511 case GDB_WATCHPOINT_WRITE:
1512 case GDB_WATCHPOINT_ACCESS:
1513 switch (len) {
1514 case 1:
1515 break;
1516 case 2:
1517 case 4:
1518 case 8:
1519 if (addr & (len - 1))
1520 return -EINVAL;
1521 break;
1522 default:
1523 return -EINVAL;
1524 }
1525 break;
1526 default:
1527 return -ENOSYS;
1528 }
1529
1530 if (nb_hw_breakpoint == 4)
1531 return -ENOBUFS;
1532
1533 if (find_hw_breakpoint(addr, len, type) >= 0)
1534 return -EEXIST;
1535
1536 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1537 hw_breakpoint[nb_hw_breakpoint].len = len;
1538 hw_breakpoint[nb_hw_breakpoint].type = type;
1539 nb_hw_breakpoint++;
1540
1541 return 0;
1542 }
1543
1544 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1545 target_ulong len, int type)
1546 {
1547 int n;
1548
1549 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1550 if (n < 0)
1551 return -ENOENT;
1552
1553 nb_hw_breakpoint--;
1554 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1555
1556 return 0;
1557 }
1558
1559 void kvm_arch_remove_all_hw_breakpoints(void)
1560 {
1561 nb_hw_breakpoint = 0;
1562 }
1563
1564 static CPUWatchpoint hw_watchpoint;
1565
1566 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1567 {
1568 int handle = 0;
1569 int n;
1570
1571 if (arch_info->exception == 1) {
1572 if (arch_info->dr6 & (1 << 14)) {
1573 if (cpu_single_env->singlestep_enabled)
1574 handle = 1;
1575 } else {
1576 for (n = 0; n < 4; n++)
1577 if (arch_info->dr6 & (1 << n))
1578 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1579 case 0x0:
1580 handle = 1;
1581 break;
1582 case 0x1:
1583 handle = 1;
1584 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1585 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1586 hw_watchpoint.flags = BP_MEM_WRITE;
1587 break;
1588 case 0x3:
1589 handle = 1;
1590 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1591 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1592 hw_watchpoint.flags = BP_MEM_ACCESS;
1593 break;
1594 }
1595 }
1596 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1597 handle = 1;
1598
1599 if (!handle)
1600 kvm_update_guest_debug(cpu_single_env,
1601 (arch_info->exception == 1) ?
1602 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1603
1604 return handle;
1605 }
1606
1607 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1608 {
1609 const uint8_t type_code[] = {
1610 [GDB_BREAKPOINT_HW] = 0x0,
1611 [GDB_WATCHPOINT_WRITE] = 0x1,
1612 [GDB_WATCHPOINT_ACCESS] = 0x3
1613 };
1614 const uint8_t len_code[] = {
1615 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1616 };
1617 int n;
1618
1619 if (kvm_sw_breakpoints_active(env))
1620 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1621
1622 if (nb_hw_breakpoint > 0) {
1623 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1624 dbg->arch.debugreg[7] = 0x0600;
1625 for (n = 0; n < nb_hw_breakpoint; n++) {
1626 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1627 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1628 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1629 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1630 }
1631 }
1632 }
1633 #endif
1634
1635 void kvm_arch_do_ioperm(void *_data)
1636 {
1637 struct ioperm_data *data = _data;
1638 ioperm(data->start_port, data->num, data->turn_on);
1639 }
1640
1641 /*
1642 * Setup x86 specific IRQ routing
1643 */
1644 int kvm_arch_init_irq_routing(void)
1645 {
1646 int i, r;
1647
1648 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1649 kvm_clear_gsi_routes(kvm_context);
1650 for (i = 0; i < 8; ++i) {
1651 if (i == 2)
1652 continue;
1653 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1654 if (r < 0)
1655 return r;
1656 }
1657 for (i = 8; i < 16; ++i) {
1658 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1659 if (r < 0)
1660 return r;
1661 }
1662 for (i = 0; i < 24; ++i) {
1663 if (i == 0) {
1664 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1665 } else if (i != 2) {
1666 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1667 }
1668 if (r < 0)
1669 return r;
1670 }
1671 kvm_commit_irq_routes(kvm_context);
1672 }
1673 return 0;
1674 }
1675
1676 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1677 int reg)
1678 {
1679 return kvm_get_supported_cpuid(kvm_context, function, reg);
1680 }
1681
1682 void kvm_arch_process_irqchip_events(CPUState *env)
1683 {
1684 kvm_arch_save_regs(env);
1685 if (env->interrupt_request & CPU_INTERRUPT_INIT)
1686 do_cpu_init(env);
1687 if (env->interrupt_request & CPU_INTERRUPT_SIPI)
1688 do_cpu_sipi(env);
1689 kvm_arch_load_regs(env);
1690 }
QEMU modified to work with kvm