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virtio-scsi: do not compare 32-bit QEMU tags against 64-bit virtio-scsi tags
[qemu-kvm.git] / hw / exynos4210_mct.c
blob7a22b1f900a99848d1d3c9505921660b02327974
1 /*
2 * Samsung exynos4210 Multi Core timer
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 *
7 * Evgeny Voevodin <e.voevodin@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 /*
24 * Global Timer:
25 *
26 * Consists of two timers. First represents Free Running Counter and second
27 * is used to measure interval from FRC to nearest comparator.
28 *
29 * 0 UINT64_MAX
30 * | timer0 |
31 * | <-------------------------------------------------------------- |
32 * | --------------------------------------------frc---------------> |
33 * |______________________________________________|__________________|
34 * CMP0 CMP1 CMP2 | CMP3
35 * __| |_
36 * | timer1 |
37 * | -------------> |
38 * frc CMPx
39 *
40 * Problem: when implementing global timer as is, overflow arises.
41 * next_time = cur_time + period * count;
42 * period and count are 64 bits width.
43 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT
44 * register during each event.
45 *
46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
48 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0
49 * generates IRQs suffers from too frequently events. Better to have one
50 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT,
51 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values,
52 * there is no way to avoid frequently events).
53 */
54
55 #include "sysbus.h"
56 #include "qemu-timer.h"
57 #include "qemu-common.h"
58 #include "ptimer.h"
59
60 #include "exynos4210.h"
61
62 //#define DEBUG_MCT
63
64 #ifdef DEBUG_MCT
65 #define DPRINTF(fmt, ...) \
66 do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \
67 ## __VA_ARGS__); } while (0)
68 #else
69 #define DPRINTF(fmt, ...) do {} while (0)
70 #endif
71
72 #define MCT_CFG 0x000
73 #define G_CNT_L 0x100
74 #define G_CNT_U 0x104
75 #define G_CNT_WSTAT 0x110
76 #define G_COMP0_L 0x200
77 #define G_COMP0_U 0x204
78 #define G_COMP0_ADD_INCR 0x208
79 #define G_COMP1_L 0x210
80 #define G_COMP1_U 0x214
81 #define G_COMP1_ADD_INCR 0x218
82 #define G_COMP2_L 0x220
83 #define G_COMP2_U 0x224
84 #define G_COMP2_ADD_INCR 0x228
85 #define G_COMP3_L 0x230
86 #define G_COMP3_U 0x234
87 #define G_COMP3_ADD_INCR 0x238
88 #define G_TCON 0x240
89 #define G_INT_CSTAT 0x244
90 #define G_INT_ENB 0x248
91 #define G_WSTAT 0x24C
92 #define L0_TCNTB 0x300
93 #define L0_TCNTO 0x304
94 #define L0_ICNTB 0x308
95 #define L0_ICNTO 0x30C
96 #define L0_FRCNTB 0x310
97 #define L0_FRCNTO 0x314
98 #define L0_TCON 0x320
99 #define L0_INT_CSTAT 0x330
100 #define L0_INT_ENB 0x334
101 #define L0_WSTAT 0x340
102 #define L1_TCNTB 0x400
103 #define L1_TCNTO 0x404
104 #define L1_ICNTB 0x408
105 #define L1_ICNTO 0x40C
106 #define L1_FRCNTB 0x410
107 #define L1_FRCNTO 0x414
108 #define L1_TCON 0x420
109 #define L1_INT_CSTAT 0x430
110 #define L1_INT_ENB 0x434
111 #define L1_WSTAT 0x440
112
113 #define MCT_CFG_GET_PRESCALER(x) ((x) & 0xFF)
114 #define MCT_CFG_GET_DIVIDER(x) (1 << ((x) >> 8 & 7))
115
116 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10)
117 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
118
119 #define G_COMP_L(x) (G_COMP0_L + (x) * 0x10)
120 #define G_COMP_U(x) (G_COMP0_U + (x) * 0x10)
121
122 #define G_COMP_ADD_INCR(x) (G_COMP0_ADD_INCR + (x) * 0x10)
123
124 /* MCT bits */
125 #define G_TCON_COMP_ENABLE(x) (1 << 2 * (x))
126 #define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1))
127 #define G_TCON_TIMER_ENABLE (1 << 8)
128
129 #define G_INT_ENABLE(x) (1 << (x))
130 #define G_INT_CSTAT_COMP(x) (1 << (x))
131
132 #define G_CNT_WSTAT_L 1
133 #define G_CNT_WSTAT_U 2
134
135 #define G_WSTAT_COMP_L(x) (1 << 4 * (x))
136 #define G_WSTAT_COMP_U(x) (1 << ((4 * (x)) + 1))
137 #define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2))
138 #define G_WSTAT_TCON_WRITE (1 << 16)
139
140 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
141 #define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \
142 (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2)
143
144 #define L_ICNTB_MANUAL_UPDATE (1 << 31)
145
146 #define L_TCON_TICK_START (1)
147 #define L_TCON_INT_START (1 << 1)
148 #define L_TCON_INTERVAL_MODE (1 << 2)
149 #define L_TCON_FRC_START (1 << 3)
150
151 #define L_INT_CSTAT_INTCNT (1 << 0)
152 #define L_INT_CSTAT_FRCCNT (1 << 1)
153
154 #define L_INT_INTENB_ICNTEIE (1 << 0)
155 #define L_INT_INTENB_FRCEIE (1 << 1)
156
157 #define L_WSTAT_TCNTB_WRITE (1 << 0)
158 #define L_WSTAT_ICNTB_WRITE (1 << 1)
159 #define L_WSTAT_FRCCNTB_WRITE (1 << 2)
160 #define L_WSTAT_TCON_WRITE (1 << 3)
161
162 enum LocalTimerRegCntIndexes {
163 L_REG_CNT_TCNTB,
164 L_REG_CNT_TCNTO,
165 L_REG_CNT_ICNTB,
166 L_REG_CNT_ICNTO,
167 L_REG_CNT_FRCCNTB,
168 L_REG_CNT_FRCCNTO,
169
170 L_REG_CNT_AMOUNT
171 };
172
173 #define MCT_NIRQ 6
174 #define MCT_SFR_SIZE 0x444
175
176 #define MCT_GT_CMP_NUM 4
177
178 #define MCT_GT_MAX_VAL UINT64_MAX
179
180 #define MCT_GT_COUNTER_STEP 0x100000000ULL
181 #define MCT_LT_COUNTER_STEP 0x100000000ULL
182 #define MCT_LT_CNT_LOW_LIMIT 0x100
183
184 /* global timer */
185 typedef struct {
186 qemu_irq irq[MCT_GT_CMP_NUM];
187
188 struct gregs {
189 uint64_t cnt;
190 uint32_t cnt_wstat;
191 uint32_t tcon;
192 uint32_t int_cstat;
193 uint32_t int_enb;
194 uint32_t wstat;
195 uint64_t comp[MCT_GT_CMP_NUM];
196 uint32_t comp_add_incr[MCT_GT_CMP_NUM];
197 } reg;
198
199 uint64_t count; /* Value FRC was armed with */
200 int32_t curr_comp; /* Current comparator FRC is running to */
201
202 ptimer_state *ptimer_frc; /* FRC timer */
203
204 } Exynos4210MCTGT;
205
206 /* local timer */
207 typedef struct {
208 int id; /* timer id */
209 qemu_irq irq; /* local timer irq */
210
211 struct tick_timer {
212 uint32_t cnt_run; /* cnt timer is running */
213 uint32_t int_run; /* int timer is running */
214
215 uint32_t last_icnto;
216 uint32_t last_tcnto;
217 uint32_t tcntb; /* initial value for TCNTB */
218 uint32_t icntb; /* initial value for ICNTB */
219
220 /* for step mode */
221 uint64_t distance; /* distance to count to the next event */
222 uint64_t progress; /* progress when counting by steps */
223 uint64_t count; /* count to arm timer with */
224
225 ptimer_state *ptimer_tick; /* timer for tick counter */
226 } tick_timer;
227
228 /* use ptimer.c to represent count down timer */
229
230 ptimer_state *ptimer_frc; /* timer for free running counter */
231
232 /* registers */
233 struct lregs {
234 uint32_t cnt[L_REG_CNT_AMOUNT];
235 uint32_t tcon;
236 uint32_t int_cstat;
237 uint32_t int_enb;
238 uint32_t wstat;
239 } reg;
240
241 } Exynos4210MCTLT;
242
243 typedef struct Exynos4210MCTState {
244 SysBusDevice busdev;
245 MemoryRegion iomem;
246
247 /* Registers */
248 uint32_t reg_mct_cfg;
249
250 Exynos4210MCTLT l_timer[2];
251 Exynos4210MCTGT g_timer;
252
253 uint32_t freq; /* all timers tick frequency, TCLK */
254 } Exynos4210MCTState;
255
256 /*** VMState ***/
257 static const VMStateDescription vmstate_tick_timer = {
258 .name = "exynos4210.mct.tick_timer",
259 .version_id = 1,
260 .minimum_version_id = 1,
261 .minimum_version_id_old = 1,
262 .fields = (VMStateField[]) {
263 VMSTATE_UINT32(cnt_run, struct tick_timer),
264 VMSTATE_UINT32(int_run, struct tick_timer),
265 VMSTATE_UINT32(last_icnto, struct tick_timer),
266 VMSTATE_UINT32(last_tcnto, struct tick_timer),
267 VMSTATE_UINT32(tcntb, struct tick_timer),
268 VMSTATE_UINT32(icntb, struct tick_timer),
269 VMSTATE_UINT64(distance, struct tick_timer),
270 VMSTATE_UINT64(progress, struct tick_timer),
271 VMSTATE_UINT64(count, struct tick_timer),
272 VMSTATE_PTIMER(ptimer_tick, struct tick_timer),
273 VMSTATE_END_OF_LIST()
274 }
275 };
276
277 static const VMStateDescription vmstate_lregs = {
278 .name = "exynos4210.mct.lregs",
279 .version_id = 1,
280 .minimum_version_id = 1,
281 .minimum_version_id_old = 1,
282 .fields = (VMStateField[]) {
283 VMSTATE_UINT32_ARRAY(cnt, struct lregs, L_REG_CNT_AMOUNT),
284 VMSTATE_UINT32(tcon, struct lregs),
285 VMSTATE_UINT32(int_cstat, struct lregs),
286 VMSTATE_UINT32(int_enb, struct lregs),
287 VMSTATE_UINT32(wstat, struct lregs),
288 VMSTATE_END_OF_LIST()
289 }
290 };
291
292 static const VMStateDescription vmstate_exynos4210_mct_lt = {
293 .name = "exynos4210.mct.lt",
294 .version_id = 1,
295 .minimum_version_id = 1,
296 .minimum_version_id_old = 1,
297 .fields = (VMStateField[]) {
298 VMSTATE_INT32(id, Exynos4210MCTLT),
299 VMSTATE_STRUCT(tick_timer, Exynos4210MCTLT, 0,
300 vmstate_tick_timer,
301 struct tick_timer),
302 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTLT),
303 VMSTATE_STRUCT(reg, Exynos4210MCTLT, 0,
304 vmstate_lregs,
305 struct lregs),
306 VMSTATE_END_OF_LIST()
307 }
308 };
309
310 static const VMStateDescription vmstate_gregs = {
311 .name = "exynos4210.mct.lregs",
312 .version_id = 1,
313 .minimum_version_id = 1,
314 .minimum_version_id_old = 1,
315 .fields = (VMStateField[]) {
316 VMSTATE_UINT64(cnt, struct gregs),
317 VMSTATE_UINT32(cnt_wstat, struct gregs),
318 VMSTATE_UINT32(tcon, struct gregs),
319 VMSTATE_UINT32(int_cstat, struct gregs),
320 VMSTATE_UINT32(int_enb, struct gregs),
321 VMSTATE_UINT32(wstat, struct gregs),
322 VMSTATE_UINT64_ARRAY(comp, struct gregs, MCT_GT_CMP_NUM),
323 VMSTATE_UINT32_ARRAY(comp_add_incr, struct gregs,
324 MCT_GT_CMP_NUM),
325 VMSTATE_END_OF_LIST()
326 }
327 };
328
329 static const VMStateDescription vmstate_exynos4210_mct_gt = {
330 .name = "exynos4210.mct.lt",
331 .version_id = 1,
332 .minimum_version_id = 1,
333 .minimum_version_id_old = 1,
334 .fields = (VMStateField[]) {
335 VMSTATE_STRUCT(reg, Exynos4210MCTGT, 0, vmstate_gregs,
336 struct gregs),
337 VMSTATE_UINT64(count, Exynos4210MCTGT),
338 VMSTATE_INT32(curr_comp, Exynos4210MCTGT),
339 VMSTATE_PTIMER(ptimer_frc, Exynos4210MCTGT),
340 VMSTATE_END_OF_LIST()
341 }
342 };
343
344 static const VMStateDescription vmstate_exynos4210_mct_state = {
345 .name = "exynos4210.mct",
346 .version_id = 1,
347 .minimum_version_id = 1,
348 .minimum_version_id_old = 1,
349 .fields = (VMStateField[]) {
350 VMSTATE_UINT32(reg_mct_cfg, Exynos4210MCTState),
351 VMSTATE_STRUCT_ARRAY(l_timer, Exynos4210MCTState, 2, 0,
352 vmstate_exynos4210_mct_lt, Exynos4210MCTLT),
353 VMSTATE_STRUCT(g_timer, Exynos4210MCTState, 0,
354 vmstate_exynos4210_mct_gt, Exynos4210MCTGT),
355 VMSTATE_UINT32(freq, Exynos4210MCTState),
356 VMSTATE_END_OF_LIST()
357 }
358 };
359
360 static void exynos4210_mct_update_freq(Exynos4210MCTState *s);
361
362 /*
363 * Set counter of FRC global timer.
364 */
365 static void exynos4210_gfrc_set_count(Exynos4210MCTGT *s, uint64_t count)
366 {
367 s->count = count;
368 DPRINTF("global timer frc set count 0x%llx\n", count);
369 ptimer_set_count(s->ptimer_frc, count);
370 }
371
372 /*
373 * Get counter of FRC global timer.
374 */
375 static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT *s)
376 {
377 uint64_t count = 0;
378 count = ptimer_get_count(s->ptimer_frc);
379 count = s->count - count;
380 return s->reg.cnt + count;
381 }
382
383 /*
384 * Stop global FRC timer
385 */
386 static void exynos4210_gfrc_stop(Exynos4210MCTGT *s)
387 {
388 DPRINTF("global timer frc stop\n");
389
390 ptimer_stop(s->ptimer_frc);
391 }
392
393 /*
394 * Start global FRC timer
395 */
396 static void exynos4210_gfrc_start(Exynos4210MCTGT *s)
397 {
398 DPRINTF("global timer frc start\n");
399
400 ptimer_run(s->ptimer_frc, 1);
401 }
402
403 /*
404 * Find next nearest Comparator. If current Comparator value equals to other
405 * Comparator value, skip them both
406 */
407 static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s)
408 {
409 int res;
410 int i;
411 int enabled;
412 uint64_t min;
413 int min_comp_i;
414 uint64_t gfrc;
415 uint64_t distance;
416 uint64_t distance_min;
417 int comp_i;
418
419 /* get gfrc count */
420 gfrc = exynos4210_gfrc_get_count(&s->g_timer);
421
422 min = UINT64_MAX;
423 distance_min = UINT64_MAX;
424 comp_i = MCT_GT_CMP_NUM;
425 min_comp_i = MCT_GT_CMP_NUM;
426 enabled = 0;
427
428 /* lookup for nearest comparator */
429 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
430
431 if (s->g_timer.reg.tcon & G_TCON_COMP_ENABLE(i)) {
432
433 enabled = 1;
434
435 if (s->g_timer.reg.comp[i] > gfrc) {
436 /* Comparator is upper then FRC */
437 distance = s->g_timer.reg.comp[i] - gfrc;
438
439 if (distance <= distance_min) {
440 distance_min = distance;
441 comp_i = i;
442 }
443 } else {
444 /* Comparator is below FRC, find the smallest */
445
446 if (s->g_timer.reg.comp[i] <= min) {
447 min = s->g_timer.reg.comp[i];
448 min_comp_i = i;
449 }
450 }
451 }
452 }
453
454 if (!enabled) {
455 /* All Comparators disabled */
456 res = -1;
457 } else if (comp_i < MCT_GT_CMP_NUM) {
458 /* Found upper Comparator */
459 res = comp_i;
460 } else {
461 /* All Comparators are below or equal to FRC */
462 res = min_comp_i;
463 }
464
465 DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
466 res,
467 s->g_timer.reg.comp[res],
468 distance_min,
469 gfrc);
470
471 return res;
472 }
473
474 /*
475 * Get distance to nearest Comparator
476 */
477 static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState *s, int32_t id)
478 {
479 if (id == -1) {
480 /* no enabled Comparators, choose max distance */
481 return MCT_GT_COUNTER_STEP;
482 }
483 if (s->g_timer.reg.comp[id] - s->g_timer.reg.cnt < MCT_GT_COUNTER_STEP) {
484 return s->g_timer.reg.comp[id] - s->g_timer.reg.cnt;
485 } else {
486 return MCT_GT_COUNTER_STEP;
487 }
488 }
489
490 /*
491 * Restart global FRC timer
492 */
493 static void exynos4210_gfrc_restart(Exynos4210MCTState *s)
494 {
495 uint64_t distance;
496
497 exynos4210_gfrc_stop(&s->g_timer);
498
499 s->g_timer.curr_comp = exynos4210_gcomp_find(s);
500
501 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
502
503 if (distance > MCT_GT_COUNTER_STEP || !distance) {
504 distance = MCT_GT_COUNTER_STEP;
505 }
506
507 exynos4210_gfrc_set_count(&s->g_timer, distance);
508 exynos4210_gfrc_start(&s->g_timer);
509 }
510
511 /*
512 * Raise global timer CMP IRQ
513 */
514 static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
515 {
516 Exynos4210MCTGT *s = opaque;
517
518 /* If CSTAT is pending and IRQ is enabled */
519 if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
520 (s->reg.int_enb & G_INT_ENABLE(id))) {
521 DPRINTF("gcmp timer[%d] IRQ\n", id);
522 qemu_irq_raise(s->irq[id]);
523 }
524 }
525
526 /*
527 * Lower global timer CMP IRQ
528 */
529 static void exynos4210_gcomp_lower_irq(void *opaque, uint32_t id)
530 {
531 Exynos4210MCTGT *s = opaque;
532 qemu_irq_lower(s->irq[id]);
533 }
534
535 /*
536 * Global timer FRC event handler.
537 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP
538 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value
539 */
540 static void exynos4210_gfrc_event(void *opaque)
541 {
542 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
543 int i;
544 uint64_t distance;
545
546 DPRINTF("\n");
547
548 s->g_timer.reg.cnt += s->g_timer.count;
549
550 /* Process all comparators */
551 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
552
553 if (s->g_timer.reg.cnt == s->g_timer.reg.comp[i]) {
554 /* reached nearest comparator */
555
556 s->g_timer.reg.int_cstat |= G_INT_CSTAT_COMP(i);
557
558 /* Auto increment */
559 if (s->g_timer.reg.tcon & G_TCON_AUTO_ICREMENT(i)) {
560 s->g_timer.reg.comp[i] += s->g_timer.reg.comp_add_incr[i];
561 }
562
563 /* IRQ */
564 exynos4210_gcomp_raise_irq(&s->g_timer, i);
565 }
566 }
567
568 /* Reload FRC to reach nearest comparator */
569 s->g_timer.curr_comp = exynos4210_gcomp_find(s);
570 distance = exynos4210_gcomp_get_distance(s, s->g_timer.curr_comp);
571 if (distance > MCT_GT_COUNTER_STEP) {
572 distance = MCT_GT_COUNTER_STEP;
573 }
574 exynos4210_gfrc_set_count(&s->g_timer, distance);
575
576 exynos4210_gfrc_start(&s->g_timer);
577
578 return;
579 }
580
581 /*
582 * Get counter of FRC local timer.
583 */
584 static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT *s)
585 {
586 return ptimer_get_count(s->ptimer_frc);
587 }
588
589 /*
590 * Set counter of FRC local timer.
591 */
592 static void exynos4210_lfrc_update_count(Exynos4210MCTLT *s)
593 {
594 if (!s->reg.cnt[L_REG_CNT_FRCCNTB]) {
595 ptimer_set_count(s->ptimer_frc, MCT_LT_COUNTER_STEP);
596 } else {
597 ptimer_set_count(s->ptimer_frc, s->reg.cnt[L_REG_CNT_FRCCNTB]);
598 }
599 }
600
601 /*
602 * Start local FRC timer
603 */
604 static void exynos4210_lfrc_start(Exynos4210MCTLT *s)
605 {
606 ptimer_run(s->ptimer_frc, 1);
607 }
608
609 /*
610 * Stop local FRC timer
611 */
612 static void exynos4210_lfrc_stop(Exynos4210MCTLT *s)
613 {
614 ptimer_stop(s->ptimer_frc);
615 }
616
617 /*
618 * Local timer free running counter tick handler
619 */
620 static void exynos4210_lfrc_event(void *opaque)
621 {
622 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque;
623
624 /* local frc expired */
625
626 DPRINTF("\n");
627
628 s->reg.int_cstat |= L_INT_CSTAT_FRCCNT;
629
630 /* update frc counter */
631 exynos4210_lfrc_update_count(s);
632
633 /* raise irq */
634 if (s->reg.int_enb & L_INT_INTENB_FRCEIE) {
635 qemu_irq_raise(s->irq);
636 }
637
638 /* we reached here, this means that timer is enabled */
639 exynos4210_lfrc_start(s);
640 }
641
642 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s);
643 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s);
644 static void exynos4210_ltick_recalc_count(struct tick_timer *s);
645
646 /*
647 * Action on enabling local tick int timer
648 */
649 static void exynos4210_ltick_int_start(struct tick_timer *s)
650 {
651 if (!s->int_run) {
652 s->int_run = 1;
653 }
654 }
655
656 /*
657 * Action on disabling local tick int timer
658 */
659 static void exynos4210_ltick_int_stop(struct tick_timer *s)
660 {
661 if (s->int_run) {
662 s->last_icnto = exynos4210_ltick_int_get_cnto(s);
663 s->int_run = 0;
664 }
665 }
666
667 /*
668 * Get count for INT timer
669 */
670 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer *s)
671 {
672 uint32_t icnto;
673 uint64_t remain;
674 uint64_t count;
675 uint64_t counted;
676 uint64_t cur_progress;
677
678 count = ptimer_get_count(s->ptimer_tick);
679 if (count) {
680 /* timer is still counting, called not from event */
681 counted = s->count - ptimer_get_count(s->ptimer_tick);
682 cur_progress = s->progress + counted;
683 } else {
684 /* timer expired earlier */
685 cur_progress = s->progress;
686 }
687
688 remain = s->distance - cur_progress;
689
690 if (!s->int_run) {
691 /* INT is stopped. */
692 icnto = s->last_icnto;
693 } else {
694 /* Both are counting */
695 icnto = remain / s->tcntb;
696 }
697
698 return icnto;
699 }
700
701 /*
702 * Start local tick cnt timer.
703 */
704 static void exynos4210_ltick_cnt_start(struct tick_timer *s)
705 {
706 if (!s->cnt_run) {
707
708 exynos4210_ltick_recalc_count(s);
709 ptimer_set_count(s->ptimer_tick, s->count);
710 ptimer_run(s->ptimer_tick, 1);
711
712 s->cnt_run = 1;
713 }
714 }
715
716 /*
717 * Stop local tick cnt timer.
718 */
719 static void exynos4210_ltick_cnt_stop(struct tick_timer *s)
720 {
721 if (s->cnt_run) {
722
723 s->last_tcnto = exynos4210_ltick_cnt_get_cnto(s);
724
725 if (s->int_run) {
726 exynos4210_ltick_int_stop(s);
727 }
728
729 ptimer_stop(s->ptimer_tick);
730
731 s->cnt_run = 0;
732 }
733 }
734
735 /*
736 * Get counter for CNT timer
737 */
738 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer *s)
739 {
740 uint32_t tcnto;
741 uint32_t icnto;
742 uint64_t remain;
743 uint64_t counted;
744 uint64_t count;
745 uint64_t cur_progress;
746
747 count = ptimer_get_count(s->ptimer_tick);
748 if (count) {
749 /* timer is still counting, called not from event */
750 counted = s->count - ptimer_get_count(s->ptimer_tick);
751 cur_progress = s->progress + counted;
752 } else {
753 /* timer expired earlier */
754 cur_progress = s->progress;
755 }
756
757 remain = s->distance - cur_progress;
758
759 if (!s->cnt_run) {
760 /* Both are stopped. */
761 tcnto = s->last_tcnto;
762 } else if (!s->int_run) {
763 /* INT counter is stopped, progress is by CNT timer */
764 tcnto = remain % s->tcntb;
765 } else {
766 /* Both are counting */
767 icnto = remain / s->tcntb;
768 if (icnto) {
769 tcnto = remain % (icnto * s->tcntb);
770 } else {
771 tcnto = remain % s->tcntb;
772 }
773 }
774
775 return tcnto;
776 }
777
778 /*
779 * Set new values of counters for CNT and INT timers
780 */
781 static void exynos4210_ltick_set_cntb(struct tick_timer *s, uint32_t new_cnt,
782 uint32_t new_int)
783 {
784 uint32_t cnt_stopped = 0;
785 uint32_t int_stopped = 0;
786
787 if (s->cnt_run) {
788 exynos4210_ltick_cnt_stop(s);
789 cnt_stopped = 1;
790 }
791
792 if (s->int_run) {
793 exynos4210_ltick_int_stop(s);
794 int_stopped = 1;
795 }
796
797 s->tcntb = new_cnt + 1;
798 s->icntb = new_int + 1;
799
800 if (cnt_stopped) {
801 exynos4210_ltick_cnt_start(s);
802 }
803 if (int_stopped) {
804 exynos4210_ltick_int_start(s);
805 }
806
807 }
808
809 /*
810 * Calculate new counter value for tick timer
811 */
812 static void exynos4210_ltick_recalc_count(struct tick_timer *s)
813 {
814 uint64_t to_count;
815
816 if ((s->cnt_run && s->last_tcnto) || (s->int_run && s->last_icnto)) {
817 /*
818 * one or both timers run and not counted to the end;
819 * distance is not passed, recalculate with last_tcnto * last_icnto
820 */
821
822 if (s->last_tcnto) {
823 to_count = s->last_tcnto * s->last_icnto;
824 } else {
825 to_count = s->last_icnto;
826 }
827 } else {
828 /* distance is passed, recalculate with tcnto * icnto */
829 if (s->icntb) {
830 s->distance = s->tcntb * s->icntb;
831 } else {
832 s->distance = s->tcntb;
833 }
834
835 to_count = s->distance;
836 s->progress = 0;
837 }
838
839 if (to_count > MCT_LT_COUNTER_STEP) {
840 /* count by step */
841 s->count = MCT_LT_COUNTER_STEP;
842 } else {
843 s->count = to_count;
844 }
845 }
846
847 /*
848 * Initialize tick_timer
849 */
850 static void exynos4210_ltick_timer_init(struct tick_timer *s)
851 {
852 exynos4210_ltick_int_stop(s);
853 exynos4210_ltick_cnt_stop(s);
854
855 s->count = 0;
856 s->distance = 0;
857 s->progress = 0;
858 s->icntb = 0;
859 s->tcntb = 0;
860 }
861
862 /*
863 * tick_timer event.
864 * Raises when abstract tick_timer expires.
865 */
866 static void exynos4210_ltick_timer_event(struct tick_timer *s)
867 {
868 s->progress += s->count;
869 }
870
871 /*
872 * Local timer tick counter handler.
873 * Don't use reloaded timers. If timer counter = zero
874 * then handler called but after handler finished no
875 * timer reload occurs.
876 */
877 static void exynos4210_ltick_event(void *opaque)
878 {
879 Exynos4210MCTLT * s = (Exynos4210MCTLT *)opaque;
880 uint32_t tcnto;
881 uint32_t icnto;
882 #ifdef DEBUG_MCT
883 static uint64_t time1[2] = {0};
884 static uint64_t time2[2] = {0};
885 #endif
886
887 /* Call tick_timer event handler, it will update its tcntb and icntb. */
888 exynos4210_ltick_timer_event(&s->tick_timer);
889
890 /* get tick_timer cnt */
891 tcnto = exynos4210_ltick_cnt_get_cnto(&s->tick_timer);
892
893 /* get tick_timer int */
894 icnto = exynos4210_ltick_int_get_cnto(&s->tick_timer);
895
896 /* raise IRQ if needed */
897 if (!icnto && s->reg.tcon & L_TCON_INT_START) {
898 /* INT counter enabled and expired */
899
900 s->reg.int_cstat |= L_INT_CSTAT_INTCNT;
901
902 /* raise interrupt if enabled */
903 if (s->reg.int_enb & L_INT_INTENB_ICNTEIE) {
904 #ifdef DEBUG_MCT
905 time2[s->id] = qemu_get_clock_ns(vm_clock);
906 DPRINTF("local timer[%d] IRQ: %llx\n", s->id,
907 time2[s->id] - time1[s->id]);
908 time1[s->id] = time2[s->id];
909 #endif
910 qemu_irq_raise(s->irq);
911 }
912
913 /* reload ICNTB */
914 if (s->reg.tcon & L_TCON_INTERVAL_MODE) {
915 exynos4210_ltick_set_cntb(&s->tick_timer,
916 s->reg.cnt[L_REG_CNT_TCNTB],
917 s->reg.cnt[L_REG_CNT_ICNTB]);
918 }
919 } else {
920 /* reload TCNTB */
921 if (!tcnto) {
922 exynos4210_ltick_set_cntb(&s->tick_timer,
923 s->reg.cnt[L_REG_CNT_TCNTB],
924 icnto);
925 }
926 }
927
928 /* start tick_timer cnt */
929 exynos4210_ltick_cnt_start(&s->tick_timer);
930
931 /* start tick_timer int */
932 exynos4210_ltick_int_start(&s->tick_timer);
933 }
934
935 /* update timer frequency */
936 static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
937 {
938 uint32_t freq = s->freq;
939 s->freq = 24000000 /
940 ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) *
941 MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
942
943 if (freq != s->freq) {
944 DPRINTF("freq=%dHz\n", s->freq);
945
946 /* global timer */
947 ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
948
949 /* local timer */
950 ptimer_set_freq(s->l_timer[0].tick_timer.ptimer_tick, s->freq);
951 ptimer_set_freq(s->l_timer[0].ptimer_frc, s->freq);
952 ptimer_set_freq(s->l_timer[1].tick_timer.ptimer_tick, s->freq);
953 ptimer_set_freq(s->l_timer[1].ptimer_frc, s->freq);
954 }
955 }
956
957 /* set defaul_timer values for all fields */
958 static void exynos4210_mct_reset(DeviceState *d)
959 {
960 Exynos4210MCTState *s = (Exynos4210MCTState *)d;
961 uint32_t i;
962
963 s->reg_mct_cfg = 0;
964
965 /* global timer */
966 memset(&s->g_timer.reg, 0, sizeof(s->g_timer.reg));
967 exynos4210_gfrc_stop(&s->g_timer);
968
969 /* local timer */
970 memset(s->l_timer[0].reg.cnt, 0, sizeof(s->l_timer[0].reg.cnt));
971 memset(s->l_timer[1].reg.cnt, 0, sizeof(s->l_timer[1].reg.cnt));
972 for (i = 0; i < 2; i++) {
973 s->l_timer[i].reg.int_cstat = 0;
974 s->l_timer[i].reg.int_enb = 0;
975 s->l_timer[i].reg.tcon = 0;
976 s->l_timer[i].reg.wstat = 0;
977 s->l_timer[i].tick_timer.count = 0;
978 s->l_timer[i].tick_timer.distance = 0;
979 s->l_timer[i].tick_timer.progress = 0;
980 ptimer_stop(s->l_timer[i].ptimer_frc);
981
982 exynos4210_ltick_timer_init(&s->l_timer[i].tick_timer);
983 }
984
985 exynos4210_mct_update_freq(s);
986
987 }
988
989 /* Multi Core Timer read */
990 static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
991 unsigned size)
992 {
993 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
994 int index;
995 int shift;
996 uint64_t count;
997 uint32_t value;
998 int lt_i;
999
1000 switch (offset) {
1001
1002 case MCT_CFG:
1003 value = s->reg_mct_cfg;
1004 break;
1005
1006 case G_CNT_L: case G_CNT_U:
1007 shift = 8 * (offset & 0x4);
1008 count = exynos4210_gfrc_get_count(&s->g_timer);
1009 value = UINT32_MAX & (count >> shift);
1010 DPRINTF("read FRC=0x%llx\n", count);
1011 break;
1012
1013 case G_CNT_WSTAT:
1014 value = s->g_timer.reg.cnt_wstat;
1015 break;
1016
1017 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1018 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1019 index = GET_G_COMP_IDX(offset);
1020 shift = 8 * (offset & 0x4);
1021 value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
1022 break;
1023
1024 case G_TCON:
1025 value = s->g_timer.reg.tcon;
1026 break;
1027
1028 case G_INT_CSTAT:
1029 value = s->g_timer.reg.int_cstat;
1030 break;
1031
1032 case G_INT_ENB:
1033 value = s->g_timer.reg.int_enb;
1034 break;
1035 break;
1036 case G_WSTAT:
1037 value = s->g_timer.reg.wstat;
1038 break;
1039
1040 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR:
1041 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR:
1042 value = s->g_timer.reg.comp_add_incr[GET_G_COMP_ADD_INCR_IDX(offset)];
1043 break;
1044
1045 /* Local timers */
1046 case L0_TCNTB: case L0_ICNTB: case L0_FRCNTB:
1047 case L1_TCNTB: case L1_ICNTB: case L1_FRCNTB:
1048 lt_i = GET_L_TIMER_IDX(offset);
1049 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1050 value = s->l_timer[lt_i].reg.cnt[index];
1051 break;
1052
1053 case L0_TCNTO: case L1_TCNTO:
1054 lt_i = GET_L_TIMER_IDX(offset);
1055
1056 value = exynos4210_ltick_cnt_get_cnto(&s->l_timer[lt_i].tick_timer);
1057 DPRINTF("local timer[%d] read TCNTO %x\n", lt_i, value);
1058 break;
1059
1060 case L0_ICNTO: case L1_ICNTO:
1061 lt_i = GET_L_TIMER_IDX(offset);
1062
1063 value = exynos4210_ltick_int_get_cnto(&s->l_timer[lt_i].tick_timer);
1064 DPRINTF("local timer[%d] read ICNTO %x\n", lt_i, value);
1065 break;
1066
1067 case L0_FRCNTO: case L1_FRCNTO:
1068 lt_i = GET_L_TIMER_IDX(offset);
1069
1070 value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
1071
1072 break;
1073
1074 case L0_TCON: case L1_TCON:
1075 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1076 value = s->l_timer[lt_i].reg.tcon;
1077 break;
1078
1079 case L0_INT_CSTAT: case L1_INT_CSTAT:
1080 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1081 value = s->l_timer[lt_i].reg.int_cstat;
1082 break;
1083
1084 case L0_INT_ENB: case L1_INT_ENB:
1085 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1086 value = s->l_timer[lt_i].reg.int_enb;
1087 break;
1088
1089 case L0_WSTAT: case L1_WSTAT:
1090 lt_i = ((offset & 0xF00) - L0_TCNTB) / 0x100;
1091 value = s->l_timer[lt_i].reg.wstat;
1092 break;
1093
1094 default:
1095 hw_error("exynos4210.mct: bad read offset "
1096 TARGET_FMT_plx "\n", offset);
1097 break;
1098 }
1099 return value;
1100 }
1101
1102 /* MCT write */
1103 static void exynos4210_mct_write(void *opaque, target_phys_addr_t offset,
1104 uint64_t value, unsigned size)
1105 {
1106 Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
1107 int index; /* index in buffer which represents register set */
1108 int shift;
1109 int lt_i;
1110 uint64_t new_frc;
1111 uint32_t i;
1112 uint32_t old_val;
1113 #ifdef DEBUG_MCT
1114 static uint32_t icntb_max[2] = {0};
1115 static uint32_t icntb_min[2] = {UINT32_MAX, UINT32_MAX};
1116 static uint32_t tcntb_max[2] = {0};
1117 static uint32_t tcntb_min[2] = {UINT32_MAX, UINT32_MAX};
1118 #endif
1119
1120 new_frc = s->g_timer.reg.cnt;
1121
1122 switch (offset) {
1123
1124 case MCT_CFG:
1125 s->reg_mct_cfg = value;
1126 exynos4210_mct_update_freq(s);
1127 break;
1128
1129 case G_CNT_L:
1130 case G_CNT_U:
1131 if (offset == G_CNT_L) {
1132
1133 DPRINTF("global timer write to reg.cntl %llx\n", value);
1134
1135 new_frc = (s->g_timer.reg.cnt & (uint64_t)UINT32_MAX << 32) + value;
1136 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_L;
1137 }
1138 if (offset == G_CNT_U) {
1139
1140 DPRINTF("global timer write to reg.cntu %llx\n", value);
1141
1142 new_frc = (s->g_timer.reg.cnt & UINT32_MAX) +
1143 ((uint64_t)value << 32);
1144 s->g_timer.reg.cnt_wstat |= G_CNT_WSTAT_U;
1145 }
1146
1147 s->g_timer.reg.cnt = new_frc;
1148 exynos4210_gfrc_restart(s);
1149 break;
1150
1151 case G_CNT_WSTAT:
1152 s->g_timer.reg.cnt_wstat &= ~(value);
1153 break;
1154
1155 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1156 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1157 index = GET_G_COMP_IDX(offset);
1158 shift = 8 * (offset & 0x4);
1159 s->g_timer.reg.comp[index] =
1160 (s->g_timer.reg.comp[index] &
1161 (((uint64_t)UINT32_MAX << 32) >> shift)) +
1162 (value << shift);
1163
1164 DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
1165
1166 if (offset&0x4) {
1167 s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
1168 } else {
1169 s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
1170 }
1171
1172 exynos4210_gfrc_restart(s);
1173 break;
1174
1175 case G_TCON:
1176 old_val = s->g_timer.reg.tcon;
1177 s->g_timer.reg.tcon = value;
1178 s->g_timer.reg.wstat |= G_WSTAT_TCON_WRITE;
1179
1180 DPRINTF("global timer write to reg.g_tcon %llx\n", value);
1181
1182 /* Start FRC if transition from disabled to enabled */
1183 if ((value & G_TCON_TIMER_ENABLE) > (old_val &
1184 G_TCON_TIMER_ENABLE)) {
1185 exynos4210_gfrc_start(&s->g_timer);
1186 }
1187 if ((value & G_TCON_TIMER_ENABLE) < (old_val &
1188 G_TCON_TIMER_ENABLE)) {
1189 exynos4210_gfrc_stop(&s->g_timer);
1190 }
1191
1192 /* Start CMP if transition from disabled to enabled */
1193 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1194 if ((value & G_TCON_COMP_ENABLE(i)) != (old_val &
1195 G_TCON_COMP_ENABLE(i))) {
1196 exynos4210_gfrc_restart(s);
1197 }
1198 }
1199 break;
1200
1201 case G_INT_CSTAT:
1202 s->g_timer.reg.int_cstat &= ~(value);
1203 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1204 if (value & G_INT_CSTAT_COMP(i)) {
1205 exynos4210_gcomp_lower_irq(&s->g_timer, i);
1206 }
1207 }
1208 break;
1209
1210 case G_INT_ENB:
1211
1212 /* Raise IRQ if transition from disabled to enabled and CSTAT pending */
1213 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1214 if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
1215 G_INT_ENABLE(i))) {
1216 if (s->g_timer.reg.int_cstat & G_INT_CSTAT_COMP(i)) {
1217 exynos4210_gcomp_raise_irq(&s->g_timer, i);
1218 }
1219 }
1220
1221 if ((value & G_INT_ENABLE(i)) < (s->g_timer.reg.tcon &
1222 G_INT_ENABLE(i))) {
1223 exynos4210_gcomp_lower_irq(&s->g_timer, i);
1224 }
1225 }
1226
1227 DPRINTF("global timer INT enable %llx\n", value);
1228 s->g_timer.reg.int_enb = value;
1229 break;
1230
1231 case G_WSTAT:
1232 s->g_timer.reg.wstat &= ~(value);
1233 break;
1234
1235 case G_COMP0_ADD_INCR: case G_COMP1_ADD_INCR:
1236 case G_COMP2_ADD_INCR: case G_COMP3_ADD_INCR:
1237 index = GET_G_COMP_ADD_INCR_IDX(offset);
1238 s->g_timer.reg.comp_add_incr[index] = value;
1239 s->g_timer.reg.wstat |= G_WSTAT_COMP_ADDINCR(index);
1240 break;
1241
1242 /* Local timers */
1243 case L0_TCON: case L1_TCON:
1244 lt_i = GET_L_TIMER_IDX(offset);
1245 old_val = s->l_timer[lt_i].reg.tcon;
1246
1247 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCON_WRITE;
1248 s->l_timer[lt_i].reg.tcon = value;
1249
1250 /* Stop local CNT */
1251 if ((value & L_TCON_TICK_START) <
1252 (old_val & L_TCON_TICK_START)) {
1253 DPRINTF("local timer[%d] stop cnt\n", lt_i);
1254 exynos4210_ltick_cnt_stop(&s->l_timer[lt_i].tick_timer);
1255 }
1256
1257 /* Stop local INT */
1258 if ((value & L_TCON_INT_START) <
1259 (old_val & L_TCON_INT_START)) {
1260 DPRINTF("local timer[%d] stop int\n", lt_i);
1261 exynos4210_ltick_int_stop(&s->l_timer[lt_i].tick_timer);
1262 }
1263
1264 /* Start local CNT */
1265 if ((value & L_TCON_TICK_START) >
1266 (old_val & L_TCON_TICK_START)) {
1267 DPRINTF("local timer[%d] start cnt\n", lt_i);
1268 exynos4210_ltick_cnt_start(&s->l_timer[lt_i].tick_timer);
1269 }
1270
1271 /* Start local INT */
1272 if ((value & L_TCON_INT_START) >
1273 (old_val & L_TCON_INT_START)) {
1274 DPRINTF("local timer[%d] start int\n", lt_i);
1275 exynos4210_ltick_int_start(&s->l_timer[lt_i].tick_timer);
1276 }
1277
1278 /* Start or Stop local FRC if TCON changed */
1279 if ((value & L_TCON_FRC_START) >
1280 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) {
1281 DPRINTF("local timer[%d] start frc\n", lt_i);
1282 exynos4210_lfrc_start(&s->l_timer[lt_i]);
1283 }
1284 if ((value & L_TCON_FRC_START) <
1285 (s->l_timer[lt_i].reg.tcon & L_TCON_FRC_START)) {
1286 DPRINTF("local timer[%d] stop frc\n", lt_i);
1287 exynos4210_lfrc_stop(&s->l_timer[lt_i]);
1288 }
1289 break;
1290
1291 case L0_TCNTB: case L1_TCNTB:
1292
1293 lt_i = GET_L_TIMER_IDX(offset);
1294 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1295
1296 /*
1297 * TCNTB is updated to internal register only after CNT expired.
1298 * Due to this we should reload timer to nearest moment when CNT is
1299 * expired and then in event handler update tcntb to new TCNTB value.
1300 */
1301 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer, value,
1302 s->l_timer[lt_i].tick_timer.icntb);
1303
1304 s->l_timer[lt_i].reg.wstat |= L_WSTAT_TCNTB_WRITE;
1305 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] = value;
1306
1307 #ifdef DEBUG_MCT
1308 if (tcntb_min[lt_i] > value) {
1309 tcntb_min[lt_i] = value;
1310 }
1311 if (tcntb_max[lt_i] < value) {
1312 tcntb_max[lt_i] = value;
1313 }
1314 DPRINTF("local timer[%d] TCNTB write %llx; max=%x, min=%x\n",
1315 lt_i, value, tcntb_max[lt_i], tcntb_min[lt_i]);
1316 #endif
1317 break;
1318
1319 case L0_ICNTB: case L1_ICNTB:
1320
1321 lt_i = GET_L_TIMER_IDX(offset);
1322 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1323
1324 s->l_timer[lt_i].reg.wstat |= L_WSTAT_ICNTB_WRITE;
1325 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] = value &
1326 ~L_ICNTB_MANUAL_UPDATE;
1327
1328 /*
1329 * We need to avoid too small values for TCNTB*ICNTB. If not, IRQ event
1330 * could raise too fast disallowing QEMU to execute target code.
1331 */
1332 if (s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] *
1333 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB] < MCT_LT_CNT_LOW_LIMIT) {
1334 if (!s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB]) {
1335 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] =
1336 MCT_LT_CNT_LOW_LIMIT;
1337 } else {
1338 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB] =
1339 MCT_LT_CNT_LOW_LIMIT /
1340 s->l_timer[lt_i].reg.cnt[L_REG_CNT_TCNTB];
1341 }
1342 }
1343
1344 if (value & L_ICNTB_MANUAL_UPDATE) {
1345 exynos4210_ltick_set_cntb(&s->l_timer[lt_i].tick_timer,
1346 s->l_timer[lt_i].tick_timer.tcntb,
1347 s->l_timer[lt_i].reg.cnt[L_REG_CNT_ICNTB]);
1348 }
1349
1350 #ifdef DEBUG_MCT
1351 if (icntb_min[lt_i] > value) {
1352 icntb_min[lt_i] = value;
1353 }
1354 if (icntb_max[lt_i] < value) {
1355 icntb_max[lt_i] = value;
1356 }
1357 DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
1358 lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
1359 #endif
1360 break;
1361
1362 case L0_FRCNTB: case L1_FRCNTB:
1363
1364 lt_i = GET_L_TIMER_IDX(offset);
1365 index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
1366
1367 DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i, value);
1368
1369 s->l_timer[lt_i].reg.wstat |= L_WSTAT_FRCCNTB_WRITE;
1370 s->l_timer[lt_i].reg.cnt[L_REG_CNT_FRCCNTB] = value;
1371
1372 break;
1373
1374 case L0_TCNTO: case L1_TCNTO:
1375 case L0_ICNTO: case L1_ICNTO:
1376 case L0_FRCNTO: case L1_FRCNTO:
1377 fprintf(stderr, "\n[exynos4210.mct: write to RO register "
1378 TARGET_FMT_plx "]\n\n", offset);
1379 break;
1380
1381 case L0_INT_CSTAT: case L1_INT_CSTAT:
1382 lt_i = GET_L_TIMER_IDX(offset);
1383
1384 DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i, value);
1385
1386 s->l_timer[lt_i].reg.int_cstat &= ~value;
1387 if (!s->l_timer[lt_i].reg.int_cstat) {
1388 qemu_irq_lower(s->l_timer[lt_i].irq);
1389 }
1390 break;
1391
1392 case L0_INT_ENB: case L1_INT_ENB:
1393 lt_i = GET_L_TIMER_IDX(offset);
1394 old_val = s->l_timer[lt_i].reg.int_enb;
1395
1396 /* Raise Local timer IRQ if cstat is pending */
1397 if ((value & L_INT_INTENB_ICNTEIE) > (old_val & L_INT_INTENB_ICNTEIE)) {
1398 if (s->l_timer[lt_i].reg.int_cstat & L_INT_CSTAT_INTCNT) {
1399 qemu_irq_raise(s->l_timer[lt_i].irq);
1400 }
1401 }
1402
1403 s->l_timer[lt_i].reg.int_enb = value;
1404
1405 break;
1406
1407 case L0_WSTAT: case L1_WSTAT:
1408 lt_i = GET_L_TIMER_IDX(offset);
1409
1410 s->l_timer[lt_i].reg.wstat &= ~value;
1411 break;
1412
1413 default:
1414 hw_error("exynos4210.mct: bad write offset "
1415 TARGET_FMT_plx "\n", offset);
1416 break;
1417 }
1418 }
1419
1420 static const MemoryRegionOps exynos4210_mct_ops = {
1421 .read = exynos4210_mct_read,
1422 .write = exynos4210_mct_write,
1423 .endianness = DEVICE_NATIVE_ENDIAN,
1424 };
1425
1426 /* MCT init */
1427 static int exynos4210_mct_init(SysBusDevice *dev)
1428 {
1429 int i;
1430 Exynos4210MCTState *s = FROM_SYSBUS(Exynos4210MCTState, dev);
1431 QEMUBH *bh[2];
1432
1433 /* Global timer */
1434 bh[0] = qemu_bh_new(exynos4210_gfrc_event, s);
1435 s->g_timer.ptimer_frc = ptimer_init(bh[0]);
1436 memset(&s->g_timer.reg, 0, sizeof(struct gregs));
1437
1438 /* Local timers */
1439 for (i = 0; i < 2; i++) {
1440 bh[0] = qemu_bh_new(exynos4210_ltick_event, &s->l_timer[i]);
1441 bh[1] = qemu_bh_new(exynos4210_lfrc_event, &s->l_timer[i]);
1442 s->l_timer[i].tick_timer.ptimer_tick = ptimer_init(bh[0]);
1443 s->l_timer[i].ptimer_frc = ptimer_init(bh[1]);
1444 s->l_timer[i].id = i;
1445 }
1446
1447 /* IRQs */
1448 for (i = 0; i < MCT_GT_CMP_NUM; i++) {
1449 sysbus_init_irq(dev, &s->g_timer.irq[i]);
1450 }
1451 for (i = 0; i < 2; i++) {
1452 sysbus_init_irq(dev, &s->l_timer[i].irq);
1453 }
1454
1455 memory_region_init_io(&s->iomem, &exynos4210_mct_ops, s, "exynos4210-mct",
1456 MCT_SFR_SIZE);
1457 sysbus_init_mmio(dev, &s->iomem);
1458
1459 return 0;
1460 }
1461
1462 static void exynos4210_mct_class_init(ObjectClass *klass, void *data)
1463 {
1464 DeviceClass *dc = DEVICE_CLASS(klass);
1465 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1466
1467 k->init = exynos4210_mct_init;
1468 dc->reset = exynos4210_mct_reset;
1469 dc->vmsd = &vmstate_exynos4210_mct_state;
1470 }
1471
1472 static TypeInfo exynos4210_mct_info = {
1473 .name = "exynos4210.mct",
1474 .parent = TYPE_SYS_BUS_DEVICE,
1475 .instance_size = sizeof(Exynos4210MCTState),
1476 .class_init = exynos4210_mct_class_init,
1477 };
1478
1479 static void exynos4210_mct_register_types(void)
1480 {
1481 type_register_static(&exynos4210_mct_info);
1482 }
1483
1484 type_init(exynos4210_mct_register_types)
QEMU modified to work with kvm