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hw: Convert from BlockDriverState to BlockBackend, mostly
[qemu-kvm.git] / hw / ide / core.c
bloba5c4698368a9983ac5d40caec67595607d5453ab
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/block-backend.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify_size(IDEState *s)
79 {
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87 }
88
89 static void ide_identify(IDEState *s)
90 {
91 uint16_t *p;
92 unsigned int oldsize;
93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
94
95 p = (uint16_t *)s->identify_data;
96 if (s->identify_set) {
97 goto fill_buffer;
98 }
99 memset(p, 0, sizeof(s->identify_data));
100
101 put_le16(p + 0, 0x0040);
102 put_le16(p + 1, s->cylinders);
103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
106 put_le16(p + 6, s->sectors);
107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
113 #if MAX_MULT_SECTORS > 1
114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
115 #endif
116 put_le16(p + 48, 1); /* dword I/O */
117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
124 oldsize = s->cylinders * s->heads * s->sectors;
125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
127 if (s->mult_sectors)
128 put_le16(p + 59, 0x100 | s->mult_sectors);
129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
133 put_le16(p + 64, 0x03); /* pio3-4 supported */
134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
161 if (blk_enable_write_cache(s->blk)) {
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 } else {
164 put_le16(p + 85, (1 << 14) | 1);
165 }
166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
169 if (s->wwn) {
170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
171 } else {
172 put_le16(p + 87, (1 << 14) | 0);
173 }
174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
175 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
176 /* *(p + 100) := nb_sectors -- see ide_identify_size */
177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
180
181 if (dev && dev->conf.physical_block_size)
182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
183 if (s->wwn) {
184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
185 put_le16(p + 108, s->wwn >> 48);
186 put_le16(p + 109, s->wwn >> 32);
187 put_le16(p + 110, s->wwn >> 16);
188 put_le16(p + 111, s->wwn);
189 }
190 if (dev && dev->conf.discard_granularity) {
191 put_le16(p + 169, 1); /* TRIM support */
192 }
193
194 ide_identify_size(s);
195 s->identify_set = 1;
196
197 fill_buffer:
198 memcpy(s->io_buffer, p, sizeof(s->identify_data));
199 }
200
201 static void ide_atapi_identify(IDEState *s)
202 {
203 uint16_t *p;
204
205 p = (uint16_t *)s->identify_data;
206 if (s->identify_set) {
207 goto fill_buffer;
208 }
209 memset(p, 0, sizeof(s->identify_data));
210
211 /* Removable CDROM, 50us response, 12 byte packets */
212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
214 put_le16(p + 20, 3); /* buffer type */
215 put_le16(p + 21, 512); /* cache size in sectors */
216 put_le16(p + 22, 4); /* ecc bytes */
217 padstr((char *)(p + 23), s->version, 8); /* firmware version */
218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
220 #ifdef USE_DMA_CDROM
221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
223 put_le16(p + 62, 7); /* single word dma0-2 supported */
224 put_le16(p + 63, 7); /* mdma0-2 supported */
225 #else
226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
229 #endif
230 put_le16(p + 64, 3); /* pio3-4 supported */
231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
235
236 put_le16(p + 71, 30); /* in ns */
237 put_le16(p + 72, 30); /* in ns */
238
239 if (s->ncq_queues) {
240 put_le16(p + 75, s->ncq_queues - 1);
241 /* NCQ supported */
242 put_le16(p + 76, (1 << 8));
243 }
244
245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
246 if (s->wwn) {
247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
248 put_le16(p + 87, (1 << 8)); /* WWN enabled */
249 }
250
251 #ifdef USE_DMA_CDROM
252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
253 #endif
254
255 if (s->wwn) {
256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
257 put_le16(p + 108, s->wwn >> 48);
258 put_le16(p + 109, s->wwn >> 32);
259 put_le16(p + 110, s->wwn >> 16);
260 put_le16(p + 111, s->wwn);
261 }
262
263 s->identify_set = 1;
264
265 fill_buffer:
266 memcpy(s->io_buffer, p, sizeof(s->identify_data));
267 }
268
269 static void ide_cfata_identify_size(IDEState *s)
270 {
271 uint16_t *p = (uint16_t *)s->identify_data;
272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
276 }
277
278 static void ide_cfata_identify(IDEState *s)
279 {
280 uint16_t *p;
281 uint32_t cur_sec;
282
283 p = (uint16_t *)s->identify_data;
284 if (s->identify_set) {
285 goto fill_buffer;
286 }
287 memset(p, 0, sizeof(s->identify_data));
288
289 cur_sec = s->cylinders * s->heads * s->sectors;
290
291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
292 put_le16(p + 1, s->cylinders); /* Default cylinders */
293 put_le16(p + 3, s->heads); /* Default heads */
294 put_le16(p + 6, s->sectors); /* Default sectors per track */
295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
298 put_le16(p + 22, 0x0004); /* ECC bytes */
299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
301 #if MAX_MULT_SECTORS > 1
302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
303 #else
304 put_le16(p + 47, 0x0000);
305 #endif
306 put_le16(p + 49, 0x0f00); /* Capabilities */
307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
309 put_le16(p + 53, 0x0003); /* Translation params valid */
310 put_le16(p + 54, s->cylinders); /* Current cylinders */
311 put_le16(p + 55, s->heads); /* Current heads */
312 put_le16(p + 56, s->sectors); /* Current sectors */
313 put_le16(p + 57, cur_sec); /* Current capacity */
314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
315 if (s->mult_sectors) /* Multiple sector setting */
316 put_le16(p + 59, 0x100 | s->mult_sectors);
317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
324 put_le16(p + 82, 0x400c); /* Command Set supported */
325 put_le16(p + 83, 0x7068); /* Command Set supported */
326 put_le16(p + 84, 0x4000); /* Features supported */
327 put_le16(p + 85, 0x000c); /* Command Set enabled */
328 put_le16(p + 86, 0x7044); /* Command Set enabled */
329 put_le16(p + 87, 0x4000); /* Features enabled */
330 put_le16(p + 91, 0x4060); /* Current APM level */
331 put_le16(p + 129, 0x0002); /* Current features option */
332 put_le16(p + 130, 0x0005); /* Reassigned sectors */
333 put_le16(p + 131, 0x0001); /* Initial power mode */
334 put_le16(p + 132, 0x0000); /* User signature */
335 put_le16(p + 160, 0x8100); /* Power requirement */
336 put_le16(p + 161, 0x8001); /* CF command set */
337
338 ide_cfata_identify_size(s);
339 s->identify_set = 1;
340
341 fill_buffer:
342 memcpy(s->io_buffer, p, sizeof(s->identify_data));
343 }
344
345 static void ide_set_signature(IDEState *s)
346 {
347 s->select &= 0xf0; /* clear head */
348 /* put signature */
349 s->nsector = 1;
350 s->sector = 1;
351 if (s->drive_kind == IDE_CD) {
352 s->lcyl = 0x14;
353 s->hcyl = 0xeb;
354 } else if (s->blk) {
355 s->lcyl = 0;
356 s->hcyl = 0;
357 } else {
358 s->lcyl = 0xff;
359 s->hcyl = 0xff;
360 }
361 }
362
363 typedef struct TrimAIOCB {
364 BlockAIOCB common;
365 QEMUBH *bh;
366 int ret;
367 QEMUIOVector *qiov;
368 BlockAIOCB *aiocb;
369 int i, j;
370 } TrimAIOCB;
371
372 static void trim_aio_cancel(BlockAIOCB *acb)
373 {
374 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
375
376 /* Exit the loop so ide_issue_trim_cb will not continue */
377 iocb->j = iocb->qiov->niov - 1;
378 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
379
380 iocb->ret = -ECANCELED;
381
382 if (iocb->aiocb) {
383 blk_aio_cancel_async(iocb->aiocb);
384 iocb->aiocb = NULL;
385 }
386 }
387
388 static const AIOCBInfo trim_aiocb_info = {
389 .aiocb_size = sizeof(TrimAIOCB),
390 .cancel_async = trim_aio_cancel,
391 };
392
393 static void ide_trim_bh_cb(void *opaque)
394 {
395 TrimAIOCB *iocb = opaque;
396
397 iocb->common.cb(iocb->common.opaque, iocb->ret);
398
399 qemu_bh_delete(iocb->bh);
400 iocb->bh = NULL;
401 qemu_aio_unref(iocb);
402 }
403
404 static void ide_issue_trim_cb(void *opaque, int ret)
405 {
406 TrimAIOCB *iocb = opaque;
407 if (ret >= 0) {
408 while (iocb->j < iocb->qiov->niov) {
409 int j = iocb->j;
410 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
411 int i = iocb->i;
412 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
413
414 /* 6-byte LBA + 2-byte range per entry */
415 uint64_t entry = le64_to_cpu(buffer[i]);
416 uint64_t sector = entry & 0x0000ffffffffffffULL;
417 uint16_t count = entry >> 48;
418
419 if (count == 0) {
420 continue;
421 }
422
423 /* Got an entry! Submit and exit. */
424 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
425 ide_issue_trim_cb, opaque);
426 return;
427 }
428
429 iocb->j++;
430 iocb->i = -1;
431 }
432 } else {
433 iocb->ret = ret;
434 }
435
436 iocb->aiocb = NULL;
437 if (iocb->bh) {
438 qemu_bh_schedule(iocb->bh);
439 }
440 }
441
442 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
443 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
444 BlockCompletionFunc *cb, void *opaque)
445 {
446 TrimAIOCB *iocb;
447
448 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
449 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
450 iocb->ret = 0;
451 iocb->qiov = qiov;
452 iocb->i = -1;
453 iocb->j = 0;
454 ide_issue_trim_cb(iocb, 0);
455 return &iocb->common;
456 }
457
458 static inline void ide_abort_command(IDEState *s)
459 {
460 ide_transfer_stop(s);
461 s->status = READY_STAT | ERR_STAT;
462 s->error = ABRT_ERR;
463 }
464
465 /* prepare data transfer and tell what to do after */
466 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
467 EndTransferFunc *end_transfer_func)
468 {
469 s->end_transfer_func = end_transfer_func;
470 s->data_ptr = buf;
471 s->data_end = buf + size;
472 if (!(s->status & ERR_STAT)) {
473 s->status |= DRQ_STAT;
474 }
475 if (s->bus->dma->ops->start_transfer) {
476 s->bus->dma->ops->start_transfer(s->bus->dma);
477 }
478 }
479
480 static void ide_cmd_done(IDEState *s)
481 {
482 if (s->bus->dma->ops->cmd_done) {
483 s->bus->dma->ops->cmd_done(s->bus->dma);
484 }
485 }
486
487 void ide_transfer_stop(IDEState *s)
488 {
489 s->end_transfer_func = ide_transfer_stop;
490 s->data_ptr = s->io_buffer;
491 s->data_end = s->io_buffer;
492 s->status &= ~DRQ_STAT;
493 ide_cmd_done(s);
494 }
495
496 int64_t ide_get_sector(IDEState *s)
497 {
498 int64_t sector_num;
499 if (s->select & 0x40) {
500 /* lba */
501 if (!s->lba48) {
502 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
503 (s->lcyl << 8) | s->sector;
504 } else {
505 sector_num = ((int64_t)s->hob_hcyl << 40) |
506 ((int64_t) s->hob_lcyl << 32) |
507 ((int64_t) s->hob_sector << 24) |
508 ((int64_t) s->hcyl << 16) |
509 ((int64_t) s->lcyl << 8) | s->sector;
510 }
511 } else {
512 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
513 (s->select & 0x0f) * s->sectors + (s->sector - 1);
514 }
515 return sector_num;
516 }
517
518 void ide_set_sector(IDEState *s, int64_t sector_num)
519 {
520 unsigned int cyl, r;
521 if (s->select & 0x40) {
522 if (!s->lba48) {
523 s->select = (s->select & 0xf0) | (sector_num >> 24);
524 s->hcyl = (sector_num >> 16);
525 s->lcyl = (sector_num >> 8);
526 s->sector = (sector_num);
527 } else {
528 s->sector = sector_num;
529 s->lcyl = sector_num >> 8;
530 s->hcyl = sector_num >> 16;
531 s->hob_sector = sector_num >> 24;
532 s->hob_lcyl = sector_num >> 32;
533 s->hob_hcyl = sector_num >> 40;
534 }
535 } else {
536 cyl = sector_num / (s->heads * s->sectors);
537 r = sector_num % (s->heads * s->sectors);
538 s->hcyl = cyl >> 8;
539 s->lcyl = cyl;
540 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
541 s->sector = (r % s->sectors) + 1;
542 }
543 }
544
545 static void ide_rw_error(IDEState *s) {
546 ide_abort_command(s);
547 ide_set_irq(s->bus);
548 }
549
550 static bool ide_sect_range_ok(IDEState *s,
551 uint64_t sector, uint64_t nb_sectors)
552 {
553 uint64_t total_sectors;
554
555 blk_get_geometry(s->blk, &total_sectors);
556 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
557 return false;
558 }
559 return true;
560 }
561
562 static void ide_sector_read_cb(void *opaque, int ret)
563 {
564 IDEState *s = opaque;
565 int n;
566
567 s->pio_aiocb = NULL;
568 s->status &= ~BUSY_STAT;
569
570 if (ret == -ECANCELED) {
571 return;
572 }
573 block_acct_done(blk_get_stats(s->blk), &s->acct);
574 if (ret != 0) {
575 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
576 IDE_RETRY_READ)) {
577 return;
578 }
579 }
580
581 n = s->nsector;
582 if (n > s->req_nb_sectors) {
583 n = s->req_nb_sectors;
584 }
585
586 /* Allow the guest to read the io_buffer */
587 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
588
589 ide_set_irq(s->bus);
590
591 ide_set_sector(s, ide_get_sector(s) + n);
592 s->nsector -= n;
593 }
594
595 void ide_sector_read(IDEState *s)
596 {
597 int64_t sector_num;
598 int n;
599
600 s->status = READY_STAT | SEEK_STAT;
601 s->error = 0; /* not needed by IDE spec, but needed by Windows */
602 sector_num = ide_get_sector(s);
603 n = s->nsector;
604
605 if (n == 0) {
606 ide_transfer_stop(s);
607 return;
608 }
609
610 s->status |= BUSY_STAT;
611
612 if (n > s->req_nb_sectors) {
613 n = s->req_nb_sectors;
614 }
615
616 #if defined(DEBUG_IDE)
617 printf("sector=%" PRId64 "\n", sector_num);
618 #endif
619
620 if (!ide_sect_range_ok(s, sector_num, n)) {
621 ide_rw_error(s);
622 return;
623 }
624
625 s->iov.iov_base = s->io_buffer;
626 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
627 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
628
629 block_acct_start(blk_get_stats(s->blk), &s->acct,
630 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
631 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n,
632 ide_sector_read_cb, s);
633 }
634
635 static void dma_buf_commit(IDEState *s)
636 {
637 qemu_sglist_destroy(&s->sg);
638 }
639
640 void ide_set_inactive(IDEState *s, bool more)
641 {
642 s->bus->dma->aiocb = NULL;
643 if (s->bus->dma->ops->set_inactive) {
644 s->bus->dma->ops->set_inactive(s->bus->dma, more);
645 }
646 ide_cmd_done(s);
647 }
648
649 void ide_dma_error(IDEState *s)
650 {
651 ide_abort_command(s);
652 ide_set_inactive(s, false);
653 ide_set_irq(s->bus);
654 }
655
656 static int ide_handle_rw_error(IDEState *s, int error, int op)
657 {
658 bool is_read = (op & IDE_RETRY_READ) != 0;
659 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
660
661 if (action == BLOCK_ERROR_ACTION_STOP) {
662 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
663 s->bus->error_status = op;
664 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
665 if (op & IDE_RETRY_DMA) {
666 dma_buf_commit(s);
667 ide_dma_error(s);
668 } else {
669 ide_rw_error(s);
670 }
671 }
672 blk_error_action(s->blk, action, is_read, error);
673 return action != BLOCK_ERROR_ACTION_IGNORE;
674 }
675
676 void ide_dma_cb(void *opaque, int ret)
677 {
678 IDEState *s = opaque;
679 int n;
680 int64_t sector_num;
681 bool stay_active = false;
682
683 if (ret == -ECANCELED) {
684 return;
685 }
686 if (ret < 0) {
687 int op = IDE_RETRY_DMA;
688
689 if (s->dma_cmd == IDE_DMA_READ)
690 op |= IDE_RETRY_READ;
691 else if (s->dma_cmd == IDE_DMA_TRIM)
692 op |= IDE_RETRY_TRIM;
693
694 if (ide_handle_rw_error(s, -ret, op)) {
695 return;
696 }
697 }
698
699 n = s->io_buffer_size >> 9;
700 if (n > s->nsector) {
701 /* The PRDs were longer than needed for this request. Shorten them so
702 * we don't get a negative remainder. The Active bit must remain set
703 * after the request completes. */
704 n = s->nsector;
705 stay_active = true;
706 }
707
708 sector_num = ide_get_sector(s);
709 if (n > 0) {
710 dma_buf_commit(s);
711 sector_num += n;
712 ide_set_sector(s, sector_num);
713 s->nsector -= n;
714 }
715
716 /* end of transfer ? */
717 if (s->nsector == 0) {
718 s->status = READY_STAT | SEEK_STAT;
719 ide_set_irq(s->bus);
720 goto eot;
721 }
722
723 /* launch next transfer */
724 n = s->nsector;
725 s->io_buffer_index = 0;
726 s->io_buffer_size = n * 512;
727 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
728 /* The PRDs were too short. Reset the Active bit, but don't raise an
729 * interrupt. */
730 s->status = READY_STAT | SEEK_STAT;
731 goto eot;
732 }
733
734 #ifdef DEBUG_AIO
735 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
736 sector_num, n, s->dma_cmd);
737 #endif
738
739 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
740 !ide_sect_range_ok(s, sector_num, n)) {
741 dma_buf_commit(s);
742 ide_dma_error(s);
743 return;
744 }
745
746 switch (s->dma_cmd) {
747 case IDE_DMA_READ:
748 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
749 ide_dma_cb, s);
750 break;
751 case IDE_DMA_WRITE:
752 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
753 ide_dma_cb, s);
754 break;
755 case IDE_DMA_TRIM:
756 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
757 ide_issue_trim, ide_dma_cb, s,
758 DMA_DIRECTION_TO_DEVICE);
759 break;
760 }
761 return;
762
763 eot:
764 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
765 block_acct_done(blk_get_stats(s->blk), &s->acct);
766 }
767 ide_set_inactive(s, stay_active);
768 }
769
770 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
771 {
772 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
773 s->io_buffer_index = 0;
774 s->io_buffer_size = 0;
775 s->dma_cmd = dma_cmd;
776
777 switch (dma_cmd) {
778 case IDE_DMA_READ:
779 block_acct_start(blk_get_stats(s->blk), &s->acct,
780 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
781 break;
782 case IDE_DMA_WRITE:
783 block_acct_start(blk_get_stats(s->blk), &s->acct,
784 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
785 break;
786 default:
787 break;
788 }
789
790 ide_start_dma(s, ide_dma_cb);
791 }
792
793 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
794 {
795 if (s->bus->dma->ops->start_dma) {
796 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
797 }
798 }
799
800 static void ide_sector_write_timer_cb(void *opaque)
801 {
802 IDEState *s = opaque;
803 ide_set_irq(s->bus);
804 }
805
806 static void ide_sector_write_cb(void *opaque, int ret)
807 {
808 IDEState *s = opaque;
809 int n;
810
811 if (ret == -ECANCELED) {
812 return;
813 }
814 block_acct_done(blk_get_stats(s->blk), &s->acct);
815
816 s->pio_aiocb = NULL;
817 s->status &= ~BUSY_STAT;
818
819 if (ret != 0) {
820 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
821 return;
822 }
823 }
824
825 n = s->nsector;
826 if (n > s->req_nb_sectors) {
827 n = s->req_nb_sectors;
828 }
829 s->nsector -= n;
830 if (s->nsector == 0) {
831 /* no more sectors to write */
832 ide_transfer_stop(s);
833 } else {
834 int n1 = s->nsector;
835 if (n1 > s->req_nb_sectors) {
836 n1 = s->req_nb_sectors;
837 }
838 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
839 ide_sector_write);
840 }
841 ide_set_sector(s, ide_get_sector(s) + n);
842
843 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
844 /* It seems there is a bug in the Windows 2000 installer HDD
845 IDE driver which fills the disk with empty logs when the
846 IDE write IRQ comes too early. This hack tries to correct
847 that at the expense of slower write performances. Use this
848 option _only_ to install Windows 2000. You must disable it
849 for normal use. */
850 timer_mod(s->sector_write_timer,
851 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
852 } else {
853 ide_set_irq(s->bus);
854 }
855 }
856
857 void ide_sector_write(IDEState *s)
858 {
859 int64_t sector_num;
860 int n;
861
862 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
863 sector_num = ide_get_sector(s);
864 #if defined(DEBUG_IDE)
865 printf("sector=%" PRId64 "\n", sector_num);
866 #endif
867 n = s->nsector;
868 if (n > s->req_nb_sectors) {
869 n = s->req_nb_sectors;
870 }
871
872 if (!ide_sect_range_ok(s, sector_num, n)) {
873 ide_rw_error(s);
874 return;
875 }
876
877 s->iov.iov_base = s->io_buffer;
878 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
879 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
880
881 block_acct_start(blk_get_stats(s->blk), &s->acct,
882 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
883 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
884 ide_sector_write_cb, s);
885 }
886
887 static void ide_flush_cb(void *opaque, int ret)
888 {
889 IDEState *s = opaque;
890
891 s->pio_aiocb = NULL;
892
893 if (ret == -ECANCELED) {
894 return;
895 }
896 if (ret < 0) {
897 /* XXX: What sector number to set here? */
898 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
899 return;
900 }
901 }
902
903 if (s->blk) {
904 block_acct_done(blk_get_stats(s->blk), &s->acct);
905 }
906 s->status = READY_STAT | SEEK_STAT;
907 ide_cmd_done(s);
908 ide_set_irq(s->bus);
909 }
910
911 void ide_flush_cache(IDEState *s)
912 {
913 if (s->blk == NULL) {
914 ide_flush_cb(s, 0);
915 return;
916 }
917
918 s->status |= BUSY_STAT;
919 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
920 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
921 }
922
923 static void ide_cfata_metadata_inquiry(IDEState *s)
924 {
925 uint16_t *p;
926 uint32_t spd;
927
928 p = (uint16_t *) s->io_buffer;
929 memset(p, 0, 0x200);
930 spd = ((s->mdata_size - 1) >> 9) + 1;
931
932 put_le16(p + 0, 0x0001); /* Data format revision */
933 put_le16(p + 1, 0x0000); /* Media property: silicon */
934 put_le16(p + 2, s->media_changed); /* Media status */
935 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
936 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
937 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
938 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
939 }
940
941 static void ide_cfata_metadata_read(IDEState *s)
942 {
943 uint16_t *p;
944
945 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
946 s->status = ERR_STAT;
947 s->error = ABRT_ERR;
948 return;
949 }
950
951 p = (uint16_t *) s->io_buffer;
952 memset(p, 0, 0x200);
953
954 put_le16(p + 0, s->media_changed); /* Media status */
955 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
956 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
957 s->nsector << 9), 0x200 - 2));
958 }
959
960 static void ide_cfata_metadata_write(IDEState *s)
961 {
962 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
963 s->status = ERR_STAT;
964 s->error = ABRT_ERR;
965 return;
966 }
967
968 s->media_changed = 0;
969
970 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
971 s->io_buffer + 2,
972 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
973 s->nsector << 9), 0x200 - 2));
974 }
975
976 /* called when the inserted state of the media has changed */
977 static void ide_cd_change_cb(void *opaque, bool load)
978 {
979 IDEState *s = opaque;
980 uint64_t nb_sectors;
981
982 s->tray_open = !load;
983 blk_get_geometry(s->blk, &nb_sectors);
984 s->nb_sectors = nb_sectors;
985
986 /*
987 * First indicate to the guest that a CD has been removed. That's
988 * done on the next command the guest sends us.
989 *
990 * Then we set UNIT_ATTENTION, by which the guest will
991 * detect a new CD in the drive. See ide_atapi_cmd() for details.
992 */
993 s->cdrom_changed = 1;
994 s->events.new_media = true;
995 s->events.eject_request = false;
996 ide_set_irq(s->bus);
997 }
998
999 static void ide_cd_eject_request_cb(void *opaque, bool force)
1000 {
1001 IDEState *s = opaque;
1002
1003 s->events.eject_request = true;
1004 if (force) {
1005 s->tray_locked = false;
1006 }
1007 ide_set_irq(s->bus);
1008 }
1009
1010 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1011 {
1012 s->lba48 = lba48;
1013
1014 /* handle the 'magic' 0 nsector count conversion here. to avoid
1015 * fiddling with the rest of the read logic, we just store the
1016 * full sector count in ->nsector and ignore ->hob_nsector from now
1017 */
1018 if (!s->lba48) {
1019 if (!s->nsector)
1020 s->nsector = 256;
1021 } else {
1022 if (!s->nsector && !s->hob_nsector)
1023 s->nsector = 65536;
1024 else {
1025 int lo = s->nsector;
1026 int hi = s->hob_nsector;
1027
1028 s->nsector = (hi << 8) | lo;
1029 }
1030 }
1031 }
1032
1033 static void ide_clear_hob(IDEBus *bus)
1034 {
1035 /* any write clears HOB high bit of device control register */
1036 bus->ifs[0].select &= ~(1 << 7);
1037 bus->ifs[1].select &= ~(1 << 7);
1038 }
1039
1040 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1041 {
1042 IDEBus *bus = opaque;
1043
1044 #ifdef DEBUG_IDE
1045 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1046 #endif
1047
1048 addr &= 7;
1049
1050 /* ignore writes to command block while busy with previous command */
1051 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1052 return;
1053
1054 switch(addr) {
1055 case 0:
1056 break;
1057 case 1:
1058 ide_clear_hob(bus);
1059 /* NOTE: data is written to the two drives */
1060 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1061 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1062 bus->ifs[0].feature = val;
1063 bus->ifs[1].feature = val;
1064 break;
1065 case 2:
1066 ide_clear_hob(bus);
1067 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1068 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1069 bus->ifs[0].nsector = val;
1070 bus->ifs[1].nsector = val;
1071 break;
1072 case 3:
1073 ide_clear_hob(bus);
1074 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1075 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1076 bus->ifs[0].sector = val;
1077 bus->ifs[1].sector = val;
1078 break;
1079 case 4:
1080 ide_clear_hob(bus);
1081 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1082 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1083 bus->ifs[0].lcyl = val;
1084 bus->ifs[1].lcyl = val;
1085 break;
1086 case 5:
1087 ide_clear_hob(bus);
1088 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1089 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1090 bus->ifs[0].hcyl = val;
1091 bus->ifs[1].hcyl = val;
1092 break;
1093 case 6:
1094 /* FIXME: HOB readback uses bit 7 */
1095 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1096 bus->ifs[1].select = (val | 0x10) | 0xa0;
1097 /* select drive */
1098 bus->unit = (val >> 4) & 1;
1099 break;
1100 default:
1101 case 7:
1102 /* command */
1103 ide_exec_cmd(bus, val);
1104 break;
1105 }
1106 }
1107
1108 static bool cmd_nop(IDEState *s, uint8_t cmd)
1109 {
1110 return true;
1111 }
1112
1113 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1114 {
1115 switch (s->feature) {
1116 case DSM_TRIM:
1117 if (s->blk) {
1118 ide_sector_start_dma(s, IDE_DMA_TRIM);
1119 return false;
1120 }
1121 break;
1122 }
1123
1124 ide_abort_command(s);
1125 return true;
1126 }
1127
1128 static bool cmd_identify(IDEState *s, uint8_t cmd)
1129 {
1130 if (s->blk && s->drive_kind != IDE_CD) {
1131 if (s->drive_kind != IDE_CFATA) {
1132 ide_identify(s);
1133 } else {
1134 ide_cfata_identify(s);
1135 }
1136 s->status = READY_STAT | SEEK_STAT;
1137 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1138 ide_set_irq(s->bus);
1139 return false;
1140 } else {
1141 if (s->drive_kind == IDE_CD) {
1142 ide_set_signature(s);
1143 }
1144 ide_abort_command(s);
1145 }
1146
1147 return true;
1148 }
1149
1150 static bool cmd_verify(IDEState *s, uint8_t cmd)
1151 {
1152 bool lba48 = (cmd == WIN_VERIFY_EXT);
1153
1154 /* do sector number check ? */
1155 ide_cmd_lba48_transform(s, lba48);
1156
1157 return true;
1158 }
1159
1160 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1161 {
1162 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1163 /* Disable Read and Write Multiple */
1164 s->mult_sectors = 0;
1165 } else if ((s->nsector & 0xff) != 0 &&
1166 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1167 (s->nsector & (s->nsector - 1)) != 0)) {
1168 ide_abort_command(s);
1169 } else {
1170 s->mult_sectors = s->nsector & 0xff;
1171 }
1172
1173 return true;
1174 }
1175
1176 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1177 {
1178 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1179
1180 if (!s->blk || !s->mult_sectors) {
1181 ide_abort_command(s);
1182 return true;
1183 }
1184
1185 ide_cmd_lba48_transform(s, lba48);
1186 s->req_nb_sectors = s->mult_sectors;
1187 ide_sector_read(s);
1188 return false;
1189 }
1190
1191 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1192 {
1193 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1194 int n;
1195
1196 if (!s->blk || !s->mult_sectors) {
1197 ide_abort_command(s);
1198 return true;
1199 }
1200
1201 ide_cmd_lba48_transform(s, lba48);
1202
1203 s->req_nb_sectors = s->mult_sectors;
1204 n = MIN(s->nsector, s->req_nb_sectors);
1205
1206 s->status = SEEK_STAT | READY_STAT;
1207 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1208
1209 s->media_changed = 1;
1210
1211 return false;
1212 }
1213
1214 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1215 {
1216 bool lba48 = (cmd == WIN_READ_EXT);
1217
1218 if (s->drive_kind == IDE_CD) {
1219 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1220 ide_abort_command(s);
1221 return true;
1222 }
1223
1224 if (!s->blk) {
1225 ide_abort_command(s);
1226 return true;
1227 }
1228
1229 ide_cmd_lba48_transform(s, lba48);
1230 s->req_nb_sectors = 1;
1231 ide_sector_read(s);
1232
1233 return false;
1234 }
1235
1236 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1237 {
1238 bool lba48 = (cmd == WIN_WRITE_EXT);
1239
1240 if (!s->blk) {
1241 ide_abort_command(s);
1242 return true;
1243 }
1244
1245 ide_cmd_lba48_transform(s, lba48);
1246
1247 s->req_nb_sectors = 1;
1248 s->status = SEEK_STAT | READY_STAT;
1249 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1250
1251 s->media_changed = 1;
1252
1253 return false;
1254 }
1255
1256 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1257 {
1258 bool lba48 = (cmd == WIN_READDMA_EXT);
1259
1260 if (!s->blk) {
1261 ide_abort_command(s);
1262 return true;
1263 }
1264
1265 ide_cmd_lba48_transform(s, lba48);
1266 ide_sector_start_dma(s, IDE_DMA_READ);
1267
1268 return false;
1269 }
1270
1271 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1272 {
1273 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1274
1275 if (!s->blk) {
1276 ide_abort_command(s);
1277 return true;
1278 }
1279
1280 ide_cmd_lba48_transform(s, lba48);
1281 ide_sector_start_dma(s, IDE_DMA_WRITE);
1282
1283 s->media_changed = 1;
1284
1285 return false;
1286 }
1287
1288 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1289 {
1290 ide_flush_cache(s);
1291 return false;
1292 }
1293
1294 static bool cmd_seek(IDEState *s, uint8_t cmd)
1295 {
1296 /* XXX: Check that seek is within bounds */
1297 return true;
1298 }
1299
1300 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1301 {
1302 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1303
1304 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1305 if (s->nb_sectors == 0) {
1306 ide_abort_command(s);
1307 return true;
1308 }
1309
1310 ide_cmd_lba48_transform(s, lba48);
1311 ide_set_sector(s, s->nb_sectors - 1);
1312
1313 return true;
1314 }
1315
1316 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1317 {
1318 s->nsector = 0xff; /* device active or idle */
1319 return true;
1320 }
1321
1322 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1323 {
1324 uint16_t *identify_data;
1325
1326 if (!s->blk) {
1327 ide_abort_command(s);
1328 return true;
1329 }
1330
1331 /* XXX: valid for CDROM ? */
1332 switch (s->feature) {
1333 case 0x02: /* write cache enable */
1334 blk_set_enable_write_cache(s->blk, true);
1335 identify_data = (uint16_t *)s->identify_data;
1336 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1337 return true;
1338 case 0x82: /* write cache disable */
1339 blk_set_enable_write_cache(s->blk, false);
1340 identify_data = (uint16_t *)s->identify_data;
1341 put_le16(identify_data + 85, (1 << 14) | 1);
1342 ide_flush_cache(s);
1343 return false;
1344 case 0xcc: /* reverting to power-on defaults enable */
1345 case 0x66: /* reverting to power-on defaults disable */
1346 case 0xaa: /* read look-ahead enable */
1347 case 0x55: /* read look-ahead disable */
1348 case 0x05: /* set advanced power management mode */
1349 case 0x85: /* disable advanced power management mode */
1350 case 0x69: /* NOP */
1351 case 0x67: /* NOP */
1352 case 0x96: /* NOP */
1353 case 0x9a: /* NOP */
1354 case 0x42: /* enable Automatic Acoustic Mode */
1355 case 0xc2: /* disable Automatic Acoustic Mode */
1356 return true;
1357 case 0x03: /* set transfer mode */
1358 {
1359 uint8_t val = s->nsector & 0x07;
1360 identify_data = (uint16_t *)s->identify_data;
1361
1362 switch (s->nsector >> 3) {
1363 case 0x00: /* pio default */
1364 case 0x01: /* pio mode */
1365 put_le16(identify_data + 62, 0x07);
1366 put_le16(identify_data + 63, 0x07);
1367 put_le16(identify_data + 88, 0x3f);
1368 break;
1369 case 0x02: /* sigle word dma mode*/
1370 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1371 put_le16(identify_data + 63, 0x07);
1372 put_le16(identify_data + 88, 0x3f);
1373 break;
1374 case 0x04: /* mdma mode */
1375 put_le16(identify_data + 62, 0x07);
1376 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1377 put_le16(identify_data + 88, 0x3f);
1378 break;
1379 case 0x08: /* udma mode */
1380 put_le16(identify_data + 62, 0x07);
1381 put_le16(identify_data + 63, 0x07);
1382 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1383 break;
1384 default:
1385 goto abort_cmd;
1386 }
1387 return true;
1388 }
1389 }
1390
1391 abort_cmd:
1392 ide_abort_command(s);
1393 return true;
1394 }
1395
1396
1397 /*** ATAPI commands ***/
1398
1399 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1400 {
1401 ide_atapi_identify(s);
1402 s->status = READY_STAT | SEEK_STAT;
1403 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1404 ide_set_irq(s->bus);
1405 return false;
1406 }
1407
1408 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1409 {
1410 ide_set_signature(s);
1411
1412 if (s->drive_kind == IDE_CD) {
1413 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1414 * devices to return a clear status register
1415 * with READY_STAT *not* set. */
1416 s->error = 0x01;
1417 } else {
1418 s->status = READY_STAT | SEEK_STAT;
1419 /* The bits of the error register are not as usual for this command!
1420 * They are part of the regular output (this is why ERR_STAT isn't set)
1421 * Device 0 passed, Device 1 passed or not present. */
1422 s->error = 0x01;
1423 ide_set_irq(s->bus);
1424 }
1425
1426 return false;
1427 }
1428
1429 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1430 {
1431 ide_set_signature(s);
1432 s->status = 0x00; /* NOTE: READY is _not_ set */
1433 s->error = 0x01;
1434
1435 return false;
1436 }
1437
1438 static bool cmd_packet(IDEState *s, uint8_t cmd)
1439 {
1440 /* overlapping commands not supported */
1441 if (s->feature & 0x02) {
1442 ide_abort_command(s);
1443 return true;
1444 }
1445
1446 s->status = READY_STAT | SEEK_STAT;
1447 s->atapi_dma = s->feature & 1;
1448 s->nsector = 1;
1449 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1450 ide_atapi_cmd);
1451 return false;
1452 }
1453
1454
1455 /*** CF-ATA commands ***/
1456
1457 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1458 {
1459 s->error = 0x09; /* miscellaneous error */
1460 s->status = READY_STAT | SEEK_STAT;
1461 ide_set_irq(s->bus);
1462
1463 return false;
1464 }
1465
1466 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1467 {
1468 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1469 * required for Windows 8 to work with AHCI */
1470
1471 if (cmd == CFA_WEAR_LEVEL) {
1472 s->nsector = 0;
1473 }
1474
1475 if (cmd == CFA_ERASE_SECTORS) {
1476 s->media_changed = 1;
1477 }
1478
1479 return true;
1480 }
1481
1482 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1483 {
1484 s->status = READY_STAT | SEEK_STAT;
1485
1486 memset(s->io_buffer, 0, 0x200);
1487 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1488 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1489 s->io_buffer[0x02] = s->select; /* Head */
1490 s->io_buffer[0x03] = s->sector; /* Sector */
1491 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1492 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1493 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1494 s->io_buffer[0x13] = 0x00; /* Erase flag */
1495 s->io_buffer[0x18] = 0x00; /* Hot count */
1496 s->io_buffer[0x19] = 0x00; /* Hot count */
1497 s->io_buffer[0x1a] = 0x01; /* Hot count */
1498
1499 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1500 ide_set_irq(s->bus);
1501
1502 return false;
1503 }
1504
1505 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1506 {
1507 switch (s->feature) {
1508 case 0x02: /* Inquiry Metadata Storage */
1509 ide_cfata_metadata_inquiry(s);
1510 break;
1511 case 0x03: /* Read Metadata Storage */
1512 ide_cfata_metadata_read(s);
1513 break;
1514 case 0x04: /* Write Metadata Storage */
1515 ide_cfata_metadata_write(s);
1516 break;
1517 default:
1518 ide_abort_command(s);
1519 return true;
1520 }
1521
1522 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1523 s->status = 0x00; /* NOTE: READY is _not_ set */
1524 ide_set_irq(s->bus);
1525
1526 return false;
1527 }
1528
1529 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1530 {
1531 switch (s->feature) {
1532 case 0x01: /* sense temperature in device */
1533 s->nsector = 0x50; /* +20 C */
1534 break;
1535 default:
1536 ide_abort_command(s);
1537 return true;
1538 }
1539
1540 return true;
1541 }
1542
1543
1544 /*** SMART commands ***/
1545
1546 static bool cmd_smart(IDEState *s, uint8_t cmd)
1547 {
1548 int n;
1549
1550 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1551 goto abort_cmd;
1552 }
1553
1554 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1555 goto abort_cmd;
1556 }
1557
1558 switch (s->feature) {
1559 case SMART_DISABLE:
1560 s->smart_enabled = 0;
1561 return true;
1562
1563 case SMART_ENABLE:
1564 s->smart_enabled = 1;
1565 return true;
1566
1567 case SMART_ATTR_AUTOSAVE:
1568 switch (s->sector) {
1569 case 0x00:
1570 s->smart_autosave = 0;
1571 break;
1572 case 0xf1:
1573 s->smart_autosave = 1;
1574 break;
1575 default:
1576 goto abort_cmd;
1577 }
1578 return true;
1579
1580 case SMART_STATUS:
1581 if (!s->smart_errors) {
1582 s->hcyl = 0xc2;
1583 s->lcyl = 0x4f;
1584 } else {
1585 s->hcyl = 0x2c;
1586 s->lcyl = 0xf4;
1587 }
1588 return true;
1589
1590 case SMART_READ_THRESH:
1591 memset(s->io_buffer, 0, 0x200);
1592 s->io_buffer[0] = 0x01; /* smart struct version */
1593
1594 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1595 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1596 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1597 }
1598
1599 /* checksum */
1600 for (n = 0; n < 511; n++) {
1601 s->io_buffer[511] += s->io_buffer[n];
1602 }
1603 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1604
1605 s->status = READY_STAT | SEEK_STAT;
1606 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1607 ide_set_irq(s->bus);
1608 return false;
1609
1610 case SMART_READ_DATA:
1611 memset(s->io_buffer, 0, 0x200);
1612 s->io_buffer[0] = 0x01; /* smart struct version */
1613
1614 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1615 int i;
1616 for (i = 0; i < 11; i++) {
1617 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1618 }
1619 }
1620
1621 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1622 if (s->smart_selftest_count == 0) {
1623 s->io_buffer[363] = 0;
1624 } else {
1625 s->io_buffer[363] =
1626 s->smart_selftest_data[3 +
1627 (s->smart_selftest_count - 1) *
1628 24];
1629 }
1630 s->io_buffer[364] = 0x20;
1631 s->io_buffer[365] = 0x01;
1632 /* offline data collection capacity: execute + self-test*/
1633 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1634 s->io_buffer[368] = 0x03; /* smart capability (1) */
1635 s->io_buffer[369] = 0x00; /* smart capability (2) */
1636 s->io_buffer[370] = 0x01; /* error logging supported */
1637 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1638 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1639 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1640
1641 for (n = 0; n < 511; n++) {
1642 s->io_buffer[511] += s->io_buffer[n];
1643 }
1644 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1645
1646 s->status = READY_STAT | SEEK_STAT;
1647 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1648 ide_set_irq(s->bus);
1649 return false;
1650
1651 case SMART_READ_LOG:
1652 switch (s->sector) {
1653 case 0x01: /* summary smart error log */
1654 memset(s->io_buffer, 0, 0x200);
1655 s->io_buffer[0] = 0x01;
1656 s->io_buffer[1] = 0x00; /* no error entries */
1657 s->io_buffer[452] = s->smart_errors & 0xff;
1658 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1659
1660 for (n = 0; n < 511; n++) {
1661 s->io_buffer[511] += s->io_buffer[n];
1662 }
1663 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1664 break;
1665 case 0x06: /* smart self test log */
1666 memset(s->io_buffer, 0, 0x200);
1667 s->io_buffer[0] = 0x01;
1668 if (s->smart_selftest_count == 0) {
1669 s->io_buffer[508] = 0;
1670 } else {
1671 s->io_buffer[508] = s->smart_selftest_count;
1672 for (n = 2; n < 506; n++) {
1673 s->io_buffer[n] = s->smart_selftest_data[n];
1674 }
1675 }
1676
1677 for (n = 0; n < 511; n++) {
1678 s->io_buffer[511] += s->io_buffer[n];
1679 }
1680 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1681 break;
1682 default:
1683 goto abort_cmd;
1684 }
1685 s->status = READY_STAT | SEEK_STAT;
1686 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1687 ide_set_irq(s->bus);
1688 return false;
1689
1690 case SMART_EXECUTE_OFFLINE:
1691 switch (s->sector) {
1692 case 0: /* off-line routine */
1693 case 1: /* short self test */
1694 case 2: /* extended self test */
1695 s->smart_selftest_count++;
1696 if (s->smart_selftest_count > 21) {
1697 s->smart_selftest_count = 1;
1698 }
1699 n = 2 + (s->smart_selftest_count - 1) * 24;
1700 s->smart_selftest_data[n] = s->sector;
1701 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1702 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1703 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1704 break;
1705 default:
1706 goto abort_cmd;
1707 }
1708 return true;
1709 }
1710
1711 abort_cmd:
1712 ide_abort_command(s);
1713 return true;
1714 }
1715
1716 #define HD_OK (1u << IDE_HD)
1717 #define CD_OK (1u << IDE_CD)
1718 #define CFA_OK (1u << IDE_CFATA)
1719 #define HD_CFA_OK (HD_OK | CFA_OK)
1720 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1721
1722 /* Set the Disk Seek Completed status bit during completion */
1723 #define SET_DSC (1u << 8)
1724
1725 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1726 static const struct {
1727 /* Returns true if the completion code should be run */
1728 bool (*handler)(IDEState *s, uint8_t cmd);
1729 int flags;
1730 } ide_cmd_table[0x100] = {
1731 /* NOP not implemented, mandatory for CD */
1732 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1733 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1734 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1735 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1736 [WIN_READ] = { cmd_read_pio, ALL_OK },
1737 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1738 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1739 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1740 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1741 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1742 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1743 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1744 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1745 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1746 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1747 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1748 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1749 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1750 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1751 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1752 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1753 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1754 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1755 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1756 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1757 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1758 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1759 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1760 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1761 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1762 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1763 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1764 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1765 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1766 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1767 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1768 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1769 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1770 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1771 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1772 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1773 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1774 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1775 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1776 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1777 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1778 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1779 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1780 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1781 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1782 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1783 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1784 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1785 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1786 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1787 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
1788 };
1789
1790 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1791 {
1792 return cmd < ARRAY_SIZE(ide_cmd_table)
1793 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1794 }
1795
1796 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1797 {
1798 IDEState *s;
1799 bool complete;
1800
1801 #if defined(DEBUG_IDE)
1802 printf("ide: CMD=%02x\n", val);
1803 #endif
1804 s = idebus_active_if(bus);
1805 /* ignore commands to non existent slave */
1806 if (s != bus->ifs && !s->blk) {
1807 return;
1808 }
1809
1810 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1811 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1812 return;
1813
1814 if (!ide_cmd_permitted(s, val)) {
1815 ide_abort_command(s);
1816 ide_set_irq(s->bus);
1817 return;
1818 }
1819
1820 s->status = READY_STAT | BUSY_STAT;
1821 s->error = 0;
1822
1823 complete = ide_cmd_table[val].handler(s, val);
1824 if (complete) {
1825 s->status &= ~BUSY_STAT;
1826 assert(!!s->error == !!(s->status & ERR_STAT));
1827
1828 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1829 s->status |= SEEK_STAT;
1830 }
1831
1832 ide_cmd_done(s);
1833 ide_set_irq(s->bus);
1834 }
1835 }
1836
1837 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1838 {
1839 IDEBus *bus = opaque;
1840 IDEState *s = idebus_active_if(bus);
1841 uint32_t addr;
1842 int ret, hob;
1843
1844 addr = addr1 & 7;
1845 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1846 //hob = s->select & (1 << 7);
1847 hob = 0;
1848 switch(addr) {
1849 case 0:
1850 ret = 0xff;
1851 break;
1852 case 1:
1853 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1854 (s != bus->ifs && !s->blk)) {
1855 ret = 0;
1856 } else if (!hob) {
1857 ret = s->error;
1858 } else {
1859 ret = s->hob_feature;
1860 }
1861 break;
1862 case 2:
1863 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1864 ret = 0;
1865 } else if (!hob) {
1866 ret = s->nsector & 0xff;
1867 } else {
1868 ret = s->hob_nsector;
1869 }
1870 break;
1871 case 3:
1872 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1873 ret = 0;
1874 } else if (!hob) {
1875 ret = s->sector;
1876 } else {
1877 ret = s->hob_sector;
1878 }
1879 break;
1880 case 4:
1881 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1882 ret = 0;
1883 } else if (!hob) {
1884 ret = s->lcyl;
1885 } else {
1886 ret = s->hob_lcyl;
1887 }
1888 break;
1889 case 5:
1890 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1891 ret = 0;
1892 } else if (!hob) {
1893 ret = s->hcyl;
1894 } else {
1895 ret = s->hob_hcyl;
1896 }
1897 break;
1898 case 6:
1899 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1900 ret = 0;
1901 } else {
1902 ret = s->select;
1903 }
1904 break;
1905 default:
1906 case 7:
1907 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1908 (s != bus->ifs && !s->blk)) {
1909 ret = 0;
1910 } else {
1911 ret = s->status;
1912 }
1913 qemu_irq_lower(bus->irq);
1914 break;
1915 }
1916 #ifdef DEBUG_IDE
1917 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1918 #endif
1919 return ret;
1920 }
1921
1922 uint32_t ide_status_read(void *opaque, uint32_t addr)
1923 {
1924 IDEBus *bus = opaque;
1925 IDEState *s = idebus_active_if(bus);
1926 int ret;
1927
1928 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1929 (s != bus->ifs && !s->blk)) {
1930 ret = 0;
1931 } else {
1932 ret = s->status;
1933 }
1934 #ifdef DEBUG_IDE
1935 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1936 #endif
1937 return ret;
1938 }
1939
1940 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1941 {
1942 IDEBus *bus = opaque;
1943 IDEState *s;
1944 int i;
1945
1946 #ifdef DEBUG_IDE
1947 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1948 #endif
1949 /* common for both drives */
1950 if (!(bus->cmd & IDE_CMD_RESET) &&
1951 (val & IDE_CMD_RESET)) {
1952 /* reset low to high */
1953 for(i = 0;i < 2; i++) {
1954 s = &bus->ifs[i];
1955 s->status = BUSY_STAT | SEEK_STAT;
1956 s->error = 0x01;
1957 }
1958 } else if ((bus->cmd & IDE_CMD_RESET) &&
1959 !(val & IDE_CMD_RESET)) {
1960 /* high to low */
1961 for(i = 0;i < 2; i++) {
1962 s = &bus->ifs[i];
1963 if (s->drive_kind == IDE_CD)
1964 s->status = 0x00; /* NOTE: READY is _not_ set */
1965 else
1966 s->status = READY_STAT | SEEK_STAT;
1967 ide_set_signature(s);
1968 }
1969 }
1970
1971 bus->cmd = val;
1972 }
1973
1974 /*
1975 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1976 * transferred from the device to the guest), false if it's a PIO in
1977 */
1978 static bool ide_is_pio_out(IDEState *s)
1979 {
1980 if (s->end_transfer_func == ide_sector_write ||
1981 s->end_transfer_func == ide_atapi_cmd) {
1982 return false;
1983 } else if (s->end_transfer_func == ide_sector_read ||
1984 s->end_transfer_func == ide_transfer_stop ||
1985 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1986 s->end_transfer_func == ide_dummy_transfer_stop) {
1987 return true;
1988 }
1989
1990 abort();
1991 }
1992
1993 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1994 {
1995 IDEBus *bus = opaque;
1996 IDEState *s = idebus_active_if(bus);
1997 uint8_t *p;
1998
1999 /* PIO data access allowed only when DRQ bit is set. The result of a write
2000 * during PIO out is indeterminate, just ignore it. */
2001 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2002 return;
2003 }
2004
2005 p = s->data_ptr;
2006 *(uint16_t *)p = le16_to_cpu(val);
2007 p += 2;
2008 s->data_ptr = p;
2009 if (p >= s->data_end)
2010 s->end_transfer_func(s);
2011 }
2012
2013 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2014 {
2015 IDEBus *bus = opaque;
2016 IDEState *s = idebus_active_if(bus);
2017 uint8_t *p;
2018 int ret;
2019
2020 /* PIO data access allowed only when DRQ bit is set. The result of a read
2021 * during PIO in is indeterminate, return 0 and don't move forward. */
2022 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2023 return 0;
2024 }
2025
2026 p = s->data_ptr;
2027 ret = cpu_to_le16(*(uint16_t *)p);
2028 p += 2;
2029 s->data_ptr = p;
2030 if (p >= s->data_end)
2031 s->end_transfer_func(s);
2032 return ret;
2033 }
2034
2035 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2036 {
2037 IDEBus *bus = opaque;
2038 IDEState *s = idebus_active_if(bus);
2039 uint8_t *p;
2040
2041 /* PIO data access allowed only when DRQ bit is set. The result of a write
2042 * during PIO out is indeterminate, just ignore it. */
2043 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2044 return;
2045 }
2046
2047 p = s->data_ptr;
2048 *(uint32_t *)p = le32_to_cpu(val);
2049 p += 4;
2050 s->data_ptr = p;
2051 if (p >= s->data_end)
2052 s->end_transfer_func(s);
2053 }
2054
2055 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2056 {
2057 IDEBus *bus = opaque;
2058 IDEState *s = idebus_active_if(bus);
2059 uint8_t *p;
2060 int ret;
2061
2062 /* PIO data access allowed only when DRQ bit is set. The result of a read
2063 * during PIO in is indeterminate, return 0 and don't move forward. */
2064 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2065 return 0;
2066 }
2067
2068 p = s->data_ptr;
2069 ret = cpu_to_le32(*(uint32_t *)p);
2070 p += 4;
2071 s->data_ptr = p;
2072 if (p >= s->data_end)
2073 s->end_transfer_func(s);
2074 return ret;
2075 }
2076
2077 static void ide_dummy_transfer_stop(IDEState *s)
2078 {
2079 s->data_ptr = s->io_buffer;
2080 s->data_end = s->io_buffer;
2081 s->io_buffer[0] = 0xff;
2082 s->io_buffer[1] = 0xff;
2083 s->io_buffer[2] = 0xff;
2084 s->io_buffer[3] = 0xff;
2085 }
2086
2087 static void ide_reset(IDEState *s)
2088 {
2089 #ifdef DEBUG_IDE
2090 printf("ide: reset\n");
2091 #endif
2092
2093 if (s->pio_aiocb) {
2094 blk_aio_cancel(s->pio_aiocb);
2095 s->pio_aiocb = NULL;
2096 }
2097
2098 if (s->drive_kind == IDE_CFATA)
2099 s->mult_sectors = 0;
2100 else
2101 s->mult_sectors = MAX_MULT_SECTORS;
2102 /* ide regs */
2103 s->feature = 0;
2104 s->error = 0;
2105 s->nsector = 0;
2106 s->sector = 0;
2107 s->lcyl = 0;
2108 s->hcyl = 0;
2109
2110 /* lba48 */
2111 s->hob_feature = 0;
2112 s->hob_sector = 0;
2113 s->hob_nsector = 0;
2114 s->hob_lcyl = 0;
2115 s->hob_hcyl = 0;
2116
2117 s->select = 0xa0;
2118 s->status = READY_STAT | SEEK_STAT;
2119
2120 s->lba48 = 0;
2121
2122 /* ATAPI specific */
2123 s->sense_key = 0;
2124 s->asc = 0;
2125 s->cdrom_changed = 0;
2126 s->packet_transfer_size = 0;
2127 s->elementary_transfer_size = 0;
2128 s->io_buffer_index = 0;
2129 s->cd_sector_size = 0;
2130 s->atapi_dma = 0;
2131 s->tray_locked = 0;
2132 s->tray_open = 0;
2133 /* ATA DMA state */
2134 s->io_buffer_size = 0;
2135 s->req_nb_sectors = 0;
2136
2137 ide_set_signature(s);
2138 /* init the transfer handler so that 0xffff is returned on data
2139 accesses */
2140 s->end_transfer_func = ide_dummy_transfer_stop;
2141 ide_dummy_transfer_stop(s);
2142 s->media_changed = 0;
2143 }
2144
2145 void ide_bus_reset(IDEBus *bus)
2146 {
2147 bus->unit = 0;
2148 bus->cmd = 0;
2149 ide_reset(&bus->ifs[0]);
2150 ide_reset(&bus->ifs[1]);
2151 ide_clear_hob(bus);
2152
2153 /* pending async DMA */
2154 if (bus->dma->aiocb) {
2155 #ifdef DEBUG_AIO
2156 printf("aio_cancel\n");
2157 #endif
2158 blk_aio_cancel(bus->dma->aiocb);
2159 bus->dma->aiocb = NULL;
2160 }
2161
2162 /* reset dma provider too */
2163 if (bus->dma->ops->reset) {
2164 bus->dma->ops->reset(bus->dma);
2165 }
2166 }
2167
2168 static bool ide_cd_is_tray_open(void *opaque)
2169 {
2170 return ((IDEState *)opaque)->tray_open;
2171 }
2172
2173 static bool ide_cd_is_medium_locked(void *opaque)
2174 {
2175 return ((IDEState *)opaque)->tray_locked;
2176 }
2177
2178 static void ide_resize_cb(void *opaque)
2179 {
2180 IDEState *s = opaque;
2181 uint64_t nb_sectors;
2182
2183 if (!s->identify_set) {
2184 return;
2185 }
2186
2187 blk_get_geometry(s->blk, &nb_sectors);
2188 s->nb_sectors = nb_sectors;
2189
2190 /* Update the identify data buffer. */
2191 if (s->drive_kind == IDE_CFATA) {
2192 ide_cfata_identify_size(s);
2193 } else {
2194 /* IDE_CD uses a different set of callbacks entirely. */
2195 assert(s->drive_kind != IDE_CD);
2196 ide_identify_size(s);
2197 }
2198 }
2199
2200 static const BlockDevOps ide_cd_block_ops = {
2201 .change_media_cb = ide_cd_change_cb,
2202 .eject_request_cb = ide_cd_eject_request_cb,
2203 .is_tray_open = ide_cd_is_tray_open,
2204 .is_medium_locked = ide_cd_is_medium_locked,
2205 };
2206
2207 static const BlockDevOps ide_hd_block_ops = {
2208 .resize_cb = ide_resize_cb,
2209 };
2210
2211 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2212 const char *version, const char *serial, const char *model,
2213 uint64_t wwn,
2214 uint32_t cylinders, uint32_t heads, uint32_t secs,
2215 int chs_trans)
2216 {
2217 uint64_t nb_sectors;
2218
2219 s->blk = blk;
2220 s->drive_kind = kind;
2221
2222 blk_get_geometry(blk, &nb_sectors);
2223 s->cylinders = cylinders;
2224 s->heads = heads;
2225 s->sectors = secs;
2226 s->chs_trans = chs_trans;
2227 s->nb_sectors = nb_sectors;
2228 s->wwn = wwn;
2229 /* The SMART values should be preserved across power cycles
2230 but they aren't. */
2231 s->smart_enabled = 1;
2232 s->smart_autosave = 1;
2233 s->smart_errors = 0;
2234 s->smart_selftest_count = 0;
2235 if (kind == IDE_CD) {
2236 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2237 blk_set_guest_block_size(blk, 2048);
2238 } else {
2239 if (!blk_is_inserted(s->blk)) {
2240 error_report("Device needs media, but drive is empty");
2241 return -1;
2242 }
2243 if (blk_is_read_only(blk)) {
2244 error_report("Can't use a read-only drive");
2245 return -1;
2246 }
2247 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2248 }
2249 if (serial) {
2250 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2251 } else {
2252 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2253 "QM%05d", s->drive_serial);
2254 }
2255 if (model) {
2256 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2257 } else {
2258 switch (kind) {
2259 case IDE_CD:
2260 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2261 break;
2262 case IDE_CFATA:
2263 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2264 break;
2265 default:
2266 strcpy(s->drive_model_str, "QEMU HARDDISK");
2267 break;
2268 }
2269 }
2270
2271 if (version) {
2272 pstrcpy(s->version, sizeof(s->version), version);
2273 } else {
2274 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2275 }
2276
2277 ide_reset(s);
2278 blk_iostatus_enable(blk);
2279 return 0;
2280 }
2281
2282 static void ide_init1(IDEBus *bus, int unit)
2283 {
2284 static int drive_serial = 1;
2285 IDEState *s = &bus->ifs[unit];
2286
2287 s->bus = bus;
2288 s->unit = unit;
2289 s->drive_serial = drive_serial++;
2290 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2291 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2292 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2293 memset(s->io_buffer, 0, s->io_buffer_total_len);
2294
2295 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2296 memset(s->smart_selftest_data, 0, 512);
2297
2298 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2299 ide_sector_write_timer_cb, s);
2300 }
2301
2302 static int ide_nop_int(IDEDMA *dma, int x)
2303 {
2304 return 0;
2305 }
2306
2307 static void ide_nop_restart(void *opaque, int x, RunState y)
2308 {
2309 }
2310
2311 static const IDEDMAOps ide_dma_nop_ops = {
2312 .prepare_buf = ide_nop_int,
2313 .rw_buf = ide_nop_int,
2314 .set_unit = ide_nop_int,
2315 .restart_cb = ide_nop_restart,
2316 };
2317
2318 static IDEDMA ide_dma_nop = {
2319 .ops = &ide_dma_nop_ops,
2320 .aiocb = NULL,
2321 };
2322
2323 void ide_init2(IDEBus *bus, qemu_irq irq)
2324 {
2325 int i;
2326
2327 for(i = 0; i < 2; i++) {
2328 ide_init1(bus, i);
2329 ide_reset(&bus->ifs[i]);
2330 }
2331 bus->irq = irq;
2332 bus->dma = &ide_dma_nop;
2333 }
2334
2335 static const MemoryRegionPortio ide_portio_list[] = {
2336 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2337 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2338 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2339 PORTIO_END_OF_LIST(),
2340 };
2341
2342 static const MemoryRegionPortio ide_portio2_list[] = {
2343 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2344 PORTIO_END_OF_LIST(),
2345 };
2346
2347 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2348 {
2349 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2350 bridge has been setup properly to always register with ISA. */
2351 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2352
2353 if (iobase2) {
2354 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2355 }
2356 }
2357
2358 static bool is_identify_set(void *opaque, int version_id)
2359 {
2360 IDEState *s = opaque;
2361
2362 return s->identify_set != 0;
2363 }
2364
2365 static EndTransferFunc* transfer_end_table[] = {
2366 ide_sector_read,
2367 ide_sector_write,
2368 ide_transfer_stop,
2369 ide_atapi_cmd_reply_end,
2370 ide_atapi_cmd,
2371 ide_dummy_transfer_stop,
2372 };
2373
2374 static int transfer_end_table_idx(EndTransferFunc *fn)
2375 {
2376 int i;
2377
2378 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2379 if (transfer_end_table[i] == fn)
2380 return i;
2381
2382 return -1;
2383 }
2384
2385 static int ide_drive_post_load(void *opaque, int version_id)
2386 {
2387 IDEState *s = opaque;
2388
2389 if (s->identify_set) {
2390 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2391 }
2392 return 0;
2393 }
2394
2395 static int ide_drive_pio_post_load(void *opaque, int version_id)
2396 {
2397 IDEState *s = opaque;
2398
2399 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2400 return -EINVAL;
2401 }
2402 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2403 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2404 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2405
2406 return 0;
2407 }
2408
2409 static void ide_drive_pio_pre_save(void *opaque)
2410 {
2411 IDEState *s = opaque;
2412 int idx;
2413
2414 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2415 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2416
2417 idx = transfer_end_table_idx(s->end_transfer_func);
2418 if (idx == -1) {
2419 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2420 __func__);
2421 s->end_transfer_fn_idx = 2;
2422 } else {
2423 s->end_transfer_fn_idx = idx;
2424 }
2425 }
2426
2427 static bool ide_drive_pio_state_needed(void *opaque)
2428 {
2429 IDEState *s = opaque;
2430
2431 return ((s->status & DRQ_STAT) != 0)
2432 || (s->bus->error_status & IDE_RETRY_PIO);
2433 }
2434
2435 static bool ide_tray_state_needed(void *opaque)
2436 {
2437 IDEState *s = opaque;
2438
2439 return s->tray_open || s->tray_locked;
2440 }
2441
2442 static bool ide_atapi_gesn_needed(void *opaque)
2443 {
2444 IDEState *s = opaque;
2445
2446 return s->events.new_media || s->events.eject_request;
2447 }
2448
2449 static bool ide_error_needed(void *opaque)
2450 {
2451 IDEBus *bus = opaque;
2452
2453 return (bus->error_status != 0);
2454 }
2455
2456 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2457 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2458 .name ="ide_drive/atapi/gesn_state",
2459 .version_id = 1,
2460 .minimum_version_id = 1,
2461 .fields = (VMStateField[]) {
2462 VMSTATE_BOOL(events.new_media, IDEState),
2463 VMSTATE_BOOL(events.eject_request, IDEState),
2464 VMSTATE_END_OF_LIST()
2465 }
2466 };
2467
2468 static const VMStateDescription vmstate_ide_tray_state = {
2469 .name = "ide_drive/tray_state",
2470 .version_id = 1,
2471 .minimum_version_id = 1,
2472 .fields = (VMStateField[]) {
2473 VMSTATE_BOOL(tray_open, IDEState),
2474 VMSTATE_BOOL(tray_locked, IDEState),
2475 VMSTATE_END_OF_LIST()
2476 }
2477 };
2478
2479 static const VMStateDescription vmstate_ide_drive_pio_state = {
2480 .name = "ide_drive/pio_state",
2481 .version_id = 1,
2482 .minimum_version_id = 1,
2483 .pre_save = ide_drive_pio_pre_save,
2484 .post_load = ide_drive_pio_post_load,
2485 .fields = (VMStateField[]) {
2486 VMSTATE_INT32(req_nb_sectors, IDEState),
2487 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2488 vmstate_info_uint8, uint8_t),
2489 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2490 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2491 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2492 VMSTATE_INT32(elementary_transfer_size, IDEState),
2493 VMSTATE_INT32(packet_transfer_size, IDEState),
2494 VMSTATE_END_OF_LIST()
2495 }
2496 };
2497
2498 const VMStateDescription vmstate_ide_drive = {
2499 .name = "ide_drive",
2500 .version_id = 3,
2501 .minimum_version_id = 0,
2502 .post_load = ide_drive_post_load,
2503 .fields = (VMStateField[]) {
2504 VMSTATE_INT32(mult_sectors, IDEState),
2505 VMSTATE_INT32(identify_set, IDEState),
2506 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2507 VMSTATE_UINT8(feature, IDEState),
2508 VMSTATE_UINT8(error, IDEState),
2509 VMSTATE_UINT32(nsector, IDEState),
2510 VMSTATE_UINT8(sector, IDEState),
2511 VMSTATE_UINT8(lcyl, IDEState),
2512 VMSTATE_UINT8(hcyl, IDEState),
2513 VMSTATE_UINT8(hob_feature, IDEState),
2514 VMSTATE_UINT8(hob_sector, IDEState),
2515 VMSTATE_UINT8(hob_nsector, IDEState),
2516 VMSTATE_UINT8(hob_lcyl, IDEState),
2517 VMSTATE_UINT8(hob_hcyl, IDEState),
2518 VMSTATE_UINT8(select, IDEState),
2519 VMSTATE_UINT8(status, IDEState),
2520 VMSTATE_UINT8(lba48, IDEState),
2521 VMSTATE_UINT8(sense_key, IDEState),
2522 VMSTATE_UINT8(asc, IDEState),
2523 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2524 VMSTATE_END_OF_LIST()
2525 },
2526 .subsections = (VMStateSubsection []) {
2527 {
2528 .vmsd = &vmstate_ide_drive_pio_state,
2529 .needed = ide_drive_pio_state_needed,
2530 }, {
2531 .vmsd = &vmstate_ide_tray_state,
2532 .needed = ide_tray_state_needed,
2533 }, {
2534 .vmsd = &vmstate_ide_atapi_gesn_state,
2535 .needed = ide_atapi_gesn_needed,
2536 }, {
2537 /* empty */
2538 }
2539 }
2540 };
2541
2542 static const VMStateDescription vmstate_ide_error_status = {
2543 .name ="ide_bus/error",
2544 .version_id = 1,
2545 .minimum_version_id = 1,
2546 .fields = (VMStateField[]) {
2547 VMSTATE_INT32(error_status, IDEBus),
2548 VMSTATE_END_OF_LIST()
2549 }
2550 };
2551
2552 const VMStateDescription vmstate_ide_bus = {
2553 .name = "ide_bus",
2554 .version_id = 1,
2555 .minimum_version_id = 1,
2556 .fields = (VMStateField[]) {
2557 VMSTATE_UINT8(cmd, IDEBus),
2558 VMSTATE_UINT8(unit, IDEBus),
2559 VMSTATE_END_OF_LIST()
2560 },
2561 .subsections = (VMStateSubsection []) {
2562 {
2563 .vmsd = &vmstate_ide_error_status,
2564 .needed = ide_error_needed,
2565 }, {
2566 /* empty */
2567 }
2568 }
2569 };
2570
2571 void ide_drive_get(DriveInfo **hd, int n)
2572 {
2573 int i;
2574 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2575 int max_devs = drive_get_max_devs(IF_IDE);
2576 int n_buses = max_devs ? (n / max_devs) : n;
2577
2578 /*
2579 * Note: The number of actual buses available is not known.
2580 * We compute this based on the size of the DriveInfo* array, n.
2581 * If it is less than max_devs * <num_real_buses>,
2582 * We will stop looking for drives prematurely instead of overfilling
2583 * the array.
2584 */
2585
2586 if (highest_bus > n_buses) {
2587 error_report("Too many IDE buses defined (%d > %d)",
2588 highest_bus, n_buses);
2589 exit(1);
2590 }
2591
2592 for (i = 0; i < n; i++) {
2593 hd[i] = drive_get_by_index(IF_IDE, i);
2594 }
2595 }
QEMU modified to work with kvm