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Merge commit '92aa5c6d77ac29574c1717bcf57827fa1e586f31' into upstream-merge
[qemu-kvm.git] / target-i386 / cpu.c
blobfd4fe2898b69fc59e63b3befae23b27da48ed5c8
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
43 */
44 static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
53 };
54 static const char *ext_feature_name[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL, NULL, "hypervisor",
63 };
64 static const char *ext2_feature_name[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL, NULL /* Linux mp */,
70 "nx|xd", NULL, "mmxext", "mmx",
71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
72 NULL, "lm|i64", "3dnowext", "3dnow",
73 };
74 static const char *ext3_feature_name[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
77 "3dnowprefetch", "osvw", "ibs", "xop",
78 "skinit", "wdt", NULL, NULL,
79 "fma4", NULL, "cvt16", "nodeid_msr",
80 NULL, NULL, NULL, NULL,
81 NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL,
83 };
84
85 static const char *kvm_feature_name[] = {
86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
89 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
90 };
91
92 static const char *svm_feature_name[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL, NULL, "pause_filter", NULL,
96 "pfthreshold", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 NULL, NULL, NULL, NULL,
99 NULL, NULL, NULL, NULL,
100 NULL, NULL, NULL, NULL,
101 };
102
103 /* collects per-function cpuid data
104 */
105 typedef struct model_features_t {
106 uint32_t *guest_feat;
107 uint32_t *host_feat;
108 uint32_t check_feat;
109 const char **flag_names;
110 uint32_t cpuid;
111 } model_features_t;
112
113 int check_cpuid = 0;
114 int enforce_cpuid = 0;
115
116 void host_cpuid(uint32_t function, uint32_t count,
117 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
118 {
119 #if defined(CONFIG_KVM)
120 uint32_t vec[4];
121
122 #ifdef __x86_64__
123 asm volatile("cpuid"
124 : "=a"(vec[0]), "=b"(vec[1]),
125 "=c"(vec[2]), "=d"(vec[3])
126 : "0"(function), "c"(count) : "cc");
127 #else
128 asm volatile("pusha \n\t"
129 "cpuid \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
134 "popa"
135 : : "a"(function), "c"(count), "S"(vec)
136 : "memory", "cc");
137 #endif
138
139 if (eax)
140 *eax = vec[0];
141 if (ebx)
142 *ebx = vec[1];
143 if (ecx)
144 *ecx = vec[2];
145 if (edx)
146 *edx = vec[3];
147 #endif
148 }
149
150 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
151
152 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
156 */
157 static int sstrcmp(const char *s1, const char *e1, const char *s2,
158 const char *e2)
159 {
160 for (;;) {
161 if (!*s1 || !*s2 || *s1 != *s2)
162 return (*s1 - *s2);
163 ++s1, ++s2;
164 if (s1 == e1 && s2 == e2)
165 return (0);
166 else if (s1 == e1)
167 return (*s2);
168 else if (s2 == e2)
169 return (*s1);
170 }
171 }
172
173 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
177 */
178 static int altcmp(const char *s, const char *e, const char *altstr)
179 {
180 const char *p, *q;
181
182 for (q = p = altstr; ; ) {
183 while (*p && *p != '|')
184 ++p;
185 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
186 return (0);
187 if (!*p)
188 return (1);
189 else
190 q = ++p;
191 }
192 }
193
194 /* search featureset for flag *[s..e), if found set corresponding bit in
195 * *pval and return true, otherwise return false
196 */
197 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
198 const char **featureset)
199 {
200 uint32_t mask;
201 const char **ppc;
202 bool found = false;
203
204 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
205 if (*ppc && !altcmp(s, e, *ppc)) {
206 *pval |= mask;
207 found = true;
208 }
209 }
210 return found;
211 }
212
213 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
214 uint32_t *ext_features,
215 uint32_t *ext2_features,
216 uint32_t *ext3_features,
217 uint32_t *kvm_features,
218 uint32_t *svm_features)
219 {
220 if (!lookup_feature(features, flagname, NULL, feature_name) &&
221 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
222 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
223 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
224 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
225 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
226 fprintf(stderr, "CPU feature %s not found\n", flagname);
227 }
228
229 typedef struct x86_def_t {
230 struct x86_def_t *next;
231 const char *name;
232 uint32_t level;
233 uint32_t vendor1, vendor2, vendor3;
234 int family;
235 int model;
236 int stepping;
237 int tsc_khz;
238 uint32_t features, ext_features, ext2_features, ext3_features;
239 uint32_t kvm_features, svm_features;
240 uint32_t xlevel;
241 char model_id[48];
242 int vendor_override;
243 /* Store the results of Centaur's CPUID instructions */
244 uint32_t ext4_features;
245 uint32_t xlevel2;
246 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
247 uint32_t cpuid_7_0_ebx_features;
248 } x86_def_t;
249
250 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
251 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
252 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
253 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
254 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
255 CPUID_PSE36 | CPUID_FXSR)
256 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
257 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
258 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
259 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
260 CPUID_PAE | CPUID_SEP | CPUID_APIC)
261 #define EXT2_FEATURE_MASK 0x0183F3FF
262
263 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
264 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
265 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
266 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
267 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
268 /* partly implemented:
269 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
270 CPUID_PSE36 (needed for Solaris) */
271 /* missing:
272 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
273 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
274 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
275 CPUID_EXT_HYPERVISOR)
276 /* missing:
277 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
278 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
279 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
280 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
281 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
282 /* missing:
283 CPUID_EXT2_PDPE1GB */
284 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
285 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
286 #define TCG_SVM_FEATURES 0
287
288 /* maintains list of cpu model definitions
289 */
290 static x86_def_t *x86_defs = {NULL};
291
292 /* built-in cpu model definitions (deprecated)
293 */
294 static x86_def_t builtin_x86_defs[] = {
295 {
296 .name = "qemu64",
297 .level = 4,
298 .vendor1 = CPUID_VENDOR_AMD_1,
299 .vendor2 = CPUID_VENDOR_AMD_2,
300 .vendor3 = CPUID_VENDOR_AMD_3,
301 .family = 6,
302 .model = 2,
303 .stepping = 3,
304 .features = PPRO_FEATURES |
305 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
306 CPUID_PSE36,
307 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
308 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
309 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
310 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
311 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
312 .xlevel = 0x8000000A,
313 },
314 {
315 .name = "phenom",
316 .level = 5,
317 .vendor1 = CPUID_VENDOR_AMD_1,
318 .vendor2 = CPUID_VENDOR_AMD_2,
319 .vendor3 = CPUID_VENDOR_AMD_3,
320 .family = 16,
321 .model = 2,
322 .stepping = 3,
323 .features = PPRO_FEATURES |
324 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
325 CPUID_PSE36 | CPUID_VME | CPUID_HT,
326 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
327 CPUID_EXT_POPCNT,
328 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
329 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
330 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
331 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
332 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
333 CPUID_EXT3_CR8LEG,
334 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
335 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
336 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
337 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
338 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
339 .xlevel = 0x8000001A,
340 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
341 },
342 {
343 .name = "core2duo",
344 .level = 10,
345 .family = 6,
346 .model = 15,
347 .stepping = 11,
348 .features = PPRO_FEATURES |
349 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
350 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
351 CPUID_HT | CPUID_TM | CPUID_PBE,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
353 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
354 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
355 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
356 .ext3_features = CPUID_EXT3_LAHF_LM,
357 .xlevel = 0x80000008,
358 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
359 },
360 {
361 .name = "kvm64",
362 .level = 5,
363 .vendor1 = CPUID_VENDOR_INTEL_1,
364 .vendor2 = CPUID_VENDOR_INTEL_2,
365 .vendor3 = CPUID_VENDOR_INTEL_3,
366 .family = 15,
367 .model = 6,
368 .stepping = 1,
369 /* Missing: CPUID_VME, CPUID_HT */
370 .features = PPRO_FEATURES |
371 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
372 CPUID_PSE36,
373 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
374 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
375 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
376 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
377 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
378 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
379 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
380 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
381 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
382 .ext3_features = 0,
383 .xlevel = 0x80000008,
384 .model_id = "Common KVM processor"
385 },
386 {
387 .name = "qemu32",
388 .level = 4,
389 .family = 6,
390 .model = 3,
391 .stepping = 3,
392 .features = PPRO_FEATURES,
393 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
394 .xlevel = 0x80000004,
395 },
396 {
397 .name = "kvm32",
398 .level = 5,
399 .family = 15,
400 .model = 6,
401 .stepping = 1,
402 .features = PPRO_FEATURES |
403 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
404 .ext_features = CPUID_EXT_SSE3,
405 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
406 .ext3_features = 0,
407 .xlevel = 0x80000008,
408 .model_id = "Common 32-bit KVM processor"
409 },
410 {
411 .name = "coreduo",
412 .level = 10,
413 .family = 6,
414 .model = 14,
415 .stepping = 8,
416 .features = PPRO_FEATURES | CPUID_VME |
417 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
418 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
420 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
421 .ext2_features = CPUID_EXT2_NX,
422 .xlevel = 0x80000008,
423 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
424 },
425 {
426 .name = "486",
427 .level = 1,
428 .family = 4,
429 .model = 0,
430 .stepping = 0,
431 .features = I486_FEATURES,
432 .xlevel = 0,
433 },
434 {
435 .name = "pentium",
436 .level = 1,
437 .family = 5,
438 .model = 4,
439 .stepping = 3,
440 .features = PENTIUM_FEATURES,
441 .xlevel = 0,
442 },
443 {
444 .name = "pentium2",
445 .level = 2,
446 .family = 6,
447 .model = 5,
448 .stepping = 2,
449 .features = PENTIUM2_FEATURES,
450 .xlevel = 0,
451 },
452 {
453 .name = "pentium3",
454 .level = 2,
455 .family = 6,
456 .model = 7,
457 .stepping = 3,
458 .features = PENTIUM3_FEATURES,
459 .xlevel = 0,
460 },
461 {
462 .name = "athlon",
463 .level = 2,
464 .vendor1 = CPUID_VENDOR_AMD_1,
465 .vendor2 = CPUID_VENDOR_AMD_2,
466 .vendor3 = CPUID_VENDOR_AMD_3,
467 .family = 6,
468 .model = 2,
469 .stepping = 3,
470 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
471 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
472 .xlevel = 0x80000008,
473 },
474 {
475 .name = "n270",
476 /* original is on level 10 */
477 .level = 5,
478 .family = 6,
479 .model = 28,
480 .stepping = 2,
481 .features = PPRO_FEATURES |
482 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
483 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
484 /* Some CPUs got no CPUID_SEP */
485 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
486 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
487 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
488 .ext3_features = CPUID_EXT3_LAHF_LM,
489 .xlevel = 0x8000000A,
490 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
491 },
492 {
493 .name = "Conroe",
494 .level = 2,
495 .vendor1 = CPUID_VENDOR_INTEL_1,
496 .vendor2 = CPUID_VENDOR_INTEL_2,
497 .vendor3 = CPUID_VENDOR_INTEL_3,
498 .family = 6,
499 .model = 2,
500 .stepping = 3,
501 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
502 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
503 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
504 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
505 CPUID_DE | CPUID_FP87,
506 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
507 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
508 .ext3_features = CPUID_EXT3_LAHF_LM,
509 .xlevel = 0x8000000A,
510 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
511 },
512 {
513 .name = "Penryn",
514 .level = 2,
515 .vendor1 = CPUID_VENDOR_INTEL_1,
516 .vendor2 = CPUID_VENDOR_INTEL_2,
517 .vendor3 = CPUID_VENDOR_INTEL_3,
518 .family = 6,
519 .model = 2,
520 .stepping = 3,
521 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
522 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
523 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
524 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
525 CPUID_DE | CPUID_FP87,
526 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
527 CPUID_EXT_SSE3,
528 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
529 .ext3_features = CPUID_EXT3_LAHF_LM,
530 .xlevel = 0x8000000A,
531 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
532 },
533 {
534 .name = "Nehalem",
535 .level = 2,
536 .vendor1 = CPUID_VENDOR_INTEL_1,
537 .vendor2 = CPUID_VENDOR_INTEL_2,
538 .vendor3 = CPUID_VENDOR_INTEL_3,
539 .family = 6,
540 .model = 2,
541 .stepping = 3,
542 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
546 CPUID_DE | CPUID_FP87,
547 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
548 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
549 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
550 .ext3_features = CPUID_EXT3_LAHF_LM,
551 .xlevel = 0x8000000A,
552 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
553 },
554 {
555 .name = "Westmere",
556 .level = 11,
557 .vendor1 = CPUID_VENDOR_INTEL_1,
558 .vendor2 = CPUID_VENDOR_INTEL_2,
559 .vendor3 = CPUID_VENDOR_INTEL_3,
560 .family = 6,
561 .model = 44,
562 .stepping = 1,
563 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
564 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
565 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
566 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
567 CPUID_DE | CPUID_FP87,
568 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
569 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
570 CPUID_EXT_SSE3,
571 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
572 .ext3_features = CPUID_EXT3_LAHF_LM,
573 .xlevel = 0x8000000A,
574 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
575 },
576 {
577 .name = "SandyBridge",
578 .level = 0xd,
579 .vendor1 = CPUID_VENDOR_INTEL_1,
580 .vendor2 = CPUID_VENDOR_INTEL_2,
581 .vendor3 = CPUID_VENDOR_INTEL_3,
582 .family = 6,
583 .model = 42,
584 .stepping = 1,
585 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
586 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
587 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
588 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
589 CPUID_DE | CPUID_FP87,
590 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
591 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
592 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
594 CPUID_EXT_SSE3,
595 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
596 CPUID_EXT2_SYSCALL,
597 .ext3_features = CPUID_EXT3_LAHF_LM,
598 .xlevel = 0x8000000A,
599 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
600 },
601 {
602 .name = "Opteron_G1",
603 .level = 5,
604 .vendor1 = CPUID_VENDOR_AMD_1,
605 .vendor2 = CPUID_VENDOR_AMD_2,
606 .vendor3 = CPUID_VENDOR_AMD_3,
607 .family = 15,
608 .model = 6,
609 .stepping = 1,
610 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
611 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
612 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
613 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
614 CPUID_DE | CPUID_FP87,
615 .ext_features = CPUID_EXT_SSE3,
616 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
617 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
618 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
619 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
620 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
621 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
622 .xlevel = 0x80000008,
623 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
624 },
625 {
626 .name = "Opteron_G2",
627 .level = 5,
628 .vendor1 = CPUID_VENDOR_AMD_1,
629 .vendor2 = CPUID_VENDOR_AMD_2,
630 .vendor3 = CPUID_VENDOR_AMD_3,
631 .family = 15,
632 .model = 6,
633 .stepping = 1,
634 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
635 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
636 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
637 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
638 CPUID_DE | CPUID_FP87,
639 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
640 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
641 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
642 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
643 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
644 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
645 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
646 CPUID_EXT2_DE | CPUID_EXT2_FPU,
647 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
648 .xlevel = 0x80000008,
649 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
650 },
651 {
652 .name = "Opteron_G3",
653 .level = 5,
654 .vendor1 = CPUID_VENDOR_AMD_1,
655 .vendor2 = CPUID_VENDOR_AMD_2,
656 .vendor3 = CPUID_VENDOR_AMD_3,
657 .family = 15,
658 .model = 6,
659 .stepping = 1,
660 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
661 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
662 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
663 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
664 CPUID_DE | CPUID_FP87,
665 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
666 CPUID_EXT_SSE3,
667 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
668 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
669 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
670 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
671 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
672 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
673 CPUID_EXT2_DE | CPUID_EXT2_FPU,
674 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
675 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
676 .xlevel = 0x80000008,
677 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
678 },
679 {
680 .name = "Opteron_G4",
681 .level = 0xd,
682 .vendor1 = CPUID_VENDOR_AMD_1,
683 .vendor2 = CPUID_VENDOR_AMD_2,
684 .vendor3 = CPUID_VENDOR_AMD_3,
685 .family = 21,
686 .model = 1,
687 .stepping = 2,
688 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
689 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
690 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
691 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
692 CPUID_DE | CPUID_FP87,
693 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
694 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
695 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
696 CPUID_EXT_SSE3,
697 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
698 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
699 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
700 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
701 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
702 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
703 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
704 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
705 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
706 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
707 CPUID_EXT3_LAHF_LM,
708 .xlevel = 0x8000001A,
709 .model_id = "AMD Opteron 62xx class CPU",
710 },
711 };
712
713 static int cpu_x86_fill_model_id(char *str)
714 {
715 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
716 int i;
717
718 for (i = 0; i < 3; i++) {
719 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
720 memcpy(str + i * 16 + 0, &eax, 4);
721 memcpy(str + i * 16 + 4, &ebx, 4);
722 memcpy(str + i * 16 + 8, &ecx, 4);
723 memcpy(str + i * 16 + 12, &edx, 4);
724 }
725 return 0;
726 }
727
728 static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
729 {
730 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
731
732 x86_cpu_def->name = "host";
733 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
734 x86_cpu_def->level = eax;
735 x86_cpu_def->vendor1 = ebx;
736 x86_cpu_def->vendor2 = edx;
737 x86_cpu_def->vendor3 = ecx;
738
739 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
740 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
741 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
742 x86_cpu_def->stepping = eax & 0x0F;
743 x86_cpu_def->ext_features = ecx;
744 x86_cpu_def->features = edx;
745
746 if (kvm_enabled() && x86_cpu_def->level >= 7) {
747 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
748 } else {
749 x86_cpu_def->cpuid_7_0_ebx_features = 0;
750 }
751
752 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
753 x86_cpu_def->xlevel = eax;
754
755 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
756 x86_cpu_def->ext2_features = edx;
757 x86_cpu_def->ext3_features = ecx;
758 cpu_x86_fill_model_id(x86_cpu_def->model_id);
759 x86_cpu_def->vendor_override = 0;
760
761 /* Call Centaur's CPUID instruction. */
762 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
763 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
764 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
765 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
766 if (eax >= 0xC0000001) {
767 /* Support VIA max extended level */
768 x86_cpu_def->xlevel2 = eax;
769 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
770 x86_cpu_def->ext4_features = edx;
771 }
772 }
773
774 /*
775 * Every SVM feature requires emulation support in KVM - so we can't just
776 * read the host features here. KVM might even support SVM features not
777 * available on the host hardware. Just set all bits and mask out the
778 * unsupported ones later.
779 */
780 x86_cpu_def->svm_features = -1;
781
782 return 0;
783 }
784
785 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
786 {
787 int i;
788
789 for (i = 0; i < 32; ++i)
790 if (1 << i & mask) {
791 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
792 " flag '%s' [0x%08x]\n",
793 f->cpuid >> 16, f->cpuid & 0xffff,
794 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
795 break;
796 }
797 return 0;
798 }
799
800 /* best effort attempt to inform user requested cpu flags aren't making
801 * their way to the guest. Note: ft[].check_feat ideally should be
802 * specified via a guest_def field to suppress report of extraneous flags.
803 */
804 static int check_features_against_host(x86_def_t *guest_def)
805 {
806 x86_def_t host_def;
807 uint32_t mask;
808 int rv, i;
809 struct model_features_t ft[] = {
810 {&guest_def->features, &host_def.features,
811 ~0, feature_name, 0x00000000},
812 {&guest_def->ext_features, &host_def.ext_features,
813 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
814 {&guest_def->ext2_features, &host_def.ext2_features,
815 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
816 {&guest_def->ext3_features, &host_def.ext3_features,
817 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
818
819 cpu_x86_fill_host(&host_def);
820 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
821 for (mask = 1; mask; mask <<= 1)
822 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
823 !(*ft[i].host_feat & mask)) {
824 unavailable_host_feature(&ft[i], mask);
825 rv = 1;
826 }
827 return rv;
828 }
829
830 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
831 const char *name, Error **errp)
832 {
833 X86CPU *cpu = X86_CPU(obj);
834 CPUX86State *env = &cpu->env;
835 int64_t value;
836
837 value = (env->cpuid_version >> 8) & 0xf;
838 if (value == 0xf) {
839 value += (env->cpuid_version >> 20) & 0xff;
840 }
841 visit_type_int(v, &value, name, errp);
842 }
843
844 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
845 const char *name, Error **errp)
846 {
847 X86CPU *cpu = X86_CPU(obj);
848 CPUX86State *env = &cpu->env;
849 const int64_t min = 0;
850 const int64_t max = 0xff + 0xf;
851 int64_t value;
852
853 visit_type_int(v, &value, name, errp);
854 if (error_is_set(errp)) {
855 return;
856 }
857 if (value < min || value > max) {
858 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
859 name ? name : "null", value, min, max);
860 return;
861 }
862
863 env->cpuid_version &= ~0xff00f00;
864 if (value > 0x0f) {
865 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
866 } else {
867 env->cpuid_version |= value << 8;
868 }
869 }
870
871 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
872 const char *name, Error **errp)
873 {
874 X86CPU *cpu = X86_CPU(obj);
875 CPUX86State *env = &cpu->env;
876 int64_t value;
877
878 value = (env->cpuid_version >> 4) & 0xf;
879 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
880 visit_type_int(v, &value, name, errp);
881 }
882
883 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
884 const char *name, Error **errp)
885 {
886 X86CPU *cpu = X86_CPU(obj);
887 CPUX86State *env = &cpu->env;
888 const int64_t min = 0;
889 const int64_t max = 0xff;
890 int64_t value;
891
892 visit_type_int(v, &value, name, errp);
893 if (error_is_set(errp)) {
894 return;
895 }
896 if (value < min || value > max) {
897 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
898 name ? name : "null", value, min, max);
899 return;
900 }
901
902 env->cpuid_version &= ~0xf00f0;
903 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
904 }
905
906 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
907 void *opaque, const char *name,
908 Error **errp)
909 {
910 X86CPU *cpu = X86_CPU(obj);
911 CPUX86State *env = &cpu->env;
912 int64_t value;
913
914 value = env->cpuid_version & 0xf;
915 visit_type_int(v, &value, name, errp);
916 }
917
918 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
919 void *opaque, const char *name,
920 Error **errp)
921 {
922 X86CPU *cpu = X86_CPU(obj);
923 CPUX86State *env = &cpu->env;
924 const int64_t min = 0;
925 const int64_t max = 0xf;
926 int64_t value;
927
928 visit_type_int(v, &value, name, errp);
929 if (error_is_set(errp)) {
930 return;
931 }
932 if (value < min || value > max) {
933 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
934 name ? name : "null", value, min, max);
935 return;
936 }
937
938 env->cpuid_version &= ~0xf;
939 env->cpuid_version |= value & 0xf;
940 }
941
942 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
943 const char *name, Error **errp)
944 {
945 X86CPU *cpu = X86_CPU(obj);
946
947 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
948 }
949
950 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
951 const char *name, Error **errp)
952 {
953 X86CPU *cpu = X86_CPU(obj);
954
955 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
956 }
957
958 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
959 const char *name, Error **errp)
960 {
961 X86CPU *cpu = X86_CPU(obj);
962
963 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
964 }
965
966 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
967 const char *name, Error **errp)
968 {
969 X86CPU *cpu = X86_CPU(obj);
970
971 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
972 }
973
974 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
975 {
976 X86CPU *cpu = X86_CPU(obj);
977 CPUX86State *env = &cpu->env;
978 char *value;
979 int i;
980
981 value = (char *)g_malloc(12 + 1);
982 for (i = 0; i < 4; i++) {
983 value[i ] = env->cpuid_vendor1 >> (8 * i);
984 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
985 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
986 }
987 value[12] = '\0';
988 return value;
989 }
990
991 static void x86_cpuid_set_vendor(Object *obj, const char *value,
992 Error **errp)
993 {
994 X86CPU *cpu = X86_CPU(obj);
995 CPUX86State *env = &cpu->env;
996 int i;
997
998 if (strlen(value) != 12) {
999 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1000 "vendor", value);
1001 return;
1002 }
1003
1004 env->cpuid_vendor1 = 0;
1005 env->cpuid_vendor2 = 0;
1006 env->cpuid_vendor3 = 0;
1007 for (i = 0; i < 4; i++) {
1008 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1009 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1010 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1011 }
1012 env->cpuid_vendor_override = 1;
1013 }
1014
1015 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1016 {
1017 X86CPU *cpu = X86_CPU(obj);
1018 CPUX86State *env = &cpu->env;
1019 char *value;
1020 int i;
1021
1022 value = g_malloc(48 + 1);
1023 for (i = 0; i < 48; i++) {
1024 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1025 }
1026 value[48] = '\0';
1027 return value;
1028 }
1029
1030 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1031 Error **errp)
1032 {
1033 X86CPU *cpu = X86_CPU(obj);
1034 CPUX86State *env = &cpu->env;
1035 int c, len, i;
1036
1037 if (model_id == NULL) {
1038 model_id = "";
1039 }
1040 len = strlen(model_id);
1041 memset(env->cpuid_model, 0, 48);
1042 for (i = 0; i < 48; i++) {
1043 if (i >= len) {
1044 c = '\0';
1045 } else {
1046 c = (uint8_t)model_id[i];
1047 }
1048 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1049 }
1050 }
1051
1052 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1053 const char *name, Error **errp)
1054 {
1055 X86CPU *cpu = X86_CPU(obj);
1056 int64_t value;
1057
1058 value = cpu->env.tsc_khz * 1000;
1059 visit_type_int(v, &value, name, errp);
1060 }
1061
1062 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1063 const char *name, Error **errp)
1064 {
1065 X86CPU *cpu = X86_CPU(obj);
1066 const int64_t min = 0;
1067 const int64_t max = INT64_MAX;
1068 int64_t value;
1069
1070 visit_type_int(v, &value, name, errp);
1071 if (error_is_set(errp)) {
1072 return;
1073 }
1074 if (value < min || value > max) {
1075 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1076 name ? name : "null", value, min, max);
1077 return;
1078 }
1079
1080 cpu->env.tsc_khz = value / 1000;
1081 }
1082
1083 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1084 {
1085 unsigned int i;
1086 x86_def_t *def;
1087
1088 char *s = g_strdup(cpu_model);
1089 char *featurestr, *name = strtok(s, ",");
1090 /* Features to be added*/
1091 uint32_t plus_features = 0, plus_ext_features = 0;
1092 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1093 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
1094 /* Features to be removed */
1095 uint32_t minus_features = 0, minus_ext_features = 0;
1096 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1097 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1098 uint32_t numvalue;
1099
1100 for (def = x86_defs; def; def = def->next)
1101 if (name && !strcmp(name, def->name))
1102 break;
1103 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1104 cpu_x86_fill_host(x86_cpu_def);
1105 } else if (!def) {
1106 goto error;
1107 } else {
1108 memcpy(x86_cpu_def, def, sizeof(*def));
1109 }
1110
1111 #if defined(CONFIG_KVM)
1112 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
1113 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1114 (1 << KVM_FEATURE_MMU_OP) |
1115 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1116 (1 << KVM_FEATURE_ASYNC_PF) |
1117 (1 << KVM_FEATURE_STEAL_TIME) |
1118 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
1119 #else
1120 plus_kvm_features = 0;
1121 #endif
1122
1123 add_flagname_to_bitmaps("hypervisor", &plus_features,
1124 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1125 &plus_kvm_features, &plus_svm_features);
1126
1127 featurestr = strtok(NULL, ",");
1128
1129 while (featurestr) {
1130 char *val;
1131 if (featurestr[0] == '+') {
1132 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1133 &plus_ext_features, &plus_ext2_features,
1134 &plus_ext3_features, &plus_kvm_features,
1135 &plus_svm_features);
1136 } else if (featurestr[0] == '-') {
1137 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1138 &minus_ext_features, &minus_ext2_features,
1139 &minus_ext3_features, &minus_kvm_features,
1140 &minus_svm_features);
1141 } else if ((val = strchr(featurestr, '='))) {
1142 *val = 0; val++;
1143 if (!strcmp(featurestr, "family")) {
1144 char *err;
1145 numvalue = strtoul(val, &err, 0);
1146 if (!*val || *err || numvalue > 0xff + 0xf) {
1147 fprintf(stderr, "bad numerical value %s\n", val);
1148 goto error;
1149 }
1150 x86_cpu_def->family = numvalue;
1151 } else if (!strcmp(featurestr, "model")) {
1152 char *err;
1153 numvalue = strtoul(val, &err, 0);
1154 if (!*val || *err || numvalue > 0xff) {
1155 fprintf(stderr, "bad numerical value %s\n", val);
1156 goto error;
1157 }
1158 x86_cpu_def->model = numvalue;
1159 } else if (!strcmp(featurestr, "stepping")) {
1160 char *err;
1161 numvalue = strtoul(val, &err, 0);
1162 if (!*val || *err || numvalue > 0xf) {
1163 fprintf(stderr, "bad numerical value %s\n", val);
1164 goto error;
1165 }
1166 x86_cpu_def->stepping = numvalue ;
1167 } else if (!strcmp(featurestr, "level")) {
1168 char *err;
1169 numvalue = strtoul(val, &err, 0);
1170 if (!*val || *err) {
1171 fprintf(stderr, "bad numerical value %s\n", val);
1172 goto error;
1173 }
1174 x86_cpu_def->level = numvalue;
1175 } else if (!strcmp(featurestr, "xlevel")) {
1176 char *err;
1177 numvalue = strtoul(val, &err, 0);
1178 if (!*val || *err) {
1179 fprintf(stderr, "bad numerical value %s\n", val);
1180 goto error;
1181 }
1182 if (numvalue < 0x80000000) {
1183 numvalue += 0x80000000;
1184 }
1185 x86_cpu_def->xlevel = numvalue;
1186 } else if (!strcmp(featurestr, "vendor")) {
1187 if (strlen(val) != 12) {
1188 fprintf(stderr, "vendor string must be 12 chars long\n");
1189 goto error;
1190 }
1191 x86_cpu_def->vendor1 = 0;
1192 x86_cpu_def->vendor2 = 0;
1193 x86_cpu_def->vendor3 = 0;
1194 for(i = 0; i < 4; i++) {
1195 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1196 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1197 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1198 }
1199 x86_cpu_def->vendor_override = 1;
1200 } else if (!strcmp(featurestr, "model_id")) {
1201 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1202 val);
1203 } else if (!strcmp(featurestr, "tsc_freq")) {
1204 int64_t tsc_freq;
1205 char *err;
1206
1207 tsc_freq = strtosz_suffix_unit(val, &err,
1208 STRTOSZ_DEFSUFFIX_B, 1000);
1209 if (tsc_freq < 0 || *err) {
1210 fprintf(stderr, "bad numerical value %s\n", val);
1211 goto error;
1212 }
1213 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1214 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1215 char *err;
1216 numvalue = strtoul(val, &err, 0);
1217 if (!*val || *err) {
1218 fprintf(stderr, "bad numerical value %s\n", val);
1219 goto error;
1220 }
1221 hyperv_set_spinlock_retries(numvalue);
1222 } else {
1223 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1224 goto error;
1225 }
1226 } else if (!strcmp(featurestr, "check")) {
1227 check_cpuid = 1;
1228 } else if (!strcmp(featurestr, "enforce")) {
1229 check_cpuid = enforce_cpuid = 1;
1230 } else if (!strcmp(featurestr, "hv_relaxed")) {
1231 hyperv_enable_relaxed_timing(true);
1232 } else if (!strcmp(featurestr, "hv_vapic")) {
1233 hyperv_enable_vapic_recommended(true);
1234 } else {
1235 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1236 goto error;
1237 }
1238 featurestr = strtok(NULL, ",");
1239 }
1240 x86_cpu_def->features |= plus_features;
1241 x86_cpu_def->ext_features |= plus_ext_features;
1242 x86_cpu_def->ext2_features |= plus_ext2_features;
1243 x86_cpu_def->ext3_features |= plus_ext3_features;
1244 x86_cpu_def->kvm_features |= plus_kvm_features;
1245 x86_cpu_def->svm_features |= plus_svm_features;
1246 x86_cpu_def->features &= ~minus_features;
1247 x86_cpu_def->ext_features &= ~minus_ext_features;
1248 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1249 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1250 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1251 x86_cpu_def->svm_features &= ~minus_svm_features;
1252 if (check_cpuid) {
1253 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1254 goto error;
1255 }
1256 g_free(s);
1257 return 0;
1258
1259 error:
1260 g_free(s);
1261 return -1;
1262 }
1263
1264 /* generate a composite string into buf of all cpuid names in featureset
1265 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1266 * if flags, suppress names undefined in featureset.
1267 */
1268 static void listflags(char *buf, int bufsize, uint32_t fbits,
1269 const char **featureset, uint32_t flags)
1270 {
1271 const char **p = &featureset[31];
1272 char *q, *b, bit;
1273 int nc;
1274
1275 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1276 *buf = '\0';
1277 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1278 if (fbits & 1 << bit && (*p || !flags)) {
1279 if (*p)
1280 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1281 else
1282 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1283 if (bufsize <= nc) {
1284 if (b) {
1285 memcpy(b, "...", sizeof("..."));
1286 }
1287 return;
1288 }
1289 q += nc;
1290 bufsize -= nc;
1291 }
1292 }
1293
1294 /* generate CPU information. */
1295 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1296 {
1297 x86_def_t *def;
1298 char buf[256];
1299
1300 for (def = x86_defs; def; def = def->next) {
1301 snprintf(buf, sizeof(buf), "%s", def->name);
1302 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1303 }
1304 if (kvm_enabled()) {
1305 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1306 }
1307 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1308 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1309 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1310 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1311 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1312 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1313 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1314 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1315 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1316 }
1317
1318 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1319 {
1320 CpuDefinitionInfoList *cpu_list = NULL;
1321 x86_def_t *def;
1322
1323 for (def = x86_defs; def; def = def->next) {
1324 CpuDefinitionInfoList *entry;
1325 CpuDefinitionInfo *info;
1326
1327 info = g_malloc0(sizeof(*info));
1328 info->name = g_strdup(def->name);
1329
1330 entry = g_malloc0(sizeof(*entry));
1331 entry->value = info;
1332 entry->next = cpu_list;
1333 cpu_list = entry;
1334 }
1335
1336 return cpu_list;
1337 }
1338
1339 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1340 {
1341 CPUX86State *env = &cpu->env;
1342 x86_def_t def1, *def = &def1;
1343 Error *error = NULL;
1344
1345 memset(def, 0, sizeof(*def));
1346
1347 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1348 return -1;
1349 if (def->vendor1) {
1350 env->cpuid_vendor1 = def->vendor1;
1351 env->cpuid_vendor2 = def->vendor2;
1352 env->cpuid_vendor3 = def->vendor3;
1353 } else {
1354 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1355 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1356 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1357 }
1358 env->cpuid_vendor_override = def->vendor_override;
1359 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1360 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1361 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1362 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1363 env->cpuid_features = def->features;
1364 env->cpuid_ext_features = def->ext_features;
1365 env->cpuid_ext2_features = def->ext2_features;
1366 env->cpuid_ext3_features = def->ext3_features;
1367 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1368 env->cpuid_kvm_features = def->kvm_features;
1369 env->cpuid_svm_features = def->svm_features;
1370 env->cpuid_ext4_features = def->ext4_features;
1371 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
1372 env->cpuid_xlevel2 = def->xlevel2;
1373 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1374 "tsc-frequency", &error);
1375 if (!kvm_enabled()) {
1376 env->cpuid_features &= TCG_FEATURES;
1377 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1378 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1379 #ifdef TARGET_X86_64
1380 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1381 #endif
1382 );
1383 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1384 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1385 }
1386 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1387 if (error_is_set(&error)) {
1388 error_free(error);
1389 return -1;
1390 }
1391 return 0;
1392 }
1393
1394 #if !defined(CONFIG_USER_ONLY)
1395
1396 void cpu_clear_apic_feature(CPUX86State *env)
1397 {
1398 env->cpuid_features &= ~CPUID_APIC;
1399 }
1400
1401 #endif /* !CONFIG_USER_ONLY */
1402
1403 /* Initialize list of CPU models, filling some non-static fields if necessary
1404 */
1405 void x86_cpudef_setup(void)
1406 {
1407 int i, j;
1408 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1409
1410 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1411 x86_def_t *def = &builtin_x86_defs[i];
1412 def->next = x86_defs;
1413
1414 /* Look for specific "cpudef" models that */
1415 /* have the QEMU version in .model_id */
1416 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1417 if (strcmp(model_with_versions[j], def->name) == 0) {
1418 pstrcpy(def->model_id, sizeof(def->model_id),
1419 "QEMU Virtual CPU version ");
1420 pstrcat(def->model_id, sizeof(def->model_id),
1421 qemu_get_version());
1422 break;
1423 }
1424 }
1425
1426 x86_defs = def;
1427 }
1428 }
1429
1430 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1431 uint32_t *ecx, uint32_t *edx)
1432 {
1433 *ebx = env->cpuid_vendor1;
1434 *edx = env->cpuid_vendor2;
1435 *ecx = env->cpuid_vendor3;
1436
1437 /* sysenter isn't supported on compatibility mode on AMD, syscall
1438 * isn't supported in compatibility mode on Intel.
1439 * Normally we advertise the actual cpu vendor, but you can override
1440 * this if you want to use KVM's sysenter/syscall emulation
1441 * in compatibility mode and when doing cross vendor migration
1442 */
1443 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1444 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1445 }
1446 }
1447
1448 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1449 uint32_t *eax, uint32_t *ebx,
1450 uint32_t *ecx, uint32_t *edx)
1451 {
1452 /* test if maximum index reached */
1453 if (index & 0x80000000) {
1454 if (index > env->cpuid_xlevel) {
1455 if (env->cpuid_xlevel2 > 0) {
1456 /* Handle the Centaur's CPUID instruction. */
1457 if (index > env->cpuid_xlevel2) {
1458 index = env->cpuid_xlevel2;
1459 } else if (index < 0xC0000000) {
1460 index = env->cpuid_xlevel;
1461 }
1462 } else {
1463 index = env->cpuid_xlevel;
1464 }
1465 }
1466 } else {
1467 if (index > env->cpuid_level)
1468 index = env->cpuid_level;
1469 }
1470
1471 switch(index) {
1472 case 0:
1473 *eax = env->cpuid_level;
1474 get_cpuid_vendor(env, ebx, ecx, edx);
1475 break;
1476 case 1:
1477 *eax = env->cpuid_version;
1478 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1479 *ecx = env->cpuid_ext_features;
1480 *edx = env->cpuid_features;
1481 if (env->nr_cores * env->nr_threads > 1) {
1482 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1483 *edx |= 1 << 28; /* HTT bit */
1484 }
1485 break;
1486 case 2:
1487 /* cache info: needed for Pentium Pro compatibility */
1488 *eax = 1;
1489 *ebx = 0;
1490 *ecx = 0;
1491 *edx = 0x2c307d;
1492 break;
1493 case 4:
1494 /* cache info: needed for Core compatibility */
1495 if (env->nr_cores > 1) {
1496 *eax = (env->nr_cores - 1) << 26;
1497 } else {
1498 *eax = 0;
1499 }
1500 switch (count) {
1501 case 0: /* L1 dcache info */
1502 *eax |= 0x0000121;
1503 *ebx = 0x1c0003f;
1504 *ecx = 0x000003f;
1505 *edx = 0x0000001;
1506 break;
1507 case 1: /* L1 icache info */
1508 *eax |= 0x0000122;
1509 *ebx = 0x1c0003f;
1510 *ecx = 0x000003f;
1511 *edx = 0x0000001;
1512 break;
1513 case 2: /* L2 cache info */
1514 *eax |= 0x0000143;
1515 if (env->nr_threads > 1) {
1516 *eax |= (env->nr_threads - 1) << 14;
1517 }
1518 *ebx = 0x3c0003f;
1519 *ecx = 0x0000fff;
1520 *edx = 0x0000001;
1521 break;
1522 default: /* end of info */
1523 *eax = 0;
1524 *ebx = 0;
1525 *ecx = 0;
1526 *edx = 0;
1527 break;
1528 }
1529 break;
1530 case 5:
1531 /* mwait info: needed for Core compatibility */
1532 *eax = 0; /* Smallest monitor-line size in bytes */
1533 *ebx = 0; /* Largest monitor-line size in bytes */
1534 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1535 *edx = 0;
1536 break;
1537 case 6:
1538 /* Thermal and Power Leaf */
1539 *eax = 0;
1540 *ebx = 0;
1541 *ecx = 0;
1542 *edx = 0;
1543 break;
1544 case 7:
1545 /* Structured Extended Feature Flags Enumeration Leaf */
1546 if (count == 0) {
1547 *eax = 0; /* Maximum ECX value for sub-leaves */
1548 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1549 *ecx = 0; /* Reserved */
1550 *edx = 0; /* Reserved */
1551 } else {
1552 *eax = 0;
1553 *ebx = 0;
1554 *ecx = 0;
1555 *edx = 0;
1556 }
1557 break;
1558 case 9:
1559 /* Direct Cache Access Information Leaf */
1560 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1561 *ebx = 0;
1562 *ecx = 0;
1563 *edx = 0;
1564 break;
1565 case 0xA:
1566 /* Architectural Performance Monitoring Leaf */
1567 if (kvm_enabled()) {
1568 KVMState *s = env->kvm_state;
1569
1570 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1571 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1572 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1573 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1574 } else {
1575 *eax = 0;
1576 *ebx = 0;
1577 *ecx = 0;
1578 *edx = 0;
1579 }
1580 break;
1581 case 0xD:
1582 /* Processor Extended State */
1583 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1584 *eax = 0;
1585 *ebx = 0;
1586 *ecx = 0;
1587 *edx = 0;
1588 break;
1589 }
1590 if (kvm_enabled()) {
1591 KVMState *s = env->kvm_state;
1592
1593 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1594 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1595 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1596 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1597 } else {
1598 *eax = 0;
1599 *ebx = 0;
1600 *ecx = 0;
1601 *edx = 0;
1602 }
1603 break;
1604 case 0x80000000:
1605 *eax = env->cpuid_xlevel;
1606 *ebx = env->cpuid_vendor1;
1607 *edx = env->cpuid_vendor2;
1608 *ecx = env->cpuid_vendor3;
1609 break;
1610 case 0x80000001:
1611 *eax = env->cpuid_version;
1612 *ebx = 0;
1613 *ecx = env->cpuid_ext3_features;
1614 *edx = env->cpuid_ext2_features;
1615
1616 /* The Linux kernel checks for the CMPLegacy bit and
1617 * discards multiple thread information if it is set.
1618 * So dont set it here for Intel to make Linux guests happy.
1619 */
1620 if (env->nr_cores * env->nr_threads > 1) {
1621 uint32_t tebx, tecx, tedx;
1622 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1623 if (tebx != CPUID_VENDOR_INTEL_1 ||
1624 tedx != CPUID_VENDOR_INTEL_2 ||
1625 tecx != CPUID_VENDOR_INTEL_3) {
1626 *ecx |= 1 << 1; /* CmpLegacy bit */
1627 }
1628 }
1629 break;
1630 case 0x80000002:
1631 case 0x80000003:
1632 case 0x80000004:
1633 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1634 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1635 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1636 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1637 break;
1638 case 0x80000005:
1639 /* cache info (L1 cache) */
1640 *eax = 0x01ff01ff;
1641 *ebx = 0x01ff01ff;
1642 *ecx = 0x40020140;
1643 *edx = 0x40020140;
1644 break;
1645 case 0x80000006:
1646 /* cache info (L2 cache) */
1647 *eax = 0;
1648 *ebx = 0x42004200;
1649 *ecx = 0x02008140;
1650 *edx = 0;
1651 break;
1652 case 0x80000008:
1653 /* virtual & phys address size in low 2 bytes. */
1654 /* XXX: This value must match the one used in the MMU code. */
1655 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1656 /* 64 bit processor */
1657 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1658 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1659 } else {
1660 if (env->cpuid_features & CPUID_PSE36)
1661 *eax = 0x00000024; /* 36 bits physical */
1662 else
1663 *eax = 0x00000020; /* 32 bits physical */
1664 }
1665 *ebx = 0;
1666 *ecx = 0;
1667 *edx = 0;
1668 if (env->nr_cores * env->nr_threads > 1) {
1669 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1670 }
1671 break;
1672 case 0x8000000A:
1673 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1674 *eax = 0x00000001; /* SVM Revision */
1675 *ebx = 0x00000010; /* nr of ASIDs */
1676 *ecx = 0;
1677 *edx = env->cpuid_svm_features; /* optional features */
1678 } else {
1679 *eax = 0;
1680 *ebx = 0;
1681 *ecx = 0;
1682 *edx = 0;
1683 }
1684 break;
1685 case 0xC0000000:
1686 *eax = env->cpuid_xlevel2;
1687 *ebx = 0;
1688 *ecx = 0;
1689 *edx = 0;
1690 break;
1691 case 0xC0000001:
1692 /* Support for VIA CPU's CPUID instruction */
1693 *eax = env->cpuid_version;
1694 *ebx = 0;
1695 *ecx = 0;
1696 *edx = env->cpuid_ext4_features;
1697 break;
1698 case 0xC0000002:
1699 case 0xC0000003:
1700 case 0xC0000004:
1701 /* Reserved for the future, and now filled with zero */
1702 *eax = 0;
1703 *ebx = 0;
1704 *ecx = 0;
1705 *edx = 0;
1706 break;
1707 default:
1708 /* reserved values: zero */
1709 *eax = 0;
1710 *ebx = 0;
1711 *ecx = 0;
1712 *edx = 0;
1713 break;
1714 }
1715 }
1716
1717 /* CPUClass::reset() */
1718 static void x86_cpu_reset(CPUState *s)
1719 {
1720 X86CPU *cpu = X86_CPU(s);
1721 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1722 CPUX86State *env = &cpu->env;
1723 int i;
1724
1725 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1726 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1727 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1728 }
1729
1730 xcc->parent_reset(s);
1731
1732
1733 memset(env, 0, offsetof(CPUX86State, breakpoints));
1734
1735 tlb_flush(env, 1);
1736
1737 env->old_exception = -1;
1738
1739 /* init to reset state */
1740
1741 #ifdef CONFIG_SOFTMMU
1742 env->hflags |= HF_SOFTMMU_MASK;
1743 #endif
1744 env->hflags2 |= HF2_GIF_MASK;
1745
1746 cpu_x86_update_cr0(env, 0x60000010);
1747 env->a20_mask = ~0x0;
1748 env->smbase = 0x30000;
1749
1750 env->idt.limit = 0xffff;
1751 env->gdt.limit = 0xffff;
1752 env->ldt.limit = 0xffff;
1753 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1754 env->tr.limit = 0xffff;
1755 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1756
1757 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1758 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1759 DESC_R_MASK | DESC_A_MASK);
1760 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1761 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1762 DESC_A_MASK);
1763 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1764 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1765 DESC_A_MASK);
1766 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1767 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1768 DESC_A_MASK);
1769 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1770 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1771 DESC_A_MASK);
1772 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1773 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1774 DESC_A_MASK);
1775
1776 env->eip = 0xfff0;
1777 env->regs[R_EDX] = env->cpuid_version;
1778
1779 env->eflags = 0x2;
1780
1781 /* FPU init */
1782 for (i = 0; i < 8; i++) {
1783 env->fptags[i] = 1;
1784 }
1785 env->fpuc = 0x37f;
1786
1787 env->mxcsr = 0x1f80;
1788
1789 env->pat = 0x0007040600070406ULL;
1790 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1791
1792 memset(env->dr, 0, sizeof(env->dr));
1793 env->dr[6] = DR6_FIXED_1;
1794 env->dr[7] = DR7_FIXED_1;
1795 cpu_breakpoint_remove_all(env, BP_CPU);
1796 cpu_watchpoint_remove_all(env, BP_CPU);
1797
1798 #if !defined(CONFIG_USER_ONLY)
1799 /* We hard-wire the BSP to the first CPU. */
1800 if (env->cpu_index == 0) {
1801 apic_designate_bsp(env->apic_state);
1802 }
1803
1804 env->halted = !cpu_is_bsp(cpu);
1805 #endif
1806 }
1807
1808 #ifndef CONFIG_USER_ONLY
1809 bool cpu_is_bsp(X86CPU *cpu)
1810 {
1811 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1812 }
1813
1814 /* TODO: remove me, when reset over QOM tree is implemented */
1815 static void x86_cpu_machine_reset_cb(void *opaque)
1816 {
1817 X86CPU *cpu = opaque;
1818 cpu_reset(CPU(cpu));
1819 }
1820 #endif
1821
1822 static void mce_init(X86CPU *cpu)
1823 {
1824 CPUX86State *cenv = &cpu->env;
1825 unsigned int bank;
1826
1827 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1828 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1829 (CPUID_MCE | CPUID_MCA)) {
1830 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1831 cenv->mcg_ctl = ~(uint64_t)0;
1832 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1833 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1834 }
1835 }
1836 }
1837
1838 void x86_cpu_realize(Object *obj, Error **errp)
1839 {
1840 X86CPU *cpu = X86_CPU(obj);
1841
1842 #ifndef CONFIG_USER_ONLY
1843 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1844 #endif
1845
1846 mce_init(cpu);
1847 qemu_init_vcpu(&cpu->env);
1848 cpu_reset(CPU(cpu));
1849 }
1850
1851 static void x86_cpu_initfn(Object *obj)
1852 {
1853 X86CPU *cpu = X86_CPU(obj);
1854 CPUX86State *env = &cpu->env;
1855 static int inited;
1856
1857 cpu_exec_init(env);
1858
1859 object_property_add(obj, "family", "int",
1860 x86_cpuid_version_get_family,
1861 x86_cpuid_version_set_family, NULL, NULL, NULL);
1862 object_property_add(obj, "model", "int",
1863 x86_cpuid_version_get_model,
1864 x86_cpuid_version_set_model, NULL, NULL, NULL);
1865 object_property_add(obj, "stepping", "int",
1866 x86_cpuid_version_get_stepping,
1867 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
1868 object_property_add(obj, "level", "int",
1869 x86_cpuid_get_level,
1870 x86_cpuid_set_level, NULL, NULL, NULL);
1871 object_property_add(obj, "xlevel", "int",
1872 x86_cpuid_get_xlevel,
1873 x86_cpuid_set_xlevel, NULL, NULL, NULL);
1874 object_property_add_str(obj, "vendor",
1875 x86_cpuid_get_vendor,
1876 x86_cpuid_set_vendor, NULL);
1877 object_property_add_str(obj, "model-id",
1878 x86_cpuid_get_model_id,
1879 x86_cpuid_set_model_id, NULL);
1880 object_property_add(obj, "tsc-frequency", "int",
1881 x86_cpuid_get_tsc_freq,
1882 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
1883
1884 env->cpuid_apic_id = env->cpu_index;
1885
1886 /* init various static tables used in TCG mode */
1887 if (tcg_enabled() && !inited) {
1888 inited = 1;
1889 optimize_flags_init();
1890 #ifndef CONFIG_USER_ONLY
1891 cpu_set_debug_excp_handler(breakpoint_handler);
1892 #endif
1893 }
1894 }
1895
1896 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1897 {
1898 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1899 CPUClass *cc = CPU_CLASS(oc);
1900
1901 xcc->parent_reset = cc->reset;
1902 cc->reset = x86_cpu_reset;
1903 }
1904
1905 static const TypeInfo x86_cpu_type_info = {
1906 .name = TYPE_X86_CPU,
1907 .parent = TYPE_CPU,
1908 .instance_size = sizeof(X86CPU),
1909 .instance_init = x86_cpu_initfn,
1910 .abstract = false,
1911 .class_size = sizeof(X86CPUClass),
1912 .class_init = x86_cpu_common_class_init,
1913 };
1914
1915 static void x86_cpu_register_types(void)
1916 {
1917 type_register_static(&x86_cpu_type_info);
1918 }
1919
1920 type_init(x86_cpu_register_types)
QEMU modified to work with kvm