2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Register definitions
31 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG TCG_REG_R55
46 #define TCG_GUEST_BASE_REG TCG_REG_R0
52 /* Branch registers */
64 /* Floating point registers */
84 /* Predicate registers */
104 /* Application registers */
109 static const int tcg_target_reg_alloc_order
[] = {
164 static const int tcg_target_call_iarg_regs
[8] = {
175 static const int tcg_target_call_oarg_regs
[] = {
183 /* bundle templates: stops (double bar in the IA64 manual) are marked with
184 an uppercase letter. */
213 OPC_ADD_A1
= 0x10000000000ull
,
214 OPC_AND_A1
= 0x10060000000ull
,
215 OPC_AND_A3
= 0x10160000000ull
,
216 OPC_ANDCM_A1
= 0x10068000000ull
,
217 OPC_ANDCM_A3
= 0x10168000000ull
,
218 OPC_ADDS_A4
= 0x10800000000ull
,
219 OPC_ADDL_A5
= 0x12000000000ull
,
220 OPC_ALLOC_M34
= 0x02c00000000ull
,
221 OPC_BR_DPTK_FEW_B1
= 0x08400000000ull
,
222 OPC_BR_SPTK_MANY_B1
= 0x08000001000ull
,
223 OPC_BR_SPTK_MANY_B4
= 0x00100001000ull
,
224 OPC_BR_CALL_SPTK_MANY_B5
= 0x02100001000ull
,
225 OPC_BR_RET_SPTK_MANY_B4
= 0x00108001100ull
,
226 OPC_BRL_SPTK_MANY_X3
= 0x18000001000ull
,
227 OPC_CMP_LT_A6
= 0x18000000000ull
,
228 OPC_CMP_LTU_A6
= 0x1a000000000ull
,
229 OPC_CMP_EQ_A6
= 0x1c000000000ull
,
230 OPC_CMP4_LT_A6
= 0x18400000000ull
,
231 OPC_CMP4_LTU_A6
= 0x1a400000000ull
,
232 OPC_CMP4_EQ_A6
= 0x1c400000000ull
,
233 OPC_DEP_Z_I12
= 0x0a600000000ull
,
234 OPC_EXTR_I11
= 0x0a400002000ull
,
235 OPC_EXTR_U_I11
= 0x0a400000000ull
,
236 OPC_FCVT_FX_TRUNC_S1_F10
= 0x004d0000000ull
,
237 OPC_FCVT_FXU_TRUNC_S1_F10
= 0x004d8000000ull
,
238 OPC_FCVT_XF_F11
= 0x000e0000000ull
,
239 OPC_FMA_S1_F1
= 0x10400000000ull
,
240 OPC_FNMA_S1_F1
= 0x18400000000ull
,
241 OPC_FRCPA_S1_F6
= 0x00600000000ull
,
242 OPC_GETF_SIG_M19
= 0x08708000000ull
,
243 OPC_LD1_M1
= 0x08000000000ull
,
244 OPC_LD1_M3
= 0x0a000000000ull
,
245 OPC_LD2_M1
= 0x08040000000ull
,
246 OPC_LD2_M3
= 0x0a040000000ull
,
247 OPC_LD4_M1
= 0x08080000000ull
,
248 OPC_LD4_M3
= 0x0a080000000ull
,
249 OPC_LD8_M1
= 0x080c0000000ull
,
250 OPC_LD8_M3
= 0x0a0c0000000ull
,
251 OPC_MUX1_I3
= 0x0eca0000000ull
,
252 OPC_NOP_B9
= 0x04008000000ull
,
253 OPC_NOP_F16
= 0x00008000000ull
,
254 OPC_NOP_I18
= 0x00008000000ull
,
255 OPC_NOP_M48
= 0x00008000000ull
,
256 OPC_MOV_I21
= 0x00e00100000ull
,
257 OPC_MOV_RET_I21
= 0x00e00500000ull
,
258 OPC_MOV_I22
= 0x00188000000ull
,
259 OPC_MOV_I_I26
= 0x00150000000ull
,
260 OPC_MOVL_X2
= 0x0c000000000ull
,
261 OPC_OR_A1
= 0x10070000000ull
,
262 OPC_SETF_EXP_M18
= 0x0c748000000ull
,
263 OPC_SETF_SIG_M18
= 0x0c708000000ull
,
264 OPC_SHL_I7
= 0x0f240000000ull
,
265 OPC_SHR_I5
= 0x0f220000000ull
,
266 OPC_SHR_U_I5
= 0x0f200000000ull
,
267 OPC_SHRP_I10
= 0x0ac00000000ull
,
268 OPC_SXT1_I29
= 0x000a0000000ull
,
269 OPC_SXT2_I29
= 0x000a8000000ull
,
270 OPC_SXT4_I29
= 0x000b0000000ull
,
271 OPC_ST1_M4
= 0x08c00000000ull
,
272 OPC_ST2_M4
= 0x08c40000000ull
,
273 OPC_ST4_M4
= 0x08c80000000ull
,
274 OPC_ST8_M4
= 0x08cc0000000ull
,
275 OPC_SUB_A1
= 0x10028000000ull
,
276 OPC_SUB_A3
= 0x10128000000ull
,
277 OPC_UNPACK4_L_I2
= 0x0f860000000ull
,
278 OPC_XMA_L_F2
= 0x1d000000000ull
,
279 OPC_XOR_A1
= 0x10078000000ull
,
280 OPC_ZXT1_I29
= 0x00080000000ull
,
281 OPC_ZXT2_I29
= 0x00088000000ull
,
282 OPC_ZXT4_I29
= 0x00090000000ull
,
285 static inline uint64_t tcg_opc_a1(int qp
, uint64_t opc
, int r1
,
289 | ((r3
& 0x7f) << 20)
290 | ((r2
& 0x7f) << 13)
295 static inline uint64_t tcg_opc_a3(int qp
, uint64_t opc
, int r1
,
296 uint64_t imm
, int r3
)
299 | ((imm
& 0x80) << 29) /* s */
300 | ((imm
& 0x7f) << 13) /* imm7b */
301 | ((r3
& 0x7f) << 20)
306 static inline uint64_t tcg_opc_a4(int qp
, uint64_t opc
, int r1
,
307 uint64_t imm
, int r3
)
310 | ((imm
& 0x2000) << 23) /* s */
311 | ((imm
& 0x1f80) << 20) /* imm6d */
312 | ((imm
& 0x007f) << 13) /* imm7b */
313 | ((r3
& 0x7f) << 20)
318 static inline uint64_t tcg_opc_a5(int qp
, uint64_t opc
, int r1
,
319 uint64_t imm
, int r3
)
322 | ((imm
& 0x200000) << 15) /* s */
323 | ((imm
& 0x1f0000) << 6) /* imm5c */
324 | ((imm
& 0x00ff80) << 20) /* imm9d */
325 | ((imm
& 0x00007f) << 13) /* imm7b */
326 | ((r3
& 0x03) << 20)
331 static inline uint64_t tcg_opc_a6(int qp
, uint64_t opc
, int p1
,
332 int p2
, int r2
, int r3
)
335 | ((p2
& 0x3f) << 27)
336 | ((r3
& 0x7f) << 20)
337 | ((r2
& 0x7f) << 13)
342 static inline uint64_t tcg_opc_b1(int qp
, uint64_t opc
, uint64_t imm
)
345 | ((imm
& 0x100000) << 16) /* s */
346 | ((imm
& 0x0fffff) << 13) /* imm20b */
350 static inline uint64_t tcg_opc_b4(int qp
, uint64_t opc
, int b2
)
357 static inline uint64_t tcg_opc_b5(int qp
, uint64_t opc
, int b1
, int b2
)
366 static inline uint64_t tcg_opc_b9(int qp
, uint64_t opc
, uint64_t imm
)
369 | ((imm
& 0x100000) << 16) /* i */
370 | ((imm
& 0x0fffff) << 6) /* imm20a */
374 static inline uint64_t tcg_opc_f1(int qp
, uint64_t opc
, int f1
,
375 int f3
, int f4
, int f2
)
378 | ((f4
& 0x7f) << 27)
379 | ((f3
& 0x7f) << 20)
380 | ((f2
& 0x7f) << 13)
385 static inline uint64_t tcg_opc_f2(int qp
, uint64_t opc
, int f1
,
386 int f3
, int f4
, int f2
)
389 | ((f4
& 0x7f) << 27)
390 | ((f3
& 0x7f) << 20)
391 | ((f2
& 0x7f) << 13)
396 static inline uint64_t tcg_opc_f6(int qp
, uint64_t opc
, int f1
,
397 int p2
, int f2
, int f3
)
400 | ((p2
& 0x3f) << 27)
401 | ((f3
& 0x7f) << 20)
402 | ((f2
& 0x7f) << 13)
407 static inline uint64_t tcg_opc_f10(int qp
, uint64_t opc
, int f1
, int f2
)
410 | ((f2
& 0x7f) << 13)
415 static inline uint64_t tcg_opc_f11(int qp
, uint64_t opc
, int f1
, int f2
)
418 | ((f2
& 0x7f) << 13)
423 static inline uint64_t tcg_opc_f16(int qp
, uint64_t opc
, uint64_t imm
)
426 | ((imm
& 0x100000) << 16) /* i */
427 | ((imm
& 0x0fffff) << 6) /* imm20a */
431 static inline uint64_t tcg_opc_i2(int qp
, uint64_t opc
, int r1
,
435 | ((r3
& 0x7f) << 20)
436 | ((r2
& 0x7f) << 13)
441 static inline uint64_t tcg_opc_i3(int qp
, uint64_t opc
, int r1
,
445 | ((mbtype
& 0x0f) << 20)
446 | ((r2
& 0x7f) << 13)
451 static inline uint64_t tcg_opc_i5(int qp
, uint64_t opc
, int r1
,
455 | ((r3
& 0x7f) << 20)
456 | ((r2
& 0x7f) << 13)
461 static inline uint64_t tcg_opc_i7(int qp
, uint64_t opc
, int r1
,
465 | ((r3
& 0x7f) << 20)
466 | ((r2
& 0x7f) << 13)
471 static inline uint64_t tcg_opc_i10(int qp
, uint64_t opc
, int r1
,
472 int r2
, int r3
, uint64_t count
)
475 | ((count
& 0x3f) << 27)
476 | ((r3
& 0x7f) << 20)
477 | ((r2
& 0x7f) << 13)
482 static inline uint64_t tcg_opc_i11(int qp
, uint64_t opc
, int r1
,
483 int r3
, uint64_t pos
, uint64_t len
)
486 | ((len
& 0x3f) << 27)
487 | ((r3
& 0x7f) << 20)
488 | ((pos
& 0x3f) << 14)
493 static inline uint64_t tcg_opc_i12(int qp
, uint64_t opc
, int r1
,
494 int r2
, uint64_t pos
, uint64_t len
)
497 | ((len
& 0x3f) << 27)
498 | ((pos
& 0x3f) << 20)
499 | ((r2
& 0x7f) << 13)
504 static inline uint64_t tcg_opc_i18(int qp
, uint64_t opc
, uint64_t imm
)
507 | ((imm
& 0x100000) << 16) /* i */
508 | ((imm
& 0x0fffff) << 6) /* imm20a */
512 static inline uint64_t tcg_opc_i21(int qp
, uint64_t opc
, int b1
,
513 int r2
, uint64_t imm
)
516 | ((imm
& 0x1ff) << 24)
517 | ((r2
& 0x7f) << 13)
522 static inline uint64_t tcg_opc_i22(int qp
, uint64_t opc
, int r1
, int b2
)
530 static inline uint64_t tcg_opc_i26(int qp
, uint64_t opc
, int ar3
, int r2
)
533 | ((ar3
& 0x7f) << 20)
534 | ((r2
& 0x7f) << 13)
538 static inline uint64_t tcg_opc_i29(int qp
, uint64_t opc
, int r1
, int r3
)
541 | ((r3
& 0x7f) << 20)
546 static inline uint64_t tcg_opc_l2(uint64_t imm
)
548 return (imm
& 0x7fffffffffc00000ull
) >> 22;
551 static inline uint64_t tcg_opc_l3(uint64_t imm
)
553 return (imm
& 0x07fffffffff00000ull
) >> 18;
556 static inline uint64_t tcg_opc_m1(int qp
, uint64_t opc
, int r1
, int r3
)
559 | ((r3
& 0x7f) << 20)
564 static inline uint64_t tcg_opc_m3(int qp
, uint64_t opc
, int r1
,
565 int r3
, uint64_t imm
)
568 | ((imm
& 0x100) << 28) /* s */
569 | ((imm
& 0x080) << 20) /* i */
570 | ((imm
& 0x07f) << 13) /* imm7b */
571 | ((r3
& 0x7f) << 20)
576 static inline uint64_t tcg_opc_m4(int qp
, uint64_t opc
, int r2
, int r3
)
579 | ((r3
& 0x7f) << 20)
580 | ((r2
& 0x7f) << 13)
584 static inline uint64_t tcg_opc_m18(int qp
, uint64_t opc
, int f1
, int r2
)
587 | ((r2
& 0x7f) << 13)
592 static inline uint64_t tcg_opc_m19(int qp
, uint64_t opc
, int r1
, int f2
)
595 | ((f2
& 0x7f) << 13)
600 static inline uint64_t tcg_opc_m34(int qp
, uint64_t opc
, int r1
,
601 int sof
, int sol
, int sor
)
604 | ((sor
& 0x0f) << 27)
605 | ((sol
& 0x7f) << 20)
606 | ((sof
& 0x7f) << 13)
611 static inline uint64_t tcg_opc_m48(int qp
, uint64_t opc
, uint64_t imm
)
614 | ((imm
& 0x100000) << 16) /* i */
615 | ((imm
& 0x0fffff) << 6) /* imm20a */
619 static inline uint64_t tcg_opc_x2(int qp
, uint64_t opc
,
620 int r1
, uint64_t imm
)
623 | ((imm
& 0x8000000000000000ull
) >> 27) /* i */
624 | (imm
& 0x0000000000200000ull
) /* ic */
625 | ((imm
& 0x00000000001f0000ull
) << 6) /* imm5c */
626 | ((imm
& 0x000000000000ff80ull
) << 20) /* imm9d */
627 | ((imm
& 0x000000000000007full
) << 13) /* imm7b */
632 static inline uint64_t tcg_opc_x3(int qp
, uint64_t opc
, uint64_t imm
)
635 | ((imm
& 0x0800000000000000ull
) >> 23) /* i */
636 | ((imm
& 0x00000000000fffffull
) << 13) /* imm20b */
645 static inline void reloc_pcrel21b (void *pc
, tcg_target_long target
)
651 slot
= (tcg_target_long
) pc
& 3;
652 pc
= (void *)((tcg_target_long
) pc
& ~3);
654 disp
= target
- (tcg_target_long
) pc
;
655 imm
= (uint64_t) disp
>> 4;
659 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 8) & 0xfffffdc00003ffffull
)
660 | ((imm
& 0x100000) << 21) /* s */
661 | ((imm
& 0x0fffff) << 18); /* imm20b */
664 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xfffffffffffb8000ull
)
665 | ((imm
& 0x100000) >> 2) /* s */
666 | ((imm
& 0x0fffe0) >> 5); /* imm20b */
667 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 0) & 0x07ffffffffffffffull
)
668 | ((imm
& 0x00001f) << 59); /* imm20b */
671 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xf700000fffffffffull
)
672 | ((imm
& 0x100000) << 39) /* s */
673 | ((imm
& 0x0fffff) << 36); /* imm20b */
678 static inline uint64_t get_reloc_pcrel21b (void *pc
)
683 slot
= (tcg_target_long
) pc
& 3;
684 pc
= (void *)((tcg_target_long
) pc
& ~3);
686 low
= (*(uint64_t *)(pc
+ 0));
687 high
= (*(uint64_t *)(pc
+ 8));
691 return ((low
>> 21) & 0x100000) + /* s */
692 ((low
>> 18) & 0x0fffff); /* imm20b */
694 return ((high
<< 2) & 0x100000) + /* s */
695 ((high
<< 5) & 0x0fffe0) + /* imm20b */
696 ((low
>> 59) & 0x00001f); /* imm20b */
698 return ((high
>> 39) & 0x100000) + /* s */
699 ((high
>> 36) & 0x0fffff); /* imm20b */
705 static inline void reloc_pcrel60b (void *pc
, tcg_target_long target
)
710 disp
= target
- (tcg_target_long
) pc
;
711 imm
= (uint64_t) disp
>> 4;
713 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xf700000fff800000ull
)
714 | (imm
& 0x0800000000000000ull
) /* s */
715 | ((imm
& 0x07fffff000000000ull
) >> 36) /* imm39 */
716 | ((imm
& 0x00000000000fffffull
) << 36); /* imm20b */
717 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 0) & 0x00003fffffffffffull
)
718 | ((imm
& 0x0000000ffff00000ull
) << 28); /* imm39 */
721 static inline uint64_t get_reloc_pcrel60b (void *pc
)
725 low
= (*(uint64_t *)(pc
+ 0));
726 high
= (*(uint64_t *)(pc
+ 8));
728 return ((high
) & 0x0800000000000000ull
) + /* s */
729 ((high
>> 36) & 0x00000000000fffffull
) + /* imm20b */
730 ((high
<< 36) & 0x07fffff000000000ull
) + /* imm39 */
731 ((low
>> 28) & 0x0000000ffff00000ull
); /* imm39 */
735 static void patch_reloc(uint8_t *code_ptr
, int type
,
736 tcg_target_long value
, tcg_target_long addend
)
740 case R_IA64_PCREL21B
:
741 reloc_pcrel21b(code_ptr
, value
);
743 case R_IA64_PCREL60B
:
744 reloc_pcrel60b(code_ptr
, value
);
754 /* parse target specific constraints */
755 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
762 ct
->ct
|= TCG_CT_REG
;
763 tcg_regset_set(ct
->u
.regs
, 0xffffffffffffffffull
);
766 ct
->ct
|= TCG_CT_CONST_S22
;
769 ct
->ct
|= TCG_CT_REG
;
770 tcg_regset_set(ct
->u
.regs
, 0xffffffffffffffffull
);
771 #if defined(CONFIG_SOFTMMU)
772 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R56
);
773 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R57
);
777 /* We are cheating a bit here, using the fact that the register
778 r0 is also the register number 0. Hence there is no need
779 to check for const_args in each instruction. */
780 ct
->ct
|= TCG_CT_CONST_ZERO
;
790 /* test if a constant matches the constraint */
791 static inline int tcg_target_const_match(tcg_target_long val
,
792 const TCGArgConstraint
*arg_ct
)
796 if (ct
& TCG_CT_CONST
)
798 else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0)
800 else if ((ct
& TCG_CT_CONST_S22
) && val
== ((int32_t)val
<< 10) >> 10)
810 static uint8_t *tb_ret_addr
;
812 static inline void tcg_out_bundle(TCGContext
*s
, int template,
813 uint64_t slot0
, uint64_t slot1
,
816 template &= 0x1f; /* 5 bits */
817 slot0
&= 0x1ffffffffffull
; /* 41 bits */
818 slot1
&= 0x1ffffffffffull
; /* 41 bits */
819 slot2
&= 0x1ffffffffffull
; /* 41 bits */
821 *(uint64_t *)(s
->code_ptr
+ 0) = (slot1
<< 46) | (slot0
<< 5) | template;
822 *(uint64_t *)(s
->code_ptr
+ 8) = (slot2
<< 23) | (slot1
>> 18);
826 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
827 TCGReg ret
, TCGReg arg
)
829 tcg_out_bundle(s
, mmI
,
830 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
831 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
832 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
, ret
, 0, arg
));
835 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
836 TCGReg reg
, tcg_target_long arg
)
838 tcg_out_bundle(s
, mLX
,
839 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
841 tcg_opc_x2 (TCG_REG_P0
, OPC_MOVL_X2
, reg
, arg
));
844 static void tcg_out_br(TCGContext
*s
, int label_index
)
846 TCGLabel
*l
= &s
->labels
[label_index
];
848 /* We pay attention here to not modify the branch target by reading
849 the existing value and using it again. This ensure that caches and
850 memory are kept coherent during retranslation. */
851 tcg_out_bundle(s
, mmB
,
852 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
853 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
854 tcg_opc_b1 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B1
,
855 get_reloc_pcrel21b(s
->code_ptr
+ 2)));
858 reloc_pcrel21b((s
->code_ptr
- 16) + 2, l
->u
.value
);
860 tcg_out_reloc(s
, (s
->code_ptr
- 16) + 2,
861 R_IA64_PCREL21B
, label_index
, 0);
865 static inline void tcg_out_call(TCGContext
*s
, TCGArg addr
)
867 tcg_out_bundle(s
, MmI
,
868 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
, TCG_REG_R2
, addr
),
869 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
, TCG_REG_R3
, 8, addr
),
870 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
871 TCG_REG_B6
, TCG_REG_R2
, 0));
872 tcg_out_bundle(s
, mmB
,
873 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R3
),
874 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
875 tcg_opc_b5 (TCG_REG_P0
, OPC_BR_CALL_SPTK_MANY_B5
,
876 TCG_REG_B0
, TCG_REG_B6
));
879 static void tcg_out_exit_tb(TCGContext
*s
, tcg_target_long arg
)
884 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R8
, arg
);
886 disp
= tb_ret_addr
- s
->code_ptr
;
887 imm
= (uint64_t)disp
>> 4;
889 tcg_out_bundle(s
, mLX
,
890 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
892 tcg_opc_x3 (TCG_REG_P0
, OPC_BRL_SPTK_MANY_X3
, imm
));
895 static inline void tcg_out_goto_tb(TCGContext
*s
, TCGArg arg
)
897 if (s
->tb_jmp_offset
) {
898 /* direct jump method */
901 /* indirect jump method */
902 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
,
903 (tcg_target_long
)(s
->tb_next
+ arg
));
904 tcg_out_bundle(s
, MmI
,
905 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
,
906 TCG_REG_R2
, TCG_REG_R2
),
907 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
908 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
, TCG_REG_B6
,
910 tcg_out_bundle(s
, mmB
,
911 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
912 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
913 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
,
916 s
->tb_next_offset
[arg
] = s
->code_ptr
- s
->code_buf
;
919 static inline void tcg_out_jmp(TCGContext
*s
, TCGArg addr
)
921 tcg_out_bundle(s
, mmI
,
922 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
923 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
924 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
, TCG_REG_B6
, addr
, 0));
925 tcg_out_bundle(s
, mmB
,
926 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
927 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
928 tcg_opc_b4(TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
, TCG_REG_B6
));
931 static inline void tcg_out_ld_rel(TCGContext
*s
, uint64_t opc_m4
, TCGArg arg
,
932 TCGArg arg1
, tcg_target_long arg2
)
934 if (arg2
== ((int16_t)arg2
>> 2) << 2) {
935 tcg_out_bundle(s
, MmI
,
936 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
,
937 TCG_REG_R2
, arg2
, arg1
),
938 tcg_opc_m1 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
939 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
941 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
, arg2
);
942 tcg_out_bundle(s
, MmI
,
943 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
,
944 TCG_REG_R2
, TCG_REG_R2
, arg1
),
945 tcg_opc_m1 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
946 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
950 static inline void tcg_out_st_rel(TCGContext
*s
, uint64_t opc_m4
, TCGArg arg
,
951 TCGArg arg1
, tcg_target_long arg2
)
953 if (arg2
== ((int16_t)arg2
>> 2) << 2) {
954 tcg_out_bundle(s
, MmI
,
955 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
,
956 TCG_REG_R2
, arg2
, arg1
),
957 tcg_opc_m4 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
958 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
960 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
, arg2
);
961 tcg_out_bundle(s
, MmI
,
962 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
,
963 TCG_REG_R2
, TCG_REG_R2
, arg1
),
964 tcg_opc_m4 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
965 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
969 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
970 TCGReg arg1
, tcg_target_long arg2
)
972 if (type
== TCG_TYPE_I32
) {
973 tcg_out_ld_rel(s
, OPC_LD4_M1
, arg
, arg1
, arg2
);
975 tcg_out_ld_rel(s
, OPC_LD8_M1
, arg
, arg1
, arg2
);
979 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
980 TCGReg arg1
, tcg_target_long arg2
)
982 if (type
== TCG_TYPE_I32
) {
983 tcg_out_st_rel(s
, OPC_ST4_M4
, arg
, arg1
, arg2
);
985 tcg_out_st_rel(s
, OPC_ST8_M4
, arg
, arg1
, arg2
);
989 static inline void tcg_out_alu(TCGContext
*s
, uint64_t opc_a1
, TCGArg ret
,
990 TCGArg arg1
, int const_arg1
,
991 TCGArg arg2
, int const_arg2
)
995 if (const_arg1
&& arg1
!= 0) {
996 opc1
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
,
997 TCG_REG_R2
, arg1
, TCG_REG_R0
);
1000 opc1
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1003 if (const_arg2
&& arg2
!= 0) {
1004 opc2
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
,
1005 TCG_REG_R3
, arg2
, TCG_REG_R0
);
1008 opc2
= tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0);
1011 tcg_out_bundle(s
, mII
,
1014 tcg_opc_a1(TCG_REG_P0
, opc_a1
, ret
, arg1
, arg2
));
1017 static inline void tcg_out_eqv(TCGContext
*s
, TCGArg ret
,
1018 TCGArg arg1
, int const_arg1
,
1019 TCGArg arg2
, int const_arg2
)
1021 tcg_out_bundle(s
, mII
,
1022 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1023 tcg_opc_a1 (TCG_REG_P0
, OPC_XOR_A1
, ret
, arg1
, arg2
),
1024 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1027 static inline void tcg_out_nand(TCGContext
*s
, TCGArg ret
,
1028 TCGArg arg1
, int const_arg1
,
1029 TCGArg arg2
, int const_arg2
)
1031 tcg_out_bundle(s
, mII
,
1032 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1033 tcg_opc_a1 (TCG_REG_P0
, OPC_AND_A1
, ret
, arg1
, arg2
),
1034 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1037 static inline void tcg_out_nor(TCGContext
*s
, TCGArg ret
,
1038 TCGArg arg1
, int const_arg1
,
1039 TCGArg arg2
, int const_arg2
)
1041 tcg_out_bundle(s
, mII
,
1042 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1043 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
, arg1
, arg2
),
1044 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1047 static inline void tcg_out_orc(TCGContext
*s
, TCGArg ret
,
1048 TCGArg arg1
, int const_arg1
,
1049 TCGArg arg2
, int const_arg2
)
1051 tcg_out_bundle(s
, mII
,
1052 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1053 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, TCG_REG_R2
, -1, arg2
),
1054 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
, arg1
, TCG_REG_R2
));
1057 static inline void tcg_out_mul(TCGContext
*s
, TCGArg ret
,
1058 TCGArg arg1
, TCGArg arg2
)
1060 tcg_out_bundle(s
, mmI
,
1061 tcg_opc_m18(TCG_REG_P0
, OPC_SETF_SIG_M18
, TCG_REG_F6
, arg1
),
1062 tcg_opc_m18(TCG_REG_P0
, OPC_SETF_SIG_M18
, TCG_REG_F7
, arg2
),
1063 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1064 tcg_out_bundle(s
, mmF
,
1065 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1066 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1067 tcg_opc_f2 (TCG_REG_P0
, OPC_XMA_L_F2
, TCG_REG_F6
, TCG_REG_F6
,
1068 TCG_REG_F7
, TCG_REG_F0
));
1069 tcg_out_bundle(s
, miI
,
1070 tcg_opc_m19(TCG_REG_P0
, OPC_GETF_SIG_M19
, ret
, TCG_REG_F6
),
1071 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1072 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1075 static inline void tcg_out_sar_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1076 TCGArg arg2
, int const_arg2
)
1079 tcg_out_bundle(s
, miI
,
1080 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1081 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1082 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_I11
,
1083 ret
, arg1
, arg2
, 31 - arg2
));
1085 tcg_out_bundle(s
, mII
,
1086 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
,
1087 TCG_REG_R3
, 0x1f, arg2
),
1088 tcg_opc_i29(TCG_REG_P0
, OPC_SXT4_I29
, TCG_REG_R2
, arg1
),
1089 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_I5
, ret
,
1090 TCG_REG_R2
, TCG_REG_R3
));
1094 static inline void tcg_out_sar_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1095 TCGArg arg2
, int const_arg2
)
1098 tcg_out_bundle(s
, miI
,
1099 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1100 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1101 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_I11
,
1102 ret
, arg1
, arg2
, 63 - arg2
));
1104 tcg_out_bundle(s
, miI
,
1105 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1106 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1107 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_I5
, ret
, arg1
, arg2
));
1111 static inline void tcg_out_shl_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1112 TCGArg arg2
, int const_arg2
)
1115 tcg_out_bundle(s
, miI
,
1116 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1117 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1118 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
,
1119 arg1
, 63 - arg2
, 31 - arg2
));
1121 tcg_out_bundle(s
, mII
,
1122 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1123 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R2
,
1125 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, ret
,
1130 static inline void tcg_out_shl_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1131 TCGArg arg2
, int const_arg2
)
1134 tcg_out_bundle(s
, miI
,
1135 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1136 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1137 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
,
1138 arg1
, 63 - arg2
, 63 - arg2
));
1140 tcg_out_bundle(s
, miI
,
1141 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1142 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1143 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, ret
,
1148 static inline void tcg_out_shr_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1149 TCGArg arg2
, int const_arg2
)
1152 tcg_out_bundle(s
, miI
,
1153 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1154 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1155 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1156 arg1
, arg2
, 31 - arg2
));
1158 tcg_out_bundle(s
, mII
,
1159 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1161 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
, TCG_REG_R2
, arg1
),
1162 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1163 TCG_REG_R2
, TCG_REG_R3
));
1167 static inline void tcg_out_shr_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1168 TCGArg arg2
, int const_arg2
)
1171 tcg_out_bundle(s
, miI
,
1172 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1173 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1174 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1175 arg1
, arg2
, 63 - arg2
));
1177 tcg_out_bundle(s
, miI
,
1178 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1179 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1180 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1185 static inline void tcg_out_rotl_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1186 TCGArg arg2
, int const_arg2
)
1189 tcg_out_bundle(s
, mII
,
1190 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1191 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1192 TCG_REG_R2
, arg1
, arg1
),
1193 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1194 TCG_REG_R2
, 32 - arg2
, 31));
1196 tcg_out_bundle(s
, miI
,
1197 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1198 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1199 TCG_REG_R2
, arg1
, arg1
),
1200 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1202 tcg_out_bundle(s
, mII
,
1203 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1204 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R3
,
1206 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1207 TCG_REG_R2
, TCG_REG_R3
));
1211 static inline void tcg_out_rotl_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1212 TCGArg arg2
, int const_arg2
)
1215 tcg_out_bundle(s
, miI
,
1216 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1217 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1218 tcg_opc_i10(TCG_REG_P0
, OPC_SHRP_I10
, ret
, arg1
,
1219 arg1
, 0x40 - arg2
));
1221 tcg_out_bundle(s
, mII
,
1222 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R2
,
1224 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, TCG_REG_R3
,
1226 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, TCG_REG_R2
,
1228 tcg_out_bundle(s
, miI
,
1229 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1230 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1231 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
,
1232 TCG_REG_R2
, TCG_REG_R3
));
1236 static inline void tcg_out_rotr_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1237 TCGArg arg2
, int const_arg2
)
1240 tcg_out_bundle(s
, mII
,
1241 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1242 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1243 TCG_REG_R2
, arg1
, arg1
),
1244 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1245 TCG_REG_R2
, arg2
, 31));
1247 tcg_out_bundle(s
, mII
,
1248 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1250 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1251 TCG_REG_R2
, arg1
, arg1
),
1252 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1253 TCG_REG_R2
, TCG_REG_R3
));
1257 static inline void tcg_out_rotr_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1258 TCGArg arg2
, int const_arg2
)
1261 tcg_out_bundle(s
, miI
,
1262 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1263 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1264 tcg_opc_i10(TCG_REG_P0
, OPC_SHRP_I10
, ret
, arg1
,
1267 tcg_out_bundle(s
, mII
,
1268 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R2
,
1270 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, TCG_REG_R3
,
1272 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, TCG_REG_R2
,
1274 tcg_out_bundle(s
, miI
,
1275 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1276 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1277 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
,
1278 TCG_REG_R2
, TCG_REG_R3
));
1282 static inline void tcg_out_ext(TCGContext
*s
, uint64_t opc_i29
,
1283 TCGArg ret
, TCGArg arg
)
1285 tcg_out_bundle(s
, miI
,
1286 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1287 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1288 tcg_opc_i29(TCG_REG_P0
, opc_i29
, ret
, arg
));
1291 static inline void tcg_out_bswap16(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1293 tcg_out_bundle(s
, mII
,
1294 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1295 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
, arg
, 15, 15),
1296 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, ret
, 0xb));
1299 static inline void tcg_out_bswap32(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1301 tcg_out_bundle(s
, mII
,
1302 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1303 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
, arg
, 31, 31),
1304 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, ret
, 0xb));
1307 static inline void tcg_out_bswap64(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1309 tcg_out_bundle(s
, miI
,
1310 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1311 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1312 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, arg
, 0xb));
1315 static inline uint64_t tcg_opc_cmp_a(int qp
, TCGCond cond
, TCGArg arg1
,
1316 TCGArg arg2
, int cmp4
)
1318 uint64_t opc_eq_a6
, opc_lt_a6
, opc_ltu_a6
;
1321 opc_eq_a6
= OPC_CMP4_EQ_A6
;
1322 opc_lt_a6
= OPC_CMP4_LT_A6
;
1323 opc_ltu_a6
= OPC_CMP4_LTU_A6
;
1325 opc_eq_a6
= OPC_CMP_EQ_A6
;
1326 opc_lt_a6
= OPC_CMP_LT_A6
;
1327 opc_ltu_a6
= OPC_CMP_LTU_A6
;
1332 return tcg_opc_a6 (qp
, opc_eq_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1334 return tcg_opc_a6 (qp
, opc_eq_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1336 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1338 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1340 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1342 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1344 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P7
, TCG_REG_P6
, arg2
, arg1
);
1346 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P7
, TCG_REG_P6
, arg2
, arg1
);
1348 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P6
, TCG_REG_P7
, arg2
, arg1
);
1350 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P6
, TCG_REG_P7
, arg2
, arg1
);
1357 static inline void tcg_out_brcond(TCGContext
*s
, TCGCond cond
, TCGArg arg1
,
1358 int const_arg1
, TCGArg arg2
, int const_arg2
,
1359 int label_index
, int cmp4
)
1361 TCGLabel
*l
= &s
->labels
[label_index
];
1362 uint64_t opc1
, opc2
;
1364 if (const_arg1
&& arg1
!= 0) {
1365 opc1
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R2
,
1369 opc1
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1372 if (const_arg2
&& arg2
!= 0) {
1373 opc2
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R3
,
1377 opc2
= tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0);
1380 tcg_out_bundle(s
, mII
,
1383 tcg_opc_cmp_a(TCG_REG_P0
, cond
, arg1
, arg2
, cmp4
));
1384 tcg_out_bundle(s
, mmB
,
1385 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1386 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1387 tcg_opc_b1 (TCG_REG_P6
, OPC_BR_DPTK_FEW_B1
,
1388 get_reloc_pcrel21b(s
->code_ptr
+ 2)));
1391 reloc_pcrel21b((s
->code_ptr
- 16) + 2, l
->u
.value
);
1393 tcg_out_reloc(s
, (s
->code_ptr
- 16) + 2,
1394 R_IA64_PCREL21B
, label_index
, 0);
1398 static inline void tcg_out_setcond(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
1399 TCGArg arg1
, TCGArg arg2
, int cmp4
)
1401 tcg_out_bundle(s
, MmI
,
1402 tcg_opc_cmp_a(TCG_REG_P0
, cond
, arg1
, arg2
, cmp4
),
1403 tcg_opc_a5(TCG_REG_P6
, OPC_ADDL_A5
, ret
, 1, TCG_REG_R0
),
1404 tcg_opc_a5(TCG_REG_P7
, OPC_ADDL_A5
, ret
, 0, TCG_REG_R0
));
1407 #if defined(CONFIG_SOFTMMU)
1409 #include "../../softmmu_defs.h"
1411 /* Load and compare a TLB entry, and return the result in (p6, p7).
1412 R2 is loaded with the address of the addend TLB entry.
1413 R56 is loaded with the address, zero extented on 32-bit targets. */
1414 static inline void tcg_out_qemu_tlb(TCGContext
*s
, TCGArg addr_reg
,
1415 int s_bits
, uint64_t offset_rw
,
1416 uint64_t offset_addend
)
1418 tcg_out_bundle(s
, mII
,
1419 tcg_opc_a5 (TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R3
,
1420 TARGET_PAGE_MASK
| ((1 << s_bits
) - 1),
1422 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, TCG_REG_R2
,
1423 addr_reg
, TARGET_PAGE_BITS
, CPU_TLB_BITS
- 1),
1424 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, TCG_REG_R2
,
1425 TCG_REG_R2
, 63 - CPU_TLB_ENTRY_BITS
,
1426 63 - CPU_TLB_ENTRY_BITS
));
1427 tcg_out_bundle(s
, mII
,
1428 tcg_opc_a5 (TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R2
,
1429 offset_rw
, TCG_REG_R2
),
1430 #if TARGET_LONG_BITS == 32
1431 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
, TCG_REG_R56
, addr_reg
),
1433 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
, TCG_REG_R56
,
1436 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1437 TCG_REG_R2
, TCG_AREG0
));
1438 tcg_out_bundle(s
, mII
,
1439 tcg_opc_m3 (TCG_REG_P0
,
1440 (TARGET_LONG_BITS
== 32
1441 ? OPC_LD4_M3
: OPC_LD8_M3
), TCG_REG_R57
,
1442 TCG_REG_R2
, offset_addend
- offset_rw
),
1443 tcg_opc_a1 (TCG_REG_P0
, OPC_AND_A1
, TCG_REG_R3
,
1444 TCG_REG_R3
, TCG_REG_R56
),
1445 tcg_opc_a6 (TCG_REG_P0
, OPC_CMP_EQ_A6
, TCG_REG_P6
,
1446 TCG_REG_P7
, TCG_REG_R3
, TCG_REG_R57
));
1449 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1451 static const void * const qemu_ld_helpers
[4] = {
1458 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1460 int addr_reg
, data_reg
, mem_index
, s_bits
, bswap
;
1461 uint64_t opc_ld_m1
[4] = { OPC_LD1_M1
, OPC_LD2_M1
, OPC_LD4_M1
, OPC_LD8_M1
};
1462 uint64_t opc_ext_i29
[8] = { OPC_ZXT1_I29
, OPC_ZXT2_I29
, OPC_ZXT4_I29
, 0,
1463 OPC_SXT1_I29
, OPC_SXT2_I29
, OPC_SXT4_I29
, 0 };
1470 #ifdef TARGET_WORDS_BIGENDIAN
1476 /* Read the TLB entry */
1477 tcg_out_qemu_tlb(s
, addr_reg
, s_bits
,
1478 offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
),
1479 offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
));
1481 /* P6 is the fast path, and P7 the slow path */
1482 tcg_out_bundle(s
, mLX
,
1483 tcg_opc_a5 (TCG_REG_P7
, OPC_ADDL_A5
, TCG_REG_R57
,
1484 mem_index
, TCG_REG_R0
),
1485 tcg_opc_l2 ((tcg_target_long
) qemu_ld_helpers
[s_bits
]),
1486 tcg_opc_x2 (TCG_REG_P7
, OPC_MOVL_X2
, TCG_REG_R2
,
1487 (tcg_target_long
) qemu_ld_helpers
[s_bits
]));
1488 tcg_out_bundle(s
, MmI
,
1489 tcg_opc_m3 (TCG_REG_P0
, OPC_LD8_M3
, TCG_REG_R3
,
1491 tcg_opc_a1 (TCG_REG_P6
, OPC_ADD_A1
, TCG_REG_R3
,
1492 TCG_REG_R3
, TCG_REG_R56
),
1493 tcg_opc_i21(TCG_REG_P7
, OPC_MOV_I21
, TCG_REG_B6
,
1495 if (bswap
&& s_bits
== 1) {
1496 tcg_out_bundle(s
, MmI
,
1497 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1498 TCG_REG_R8
, TCG_REG_R3
),
1499 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1500 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1501 TCG_REG_R8
, TCG_REG_R8
, 15, 15));
1502 } else if (bswap
&& s_bits
== 2) {
1503 tcg_out_bundle(s
, MmI
,
1504 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1505 TCG_REG_R8
, TCG_REG_R3
),
1506 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1507 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1508 TCG_REG_R8
, TCG_REG_R8
, 31, 31));
1510 tcg_out_bundle(s
, mmI
,
1511 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1512 TCG_REG_R8
, TCG_REG_R3
),
1513 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1514 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1516 /* XXX/FIXME: suboptimal */
1517 tcg_out_bundle(s
, mII
,
1518 tcg_opc_a5 (TCG_REG_P7
, OPC_ADDL_A5
, TCG_REG_R58
,
1519 mem_index
, TCG_REG_R0
),
1520 tcg_opc_a4 (TCG_REG_P7
, OPC_ADDS_A4
,
1521 TCG_REG_R57
, 0, TCG_REG_R56
),
1522 tcg_opc_a4 (TCG_REG_P7
, OPC_ADDS_A4
,
1523 TCG_REG_R56
, 0, TCG_AREG0
));
1524 if (!bswap
|| s_bits
== 0) {
1525 tcg_out_bundle(s
, miB
,
1526 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1527 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1528 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1529 TCG_REG_B0
, TCG_REG_B6
));
1531 tcg_out_bundle(s
, miB
,
1532 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1533 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1534 TCG_REG_R8
, TCG_REG_R8
, 0xb),
1535 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1536 TCG_REG_B0
, TCG_REG_B6
));
1540 tcg_out_bundle(s
, miI
,
1541 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1542 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1543 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
1544 data_reg
, 0, TCG_REG_R8
));
1546 tcg_out_bundle(s
, miI
,
1547 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1548 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1549 tcg_opc_i29(TCG_REG_P0
, opc_ext_i29
[opc
],
1550 data_reg
, TCG_REG_R8
));
1554 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1555 uintxx_t val, int mmu_idx) */
1556 static const void * const qemu_st_helpers
[4] = {
1563 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1565 int addr_reg
, data_reg
, mem_index
, bswap
;
1566 uint64_t opc_st_m4
[4] = { OPC_ST1_M4
, OPC_ST2_M4
, OPC_ST4_M4
, OPC_ST8_M4
};
1572 #ifdef TARGET_WORDS_BIGENDIAN
1578 tcg_out_qemu_tlb(s
, addr_reg
, opc
,
1579 offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_write
),
1580 offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
));
1582 /* P6 is the fast path, and P7 the slow path */
1583 tcg_out_bundle(s
, mLX
,
1584 tcg_opc_a4(TCG_REG_P7
, OPC_ADDS_A4
, TCG_REG_R57
,
1586 tcg_opc_l2 ((tcg_target_long
) qemu_st_helpers
[opc
]),
1587 tcg_opc_x2 (TCG_REG_P7
, OPC_MOVL_X2
, TCG_REG_R2
,
1588 (tcg_target_long
) qemu_st_helpers
[opc
]));
1589 tcg_out_bundle(s
, MmI
,
1590 tcg_opc_m3 (TCG_REG_P0
, OPC_LD8_M3
, TCG_REG_R3
,
1592 tcg_opc_a1 (TCG_REG_P6
, OPC_ADD_A1
, TCG_REG_R3
,
1593 TCG_REG_R3
, TCG_REG_R56
),
1594 tcg_opc_i21(TCG_REG_P7
, OPC_MOV_I21
, TCG_REG_B6
,
1597 if (!bswap
|| opc
== 0) {
1598 tcg_out_bundle(s
, mII
,
1599 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1600 TCG_REG_R1
, TCG_REG_R2
),
1601 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1602 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1603 } else if (opc
== 1) {
1604 tcg_out_bundle(s
, mII
,
1605 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1606 TCG_REG_R1
, TCG_REG_R2
),
1607 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1608 TCG_REG_R2
, data_reg
, 15, 15),
1609 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1610 TCG_REG_R2
, TCG_REG_R2
, 0xb));
1611 data_reg
= TCG_REG_R2
;
1612 } else if (opc
== 2) {
1613 tcg_out_bundle(s
, mII
,
1614 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1615 TCG_REG_R1
, TCG_REG_R2
),
1616 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1617 TCG_REG_R2
, data_reg
, 31, 31),
1618 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1619 TCG_REG_R2
, TCG_REG_R2
, 0xb));
1620 data_reg
= TCG_REG_R2
;
1621 } else if (opc
== 3) {
1622 tcg_out_bundle(s
, miI
,
1623 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1624 TCG_REG_R1
, TCG_REG_R2
),
1625 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1626 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1627 TCG_REG_R2
, data_reg
, 0xb));
1628 data_reg
= TCG_REG_R2
;
1631 /* XXX/FIXME: suboptimal */
1632 tcg_out_bundle(s
, mII
,
1633 tcg_opc_a5 (TCG_REG_P7
, OPC_ADDL_A5
, TCG_REG_R59
,
1634 mem_index
, TCG_REG_R0
),
1635 tcg_opc_a4 (TCG_REG_P7
, OPC_ADDS_A4
,
1636 TCG_REG_R58
, 0, TCG_REG_R57
),
1637 tcg_opc_a4 (TCG_REG_P7
, OPC_ADDS_A4
,
1638 TCG_REG_R57
, 0, TCG_REG_R56
));
1639 tcg_out_bundle(s
, miB
,
1640 tcg_opc_m4 (TCG_REG_P6
, opc_st_m4
[opc
],
1641 data_reg
, TCG_REG_R3
),
1642 tcg_opc_a4 (TCG_REG_P7
, OPC_ADDS_A4
,
1643 TCG_REG_R56
, 0, TCG_AREG0
),
1644 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1645 TCG_REG_B0
, TCG_REG_B6
));
1648 #else /* !CONFIG_SOFTMMU */
1650 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1652 static uint64_t const opc_ld_m1
[4] = {
1653 OPC_LD1_M1
, OPC_LD2_M1
, OPC_LD4_M1
, OPC_LD8_M1
1655 static uint64_t const opc_sxt_i29
[4] = {
1656 OPC_SXT1_I29
, OPC_SXT2_I29
, OPC_SXT4_I29
, 0
1658 int addr_reg
, data_reg
, s_bits
, bswap
;
1664 #ifdef TARGET_WORDS_BIGENDIAN
1670 #if TARGET_LONG_BITS == 32
1671 if (GUEST_BASE
!= 0) {
1672 tcg_out_bundle(s
, mII
,
1673 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1674 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1675 TCG_REG_R3
, addr_reg
),
1676 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1677 TCG_GUEST_BASE_REG
, TCG_REG_R3
));
1679 tcg_out_bundle(s
, miI
,
1680 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1681 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1682 TCG_REG_R2
, addr_reg
),
1683 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1686 if (!bswap
|| s_bits
== 0) {
1687 if (s_bits
== opc
) {
1688 tcg_out_bundle(s
, miI
,
1689 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1690 data_reg
, TCG_REG_R2
),
1691 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1692 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1694 tcg_out_bundle(s
, mII
,
1695 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1696 data_reg
, TCG_REG_R2
),
1697 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1698 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1699 data_reg
, data_reg
));
1701 } else if (s_bits
== 3) {
1702 tcg_out_bundle(s
, mII
,
1703 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1704 data_reg
, TCG_REG_R2
),
1705 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1706 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1707 data_reg
, data_reg
, 0xb));
1710 tcg_out_bundle(s
, mII
,
1711 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1712 data_reg
, TCG_REG_R2
),
1713 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1714 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1715 data_reg
, data_reg
, 15, 15));
1717 tcg_out_bundle(s
, mII
,
1718 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1719 data_reg
, TCG_REG_R2
),
1720 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1721 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1722 data_reg
, data_reg
, 31, 31));
1724 if (opc
== s_bits
) {
1725 tcg_out_bundle(s
, miI
,
1726 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1727 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1728 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1729 data_reg
, data_reg
, 0xb));
1731 tcg_out_bundle(s
, mII
,
1732 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1733 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1734 data_reg
, data_reg
, 0xb),
1735 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1736 data_reg
, data_reg
));
1740 if (GUEST_BASE
!= 0) {
1741 tcg_out_bundle(s
, MmI
,
1742 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1743 TCG_GUEST_BASE_REG
, addr_reg
),
1744 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1745 data_reg
, TCG_REG_R2
),
1746 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1748 tcg_out_bundle(s
, mmI
,
1749 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1750 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1751 data_reg
, addr_reg
),
1752 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1755 if (bswap
&& s_bits
== 1) {
1756 tcg_out_bundle(s
, mII
,
1757 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1758 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1759 data_reg
, data_reg
, 15, 15),
1760 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1761 data_reg
, data_reg
, 0xb));
1762 } else if (bswap
&& s_bits
== 2) {
1763 tcg_out_bundle(s
, mII
,
1764 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1765 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1766 data_reg
, data_reg
, 31, 31),
1767 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1768 data_reg
, data_reg
, 0xb));
1769 } else if (bswap
&& s_bits
== 3) {
1770 tcg_out_bundle(s
, miI
,
1771 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1772 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1773 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1774 data_reg
, data_reg
, 0xb));
1776 if (s_bits
!= opc
) {
1777 tcg_out_bundle(s
, miI
,
1778 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1779 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1780 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1781 data_reg
, data_reg
));
1786 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1788 static uint64_t const opc_st_m4
[4] = {
1789 OPC_ST1_M4
, OPC_ST2_M4
, OPC_ST4_M4
, OPC_ST8_M4
1791 int addr_reg
, data_reg
, bswap
;
1792 #if TARGET_LONG_BITS == 64
1793 uint64_t add_guest_base
;
1799 #ifdef TARGET_WORDS_BIGENDIAN
1805 #if TARGET_LONG_BITS == 32
1806 if (GUEST_BASE
!= 0) {
1807 tcg_out_bundle(s
, mII
,
1808 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1809 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1810 TCG_REG_R3
, addr_reg
),
1811 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1812 TCG_GUEST_BASE_REG
, TCG_REG_R3
));
1814 tcg_out_bundle(s
, miI
,
1815 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1816 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1817 TCG_REG_R2
, addr_reg
),
1818 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1823 tcg_out_bundle(s
, mII
,
1824 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1825 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1826 TCG_REG_R3
, data_reg
, 15, 15),
1827 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1828 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1829 data_reg
= TCG_REG_R3
;
1830 } else if (opc
== 2) {
1831 tcg_out_bundle(s
, mII
,
1832 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1833 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1834 TCG_REG_R3
, data_reg
, 31, 31),
1835 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1836 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1837 data_reg
= TCG_REG_R3
;
1838 } else if (opc
== 3) {
1839 tcg_out_bundle(s
, miI
,
1840 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1841 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1842 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1843 TCG_REG_R3
, data_reg
, 0xb));
1844 data_reg
= TCG_REG_R3
;
1847 tcg_out_bundle(s
, mmI
,
1848 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1849 data_reg
, TCG_REG_R2
),
1850 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1851 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1853 if (GUEST_BASE
!= 0) {
1854 add_guest_base
= tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1855 TCG_GUEST_BASE_REG
, addr_reg
);
1856 addr_reg
= TCG_REG_R2
;
1858 add_guest_base
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1861 if (!bswap
|| opc
== 0) {
1862 tcg_out_bundle(s
, (GUEST_BASE
? MmI
: mmI
),
1864 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1865 data_reg
, addr_reg
),
1866 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1869 tcg_out_bundle(s
, mII
,
1871 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1872 TCG_REG_R3
, data_reg
, 15, 15),
1873 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1874 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1875 data_reg
= TCG_REG_R3
;
1876 } else if (opc
== 2) {
1877 tcg_out_bundle(s
, mII
,
1879 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1880 TCG_REG_R3
, data_reg
, 31, 31),
1881 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1882 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1883 data_reg
= TCG_REG_R3
;
1884 } else if (opc
== 3) {
1885 tcg_out_bundle(s
, miI
,
1887 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1888 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1889 TCG_REG_R3
, data_reg
, 0xb));
1890 data_reg
= TCG_REG_R3
;
1892 tcg_out_bundle(s
, miI
,
1893 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1894 data_reg
, addr_reg
),
1895 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1896 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1903 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1904 const TCGArg
*args
, const int *const_args
)
1907 case INDEX_op_exit_tb
:
1908 tcg_out_exit_tb(s
, args
[0]);
1911 tcg_out_br(s
, args
[0]);
1914 tcg_out_call(s
, args
[0]);
1916 case INDEX_op_goto_tb
:
1917 tcg_out_goto_tb(s
, args
[0]);
1920 case INDEX_op_movi_i32
:
1921 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1923 case INDEX_op_movi_i64
:
1924 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
1927 case INDEX_op_ld8u_i32
:
1928 case INDEX_op_ld8u_i64
:
1929 tcg_out_ld_rel(s
, OPC_LD1_M1
, args
[0], args
[1], args
[2]);
1931 case INDEX_op_ld8s_i32
:
1932 case INDEX_op_ld8s_i64
:
1933 tcg_out_ld_rel(s
, OPC_LD1_M1
, args
[0], args
[1], args
[2]);
1934 tcg_out_ext(s
, OPC_SXT1_I29
, args
[0], args
[0]);
1936 case INDEX_op_ld16u_i32
:
1937 case INDEX_op_ld16u_i64
:
1938 tcg_out_ld_rel(s
, OPC_LD2_M1
, args
[0], args
[1], args
[2]);
1940 case INDEX_op_ld16s_i32
:
1941 case INDEX_op_ld16s_i64
:
1942 tcg_out_ld_rel(s
, OPC_LD2_M1
, args
[0], args
[1], args
[2]);
1943 tcg_out_ext(s
, OPC_SXT2_I29
, args
[0], args
[0]);
1945 case INDEX_op_ld_i32
:
1946 case INDEX_op_ld32u_i64
:
1947 tcg_out_ld_rel(s
, OPC_LD4_M1
, args
[0], args
[1], args
[2]);
1949 case INDEX_op_ld32s_i64
:
1950 tcg_out_ld_rel(s
, OPC_LD4_M1
, args
[0], args
[1], args
[2]);
1951 tcg_out_ext(s
, OPC_SXT4_I29
, args
[0], args
[0]);
1953 case INDEX_op_ld_i64
:
1954 tcg_out_ld_rel(s
, OPC_LD8_M1
, args
[0], args
[1], args
[2]);
1956 case INDEX_op_st8_i32
:
1957 case INDEX_op_st8_i64
:
1958 tcg_out_st_rel(s
, OPC_ST1_M4
, args
[0], args
[1], args
[2]);
1960 case INDEX_op_st16_i32
:
1961 case INDEX_op_st16_i64
:
1962 tcg_out_st_rel(s
, OPC_ST2_M4
, args
[0], args
[1], args
[2]);
1964 case INDEX_op_st_i32
:
1965 case INDEX_op_st32_i64
:
1966 tcg_out_st_rel(s
, OPC_ST4_M4
, args
[0], args
[1], args
[2]);
1968 case INDEX_op_st_i64
:
1969 tcg_out_st_rel(s
, OPC_ST8_M4
, args
[0], args
[1], args
[2]);
1972 case INDEX_op_add_i32
:
1973 case INDEX_op_add_i64
:
1974 tcg_out_alu(s
, OPC_ADD_A1
, args
[0], args
[1], const_args
[1],
1975 args
[2], const_args
[2]);
1977 case INDEX_op_sub_i32
:
1978 case INDEX_op_sub_i64
:
1979 tcg_out_alu(s
, OPC_SUB_A1
, args
[0], args
[1], const_args
[1],
1980 args
[2], const_args
[2]);
1983 case INDEX_op_and_i32
:
1984 case INDEX_op_and_i64
:
1985 tcg_out_alu(s
, OPC_AND_A1
, args
[0], args
[1], const_args
[1],
1986 args
[2], const_args
[2]);
1988 case INDEX_op_andc_i32
:
1989 case INDEX_op_andc_i64
:
1990 tcg_out_alu(s
, OPC_ANDCM_A1
, args
[0], args
[1], const_args
[1],
1991 args
[2], const_args
[2]);
1993 case INDEX_op_eqv_i32
:
1994 case INDEX_op_eqv_i64
:
1995 tcg_out_eqv(s
, args
[0], args
[1], const_args
[1],
1996 args
[2], const_args
[2]);
1998 case INDEX_op_nand_i32
:
1999 case INDEX_op_nand_i64
:
2000 tcg_out_nand(s
, args
[0], args
[1], const_args
[1],
2001 args
[2], const_args
[2]);
2003 case INDEX_op_nor_i32
:
2004 case INDEX_op_nor_i64
:
2005 tcg_out_nor(s
, args
[0], args
[1], const_args
[1],
2006 args
[2], const_args
[2]);
2008 case INDEX_op_or_i32
:
2009 case INDEX_op_or_i64
:
2010 tcg_out_alu(s
, OPC_OR_A1
, args
[0], args
[1], const_args
[1],
2011 args
[2], const_args
[2]);
2013 case INDEX_op_orc_i32
:
2014 case INDEX_op_orc_i64
:
2015 tcg_out_orc(s
, args
[0], args
[1], const_args
[1],
2016 args
[2], const_args
[2]);
2018 case INDEX_op_xor_i32
:
2019 case INDEX_op_xor_i64
:
2020 tcg_out_alu(s
, OPC_XOR_A1
, args
[0], args
[1], const_args
[1],
2021 args
[2], const_args
[2]);
2024 case INDEX_op_mul_i32
:
2025 case INDEX_op_mul_i64
:
2026 tcg_out_mul(s
, args
[0], args
[1], args
[2]);
2029 case INDEX_op_sar_i32
:
2030 tcg_out_sar_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2032 case INDEX_op_sar_i64
:
2033 tcg_out_sar_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2035 case INDEX_op_shl_i32
:
2036 tcg_out_shl_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2038 case INDEX_op_shl_i64
:
2039 tcg_out_shl_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2041 case INDEX_op_shr_i32
:
2042 tcg_out_shr_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2044 case INDEX_op_shr_i64
:
2045 tcg_out_shr_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2047 case INDEX_op_rotl_i32
:
2048 tcg_out_rotl_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2050 case INDEX_op_rotl_i64
:
2051 tcg_out_rotl_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2053 case INDEX_op_rotr_i32
:
2054 tcg_out_rotr_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2056 case INDEX_op_rotr_i64
:
2057 tcg_out_rotr_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2060 case INDEX_op_ext8s_i32
:
2061 case INDEX_op_ext8s_i64
:
2062 tcg_out_ext(s
, OPC_SXT1_I29
, args
[0], args
[1]);
2064 case INDEX_op_ext8u_i32
:
2065 case INDEX_op_ext8u_i64
:
2066 tcg_out_ext(s
, OPC_ZXT1_I29
, args
[0], args
[1]);
2068 case INDEX_op_ext16s_i32
:
2069 case INDEX_op_ext16s_i64
:
2070 tcg_out_ext(s
, OPC_SXT2_I29
, args
[0], args
[1]);
2072 case INDEX_op_ext16u_i32
:
2073 case INDEX_op_ext16u_i64
:
2074 tcg_out_ext(s
, OPC_ZXT2_I29
, args
[0], args
[1]);
2076 case INDEX_op_ext32s_i64
:
2077 tcg_out_ext(s
, OPC_SXT4_I29
, args
[0], args
[1]);
2079 case INDEX_op_ext32u_i64
:
2080 tcg_out_ext(s
, OPC_ZXT4_I29
, args
[0], args
[1]);
2083 case INDEX_op_bswap16_i32
:
2084 case INDEX_op_bswap16_i64
:
2085 tcg_out_bswap16(s
, args
[0], args
[1]);
2087 case INDEX_op_bswap32_i32
:
2088 case INDEX_op_bswap32_i64
:
2089 tcg_out_bswap32(s
, args
[0], args
[1]);
2091 case INDEX_op_bswap64_i64
:
2092 tcg_out_bswap64(s
, args
[0], args
[1]);
2095 case INDEX_op_brcond_i32
:
2096 tcg_out_brcond(s
, args
[2], args
[0], const_args
[0],
2097 args
[1], const_args
[1], args
[3], 1);
2099 case INDEX_op_brcond_i64
:
2100 tcg_out_brcond(s
, args
[2], args
[0], const_args
[0],
2101 args
[1], const_args
[1], args
[3], 0);
2103 case INDEX_op_setcond_i32
:
2104 tcg_out_setcond(s
, args
[3], args
[0], args
[1], args
[2], 1);
2106 case INDEX_op_setcond_i64
:
2107 tcg_out_setcond(s
, args
[3], args
[0], args
[1], args
[2], 0);
2110 case INDEX_op_qemu_ld8u
:
2111 tcg_out_qemu_ld(s
, args
, 0);
2113 case INDEX_op_qemu_ld8s
:
2114 tcg_out_qemu_ld(s
, args
, 0 | 4);
2116 case INDEX_op_qemu_ld16u
:
2117 tcg_out_qemu_ld(s
, args
, 1);
2119 case INDEX_op_qemu_ld16s
:
2120 tcg_out_qemu_ld(s
, args
, 1 | 4);
2122 case INDEX_op_qemu_ld32
:
2123 case INDEX_op_qemu_ld32u
:
2124 tcg_out_qemu_ld(s
, args
, 2);
2126 case INDEX_op_qemu_ld32s
:
2127 tcg_out_qemu_ld(s
, args
, 2 | 4);
2129 case INDEX_op_qemu_ld64
:
2130 tcg_out_qemu_ld(s
, args
, 3);
2133 case INDEX_op_qemu_st8
:
2134 tcg_out_qemu_st(s
, args
, 0);
2136 case INDEX_op_qemu_st16
:
2137 tcg_out_qemu_st(s
, args
, 1);
2139 case INDEX_op_qemu_st32
:
2140 tcg_out_qemu_st(s
, args
, 2);
2142 case INDEX_op_qemu_st64
:
2143 tcg_out_qemu_st(s
, args
, 3);
2151 static const TCGTargetOpDef ia64_op_defs
[] = {
2152 { INDEX_op_br
, { } },
2153 { INDEX_op_call
, { "r" } },
2154 { INDEX_op_exit_tb
, { } },
2155 { INDEX_op_goto_tb
, { } },
2157 { INDEX_op_mov_i32
, { "r", "r" } },
2158 { INDEX_op_movi_i32
, { "r" } },
2160 { INDEX_op_ld8u_i32
, { "r", "r" } },
2161 { INDEX_op_ld8s_i32
, { "r", "r" } },
2162 { INDEX_op_ld16u_i32
, { "r", "r" } },
2163 { INDEX_op_ld16s_i32
, { "r", "r" } },
2164 { INDEX_op_ld_i32
, { "r", "r" } },
2165 { INDEX_op_st8_i32
, { "rZ", "r" } },
2166 { INDEX_op_st16_i32
, { "rZ", "r" } },
2167 { INDEX_op_st_i32
, { "rZ", "r" } },
2169 { INDEX_op_add_i32
, { "r", "rI", "rI" } },
2170 { INDEX_op_sub_i32
, { "r", "rI", "rI" } },
2172 { INDEX_op_and_i32
, { "r", "rI", "rI" } },
2173 { INDEX_op_andc_i32
, { "r", "rI", "rI" } },
2174 { INDEX_op_eqv_i32
, { "r", "rZ", "rZ" } },
2175 { INDEX_op_nand_i32
, { "r", "rZ", "rZ" } },
2176 { INDEX_op_nor_i32
, { "r", "rZ", "rZ" } },
2177 { INDEX_op_or_i32
, { "r", "rI", "rI" } },
2178 { INDEX_op_orc_i32
, { "r", "rZ", "rZ" } },
2179 { INDEX_op_xor_i32
, { "r", "rI", "rI" } },
2181 { INDEX_op_mul_i32
, { "r", "rZ", "rZ" } },
2183 { INDEX_op_sar_i32
, { "r", "rZ", "ri" } },
2184 { INDEX_op_shl_i32
, { "r", "rZ", "ri" } },
2185 { INDEX_op_shr_i32
, { "r", "rZ", "ri" } },
2186 { INDEX_op_rotl_i32
, { "r", "rZ", "ri" } },
2187 { INDEX_op_rotr_i32
, { "r", "rZ", "ri" } },
2189 { INDEX_op_ext8s_i32
, { "r", "rZ"} },
2190 { INDEX_op_ext8u_i32
, { "r", "rZ"} },
2191 { INDEX_op_ext16s_i32
, { "r", "rZ"} },
2192 { INDEX_op_ext16u_i32
, { "r", "rZ"} },
2194 { INDEX_op_bswap16_i32
, { "r", "rZ" } },
2195 { INDEX_op_bswap32_i32
, { "r", "rZ" } },
2197 { INDEX_op_brcond_i32
, { "rI", "rI" } },
2198 { INDEX_op_setcond_i32
, { "r", "rZ", "rZ" } },
2200 { INDEX_op_mov_i64
, { "r", "r" } },
2201 { INDEX_op_movi_i64
, { "r" } },
2203 { INDEX_op_ld8u_i64
, { "r", "r" } },
2204 { INDEX_op_ld8s_i64
, { "r", "r" } },
2205 { INDEX_op_ld16u_i64
, { "r", "r" } },
2206 { INDEX_op_ld16s_i64
, { "r", "r" } },
2207 { INDEX_op_ld32u_i64
, { "r", "r" } },
2208 { INDEX_op_ld32s_i64
, { "r", "r" } },
2209 { INDEX_op_ld_i64
, { "r", "r" } },
2210 { INDEX_op_st8_i64
, { "rZ", "r" } },
2211 { INDEX_op_st16_i64
, { "rZ", "r" } },
2212 { INDEX_op_st32_i64
, { "rZ", "r" } },
2213 { INDEX_op_st_i64
, { "rZ", "r" } },
2215 { INDEX_op_add_i64
, { "r", "rI", "rI" } },
2216 { INDEX_op_sub_i64
, { "r", "rI", "rI" } },
2218 { INDEX_op_and_i64
, { "r", "rI", "rI" } },
2219 { INDEX_op_andc_i64
, { "r", "rI", "rI" } },
2220 { INDEX_op_eqv_i64
, { "r", "rZ", "rZ" } },
2221 { INDEX_op_nand_i64
, { "r", "rZ", "rZ" } },
2222 { INDEX_op_nor_i64
, { "r", "rZ", "rZ" } },
2223 { INDEX_op_or_i64
, { "r", "rI", "rI" } },
2224 { INDEX_op_orc_i64
, { "r", "rZ", "rZ" } },
2225 { INDEX_op_xor_i64
, { "r", "rI", "rI" } },
2227 { INDEX_op_mul_i64
, { "r", "rZ", "rZ" } },
2229 { INDEX_op_sar_i64
, { "r", "rZ", "ri" } },
2230 { INDEX_op_shl_i64
, { "r", "rZ", "ri" } },
2231 { INDEX_op_shr_i64
, { "r", "rZ", "ri" } },
2232 { INDEX_op_rotl_i64
, { "r", "rZ", "ri" } },
2233 { INDEX_op_rotr_i64
, { "r", "rZ", "ri" } },
2235 { INDEX_op_ext8s_i64
, { "r", "rZ"} },
2236 { INDEX_op_ext8u_i64
, { "r", "rZ"} },
2237 { INDEX_op_ext16s_i64
, { "r", "rZ"} },
2238 { INDEX_op_ext16u_i64
, { "r", "rZ"} },
2239 { INDEX_op_ext32s_i64
, { "r", "rZ"} },
2240 { INDEX_op_ext32u_i64
, { "r", "rZ"} },
2242 { INDEX_op_bswap16_i64
, { "r", "rZ" } },
2243 { INDEX_op_bswap32_i64
, { "r", "rZ" } },
2244 { INDEX_op_bswap64_i64
, { "r", "rZ" } },
2246 { INDEX_op_brcond_i64
, { "rI", "rI" } },
2247 { INDEX_op_setcond_i64
, { "r", "rZ", "rZ" } },
2249 { INDEX_op_qemu_ld8u
, { "r", "r" } },
2250 { INDEX_op_qemu_ld8s
, { "r", "r" } },
2251 { INDEX_op_qemu_ld16u
, { "r", "r" } },
2252 { INDEX_op_qemu_ld16s
, { "r", "r" } },
2253 { INDEX_op_qemu_ld32
, { "r", "r" } },
2254 { INDEX_op_qemu_ld32u
, { "r", "r" } },
2255 { INDEX_op_qemu_ld32s
, { "r", "r" } },
2256 { INDEX_op_qemu_ld64
, { "r", "r" } },
2258 { INDEX_op_qemu_st8
, { "SZ", "r" } },
2259 { INDEX_op_qemu_st16
, { "SZ", "r" } },
2260 { INDEX_op_qemu_st32
, { "SZ", "r" } },
2261 { INDEX_op_qemu_st64
, { "SZ", "r" } },
2266 /* Generate global QEMU prologue and epilogue code */
2267 static void tcg_target_qemu_prologue(TCGContext
*s
)
2271 /* reserve some stack space */
2272 frame_size
= TCG_STATIC_CALL_ARGS_SIZE
;
2273 frame_size
= (frame_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2274 ~(TCG_TARGET_STACK_ALIGN
- 1);
2276 /* First emit adhoc function descriptor */
2277 *(uint64_t *)(s
->code_ptr
) = (uint64_t)s
->code_ptr
+ 16; /* entry point */
2278 s
->code_ptr
+= 16; /* skip GP */
2281 tcg_out_bundle(s
, miI
,
2282 tcg_opc_m34(TCG_REG_P0
, OPC_ALLOC_M34
,
2283 TCG_REG_R34
, 32, 24, 0),
2284 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
2285 TCG_AREG0
, 0, TCG_REG_R32
),
2286 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
2287 TCG_REG_B6
, TCG_REG_R33
, 0));
2289 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2290 an ADDL in the M slot of the next bundle. */
2291 if (GUEST_BASE
!= 0) {
2292 tcg_out_bundle(s
, mlx
,
2293 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2294 tcg_opc_l2 (GUEST_BASE
),
2295 tcg_opc_x2 (TCG_REG_P0
, OPC_MOVL_X2
,
2296 TCG_GUEST_BASE_REG
, GUEST_BASE
));
2297 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
2300 tcg_out_bundle(s
, miB
,
2301 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
2302 TCG_REG_R12
, -frame_size
, TCG_REG_R12
),
2303 tcg_opc_i22(TCG_REG_P0
, OPC_MOV_I22
,
2304 TCG_REG_R32
, TCG_REG_B0
),
2305 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
, TCG_REG_B6
));
2308 tb_ret_addr
= s
->code_ptr
;
2309 tcg_out_bundle(s
, miI
,
2310 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2311 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
2312 TCG_REG_B0
, TCG_REG_R32
, 0),
2313 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
2314 TCG_REG_R12
, frame_size
, TCG_REG_R12
));
2315 tcg_out_bundle(s
, miB
,
2316 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2317 tcg_opc_i26(TCG_REG_P0
, OPC_MOV_I_I26
,
2318 TCG_REG_PFS
, TCG_REG_R34
),
2319 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_RET_SPTK_MANY_B4
,
2323 static void tcg_target_init(TCGContext
*s
)
2325 tcg_regset_set(tcg_target_available_regs
[TCG_TYPE_I32
],
2326 0xffffffffffffffffull
);
2327 tcg_regset_set(tcg_target_available_regs
[TCG_TYPE_I64
],
2328 0xffffffffffffffffull
);
2330 tcg_regset_clear(tcg_target_call_clobber_regs
);
2331 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R8
);
2332 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R9
);
2333 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R10
);
2334 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R11
);
2335 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R14
);
2336 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R15
);
2337 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R16
);
2338 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R17
);
2339 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R18
);
2340 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R19
);
2341 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R20
);
2342 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R21
);
2343 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R22
);
2344 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R23
);
2345 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R24
);
2346 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R25
);
2347 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R26
);
2348 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R27
);
2349 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R28
);
2350 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R29
);
2351 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R30
);
2352 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R31
);
2353 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R56
);
2354 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R57
);
2355 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R58
);
2356 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R59
);
2357 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R60
);
2358 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R61
);
2359 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R62
);
2360 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R63
);
2362 tcg_regset_clear(s
->reserved_regs
);
2363 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
); /* zero register */
2364 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
); /* global pointer */
2365 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
); /* internal use */
2366 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R3
); /* internal use */
2367 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R12
); /* stack pointer */
2368 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
); /* thread pointer */
2369 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R32
); /* return address */
2370 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R34
); /* PFS */
2372 /* The following 3 are not in use, are call-saved, but *not* saved
2373 by the prologue. Therefore we cannot use them without modifying
2374 the prologue. There doesn't seem to be any good reason to use
2375 these as opposed to the windowed registers. */
2376 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R4
);
2377 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R5
);
2378 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R6
);
2380 tcg_add_target_add_op_defs(ia64_op_defs
);
2381 tcg_set_frame(s
, TCG_AREG0
, offsetof(CPUArchState
, temp_buf
),
2382 CPU_TEMP_BUF_NLONGS
* sizeof(long));