target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7 #define TARGET_HAS_ICE 1
   8
   9 #define ELF_MACHINE     EM_MIPS
  10
  11 #define CPUArchState struct CPUMIPSState
  12
  13 #include "config.h"
  14 #include "qemu-common.h"
  15 #include "mips-defs.h"
  16 #include "exec/cpu-defs.h"
  17 #include "fpu/softfloat.h"
  18
  19 struct CPUMIPSState;
  20
  21 typedef struct r4k_tlb_t r4k_tlb_t;
  22 struct r4k_tlb_t {
  23     target_ulong VPN;
  24     uint32_t PageMask;
  25     uint_fast8_t ASID;
  26     uint_fast16_t G:1;
  27     uint_fast16_t C0:3;
  28     uint_fast16_t C1:3;
  29     uint_fast16_t V0:1;
  30     uint_fast16_t V1:1;
  31     uint_fast16_t D0:1;
  32     uint_fast16_t D1:1;
  33     uint_fast16_t XI0:1;
  34     uint_fast16_t XI1:1;
  35     uint_fast16_t RI0:1;
  36     uint_fast16_t RI1:1;
  37     uint_fast16_t EHINV:1;
  38     target_ulong PFN[2];
  39 };
  40
  41 #if !defined(CONFIG_USER_ONLY)
  42 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  43 struct CPUMIPSTLBContext {
  44     uint32_t nb_tlb;
  45     uint32_t tlb_in_use;
  46     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  47     void (*helper_tlbwi)(struct CPUMIPSState *env);
  48     void (*helper_tlbwr)(struct CPUMIPSState *env);
  49     void (*helper_tlbp)(struct CPUMIPSState *env);
  50     void (*helper_tlbr)(struct CPUMIPSState *env);
  51     void (*helper_tlbinv)(struct CPUMIPSState *env);
  52     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  53     union {
  54         struct {
  55             r4k_tlb_t tlb[MIPS_TLB_MAX];
  56         } r4k;
  57     } mmu;
  58 };
  59 #endif
  60
  61 typedef union fpr_t fpr_t;
  62 union fpr_t {
  63     float64  fd;   /* ieee double precision */
  64     float32  fs[2];/* ieee single precision */
  65     uint64_t d;    /* binary double fixed-point */
  66     uint32_t w[2]; /* binary single fixed-point */
  67 };
  68 /* define FP_ENDIAN_IDX to access the same location
  69  * in the fpr_t union regardless of the host endianness
  70  */
  71 #if defined(HOST_WORDS_BIGENDIAN)
  72 #  define FP_ENDIAN_IDX 1
  73 #else
  74 #  define FP_ENDIAN_IDX 0
  75 #endif
  76
  77 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  78 struct CPUMIPSFPUContext {
  79     /* Floating point registers */
  80     fpr_t fpr[32];
  81     float_status fp_status;
  82     /* fpu implementation/revision register (fir) */
  83     uint32_t fcr0;
  84 #define FCR0_UFRP 28
  85 #define FCR0_F64 22
  86 #define FCR0_L 21
  87 #define FCR0_W 20
  88 #define FCR0_3D 19
  89 #define FCR0_PS 18
  90 #define FCR0_D 17
  91 #define FCR0_S 16
  92 #define FCR0_PRID 8
  93 #define FCR0_REV 0
  94     /* fcsr */
  95     uint32_t fcr31;
  96 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  97 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  98 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  99 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 100 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 101 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 102 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 103 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 104 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 105 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 106 #define FP_INEXACT        1
 107 #define FP_UNDERFLOW      2
 108 #define FP_OVERFLOW       4
 109 #define FP_DIV0           8
 110 #define FP_INVALID        16
 111 #define FP_UNIMPLEMENTED  32
 112 };
 113
 114 #define NB_MMU_MODES 3
 115
 116 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 117 struct CPUMIPSMVPContext {
 118     int32_t CP0_MVPControl;
 119 #define CP0MVPCo_CPA    3
 120 #define CP0MVPCo_STLB   2
 121 #define CP0MVPCo_VPC    1
 122 #define CP0MVPCo_EVP    0
 123     int32_t CP0_MVPConf0;
 124 #define CP0MVPC0_M      31
 125 #define CP0MVPC0_TLBS   29
 126 #define CP0MVPC0_GS     28
 127 #define CP0MVPC0_PCP    27
 128 #define CP0MVPC0_PTLBE  16
 129 #define CP0MVPC0_TCA    15
 130 #define CP0MVPC0_PVPE   10
 131 #define CP0MVPC0_PTC    0
 132     int32_t CP0_MVPConf1;
 133 #define CP0MVPC1_CIM    31
 134 #define CP0MVPC1_CIF    30
 135 #define CP0MVPC1_PCX    20
 136 #define CP0MVPC1_PCP2   10
 137 #define CP0MVPC1_PCP1   0
 138 };
 139
 140 typedef struct mips_def_t mips_def_t;
 141
 142 #define MIPS_SHADOW_SET_MAX 16
 143 #define MIPS_TC_MAX 5
 144 #define MIPS_FPU_MAX 1
 145 #define MIPS_DSP_ACC 4
 146 #define MIPS_KSCRATCH_NUM 6
 147
 148 typedef struct TCState TCState;
 149 struct TCState {
 150     target_ulong gpr[32];
 151     target_ulong PC;
 152     target_ulong HI[MIPS_DSP_ACC];
 153     target_ulong LO[MIPS_DSP_ACC];
 154     target_ulong ACX[MIPS_DSP_ACC];
 155     target_ulong DSPControl;
 156     int32_t CP0_TCStatus;
 157 #define CP0TCSt_TCU3    31
 158 #define CP0TCSt_TCU2    30
 159 #define CP0TCSt_TCU1    29
 160 #define CP0TCSt_TCU0    28
 161 #define CP0TCSt_TMX     27
 162 #define CP0TCSt_RNST    23
 163 #define CP0TCSt_TDS     21
 164 #define CP0TCSt_DT      20
 165 #define CP0TCSt_DA      15
 166 #define CP0TCSt_A       13
 167 #define CP0TCSt_TKSU    11
 168 #define CP0TCSt_IXMT    10
 169 #define CP0TCSt_TASID   0
 170     int32_t CP0_TCBind;
 171 #define CP0TCBd_CurTC   21
 172 #define CP0TCBd_TBE     17
 173 #define CP0TCBd_CurVPE  0
 174     target_ulong CP0_TCHalt;
 175     target_ulong CP0_TCContext;
 176     target_ulong CP0_TCSchedule;
 177     target_ulong CP0_TCScheFBack;
 178     int32_t CP0_Debug_tcstatus;
 179     target_ulong CP0_UserLocal;
 180 };
 181
 182 typedef struct CPUMIPSState CPUMIPSState;
 183 struct CPUMIPSState {
 184     TCState active_tc;
 185     CPUMIPSFPUContext active_fpu;
 186
 187     uint32_t current_tc;
 188     uint32_t current_fpu;
 189
 190     uint32_t SEGBITS;
 191     uint32_t PABITS;
 192     target_ulong SEGMask;
 193     target_ulong PAMask;
 194
 195     int32_t CP0_Index;
 196     /* CP0_MVP* are per MVP registers. */
 197     int32_t CP0_Random;
 198     int32_t CP0_VPEControl;
 199 #define CP0VPECo_YSI    21
 200 #define CP0VPECo_GSI    20
 201 #define CP0VPECo_EXCPT  16
 202 #define CP0VPECo_TE     15
 203 #define CP0VPECo_TargTC 0
 204     int32_t CP0_VPEConf0;
 205 #define CP0VPEC0_M      31
 206 #define CP0VPEC0_XTC    21
 207 #define CP0VPEC0_TCS    19
 208 #define CP0VPEC0_SCS    18
 209 #define CP0VPEC0_DSC    17
 210 #define CP0VPEC0_ICS    16
 211 #define CP0VPEC0_MVP    1
 212 #define CP0VPEC0_VPA    0
 213     int32_t CP0_VPEConf1;
 214 #define CP0VPEC1_NCX    20
 215 #define CP0VPEC1_NCP2   10
 216 #define CP0VPEC1_NCP1   0
 217     target_ulong CP0_YQMask;
 218     target_ulong CP0_VPESchedule;
 219     target_ulong CP0_VPEScheFBack;
 220     int32_t CP0_VPEOpt;
 221 #define CP0VPEOpt_IWX7  15
 222 #define CP0VPEOpt_IWX6  14
 223 #define CP0VPEOpt_IWX5  13
 224 #define CP0VPEOpt_IWX4  12
 225 #define CP0VPEOpt_IWX3  11
 226 #define CP0VPEOpt_IWX2  10
 227 #define CP0VPEOpt_IWX1  9
 228 #define CP0VPEOpt_IWX0  8
 229 #define CP0VPEOpt_DWX7  7
 230 #define CP0VPEOpt_DWX6  6
 231 #define CP0VPEOpt_DWX5  5
 232 #define CP0VPEOpt_DWX4  4
 233 #define CP0VPEOpt_DWX3  3
 234 #define CP0VPEOpt_DWX2  2
 235 #define CP0VPEOpt_DWX1  1
 236 #define CP0VPEOpt_DWX0  0
 237     target_ulong CP0_EntryLo0;
 238     target_ulong CP0_EntryLo1;
 239 #if defined(TARGET_MIPS64)
 240 # define CP0EnLo_RI 63
 241 # define CP0EnLo_XI 62
 242 #else
 243 # define CP0EnLo_RI 31
 244 # define CP0EnLo_XI 30
 245 #endif
 246     target_ulong CP0_Context;
 247     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 248     int32_t CP0_PageMask;
 249     int32_t CP0_PageGrain_rw_bitmask;
 250     int32_t CP0_PageGrain;
 251 #define CP0PG_RIE 31
 252 #define CP0PG_XIE 30
 253 #define CP0PG_IEC 27
 254     int32_t CP0_Wired;
 255     int32_t CP0_SRSConf0_rw_bitmask;
 256     int32_t CP0_SRSConf0;
 257 #define CP0SRSC0_M      31
 258 #define CP0SRSC0_SRS3   20
 259 #define CP0SRSC0_SRS2   10
 260 #define CP0SRSC0_SRS1   0
 261     int32_t CP0_SRSConf1_rw_bitmask;
 262     int32_t CP0_SRSConf1;
 263 #define CP0SRSC1_M      31
 264 #define CP0SRSC1_SRS6   20
 265 #define CP0SRSC1_SRS5   10
 266 #define CP0SRSC1_SRS4   0
 267     int32_t CP0_SRSConf2_rw_bitmask;
 268     int32_t CP0_SRSConf2;
 269 #define CP0SRSC2_M      31
 270 #define CP0SRSC2_SRS9   20
 271 #define CP0SRSC2_SRS8   10
 272 #define CP0SRSC2_SRS7   0
 273     int32_t CP0_SRSConf3_rw_bitmask;
 274     int32_t CP0_SRSConf3;
 275 #define CP0SRSC3_M      31
 276 #define CP0SRSC3_SRS12  20
 277 #define CP0SRSC3_SRS11  10
 278 #define CP0SRSC3_SRS10  0
 279     int32_t CP0_SRSConf4_rw_bitmask;
 280     int32_t CP0_SRSConf4;
 281 #define CP0SRSC4_SRS15  20
 282 #define CP0SRSC4_SRS14  10
 283 #define CP0SRSC4_SRS13  0
 284     int32_t CP0_HWREna;
 285     target_ulong CP0_BadVAddr;
 286     uint32_t CP0_BadInstr;
 287     uint32_t CP0_BadInstrP;
 288     int32_t CP0_Count;
 289     target_ulong CP0_EntryHi;
 290 #define CP0EnHi_EHINV 10
 291     int32_t CP0_Compare;
 292     int32_t CP0_Status;
 293 #define CP0St_CU3   31
 294 #define CP0St_CU2   30
 295 #define CP0St_CU1   29
 296 #define CP0St_CU0   28
 297 #define CP0St_RP    27
 298 #define CP0St_FR    26
 299 #define CP0St_RE    25
 300 #define CP0St_MX    24
 301 #define CP0St_PX    23
 302 #define CP0St_BEV   22
 303 #define CP0St_TS    21
 304 #define CP0St_SR    20
 305 #define CP0St_NMI   19
 306 #define CP0St_IM    8
 307 #define CP0St_KX    7
 308 #define CP0St_SX    6
 309 #define CP0St_UX    5
 310 #define CP0St_KSU   3
 311 #define CP0St_ERL   2
 312 #define CP0St_EXL   1
 313 #define CP0St_IE    0
 314     int32_t CP0_IntCtl;
 315 #define CP0IntCtl_IPTI 29
 316 #define CP0IntCtl_IPPC1 26
 317 #define CP0IntCtl_VS 5
 318     int32_t CP0_SRSCtl;
 319 #define CP0SRSCtl_HSS 26
 320 #define CP0SRSCtl_EICSS 18
 321 #define CP0SRSCtl_ESS 12
 322 #define CP0SRSCtl_PSS 6
 323 #define CP0SRSCtl_CSS 0
 324     int32_t CP0_SRSMap;
 325 #define CP0SRSMap_SSV7 28
 326 #define CP0SRSMap_SSV6 24
 327 #define CP0SRSMap_SSV5 20
 328 #define CP0SRSMap_SSV4 16
 329 #define CP0SRSMap_SSV3 12
 330 #define CP0SRSMap_SSV2 8
 331 #define CP0SRSMap_SSV1 4
 332 #define CP0SRSMap_SSV0 0
 333     int32_t CP0_Cause;
 334 #define CP0Ca_BD   31
 335 #define CP0Ca_TI   30
 336 #define CP0Ca_CE   28
 337 #define CP0Ca_DC   27
 338 #define CP0Ca_PCI  26
 339 #define CP0Ca_IV   23
 340 #define CP0Ca_WP   22
 341 #define CP0Ca_IP    8
 342 #define CP0Ca_IP_mask 0x0000FF00
 343 #define CP0Ca_EC    2
 344     target_ulong CP0_EPC;
 345     int32_t CP0_PRid;
 346     int32_t CP0_EBase;
 347     int32_t CP0_Config0;
 348 #define CP0C0_M    31
 349 #define CP0C0_K23  28
 350 #define CP0C0_KU   25
 351 #define CP0C0_MDU  20
 352 #define CP0C0_MM   17
 353 #define CP0C0_BM   16
 354 #define CP0C0_BE   15
 355 #define CP0C0_AT   13
 356 #define CP0C0_AR   10
 357 #define CP0C0_MT   7
 358 #define CP0C0_VI   3
 359 #define CP0C0_K0   0
 360     int32_t CP0_Config1;
 361 #define CP0C1_M    31
 362 #define CP0C1_MMU  25
 363 #define CP0C1_IS   22
 364 #define CP0C1_IL   19
 365 #define CP0C1_IA   16
 366 #define CP0C1_DS   13
 367 #define CP0C1_DL   10
 368 #define CP0C1_DA   7
 369 #define CP0C1_C2   6
 370 #define CP0C1_MD   5
 371 #define CP0C1_PC   4
 372 #define CP0C1_WR   3
 373 #define CP0C1_CA   2
 374 #define CP0C1_EP   1
 375 #define CP0C1_FP   0
 376     int32_t CP0_Config2;
 377 #define CP0C2_M    31
 378 #define CP0C2_TU   28
 379 #define CP0C2_TS   24
 380 #define CP0C2_TL   20
 381 #define CP0C2_TA   16
 382 #define CP0C2_SU   12
 383 #define CP0C2_SS   8
 384 #define CP0C2_SL   4
 385 #define CP0C2_SA   0
 386     int32_t CP0_Config3;
 387 #define CP0C3_M    31
 388 #define CP0C3_BP 27
 389 #define CP0C3_BI 26
 390 #define CP0C3_ISA_ON_EXC 16
 391 #define CP0C3_ULRI 13
 392 #define CP0C3_RXI  12
 393 #define CP0C3_DSPP 10
 394 #define CP0C3_LPA  7
 395 #define CP0C3_VEIC 6
 396 #define CP0C3_VInt 5
 397 #define CP0C3_SP   4
 398 #define CP0C3_MT   2
 399 #define CP0C3_SM   1
 400 #define CP0C3_TL   0
 401     uint32_t CP0_Config4;
 402     uint32_t CP0_Config4_rw_bitmask;
 403 #define CP0C4_M    31
 404 #define CP0C4_IE   29
 405 #define CP0C4_KScrExist 16
 406     uint32_t CP0_Config5;
 407     uint32_t CP0_Config5_rw_bitmask;
 408 #define CP0C5_M          31
 409 #define CP0C5_K          30
 410 #define CP0C5_CV         29
 411 #define CP0C5_EVA        28
 412 #define CP0C5_MSAEn      27
 413 #define CP0C5_SBRI       6
 414 #define CP0C5_UFR        2
 415 #define CP0C5_NFExists   0
 416     int32_t CP0_Config6;
 417     int32_t CP0_Config7;
 418     /* XXX: Maybe make LLAddr per-TC? */
 419     target_ulong lladdr;
 420     target_ulong llval;
 421     target_ulong llnewval;
 422     target_ulong llreg;
 423     target_ulong CP0_LLAddr_rw_bitmask;
 424     int CP0_LLAddr_shift;
 425     target_ulong CP0_WatchLo[8];
 426     int32_t CP0_WatchHi[8];
 427     target_ulong CP0_XContext;
 428     int32_t CP0_Framemask;
 429     int32_t CP0_Debug;
 430 #define CP0DB_DBD  31
 431 #define CP0DB_DM   30
 432 #define CP0DB_LSNM 28
 433 #define CP0DB_Doze 27
 434 #define CP0DB_Halt 26
 435 #define CP0DB_CNT  25
 436 #define CP0DB_IBEP 24
 437 #define CP0DB_DBEP 21
 438 #define CP0DB_IEXI 20
 439 #define CP0DB_VER  15
 440 #define CP0DB_DEC  10
 441 #define CP0DB_SSt  8
 442 #define CP0DB_DINT 5
 443 #define CP0DB_DIB  4
 444 #define CP0DB_DDBS 3
 445 #define CP0DB_DDBL 2
 446 #define CP0DB_DBp  1
 447 #define CP0DB_DSS  0
 448     target_ulong CP0_DEPC;
 449     int32_t CP0_Performance0;
 450     int32_t CP0_TagLo;
 451     int32_t CP0_DataLo;
 452     int32_t CP0_TagHi;
 453     int32_t CP0_DataHi;
 454     target_ulong CP0_ErrorEPC;
 455     int32_t CP0_DESAVE;
 456     /* We waste some space so we can handle shadow registers like TCs. */
 457     TCState tcs[MIPS_SHADOW_SET_MAX];
 458     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 459     /* QEMU */
 460     int error_code;
 461 #define EXCP_TLB_NOMATCH   0x1
 462 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 463     uint32_t hflags;    /* CPU State */
 464     /* TMASK defines different execution modes */
 465 #define MIPS_HFLAG_TMASK  0x5807FF
 466 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 467     /* The KSU flags must be the lowest bits in hflags. The flag order
 468        must be the same as defined for CP0 Status. This allows to use
 469        the bits as the value of mmu_idx. */
 470 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 471 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 472 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 473 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 474 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 475 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 476 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 477 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 478 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 479     /* True if the MIPS IV COP1X instructions can be used.  This also
 480        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 481        and RSQRT.D.  */
 482 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 483 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 484 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 485 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 486 #define MIPS_HFLAG_M16_SHIFT 10
 487     /* If translation is interrupted between the branch instruction and
 488      * the delay slot, record what type of branch it is so that we can
 489      * resume translation properly.  It might be possible to reduce
 490      * this from three bits to two.  */
 491 #define MIPS_HFLAG_BMASK_BASE  0x803800
 492 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 493 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 494 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 495 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 496     /* Extra flags about the current pending branch.  */
 497 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 498 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 499 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 500 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 501 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 502 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 503 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 504     /* MIPS DSP resources access. */
 505 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 506 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 507     /* Extra flag about HWREna register. */
 508 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 509 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 510 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 511     target_ulong btarget;        /* Jump / branch target               */
 512     target_ulong bcond;          /* Branch condition (if needed)       */
 513
 514     int SYNCI_Step; /* Address step size for SYNCI */
 515     int CCRes; /* Cycle count resolution/divisor */
 516     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 517     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 518     int insn_flags; /* Supported instruction set */
 519
 520     CPU_COMMON
 521
 522     /* Fields from here on are preserved across CPU reset. */
 523     CPUMIPSMVPContext *mvp;
 524 #if !defined(CONFIG_USER_ONLY)
 525     CPUMIPSTLBContext *tlb;
 526 #endif
 527
 528     const mips_def_t *cpu_model;
 529     void *irq[8];
 530     QEMUTimer *timer; /* Internal timer */
 531 };
 532
 533 #include "cpu-qom.h"
 534
 535 #if !defined(CONFIG_USER_ONLY)
 536 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 537                         target_ulong address, int rw, int access_type);
 538 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 539                            target_ulong address, int rw, int access_type);
 540 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 541                      target_ulong address, int rw, int access_type);
 542 void r4k_helper_tlbwi(CPUMIPSState *env);
 543 void r4k_helper_tlbwr(CPUMIPSState *env);
 544 void r4k_helper_tlbp(CPUMIPSState *env);
 545 void r4k_helper_tlbr(CPUMIPSState *env);
 546 void r4k_helper_tlbinv(CPUMIPSState *env);
 547 void r4k_helper_tlbinvf(CPUMIPSState *env);
 548
 549 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 550                                 bool is_write, bool is_exec, int unused,
 551                                 unsigned size);
 552 #endif
 553
 554 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 555
 556 #define cpu_exec cpu_mips_exec
 557 #define cpu_gen_code cpu_mips_gen_code
 558 #define cpu_signal_handler cpu_mips_signal_handler
 559 #define cpu_list mips_cpu_list
 560
 561 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 562 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 563
 564 #define CPU_SAVE_VERSION 5
 565
 566 /* MMU modes definitions. We carefully match the indices with our
 567    hflags layout. */
 568 #define MMU_MODE0_SUFFIX _kernel
 569 #define MMU_MODE1_SUFFIX _super
 570 #define MMU_MODE2_SUFFIX _user
 571 #define MMU_USER_IDX 2
 572 static inline int cpu_mmu_index (CPUMIPSState *env)
 573 {
 574     return env->hflags & MIPS_HFLAG_KSU;
 575 }
 576
 577 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 578 {
 579     int32_t pending;
 580     int32_t status;
 581     int r;
 582
 583     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 584         (env->CP0_Status & (1 << CP0St_EXL)) ||
 585         (env->CP0_Status & (1 << CP0St_ERL)) ||
 586         /* Note that the TCStatus IXMT field is initialized to zero,
 587            and only MT capable cores can set it to one. So we don't
 588            need to check for MT capabilities here.  */
 589         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 590         (env->hflags & MIPS_HFLAG_DM)) {
 591         /* Interrupts are disabled */
 592         return 0;
 593     }
 594
 595     pending = env->CP0_Cause & CP0Ca_IP_mask;
 596     status = env->CP0_Status & CP0Ca_IP_mask;
 597
 598     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 599         /* A MIPS configured with a vectorizing external interrupt controller
 600            will feed a vector into the Cause pending lines. The core treats
 601            the status lines as a vector level, not as indiviual masks.  */
 602         r = pending > status;
 603     } else {
 604         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 605            treats the pending lines as individual interrupt lines, the status
 606            lines are individual masks.  */
 607         r = pending & status;
 608     }
 609     return r;
 610 }
 611
 612 #include "exec/cpu-all.h"
 613
 614 /* Memory access type :
 615  * may be needed for precise access rights control and precise exceptions.
 616  */
 617 enum {
 618     /* 1 bit to define user level / supervisor access */
 619     ACCESS_USER  = 0x00,
 620     ACCESS_SUPER = 0x01,
 621     /* 1 bit to indicate direction */
 622     ACCESS_STORE = 0x02,
 623     /* Type of instruction that generated the access */
 624     ACCESS_CODE  = 0x10, /* Code fetch access                */
 625     ACCESS_INT   = 0x20, /* Integer load/store access        */
 626     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 627 };
 628
 629 /* Exceptions */
 630 enum {
 631     EXCP_NONE          = -1,
 632     EXCP_RESET         = 0,
 633     EXCP_SRESET,
 634     EXCP_DSS,
 635     EXCP_DINT,
 636     EXCP_DDBL,
 637     EXCP_DDBS,
 638     EXCP_NMI,
 639     EXCP_MCHECK,
 640     EXCP_EXT_INTERRUPT, /* 8 */
 641     EXCP_DFWATCH,
 642     EXCP_DIB,
 643     EXCP_IWATCH,
 644     EXCP_AdEL,
 645     EXCP_AdES,
 646     EXCP_TLBF,
 647     EXCP_IBE,
 648     EXCP_DBp, /* 16 */
 649     EXCP_SYSCALL,
 650     EXCP_BREAK,
 651     EXCP_CpU,
 652     EXCP_RI,
 653     EXCP_OVERFLOW,
 654     EXCP_TRAP,
 655     EXCP_FPE,
 656     EXCP_DWATCH, /* 24 */
 657     EXCP_LTLBL,
 658     EXCP_TLBL,
 659     EXCP_TLBS,
 660     EXCP_DBE,
 661     EXCP_THREAD,
 662     EXCP_MDMX,
 663     EXCP_C2E,
 664     EXCP_CACHE, /* 32 */
 665     EXCP_DSPDIS,
 666     EXCP_TLBXI,
 667     EXCP_TLBRI,
 668
 669     EXCP_LAST = EXCP_TLBRI,
 670 };
 671 /* Dummy exception for conditional stores.  */
 672 #define EXCP_SC 0x100
 673
 674 /*
 675  * This is an interrnally generated WAKE request line.
 676  * It is driven by the CPU itself. Raised when the MT
 677  * block wants to wake a VPE from an inactive state and
 678  * cleared when VPE goes from active to inactive.
 679  */
 680 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 681
 682 int cpu_mips_exec(CPUMIPSState *s);
 683 void mips_tcg_init(void);
 684 MIPSCPU *cpu_mips_init(const char *cpu_model);
 685 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 686
 687 static inline CPUMIPSState *cpu_init(const char *cpu_model)
 688 {
 689     MIPSCPU *cpu = cpu_mips_init(cpu_model);
 690     if (cpu == NULL) {
 691         return NULL;
 692     }
 693     return &cpu->env;
 694 }
 695
 696 /* TODO QOM'ify CPU reset and remove */
 697 void cpu_state_reset(CPUMIPSState *s);
 698
 699 /* mips_timer.c */
 700 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 701 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 702 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 703 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 704 void cpu_mips_start_count(CPUMIPSState *env);
 705 void cpu_mips_stop_count(CPUMIPSState *env);
 706
 707 /* mips_int.c */
 708 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 709
 710 /* helper.c */
 711 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 712                               int mmu_idx);
 713 #if !defined(CONFIG_USER_ONLY)
 714 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 715 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 716                                                int rw);
 717 #endif
 718 target_ulong exception_resume_pc (CPUMIPSState *env);
 719
 720 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 721                                         target_ulong *cs_base, int *flags)
 722 {
 723     *pc = env->active_tc.PC;
 724     *cs_base = 0;
 725     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 726                             MIPS_HFLAG_HWRENA_ULR);
 727 }
 728
 729 static inline int mips_vpe_active(CPUMIPSState *env)
 730 {
 731     int active = 1;
 732
 733     /* Check that the VPE is enabled.  */
 734     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 735         active = 0;
 736     }
 737     /* Check that the VPE is activated.  */
 738     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 739         active = 0;
 740     }
 741
 742     /* Now verify that there are active thread contexts in the VPE.
 743
 744        This assumes the CPU model will internally reschedule threads
 745        if the active one goes to sleep. If there are no threads available
 746        the active one will be in a sleeping state, and we can turn off
 747        the entire VPE.  */
 748     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 749         /* TC is not activated.  */
 750         active = 0;
 751     }
 752     if (env->active_tc.CP0_TCHalt & 1) {
 753         /* TC is in halt state.  */
 754         active = 0;
 755     }
 756
 757     return active;
 758 }
 759
 760 #include "exec/exec-all.h"
 761
 762 static inline void compute_hflags(CPUMIPSState *env)
 763 {
 764     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 765                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 766                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 767                      MIPS_HFLAG_SBRI);
 768     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 769         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 770         !(env->hflags & MIPS_HFLAG_DM)) {
 771         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 772     }
 773 #if defined(TARGET_MIPS64)
 774     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 775         (env->CP0_Status & (1 << CP0St_PX)) ||
 776         (env->CP0_Status & (1 << CP0St_UX))) {
 777         env->hflags |= MIPS_HFLAG_64;
 778     }
 779
 780     if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 781         !(env->CP0_Status & (1 << CP0St_UX))) {
 782         env->hflags |= MIPS_HFLAG_AWRAP;
 783     } else if (env->insn_flags & ISA_MIPS32R6) {
 784         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 785         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 786              !(env->CP0_Status & (1 << CP0St_SX))) ||
 787             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 788              !(env->CP0_Status & (1 << CP0St_KX)))) {
 789             env->hflags |= MIPS_HFLAG_AWRAP;
 790         }
 791     }
 792 #endif
 793     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 794         !(env->hflags & MIPS_HFLAG_KSU)) {
 795         env->hflags |= MIPS_HFLAG_CP0;
 796     }
 797     if (env->CP0_Status & (1 << CP0St_CU1)) {
 798         env->hflags |= MIPS_HFLAG_FPU;
 799     }
 800     if (env->CP0_Status & (1 << CP0St_FR)) {
 801         env->hflags |= MIPS_HFLAG_F64;
 802     }
 803     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 804         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 805         env->hflags |= MIPS_HFLAG_SBRI;
 806     }
 807     if (env->insn_flags & ASE_DSPR2) {
 808         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 809            so enable to access DSPR2 resources. */
 810         if (env->CP0_Status & (1 << CP0St_MX)) {
 811             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 812         }
 813
 814     } else if (env->insn_flags & ASE_DSP) {
 815         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 816            so enable to access DSP resources. */
 817         if (env->CP0_Status & (1 << CP0St_MX)) {
 818             env->hflags |= MIPS_HFLAG_DSP;
 819         }
 820
 821     }
 822     if (env->insn_flags & ISA_MIPS32R2) {
 823         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 824             env->hflags |= MIPS_HFLAG_COP1X;
 825         }
 826     } else if (env->insn_flags & ISA_MIPS32) {
 827         if (env->hflags & MIPS_HFLAG_64) {
 828             env->hflags |= MIPS_HFLAG_COP1X;
 829         }
 830     } else if (env->insn_flags & ISA_MIPS4) {
 831         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 832            and disable the MIPS IV extensions to the MIPS III ISA.
 833            Some other MIPS IV CPUs ignore the bit, so the check here
 834            would be too restrictive for them.  */
 835         if (env->CP0_Status & (1U << CP0St_CU3)) {
 836             env->hflags |= MIPS_HFLAG_COP1X;
 837         }
 838     }
 839 }
 840
 841 #endif /* !defined (__MIPS_CPU_H__) */