target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "dyngen-exec.h"
  30 #include "helper.h"
  31 #include "host-utils.h"
  32
  33 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
  34                                 uintptr_t retaddr);
  35
  36 #define ALIGNED_ONLY
  37 #define MMUSUFFIX _mmu
  38
  39 #define SHIFT 0
  40 #include "softmmu_template.h"
  41
  42 #define SHIFT 1
  43 #include "softmmu_template.h"
  44
  45 #define SHIFT 2
  46 #include "softmmu_template.h"
  47
  48 #define SHIFT 3
  49 #include "softmmu_template.h"
  50
  51 static void do_restore_state(uintptr_t pc)
  52 {
  53     TranslationBlock *tb;
  54
  55     tb = tb_find_pc(pc);
  56     if (tb) {
  57         cpu_restore_state(tb, env, pc);
  58     }
  59 }
  60
  61 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
  62                                 uintptr_t retaddr)
  63 {
  64     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  65             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  66         do_restore_state(retaddr);
  67         HELPER(exception_cause_vaddr)(
  68                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  69     }
  70 }
  71
  72 void tlb_fill(CPUXtensaState *env1, target_ulong vaddr, int is_write, int mmu_idx,
  73               uintptr_t retaddr)
  74 {
  75     CPUXtensaState *saved_env = env;
  76
  77     env = env1;
  78     {
  79         uint32_t paddr;
  80         uint32_t page_size;
  81         unsigned access;
  82         int ret = xtensa_get_physical_addr(env, vaddr, is_write, mmu_idx,
  83                 &paddr, &page_size, &access);
  84
  85         qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  86                 vaddr, is_write, mmu_idx, paddr, ret);
  87
  88         if (ret == 0) {
  89             tlb_set_page(env,
  90                     vaddr & TARGET_PAGE_MASK,
  91                     paddr & TARGET_PAGE_MASK,
  92                     access, mmu_idx, page_size);
  93         } else {
  94             do_restore_state(retaddr);
  95             HELPER(exception_cause_vaddr)(env->pc, ret, vaddr);
  96         }
  97     }
  98     env = saved_env;
  99 }
 100
 101 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
 102 {
 103     uint32_t paddr;
 104     uint32_t page_size;
 105     unsigned access;
 106     int ret = xtensa_get_physical_addr(env, vaddr, 2, 0,
 107             &paddr, &page_size, &access);
 108     if (ret == 0) {
 109         tb_invalidate_phys_addr(paddr);
 110     }
 111 }
 112
 113 void HELPER(exception)(uint32_t excp)
 114 {
 115     env->exception_index = excp;
 116     cpu_loop_exit(env);
 117 }
 118
 119 void HELPER(exception_cause)(uint32_t pc, uint32_t cause)
 120 {
 121     uint32_t vector;
 122
 123     env->pc = pc;
 124     if (env->sregs[PS] & PS_EXCM) {
 125         if (env->config->ndepc) {
 126             env->sregs[DEPC] = pc;
 127         } else {
 128             env->sregs[EPC1] = pc;
 129         }
 130         vector = EXC_DOUBLE;
 131     } else {
 132         env->sregs[EPC1] = pc;
 133         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 134     }
 135
 136     env->sregs[EXCCAUSE] = cause;
 137     env->sregs[PS] |= PS_EXCM;
 138
 139     HELPER(exception)(vector);
 140 }
 141
 142 void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
 143 {
 144     env->sregs[EXCVADDR] = vaddr;
 145     HELPER(exception_cause)(pc, cause);
 146 }
 147
 148 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause)
 149 {
 150     if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) {
 151         env = new_env;
 152         HELPER(debug_exception)(env->pc, cause);
 153     }
 154 }
 155
 156 void HELPER(debug_exception)(uint32_t pc, uint32_t cause)
 157 {
 158     unsigned level = env->config->debug_level;
 159
 160     env->pc = pc;
 161     env->sregs[DEBUGCAUSE] = cause;
 162     env->sregs[EPC1 + level - 1] = pc;
 163     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 164     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 165         (level << PS_INTLEVEL_SHIFT);
 166     HELPER(exception)(EXC_DEBUG);
 167 }
 168
 169 uint32_t HELPER(nsa)(uint32_t v)
 170 {
 171     if (v & 0x80000000) {
 172         v = ~v;
 173     }
 174     return v ? clz32(v) - 1 : 31;
 175 }
 176
 177 uint32_t HELPER(nsau)(uint32_t v)
 178 {
 179     return v ? clz32(v) : 32;
 180 }
 181
 182 static void copy_window_from_phys(CPUXtensaState *env,
 183         uint32_t window, uint32_t phys, uint32_t n)
 184 {
 185     assert(phys < env->config->nareg);
 186     if (phys + n <= env->config->nareg) {
 187         memcpy(env->regs + window, env->phys_regs + phys,
 188                 n * sizeof(uint32_t));
 189     } else {
 190         uint32_t n1 = env->config->nareg - phys;
 191         memcpy(env->regs + window, env->phys_regs + phys,
 192                 n1 * sizeof(uint32_t));
 193         memcpy(env->regs + window + n1, env->phys_regs,
 194                 (n - n1) * sizeof(uint32_t));
 195     }
 196 }
 197
 198 static void copy_phys_from_window(CPUXtensaState *env,
 199         uint32_t phys, uint32_t window, uint32_t n)
 200 {
 201     assert(phys < env->config->nareg);
 202     if (phys + n <= env->config->nareg) {
 203         memcpy(env->phys_regs + phys, env->regs + window,
 204                 n * sizeof(uint32_t));
 205     } else {
 206         uint32_t n1 = env->config->nareg - phys;
 207         memcpy(env->phys_regs + phys, env->regs + window,
 208                 n1 * sizeof(uint32_t));
 209         memcpy(env->phys_regs, env->regs + window + n1,
 210                 (n - n1) * sizeof(uint32_t));
 211     }
 212 }
 213
 214
 215 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 216 {
 217     return a & (env->config->nareg / 4 - 1);
 218 }
 219
 220 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 221 {
 222     return 1 << windowbase_bound(a, env);
 223 }
 224
 225 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 226 {
 227     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 228 }
 229
 230 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 231 {
 232     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 233 }
 234
 235 static void rotate_window_abs(uint32_t position)
 236 {
 237     xtensa_sync_phys_from_window(env);
 238     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 239     xtensa_sync_window_from_phys(env);
 240 }
 241
 242 static void rotate_window(uint32_t delta)
 243 {
 244     rotate_window_abs(env->sregs[WINDOW_BASE] + delta);
 245 }
 246
 247 void HELPER(wsr_windowbase)(uint32_t v)
 248 {
 249     rotate_window_abs(v);
 250 }
 251
 252 void HELPER(entry)(uint32_t pc, uint32_t s, uint32_t imm)
 253 {
 254     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 255     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 256         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 257                 pc, env->sregs[PS]);
 258         HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
 259     } else {
 260         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 261         rotate_window(callinc);
 262         env->sregs[WINDOW_START] |=
 263             windowstart_bit(env->sregs[WINDOW_BASE], env);
 264     }
 265 }
 266
 267 void HELPER(window_check)(uint32_t pc, uint32_t w)
 268 {
 269     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 270     uint32_t windowstart = env->sregs[WINDOW_START];
 271     uint32_t m, n;
 272
 273     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 274         return;
 275     }
 276
 277     for (n = 1; ; ++n) {
 278         if (n > w) {
 279             return;
 280         }
 281         if (windowstart & windowstart_bit(windowbase + n, env)) {
 282             break;
 283         }
 284     }
 285
 286     m = windowbase_bound(windowbase + n, env);
 287     rotate_window(n);
 288     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 289         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 290     env->sregs[EPC1] = env->pc = pc;
 291
 292     if (windowstart & windowstart_bit(m + 1, env)) {
 293         HELPER(exception)(EXC_WINDOW_OVERFLOW4);
 294     } else if (windowstart & windowstart_bit(m + 2, env)) {
 295         HELPER(exception)(EXC_WINDOW_OVERFLOW8);
 296     } else {
 297         HELPER(exception)(EXC_WINDOW_OVERFLOW12);
 298     }
 299 }
 300
 301 uint32_t HELPER(retw)(uint32_t pc)
 302 {
 303     int n = (env->regs[0] >> 30) & 0x3;
 304     int m = 0;
 305     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 306     uint32_t windowstart = env->sregs[WINDOW_START];
 307     uint32_t ret_pc = 0;
 308
 309     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 310         m = 1;
 311     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 312         m = 2;
 313     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 314         m = 3;
 315     }
 316
 317     if (n == 0 || (m != 0 && m != n) ||
 318             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 319         qemu_log("Illegal retw instruction(pc = %08x), "
 320                 "PS = %08x, m = %d, n = %d\n",
 321                 pc, env->sregs[PS], m, n);
 322         HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
 323     } else {
 324         int owb = windowbase;
 325
 326         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 327
 328         rotate_window(-n);
 329         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 330             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 331         } else {
 332             /* window underflow */
 333             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 334                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 335             env->sregs[EPC1] = env->pc = pc;
 336
 337             if (n == 1) {
 338                 HELPER(exception)(EXC_WINDOW_UNDERFLOW4);
 339             } else if (n == 2) {
 340                 HELPER(exception)(EXC_WINDOW_UNDERFLOW8);
 341             } else if (n == 3) {
 342                 HELPER(exception)(EXC_WINDOW_UNDERFLOW12);
 343             }
 344         }
 345     }
 346     return ret_pc;
 347 }
 348
 349 void HELPER(rotw)(uint32_t imm4)
 350 {
 351     rotate_window(imm4);
 352 }
 353
 354 void HELPER(restore_owb)(void)
 355 {
 356     rotate_window_abs((env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 357 }
 358
 359 void HELPER(movsp)(uint32_t pc)
 360 {
 361     if ((env->sregs[WINDOW_START] &
 362             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 363              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 364              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 365         HELPER(exception_cause)(pc, ALLOCA_CAUSE);
 366     }
 367 }
 368
 369 void HELPER(wsr_lbeg)(uint32_t v)
 370 {
 371     if (env->sregs[LBEG] != v) {
 372         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 373         env->sregs[LBEG] = v;
 374     }
 375 }
 376
 377 void HELPER(wsr_lend)(uint32_t v)
 378 {
 379     if (env->sregs[LEND] != v) {
 380         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 381         env->sregs[LEND] = v;
 382         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 383     }
 384 }
 385
 386 void HELPER(dump_state)(void)
 387 {
 388     cpu_dump_state(env, stderr, fprintf, 0);
 389 }
 390
 391 void HELPER(waiti)(uint32_t pc, uint32_t intlevel)
 392 {
 393     env->pc = pc;
 394     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 395         (intlevel << PS_INTLEVEL_SHIFT);
 396     check_interrupts(env);
 397     if (env->pending_irq_level) {
 398         cpu_loop_exit(env);
 399         return;
 400     }
 401
 402     env->halt_clock = qemu_get_clock_ns(vm_clock);
 403     env->halted = 1;
 404     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 405         xtensa_rearm_ccompare_timer(env);
 406     }
 407     HELPER(exception)(EXCP_HLT);
 408 }
 409
 410 void HELPER(timer_irq)(uint32_t id, uint32_t active)
 411 {
 412     xtensa_timer_irq(env, id, active);
 413 }
 414
 415 void HELPER(advance_ccount)(uint32_t d)
 416 {
 417     xtensa_advance_ccount(env, d);
 418 }
 419
 420 void HELPER(check_interrupts)(CPUXtensaState *env)
 421 {
 422     check_interrupts(env);
 423 }
 424
 425 void HELPER(wsr_rasid)(uint32_t v)
 426 {
 427     v = (v & 0xffffff00) | 0x1;
 428     if (v != env->sregs[RASID]) {
 429         env->sregs[RASID] = v;
 430         tlb_flush(env, 1);
 431     }
 432 }
 433
 434 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 435 {
 436     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 437
 438     switch (way) {
 439     case 4:
 440         return (tlbcfg >> 16) & 0x3;
 441
 442     case 5:
 443         return (tlbcfg >> 20) & 0x1;
 444
 445     case 6:
 446         return (tlbcfg >> 24) & 0x1;
 447
 448     default:
 449         return 0;
 450     }
 451 }
 452
 453 /*!
 454  * Get bit mask for the virtual address bits translated by the TLB way
 455  */
 456 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 457 {
 458     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 459         bool varway56 = dtlb ?
 460             env->config->dtlb.varway56 :
 461             env->config->itlb.varway56;
 462
 463         switch (way) {
 464         case 4:
 465             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 466
 467         case 5:
 468             if (varway56) {
 469                 return 0xf8000000 << get_page_size(env, dtlb, way);
 470             } else {
 471                 return 0xf8000000;
 472             }
 473
 474         case 6:
 475             if (varway56) {
 476                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 477             } else {
 478                 return 0xf0000000;
 479             }
 480
 481         default:
 482             return 0xfffff000;
 483         }
 484     } else {
 485         return REGION_PAGE_MASK;
 486     }
 487 }
 488
 489 /*!
 490  * Get bit mask for the 'VPN without index' field.
 491  * See ISA, 4.6.5.6, data format for RxTLB0
 492  */
 493 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 494 {
 495     if (way < 4) {
 496         bool is32 = (dtlb ?
 497                 env->config->dtlb.nrefillentries :
 498                 env->config->itlb.nrefillentries) == 32;
 499         return is32 ? 0xffff8000 : 0xffffc000;
 500     } else if (way == 4) {
 501         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 502     } else if (way <= 6) {
 503         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 504         bool varway56 = dtlb ?
 505             env->config->dtlb.varway56 :
 506             env->config->itlb.varway56;
 507
 508         if (varway56) {
 509             return mask << (way == 5 ? 2 : 3);
 510         } else {
 511             return mask << 1;
 512         }
 513     } else {
 514         return 0xfffff000;
 515     }
 516 }
 517
 518 /*!
 519  * Split virtual address into VPN (with index) and entry index
 520  * for the given TLB way
 521  */
 522 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 523         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 524 {
 525     bool varway56 = dtlb ?
 526         env->config->dtlb.varway56 :
 527         env->config->itlb.varway56;
 528
 529     if (!dtlb) {
 530         wi &= 7;
 531     }
 532
 533     if (wi < 4) {
 534         bool is32 = (dtlb ?
 535                 env->config->dtlb.nrefillentries :
 536                 env->config->itlb.nrefillentries) == 32;
 537         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 538     } else {
 539         switch (wi) {
 540         case 4:
 541             {
 542                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 543                 *ei = (v >> eibase) & 0x3;
 544             }
 545             break;
 546
 547         case 5:
 548             if (varway56) {
 549                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 550                 *ei = (v >> eibase) & 0x3;
 551             } else {
 552                 *ei = (v >> 27) & 0x1;
 553             }
 554             break;
 555
 556         case 6:
 557             if (varway56) {
 558                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 559                 *ei = (v >> eibase) & 0x7;
 560             } else {
 561                 *ei = (v >> 28) & 0x1;
 562             }
 563             break;
 564
 565         default:
 566             *ei = 0;
 567             break;
 568         }
 569     }
 570     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 571 }
 572
 573 /*!
 574  * Split TLB address into TLB way, entry index and VPN (with index).
 575  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 576  */
 577 static void split_tlb_entry_spec(uint32_t v, bool dtlb,
 578         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 579 {
 580     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 581         *wi = v & (dtlb ? 0xf : 0x7);
 582         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 583     } else {
 584         *vpn = v & REGION_PAGE_MASK;
 585         *wi = 0;
 586         *ei = (v >> 29) & 0x7;
 587     }
 588 }
 589
 590 static xtensa_tlb_entry *get_tlb_entry(uint32_t v, bool dtlb, uint32_t *pwi)
 591 {
 592     uint32_t vpn;
 593     uint32_t wi;
 594     uint32_t ei;
 595
 596     split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
 597     if (pwi) {
 598         *pwi = wi;
 599     }
 600     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 601 }
 602
 603 uint32_t HELPER(rtlb0)(uint32_t v, uint32_t dtlb)
 604 {
 605     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 606         uint32_t wi;
 607         const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
 608         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 609     } else {
 610         return v & REGION_PAGE_MASK;
 611     }
 612 }
 613
 614 uint32_t HELPER(rtlb1)(uint32_t v, uint32_t dtlb)
 615 {
 616     const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, NULL);
 617     return entry->paddr | entry->attr;
 618 }
 619
 620 void HELPER(itlb)(uint32_t v, uint32_t dtlb)
 621 {
 622     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 623         uint32_t wi;
 624         xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
 625         if (entry->variable && entry->asid) {
 626             tlb_flush_page(env, entry->vaddr);
 627             entry->asid = 0;
 628         }
 629     }
 630 }
 631
 632 uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
 633 {
 634     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 635         uint32_t wi;
 636         uint32_t ei;
 637         uint8_t ring;
 638         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 639
 640         switch (res) {
 641         case 0:
 642             if (ring >= xtensa_get_ring(env)) {
 643                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 644             }
 645             break;
 646
 647         case INST_TLB_MULTI_HIT_CAUSE:
 648         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 649             HELPER(exception_cause_vaddr)(env->pc, res, v);
 650             break;
 651         }
 652         return 0;
 653     } else {
 654         return (v & REGION_PAGE_MASK) | 0x1;
 655     }
 656 }
 657
 658 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 659         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 660 {
 661     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 662
 663     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 664         if (entry->variable) {
 665             if (entry->asid) {
 666                 tlb_flush_page(env, entry->vaddr);
 667             }
 668             entry->vaddr = vpn;
 669             entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 670             entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 671             entry->attr = pte & 0xf;
 672         } else {
 673             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 674                     __func__, dtlb, wi, ei);
 675         }
 676     } else {
 677         tlb_flush_page(env, entry->vaddr);
 678         if (xtensa_option_enabled(env->config,
 679                     XTENSA_OPTION_REGION_TRANSLATION)) {
 680             entry->paddr = pte & REGION_PAGE_MASK;
 681         }
 682         entry->attr = pte & 0xf;
 683     }
 684 }
 685
 686 void HELPER(wtlb)(uint32_t p, uint32_t v, uint32_t dtlb)
 687 {
 688     uint32_t vpn;
 689     uint32_t wi;
 690     uint32_t ei;
 691     split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
 692     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 693 }
 694
 695
 696 void HELPER(wsr_ibreakenable)(uint32_t v)
 697 {
 698     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 699     unsigned i;
 700
 701     for (i = 0; i < env->config->nibreak; ++i) {
 702         if (change & (1 << i)) {
 703             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 704         }
 705     }
 706     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 707 }
 708
 709 void HELPER(wsr_ibreaka)(uint32_t i, uint32_t v)
 710 {
 711     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 712         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 713         tb_invalidate_virtual_addr(env, v);
 714     }
 715     env->sregs[IBREAKA + i] = v;
 716 }
 717
 718 static void set_dbreak(unsigned i, uint32_t dbreaka, uint32_t dbreakc)
 719 {
 720     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 721     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 722
 723     if (env->cpu_watchpoint[i]) {
 724         cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 725     }
 726     if (dbreakc & DBREAKC_SB) {
 727         flags |= BP_MEM_WRITE;
 728     }
 729     if (dbreakc & DBREAKC_LB) {
 730         flags |= BP_MEM_READ;
 731     }
 732     /* contiguous mask after inversion is one less than some power of 2 */
 733     if ((~mask + 1) & ~mask) {
 734         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 735         /* cut mask after the first zero bit */
 736         mask = 0xffffffff << (32 - clo32(mask));
 737     }
 738     if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
 739             flags, &env->cpu_watchpoint[i])) {
 740         env->cpu_watchpoint[i] = NULL;
 741         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 742                 dbreaka & mask, ~mask + 1);
 743     }
 744 }
 745
 746 void HELPER(wsr_dbreaka)(uint32_t i, uint32_t v)
 747 {
 748     uint32_t dbreakc = env->sregs[DBREAKC + i];
 749
 750     if ((dbreakc & DBREAKC_SB_LB) &&
 751             env->sregs[DBREAKA + i] != v) {
 752         set_dbreak(i, v, dbreakc);
 753     }
 754     env->sregs[DBREAKA + i] = v;
 755 }
 756
 757 void HELPER(wsr_dbreakc)(uint32_t i, uint32_t v)
 758 {
 759     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 760         if (v & DBREAKC_SB_LB) {
 761             set_dbreak(i, env->sregs[DBREAKA + i], v);
 762         } else {
 763             if (env->cpu_watchpoint[i]) {
 764                 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 765                 env->cpu_watchpoint[i] = NULL;
 766             }
 767         }
 768     }
 769     env->sregs[DBREAKC + i] = v;
 770 }