cpu-common.h

   1 #ifndef CPU_COMMON_H
   2 #define CPU_COMMON_H 1
   3
   4 /* CPU interfaces that are target indpendent.  */
   5
   6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
   7 #define WORDS_ALIGNED
   8 #endif
   9
  10 #ifdef TARGET_PHYS_ADDR_BITS
  11 #include "targphys.h"
  12 #endif
  13
  14 #ifndef NEED_CPU_H
  15 #include "poison.h"
  16 #endif
  17
  18 #include "bswap.h"
  19 #include "qemu-queue.h"
  20
  21 #if !defined(CONFIG_USER_ONLY)
  22
  23 enum device_endian {
  24     DEVICE_NATIVE_ENDIAN,
  25     DEVICE_BIG_ENDIAN,
  26     DEVICE_LITTLE_ENDIAN,
  27 };
  28
  29 /* address in the RAM (different from a physical address) */
  30 typedef unsigned long ram_addr_t;
  31
  32 /* memory API */
  33
  34 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
  35 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
  36
  37 void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
  38                                          ram_addr_t size,
  39                                          ram_addr_t phys_offset,
  40                                          ram_addr_t region_offset);
  41 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
  42                                                 ram_addr_t size,
  43                                                 ram_addr_t phys_offset)
  44 {
  45     cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
  46 }
  47
  48 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
  49 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
  50                         ram_addr_t size, void *host);
  51 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
  52 void qemu_ram_unmap(ram_addr_t addr);
  53 void qemu_ram_free(ram_addr_t addr);
  54 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  55 /* This should only be used for ram local to a device.  */
  56 void *qemu_get_ram_ptr(ram_addr_t addr);
  57 /* Same but slower, to use for migration, where the order of
  58  * RAMBlocks must not change. */
  59 void *qemu_safe_ram_ptr(ram_addr_t addr);
  60 /* This should not be used by devices.  */
  61 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  62 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
  63
  64 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
  65                            CPUWriteMemoryFunc * const *mem_write,
  66                            void *opaque, enum device_endian endian);
  67 void cpu_unregister_io_memory(int table_address);
  68
  69 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
  70                             int len, int is_write);
  71 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  72                                             void *buf, int len)
  73 {
  74     cpu_physical_memory_rw(addr, buf, len, 0);
  75 }
  76 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  77                                              const void *buf, int len)
  78 {
  79     cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  80 }
  81 void *cpu_physical_memory_map(target_phys_addr_t addr,
  82                               target_phys_addr_t *plen,
  83                               int is_write);
  84 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
  85                                int is_write, target_phys_addr_t access_len);
  86 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
  87 void cpu_unregister_map_client(void *cookie);
  88
  89 struct CPUPhysMemoryClient;
  90 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
  91 struct CPUPhysMemoryClient {
  92     void (*set_memory)(struct CPUPhysMemoryClient *client,
  93                        target_phys_addr_t start_addr,
  94                        ram_addr_t size,
  95                        ram_addr_t phys_offset);
  96     int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
  97                              target_phys_addr_t start_addr,
  98                              target_phys_addr_t end_addr);
  99     int (*migration_log)(struct CPUPhysMemoryClient *client,
 100                          int enable);
 101     int (*log_start)(struct CPUPhysMemoryClient *client,
 102                      target_phys_addr_t phys_addr, ram_addr_t size);
 103     int (*log_stop)(struct CPUPhysMemoryClient *client,
 104                     target_phys_addr_t phys_addr, ram_addr_t size);
 105     QLIST_ENTRY(CPUPhysMemoryClient) list;
 106 };
 107
 108 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
 109 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
 110
 111 /* Coalesced MMIO regions are areas where write operations can be reordered.
 112  * This usually implies that write operations are side-effect free.  This allows
 113  * batching which can make a major impact on performance when using
 114  * virtualization.
 115  */
 116 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 117
 118 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 119
 120 void qemu_flush_coalesced_mmio_buffer(void);
 121
 122 uint32_t ldub_phys(target_phys_addr_t addr);
 123 uint32_t lduw_phys(target_phys_addr_t addr);
 124 uint32_t ldl_phys(target_phys_addr_t addr);
 125 uint64_t ldq_phys(target_phys_addr_t addr);
 126 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 127 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 128 void stb_phys(target_phys_addr_t addr, uint32_t val);
 129 void stw_phys(target_phys_addr_t addr, uint32_t val);
 130 void stl_phys(target_phys_addr_t addr, uint32_t val);
 131 void stq_phys(target_phys_addr_t addr, uint64_t val);
 132
 133 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 134                                    const uint8_t *buf, int len);
 135
 136 #define IO_MEM_SHIFT       3
 137
 138 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 139 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 140 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 141 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
 142
 143 /* Acts like a ROM when read and like a device when written.  */
 144 #define IO_MEM_ROMD        (1)
 145 #define IO_MEM_SUBPAGE     (2)
 146
 147 #endif
 148
 149 #endif /* !CPU_COMMON_H */