4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
22 #include "qemu-timer.h"
23 #include "host-utils.h"
28 /* APIC Local Vector Table */
29 #define APIC_LVT_TIMER 0
30 #define APIC_LVT_THERMAL 1
31 #define APIC_LVT_PERFORM 2
32 #define APIC_LVT_LINT0 3
33 #define APIC_LVT_LINT1 4
34 #define APIC_LVT_ERROR 5
37 /* APIC delivery modes */
38 #define APIC_DM_FIXED 0
39 #define APIC_DM_LOWPRI 1
42 #define APIC_DM_INIT 5
43 #define APIC_DM_SIPI 6
44 #define APIC_DM_EXTINT 7
46 /* APIC destination mode */
47 #define APIC_DESTMODE_FLAT 0xf
48 #define APIC_DESTMODE_CLUSTER 1
50 #define APIC_TRIGGER_EDGE 0
51 #define APIC_TRIGGER_LEVEL 1
53 #define APIC_LVT_TIMER_PERIODIC (1<<17)
54 #define APIC_LVT_MASKED (1<<16)
55 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
56 #define APIC_LVT_REMOTE_IRR (1<<14)
57 #define APIC_INPUT_POLARITY (1<<13)
58 #define APIC_SEND_PENDING (1<<12)
60 #define ESR_ILLEGAL_ADDRESS (1 << 7)
62 #define APIC_SV_DIRECTED_IO (1<<12)
63 #define APIC_SV_ENABLE (1<<8)
66 #define MAX_APIC_WORDS 8
68 /* Intel APIC constants: from include/asm/msidef.h */
69 #define MSI_DATA_VECTOR_SHIFT 0
70 #define MSI_DATA_VECTOR_MASK 0x000000ff
71 #define MSI_DATA_DELIVERY_MODE_SHIFT 8
72 #define MSI_DATA_TRIGGER_SHIFT 15
73 #define MSI_DATA_LEVEL_SHIFT 14
74 #define MSI_ADDR_DEST_MODE_SHIFT 2
75 #define MSI_ADDR_DEST_ID_SHIFT 12
76 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0
78 #define MSI_ADDR_SIZE 0x100000
80 typedef struct APICState APICState
;
84 MemoryRegion io_memory
;
90 uint32_t spurious_vec
;
93 uint32_t isr
[8]; /* in service register */
94 uint32_t tmr
[8]; /* trigger mode register */
95 uint32_t irr
[8]; /* interrupt request register */
96 uint32_t lvt
[APIC_LVT_NB
];
97 uint32_t esr
; /* error register */
100 uint32_t divide_conf
;
102 uint32_t initial_count
;
103 int64_t initial_count_load_time
, next_time
;
110 static APICState
*local_apics
[MAX_APICS
+ 1];
111 static int apic_irq_delivered
;
113 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
);
114 static void apic_update_irq(APICState
*s
);
115 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
116 uint8_t dest
, uint8_t dest_mode
);
118 /* Find first bit starting from msb */
119 static int fls_bit(uint32_t value
)
121 return 31 - clz32(value
);
124 /* Find first bit starting from lsb */
125 static int ffs_bit(uint32_t value
)
130 static inline void set_bit(uint32_t *tab
, int index
)
134 mask
= 1 << (index
& 0x1f);
138 static inline void reset_bit(uint32_t *tab
, int index
)
142 mask
= 1 << (index
& 0x1f);
146 static inline int get_bit(uint32_t *tab
, int index
)
150 mask
= 1 << (index
& 0x1f);
151 return !!(tab
[i
] & mask
);
154 static void apic_local_deliver(APICState
*s
, int vector
)
156 uint32_t lvt
= s
->lvt
[vector
];
159 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
161 if (lvt
& APIC_LVT_MASKED
)
164 switch ((lvt
>> 8) & 7) {
166 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SMI
);
170 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_NMI
);
174 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
178 trigger_mode
= APIC_TRIGGER_EDGE
;
179 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
180 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
181 trigger_mode
= APIC_TRIGGER_LEVEL
;
182 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
186 void apic_deliver_pic_intr(DeviceState
*d
, int level
)
188 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
191 apic_local_deliver(s
, APIC_LVT_LINT0
);
193 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
195 switch ((lvt
>> 8) & 7) {
197 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
199 reset_bit(s
->irr
, lvt
& 0xff);
202 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
208 #define foreach_apic(apic, deliver_bitmask, code) \
210 int __i, __j, __mask;\
211 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
212 __mask = deliver_bitmask[__i];\
214 for(__j = 0; __j < 32; __j++) {\
215 if (__mask & (1 << __j)) {\
216 apic = local_apics[__i * 32 + __j];\
226 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
227 uint8_t delivery_mode
,
228 uint8_t vector_num
, uint8_t polarity
,
229 uint8_t trigger_mode
)
231 APICState
*apic_iter
;
233 switch (delivery_mode
) {
235 /* XXX: search for focus processor, arbitration */
239 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
240 if (deliver_bitmask
[i
]) {
241 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
246 apic_iter
= local_apics
[d
];
248 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
258 foreach_apic(apic_iter
, deliver_bitmask
,
259 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_SMI
) );
263 foreach_apic(apic_iter
, deliver_bitmask
,
264 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_NMI
) );
268 /* normal INIT IPI sent to processors */
269 foreach_apic(apic_iter
, deliver_bitmask
,
270 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_INIT
) );
274 /* handled in I/O APIC code */
281 foreach_apic(apic_iter
, deliver_bitmask
,
282 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
285 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
,
286 uint8_t delivery_mode
, uint8_t vector_num
,
287 uint8_t polarity
, uint8_t trigger_mode
)
289 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
291 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
292 polarity
, trigger_mode
);
294 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
295 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
299 void cpu_set_apic_base(DeviceState
*d
, uint64_t val
)
301 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
303 trace_cpu_set_apic_base(val
);
307 if (kvm_enabled() && kvm_irqchip_in_kernel())
310 s
->apicbase
= (val
& 0xfffff000) |
311 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
312 /* if disabled, cannot be enabled again */
313 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
314 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
315 cpu_clear_apic_feature(s
->cpu_env
);
316 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
320 uint64_t cpu_get_apic_base(DeviceState
*d
)
322 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
324 trace_cpu_get_apic_base(s
? (uint64_t)s
->apicbase
: 0);
326 return s
? s
->apicbase
: 0;
329 void cpu_set_apic_tpr(DeviceState
*d
, uint8_t val
)
331 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
335 s
->tpr
= (val
& 0x0f) << 4;
339 uint8_t cpu_get_apic_tpr(DeviceState
*d
)
341 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
343 return s
? s
->tpr
>> 4 : 0;
346 /* return -1 if no bit is set */
347 static int get_highest_priority_int(uint32_t *tab
)
350 for(i
= 7; i
>= 0; i
--) {
352 return i
* 32 + fls_bit(tab
[i
]);
358 static int apic_get_ppr(APICState
*s
)
363 isrv
= get_highest_priority_int(s
->isr
);
374 static int apic_get_arb_pri(APICState
*s
)
376 /* XXX: arbitration */
382 * <0 - low prio interrupt,
384 * >0 - interrupt number
386 static int apic_irq_pending(APICState
*s
)
389 irrv
= get_highest_priority_int(s
->irr
);
393 ppr
= apic_get_ppr(s
);
394 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0)) {
401 /* signal the CPU if an irq is pending */
402 static void apic_update_irq(APICState
*s
)
404 if (!(s
->spurious_vec
& APIC_SV_ENABLE
)) {
407 if (apic_irq_pending(s
) > 0) {
408 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
412 void apic_reset_irq_delivered(void)
414 trace_apic_reset_irq_delivered(apic_irq_delivered
);
416 apic_irq_delivered
= 0;
419 int apic_get_irq_delivered(void)
421 trace_apic_get_irq_delivered(apic_irq_delivered
);
423 return apic_irq_delivered
;
426 void apic_set_irq_delivered(void)
428 apic_irq_delivered
= 1;
431 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
)
433 apic_irq_delivered
+= !get_bit(s
->irr
, vector_num
);
435 trace_apic_set_irq(apic_irq_delivered
);
437 set_bit(s
->irr
, vector_num
);
439 set_bit(s
->tmr
, vector_num
);
441 reset_bit(s
->tmr
, vector_num
);
445 static void apic_eoi(APICState
*s
)
448 isrv
= get_highest_priority_int(s
->isr
);
451 reset_bit(s
->isr
, isrv
);
452 if (!(s
->spurious_vec
& APIC_SV_DIRECTED_IO
) && get_bit(s
->tmr
, isrv
)) {
453 ioapic_eoi_broadcast(isrv
);
458 static int apic_find_dest(uint8_t dest
)
460 APICState
*apic
= local_apics
[dest
];
463 if (apic
&& apic
->id
== dest
)
464 return dest
; /* shortcut in case apic->id == apic->idx */
466 for (i
= 0; i
< MAX_APICS
; i
++) {
467 apic
= local_apics
[i
];
468 if (apic
&& apic
->id
== dest
)
477 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
478 uint8_t dest
, uint8_t dest_mode
)
480 APICState
*apic_iter
;
483 if (dest_mode
== 0) {
485 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
487 int idx
= apic_find_dest(dest
);
488 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
490 set_bit(deliver_bitmask
, idx
);
493 /* XXX: cluster mode */
494 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
495 for(i
= 0; i
< MAX_APICS
; i
++) {
496 apic_iter
= local_apics
[i
];
498 if (apic_iter
->dest_mode
== 0xf) {
499 if (dest
& apic_iter
->log_dest
)
500 set_bit(deliver_bitmask
, i
);
501 } else if (apic_iter
->dest_mode
== 0x0) {
502 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
503 (dest
& apic_iter
->log_dest
& 0x0f)) {
504 set_bit(deliver_bitmask
, i
);
514 void apic_init_reset(DeviceState
*d
)
516 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
523 s
->spurious_vec
= 0xff;
526 memset(s
->isr
, 0, sizeof(s
->isr
));
527 memset(s
->tmr
, 0, sizeof(s
->tmr
));
528 memset(s
->irr
, 0, sizeof(s
->irr
));
529 for(i
= 0; i
< APIC_LVT_NB
; i
++)
530 s
->lvt
[i
] = 1 << 16; /* mask LVT */
532 memset(s
->icr
, 0, sizeof(s
->icr
));
535 s
->initial_count
= 0;
536 s
->initial_count_load_time
= 0;
538 s
->wait_for_sipi
= 1;
541 static void apic_startup(APICState
*s
, int vector_num
)
543 s
->sipi_vector
= vector_num
;
544 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
547 void apic_sipi(DeviceState
*d
)
549 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
551 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
553 if (!s
->wait_for_sipi
)
555 cpu_x86_load_seg_cache_sipi(s
->cpu_env
, s
->sipi_vector
);
556 s
->wait_for_sipi
= 0;
559 static void apic_deliver(DeviceState
*d
, uint8_t dest
, uint8_t dest_mode
,
560 uint8_t delivery_mode
, uint8_t vector_num
,
561 uint8_t polarity
, uint8_t trigger_mode
)
563 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
564 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
565 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
566 APICState
*apic_iter
;
568 switch (dest_shorthand
) {
570 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
573 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
574 set_bit(deliver_bitmask
, s
->idx
);
577 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
580 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
581 reset_bit(deliver_bitmask
, s
->idx
);
585 switch (delivery_mode
) {
588 int trig_mode
= (s
->icr
[0] >> 15) & 1;
589 int level
= (s
->icr
[0] >> 14) & 1;
590 if (level
== 0 && trig_mode
== 1) {
591 foreach_apic(apic_iter
, deliver_bitmask
,
592 apic_iter
->arb_id
= apic_iter
->id
);
599 foreach_apic(apic_iter
, deliver_bitmask
,
600 apic_startup(apic_iter
, vector_num
) );
604 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
608 int apic_get_interrupt(DeviceState
*d
)
610 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
613 /* if the APIC is installed or enabled, we let the 8259 handle the
617 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
620 intno
= apic_irq_pending(s
);
624 } else if (intno
< 0) {
625 return s
->spurious_vec
& 0xff;
627 reset_bit(s
->irr
, intno
);
628 set_bit(s
->isr
, intno
);
633 int apic_accept_pic_intr(DeviceState
*d
)
635 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
641 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
643 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
644 (lvt0
& APIC_LVT_MASKED
) == 0)
650 static uint32_t apic_get_current_count(APICState
*s
)
654 d
= (qemu_get_clock_ns(vm_clock
) - s
->initial_count_load_time
) >>
656 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
658 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
660 if (d
>= s
->initial_count
)
663 val
= s
->initial_count
- d
;
668 static void apic_timer_update(APICState
*s
, int64_t current_time
)
670 int64_t next_time
, d
;
672 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
673 d
= (current_time
- s
->initial_count_load_time
) >>
675 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
676 if (!s
->initial_count
)
678 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) * ((uint64_t)s
->initial_count
+ 1);
680 if (d
>= s
->initial_count
)
682 d
= (uint64_t)s
->initial_count
+ 1;
684 next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
685 qemu_mod_timer(s
->timer
, next_time
);
686 s
->next_time
= next_time
;
689 qemu_del_timer(s
->timer
);
693 static void apic_timer(void *opaque
)
695 APICState
*s
= opaque
;
697 apic_local_deliver(s
, APIC_LVT_TIMER
);
698 apic_timer_update(s
, s
->next_time
);
701 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
706 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
711 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
715 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
719 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
726 d
= cpu_get_current_apic();
730 s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
732 index
= (addr
>> 4) & 0xff;
737 case 0x03: /* version */
738 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
744 val
= apic_get_arb_pri(s
);
748 val
= apic_get_ppr(s
);
754 val
= s
->log_dest
<< 24;
757 val
= s
->dest_mode
<< 28;
760 val
= s
->spurious_vec
;
763 val
= s
->isr
[index
& 7];
766 val
= s
->tmr
[index
& 7];
769 val
= s
->irr
[index
& 7];
776 val
= s
->icr
[index
& 1];
779 val
= s
->lvt
[index
- 0x32];
782 val
= s
->initial_count
;
785 val
= apic_get_current_count(s
);
788 val
= s
->divide_conf
;
791 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
795 trace_apic_mem_readl(addr
, val
);
799 static void apic_send_msi(target_phys_addr_t addr
, uint32_t data
)
801 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
802 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
803 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
804 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
805 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
806 /* XXX: Ignore redirection hint. */
807 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, 0, trigger_mode
);
810 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
814 int index
= (addr
>> 4) & 0xff;
815 if (addr
> 0xfff || !index
) {
816 /* MSI and MMIO APIC are at the same memory location,
817 * but actually not on the global bus: MSI is on PCI bus
818 * APIC is connected directly to the CPU.
819 * Mapping them on the global bus happens to work because
820 * MSI registers are reserved in APIC MMIO and vice versa. */
821 apic_send_msi(addr
, val
);
825 d
= cpu_get_current_apic();
829 s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
831 trace_apic_mem_writel(addr
, val
);
850 s
->log_dest
= val
>> 24;
853 s
->dest_mode
= val
>> 28;
856 s
->spurious_vec
= val
& 0x1ff;
866 apic_deliver(d
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
867 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
868 (s
->icr
[0] >> 14) & 1, (s
->icr
[0] >> 15) & 1);
875 int n
= index
- 0x32;
877 if (n
== APIC_LVT_TIMER
)
878 apic_timer_update(s
, qemu_get_clock_ns(vm_clock
));
882 s
->initial_count
= val
;
883 s
->initial_count_load_time
= qemu_get_clock_ns(vm_clock
);
884 apic_timer_update(s
, s
->initial_count_load_time
);
891 s
->divide_conf
= val
& 0xb;
892 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
893 s
->count_shift
= (v
+ 1) & 7;
897 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
902 #ifdef KVM_CAP_IRQCHIP
904 static inline uint32_t kapic_reg(struct kvm_lapic_state
*kapic
, int reg_id
)
906 return *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4)));
909 static inline void kapic_set_reg(struct kvm_lapic_state
*kapic
,
910 int reg_id
, uint32_t val
)
912 *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4))) = val
;
915 static void kvm_kernel_lapic_save_to_user(APICState
*s
)
917 struct kvm_lapic_state apic
;
918 struct kvm_lapic_state
*kapic
= &apic
;
921 kvm_get_lapic(s
->cpu_env
, kapic
);
923 s
->id
= kapic_reg(kapic
, 0x2) >> 24;
924 s
->tpr
= kapic_reg(kapic
, 0x8);
925 s
->arb_id
= kapic_reg(kapic
, 0x9);
926 s
->log_dest
= kapic_reg(kapic
, 0xd) >> 24;
927 s
->dest_mode
= kapic_reg(kapic
, 0xe) >> 28;
928 s
->spurious_vec
= kapic_reg(kapic
, 0xf);
929 for (i
= 0; i
< 8; i
++) {
930 s
->isr
[i
] = kapic_reg(kapic
, 0x10 + i
);
931 s
->tmr
[i
] = kapic_reg(kapic
, 0x18 + i
);
932 s
->irr
[i
] = kapic_reg(kapic
, 0x20 + i
);
934 s
->esr
= kapic_reg(kapic
, 0x28);
935 s
->icr
[0] = kapic_reg(kapic
, 0x30);
936 s
->icr
[1] = kapic_reg(kapic
, 0x31);
937 for (i
= 0; i
< APIC_LVT_NB
; i
++)
938 s
->lvt
[i
] = kapic_reg(kapic
, 0x32 + i
);
939 s
->initial_count
= kapic_reg(kapic
, 0x38);
940 s
->divide_conf
= kapic_reg(kapic
, 0x3e);
942 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
943 s
->count_shift
= (v
+ 1) & 7;
945 s
->initial_count_load_time
= qemu_get_clock_ns(vm_clock
);
946 apic_timer_update(s
, s
->initial_count_load_time
);
949 static void kvm_kernel_lapic_load_from_user(APICState
*s
)
951 struct kvm_lapic_state apic
;
952 struct kvm_lapic_state
*klapic
= &apic
;
955 memset(klapic
, 0, sizeof apic
);
956 kapic_set_reg(klapic
, 0x2, s
->id
<< 24);
957 kapic_set_reg(klapic
, 0x8, s
->tpr
);
958 kapic_set_reg(klapic
, 0xd, s
->log_dest
<< 24);
959 kapic_set_reg(klapic
, 0xe, s
->dest_mode
<< 28 | 0x0fffffff);
960 kapic_set_reg(klapic
, 0xf, s
->spurious_vec
);
961 for (i
= 0; i
< 8; i
++) {
962 kapic_set_reg(klapic
, 0x10 + i
, s
->isr
[i
]);
963 kapic_set_reg(klapic
, 0x18 + i
, s
->tmr
[i
]);
964 kapic_set_reg(klapic
, 0x20 + i
, s
->irr
[i
]);
966 kapic_set_reg(klapic
, 0x28, s
->esr
);
967 kapic_set_reg(klapic
, 0x30, s
->icr
[0]);
968 kapic_set_reg(klapic
, 0x31, s
->icr
[1]);
969 for (i
= 0; i
< APIC_LVT_NB
; i
++)
970 kapic_set_reg(klapic
, 0x32 + i
, s
->lvt
[i
]);
971 kapic_set_reg(klapic
, 0x38, s
->initial_count
);
972 kapic_set_reg(klapic
, 0x3e, s
->divide_conf
);
974 kvm_set_lapic(s
->cpu_env
, klapic
);
979 void kvm_load_lapic(CPUState
*env
)
981 #ifdef KVM_CAP_IRQCHIP
982 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, env
->apic_state
);
988 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
989 kvm_kernel_lapic_load_from_user(s
);
994 void kvm_save_lapic(CPUState
*env
)
996 #ifdef KVM_CAP_IRQCHIP
997 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, env
->apic_state
);
1003 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1004 kvm_kernel_lapic_save_to_user(s
);
1009 /* This function is only used for old state version 1 and 2 */
1010 static int apic_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
1012 APICState
*s
= opaque
;
1018 /* XXX: what if the base changes? (registered memory regions) */
1019 qemu_get_be32s(f
, &s
->apicbase
);
1020 qemu_get_8s(f
, &s
->id
);
1021 qemu_get_8s(f
, &s
->arb_id
);
1022 qemu_get_8s(f
, &s
->tpr
);
1023 qemu_get_be32s(f
, &s
->spurious_vec
);
1024 qemu_get_8s(f
, &s
->log_dest
);
1025 qemu_get_8s(f
, &s
->dest_mode
);
1026 for (i
= 0; i
< 8; i
++) {
1027 qemu_get_be32s(f
, &s
->isr
[i
]);
1028 qemu_get_be32s(f
, &s
->tmr
[i
]);
1029 qemu_get_be32s(f
, &s
->irr
[i
]);
1031 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
1032 qemu_get_be32s(f
, &s
->lvt
[i
]);
1034 qemu_get_be32s(f
, &s
->esr
);
1035 qemu_get_be32s(f
, &s
->icr
[0]);
1036 qemu_get_be32s(f
, &s
->icr
[1]);
1037 qemu_get_be32s(f
, &s
->divide_conf
);
1038 s
->count_shift
=qemu_get_be32(f
);
1039 qemu_get_be32s(f
, &s
->initial_count
);
1040 s
->initial_count_load_time
=qemu_get_be64(f
);
1041 s
->next_time
=qemu_get_be64(f
);
1043 if (version_id
>= 2)
1044 qemu_get_timer(f
, s
->timer
);
1048 static const VMStateDescription vmstate_apic
= {
1051 .minimum_version_id
= 3,
1052 .minimum_version_id_old
= 1,
1053 .load_state_old
= apic_load_old
,
1054 .fields
= (VMStateField
[]) {
1055 VMSTATE_UINT32(apicbase
, APICState
),
1056 VMSTATE_UINT8(id
, APICState
),
1057 VMSTATE_UINT8(arb_id
, APICState
),
1058 VMSTATE_UINT8(tpr
, APICState
),
1059 VMSTATE_UINT32(spurious_vec
, APICState
),
1060 VMSTATE_UINT8(log_dest
, APICState
),
1061 VMSTATE_UINT8(dest_mode
, APICState
),
1062 VMSTATE_UINT32_ARRAY(isr
, APICState
, 8),
1063 VMSTATE_UINT32_ARRAY(tmr
, APICState
, 8),
1064 VMSTATE_UINT32_ARRAY(irr
, APICState
, 8),
1065 VMSTATE_UINT32_ARRAY(lvt
, APICState
, APIC_LVT_NB
),
1066 VMSTATE_UINT32(esr
, APICState
),
1067 VMSTATE_UINT32_ARRAY(icr
, APICState
, 2),
1068 VMSTATE_UINT32(divide_conf
, APICState
),
1069 VMSTATE_INT32(count_shift
, APICState
),
1070 VMSTATE_UINT32(initial_count
, APICState
),
1071 VMSTATE_INT64(initial_count_load_time
, APICState
),
1072 VMSTATE_INT64(next_time
, APICState
),
1073 VMSTATE_TIMER(timer
, APICState
),
1074 VMSTATE_END_OF_LIST()
1078 static void apic_reset(DeviceState
*d
)
1080 APICState
*s
= DO_UPCAST(APICState
, busdev
.qdev
, d
);
1083 bsp
= cpu_is_bsp(s
->cpu_env
);
1084 s
->apicbase
= 0xfee00000 |
1085 (bsp
? MSR_IA32_APICBASE_BSP
: 0) | MSR_IA32_APICBASE_ENABLE
;
1091 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1092 * time typically by BIOS, so PIC interrupt can be delivered to the
1093 * processor when local APIC is enabled.
1095 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
1099 static const MemoryRegionOps apic_io_ops
= {
1101 .read
= { apic_mem_readb
, apic_mem_readw
, apic_mem_readl
, },
1102 .write
= { apic_mem_writeb
, apic_mem_writew
, apic_mem_writel
, },
1104 .endianness
= DEVICE_NATIVE_ENDIAN
,
1107 static int apic_init1(SysBusDevice
*dev
)
1109 APICState
*s
= FROM_SYSBUS(APICState
, dev
);
1110 static int last_apic_idx
;
1112 if (last_apic_idx
>= MAX_APICS
) {
1115 memory_region_init_io(&s
->io_memory
, &apic_io_ops
, s
, "apic",
1117 sysbus_init_mmio_region(dev
, &s
->io_memory
);
1119 s
->timer
= qemu_new_timer_ns(vm_clock
, apic_timer
, s
);
1120 s
->idx
= last_apic_idx
++;
1121 local_apics
[s
->idx
] = s
;
1125 static SysBusDeviceInfo apic_info
= {
1127 .qdev
.name
= "apic",
1128 .qdev
.size
= sizeof(APICState
),
1129 .qdev
.vmsd
= &vmstate_apic
,
1130 .qdev
.reset
= apic_reset
,
1132 .qdev
.props
= (Property
[]) {
1133 DEFINE_PROP_UINT8("id", APICState
, id
, -1),
1134 DEFINE_PROP_PTR("cpu_env", APICState
, cpu_env
),
1135 DEFINE_PROP_END_OF_LIST(),
1139 static void apic_register_devices(void)
1141 sysbus_register_withprop(&apic_info
);
1144 device_init(apic_register_devices
)