2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
11 #include "primecell.h"
16 #include "exec-memory.h"
38 static uint8_t integrator_spd
[128] = {
39 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
40 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
43 static uint64_t integratorcm_read(void *opaque
, target_phys_addr_t offset
,
46 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
47 if (offset
>= 0x100 && offset
< 0x200) {
51 return integrator_spd
[offset
>> 2];
53 switch (offset
>> 2) {
65 if (s
->cm_lock
== 0xa05f) {
70 case 6: /* CM_LMBUSCNT */
71 /* ??? High frequency timer. */
72 hw_error("integratorcm_read: CM_LMBUSCNT");
73 case 7: /* CM_AUXOSC */
75 case 8: /* CM_SDRAM */
79 case 10: /* CM_REFCT */
80 /* ??? High frequency timer. */
81 hw_error("integratorcm_read: CM_REFCT");
82 case 12: /* CM_FLAGS */
84 case 14: /* CM_NVFLAGS */
86 case 16: /* CM_IRQ_STAT */
87 return s
->int_level
& s
->irq_enabled
;
88 case 17: /* CM_IRQ_RSTAT */
90 case 18: /* CM_IRQ_ENSET */
91 return s
->irq_enabled
;
92 case 20: /* CM_SOFT_INTSET */
93 return s
->int_level
& 1;
94 case 24: /* CM_FIQ_STAT */
95 return s
->int_level
& s
->fiq_enabled
;
96 case 25: /* CM_FIQ_RSTAT */
98 case 26: /* CM_FIQ_ENSET */
99 return s
->fiq_enabled
;
100 case 32: /* CM_VOLTAGE_CTL0 */
101 case 33: /* CM_VOLTAGE_CTL1 */
102 case 34: /* CM_VOLTAGE_CTL2 */
103 case 35: /* CM_VOLTAGE_CTL3 */
104 /* ??? Voltage control unimplemented. */
107 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
113 static void integratorcm_do_remap(integratorcm_state
*s
, int flash
)
116 if (s
->flash_mapped
) {
117 sysbus_del_memory(&s
->busdev
, &s
->flash
);
118 s
->flash_mapped
= false;
121 if (!s
->flash_mapped
) {
122 sysbus_add_memory_overlap(&s
->busdev
, 0, &s
->flash
, 1);
123 s
->flash_mapped
= true;
126 //??? tlb_flush (cpu_single_env, 1);
129 static void integratorcm_set_ctrl(integratorcm_state
*s
, uint32_t value
)
132 qemu_system_reset_request();
134 if ((s
->cm_ctrl
^ value
) & 4) {
135 integratorcm_do_remap(s
, (value
& 4) == 0);
137 if ((s
->cm_ctrl
^ value
) & 1) {
138 /* (value & 1) != 0 means the green "MISC LED" is lit.
139 * We don't have any nice place to display LEDs. printf is a bad
140 * idea because Linux uses the LED as a heartbeat and the output
141 * will swamp anything else on the terminal.
144 /* Note that the RESET bit [3] always reads as zero */
145 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
148 static void integratorcm_update(integratorcm_state
*s
)
150 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
152 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
153 hw_error("Core module interrupt\n");
156 static void integratorcm_write(void *opaque
, target_phys_addr_t offset
,
157 uint64_t value
, unsigned size
)
159 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
160 switch (offset
>> 2) {
162 if (s
->cm_lock
== 0xa05f)
165 case 3: /* CM_CTRL */
166 integratorcm_set_ctrl(s
, value
);
168 case 5: /* CM_LOCK */
169 s
->cm_lock
= value
& 0xffff;
171 case 7: /* CM_AUXOSC */
172 if (s
->cm_lock
== 0xa05f)
173 s
->cm_auxosc
= value
;
175 case 8: /* CM_SDRAM */
178 case 9: /* CM_INIT */
179 /* ??? This can change the memory bus frequency. */
182 case 12: /* CM_FLAGSS */
183 s
->cm_flags
|= value
;
185 case 13: /* CM_FLAGSC */
186 s
->cm_flags
&= ~value
;
188 case 14: /* CM_NVFLAGSS */
189 s
->cm_nvflags
|= value
;
191 case 15: /* CM_NVFLAGSS */
192 s
->cm_nvflags
&= ~value
;
194 case 18: /* CM_IRQ_ENSET */
195 s
->irq_enabled
|= value
;
196 integratorcm_update(s
);
198 case 19: /* CM_IRQ_ENCLR */
199 s
->irq_enabled
&= ~value
;
200 integratorcm_update(s
);
202 case 20: /* CM_SOFT_INTSET */
203 s
->int_level
|= (value
& 1);
204 integratorcm_update(s
);
206 case 21: /* CM_SOFT_INTCLR */
207 s
->int_level
&= ~(value
& 1);
208 integratorcm_update(s
);
210 case 26: /* CM_FIQ_ENSET */
211 s
->fiq_enabled
|= value
;
212 integratorcm_update(s
);
214 case 27: /* CM_FIQ_ENCLR */
215 s
->fiq_enabled
&= ~value
;
216 integratorcm_update(s
);
218 case 32: /* CM_VOLTAGE_CTL0 */
219 case 33: /* CM_VOLTAGE_CTL1 */
220 case 34: /* CM_VOLTAGE_CTL2 */
221 case 35: /* CM_VOLTAGE_CTL3 */
222 /* ??? Voltage control unimplemented. */
225 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
231 /* Integrator/CM control registers. */
233 static const MemoryRegionOps integratorcm_ops
= {
234 .read
= integratorcm_read
,
235 .write
= integratorcm_write
,
236 .endianness
= DEVICE_NATIVE_ENDIAN
,
239 static int integratorcm_init(SysBusDevice
*dev
)
241 integratorcm_state
*s
= FROM_SYSBUS(integratorcm_state
, dev
);
243 s
->cm_osc
= 0x01000048;
244 /* ??? What should the high bits of this value be? */
245 s
->cm_auxosc
= 0x0007feff;
246 s
->cm_sdram
= 0x00011122;
247 if (s
->memsz
>= 256) {
248 integrator_spd
[31] = 64;
250 } else if (s
->memsz
>= 128) {
251 integrator_spd
[31] = 32;
253 } else if (s
->memsz
>= 64) {
254 integrator_spd
[31] = 16;
256 } else if (s
->memsz
>= 32) {
257 integrator_spd
[31] = 4;
260 integrator_spd
[31] = 2;
262 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
263 s
->cm_init
= 0x00000112;
264 memory_region_init_ram(&s
->flash
, "integrator.flash", 0x100000);
265 vmstate_register_ram_global(&s
->flash
);
266 s
->flash_mapped
= false;
268 memory_region_init_io(&s
->iomem
, &integratorcm_ops
, s
,
269 "integratorcm", 0x00800000);
270 sysbus_init_mmio(dev
, &s
->iomem
);
272 integratorcm_do_remap(s
, 1);
273 /* ??? Save/restore. */
277 /* Integrator/CP hardware emulation. */
278 /* Primary interrupt controller. */
280 typedef struct icp_pic_state
285 uint32_t irq_enabled
;
286 uint32_t fiq_enabled
;
291 static void icp_pic_update(icp_pic_state
*s
)
295 flags
= (s
->level
& s
->irq_enabled
);
296 qemu_set_irq(s
->parent_irq
, flags
!= 0);
297 flags
= (s
->level
& s
->fiq_enabled
);
298 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
301 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
303 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
305 s
->level
|= 1 << irq
;
307 s
->level
&= ~(1 << irq
);
311 static uint64_t icp_pic_read(void *opaque
, target_phys_addr_t offset
,
314 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
316 switch (offset
>> 2) {
317 case 0: /* IRQ_STATUS */
318 return s
->level
& s
->irq_enabled
;
319 case 1: /* IRQ_RAWSTAT */
321 case 2: /* IRQ_ENABLESET */
322 return s
->irq_enabled
;
323 case 4: /* INT_SOFTSET */
325 case 8: /* FRQ_STATUS */
326 return s
->level
& s
->fiq_enabled
;
327 case 9: /* FRQ_RAWSTAT */
329 case 10: /* FRQ_ENABLESET */
330 return s
->fiq_enabled
;
331 case 3: /* IRQ_ENABLECLR */
332 case 5: /* INT_SOFTCLR */
333 case 11: /* FRQ_ENABLECLR */
335 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
340 static void icp_pic_write(void *opaque
, target_phys_addr_t offset
,
341 uint64_t value
, unsigned size
)
343 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
345 switch (offset
>> 2) {
346 case 2: /* IRQ_ENABLESET */
347 s
->irq_enabled
|= value
;
349 case 3: /* IRQ_ENABLECLR */
350 s
->irq_enabled
&= ~value
;
352 case 4: /* INT_SOFTSET */
354 icp_pic_set_irq(s
, 0, 1);
356 case 5: /* INT_SOFTCLR */
358 icp_pic_set_irq(s
, 0, 0);
360 case 10: /* FRQ_ENABLESET */
361 s
->fiq_enabled
|= value
;
363 case 11: /* FRQ_ENABLECLR */
364 s
->fiq_enabled
&= ~value
;
366 case 0: /* IRQ_STATUS */
367 case 1: /* IRQ_RAWSTAT */
368 case 8: /* FRQ_STATUS */
369 case 9: /* FRQ_RAWSTAT */
371 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
377 static const MemoryRegionOps icp_pic_ops
= {
378 .read
= icp_pic_read
,
379 .write
= icp_pic_write
,
380 .endianness
= DEVICE_NATIVE_ENDIAN
,
383 static int icp_pic_init(SysBusDevice
*dev
)
385 icp_pic_state
*s
= FROM_SYSBUS(icp_pic_state
, dev
);
387 qdev_init_gpio_in(&dev
->qdev
, icp_pic_set_irq
, 32);
388 sysbus_init_irq(dev
, &s
->parent_irq
);
389 sysbus_init_irq(dev
, &s
->parent_fiq
);
390 memory_region_init_io(&s
->iomem
, &icp_pic_ops
, s
, "icp-pic", 0x00800000);
391 sysbus_init_mmio(dev
, &s
->iomem
);
395 /* CP control registers. */
397 static uint64_t icp_control_read(void *opaque
, target_phys_addr_t offset
,
400 switch (offset
>> 2) {
401 case 0: /* CP_IDFIELD */
403 case 1: /* CP_FLASHPROG */
405 case 2: /* CP_INTREG */
407 case 3: /* CP_DECODE */
410 hw_error("icp_control_read: Bad offset %x\n", (int)offset
);
415 static void icp_control_write(void *opaque
, target_phys_addr_t offset
,
416 uint64_t value
, unsigned size
)
418 switch (offset
>> 2) {
419 case 1: /* CP_FLASHPROG */
420 case 2: /* CP_INTREG */
421 case 3: /* CP_DECODE */
422 /* Nothing interesting implemented yet. */
425 hw_error("icp_control_write: Bad offset %x\n", (int)offset
);
429 static const MemoryRegionOps icp_control_ops
= {
430 .read
= icp_control_read
,
431 .write
= icp_control_write
,
432 .endianness
= DEVICE_NATIVE_ENDIAN
,
435 static void icp_control_init(target_phys_addr_t base
)
439 io
= (MemoryRegion
*)g_malloc0(sizeof(MemoryRegion
));
440 memory_region_init_io(io
, &icp_control_ops
, NULL
,
441 "control", 0x00800000);
442 memory_region_add_subregion(get_system_memory(), base
, io
);
443 /* ??? Save/restore. */
449 static struct arm_boot_info integrator_binfo
= {
454 static void integratorcp_init(ram_addr_t ram_size
,
455 const char *boot_device
,
456 const char *kernel_filename
, const char *kernel_cmdline
,
457 const char *initrd_filename
, const char *cpu_model
)
460 MemoryRegion
*address_space_mem
= get_system_memory();
461 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
462 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
469 cpu_model
= "arm926";
470 env
= cpu_init(cpu_model
);
472 fprintf(stderr
, "Unable to find CPU definition\n");
475 memory_region_init_ram(ram
, "integrator.ram", ram_size
);
476 vmstate_register_ram_global(ram
);
477 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
478 /* ??? RAM should repeat to fill physical memory space. */
479 /* SDRAM at address zero*/
480 memory_region_add_subregion(address_space_mem
, 0, ram
);
481 /* And again at address 0x80000000 */
482 memory_region_init_alias(ram_alias
, "ram.alias", ram
, 0, ram_size
);
483 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
485 dev
= qdev_create(NULL
, "integrator_core");
486 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
487 qdev_init_nofail(dev
);
488 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
490 cpu_pic
= arm_pic_init_cpu(env
);
491 dev
= sysbus_create_varargs("integrator_pic", 0x14000000,
492 cpu_pic
[ARM_PIC_CPU_IRQ
],
493 cpu_pic
[ARM_PIC_CPU_FIQ
], NULL
);
494 for (i
= 0; i
< 32; i
++) {
495 pic
[i
] = qdev_get_gpio_in(dev
, i
);
497 sysbus_create_simple("integrator_pic", 0xca000000, pic
[26]);
498 sysbus_create_varargs("integrator_pit", 0x13000000,
499 pic
[5], pic
[6], pic
[7], NULL
);
500 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
501 sysbus_create_simple("pl011", 0x16000000, pic
[1]);
502 sysbus_create_simple("pl011", 0x17000000, pic
[2]);
503 icp_control_init(0xcb000000);
504 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
505 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
506 sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
507 if (nd_table
[0].vlan
)
508 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
510 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
512 integrator_binfo
.ram_size
= ram_size
;
513 integrator_binfo
.kernel_filename
= kernel_filename
;
514 integrator_binfo
.kernel_cmdline
= kernel_cmdline
;
515 integrator_binfo
.initrd_filename
= initrd_filename
;
516 arm_load_kernel(env
, &integrator_binfo
);
519 static QEMUMachine integratorcp_machine
= {
520 .name
= "integratorcp",
521 .desc
= "ARM Integrator/CP (ARM926EJ-S)",
522 .init
= integratorcp_init
,
526 static void integratorcp_machine_init(void)
528 qemu_register_machine(&integratorcp_machine
);
531 machine_init(integratorcp_machine_init
);
533 static SysBusDeviceInfo core_info
= {
534 .init
= integratorcm_init
,
535 .qdev
.name
= "integrator_core",
536 .qdev
.size
= sizeof(integratorcm_state
),
537 .qdev
.props
= (Property
[]) {
538 DEFINE_PROP_UINT32("memsz", integratorcm_state
, memsz
, 0),
539 DEFINE_PROP_END_OF_LIST(),
543 static void integratorcp_register_devices(void)
545 sysbus_register_dev("integrator_pic", sizeof(icp_pic_state
), icp_pic_init
);
546 sysbus_register_withprop(&core_info
);
549 device_init(integratorcp_register_devices
)