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target-s390: Convert FP SUBTRACT
[qemu-kvm.git] / target-s390x / translate.c
blob2b3b0fc789e6c29e6167fd9f8d362b279dcb73e7
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36
37 /* global register indexes */
38 static TCGv_ptr cpu_env;
39
40 #include "exec/gen-icount.h"
41 #include "helper.h"
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45
46 /* Information that (most) every instruction needs to manipulate. */
47 typedef struct DisasContext DisasContext;
48 typedef struct DisasInsn DisasInsn;
49 typedef struct DisasFields DisasFields;
50
51 struct DisasContext {
52 struct TranslationBlock *tb;
53 const DisasInsn *insn;
54 DisasFields *fields;
55 uint64_t pc, next_pc;
56 enum cc_op cc_op;
57 bool singlestep_enabled;
58 int is_jmp;
59 };
60
61 /* Information carried about a condition to be evaluated. */
62 typedef struct {
63 TCGCond cond:8;
64 bool is_64;
65 bool g1;
66 bool g2;
67 union {
68 struct { TCGv_i64 a, b; } s64;
69 struct { TCGv_i32 a, b; } s32;
70 } u;
71 } DisasCompare;
72
73 #define DISAS_EXCP 4
74
75 static void gen_op_calc_cc(DisasContext *s);
76
77 #ifdef DEBUG_INLINE_BRANCHES
78 static uint64_t inline_branch_hit[CC_OP_MAX];
79 static uint64_t inline_branch_miss[CC_OP_MAX];
80 #endif
81
82 static inline void debug_insn(uint64_t insn)
83 {
84 LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
85 }
86
87 static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
88 {
89 if (!(s->tb->flags & FLAG_MASK_64)) {
90 if (s->tb->flags & FLAG_MASK_32) {
91 return pc | 0x80000000;
92 }
93 }
94 return pc;
95 }
96
97 void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
98 int flags)
99 {
100 int i;
101
102 if (env->cc_op > 3) {
103 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
104 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
105 } else {
106 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
107 env->psw.mask, env->psw.addr, env->cc_op);
108 }
109
110 for (i = 0; i < 16; i++) {
111 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
112 if ((i % 4) == 3) {
113 cpu_fprintf(f, "\n");
114 } else {
115 cpu_fprintf(f, " ");
116 }
117 }
118
119 for (i = 0; i < 16; i++) {
120 cpu_fprintf(f, "F%02d=%016" PRIx64, i, env->fregs[i].ll);
121 if ((i % 4) == 3) {
122 cpu_fprintf(f, "\n");
123 } else {
124 cpu_fprintf(f, " ");
125 }
126 }
127
128 #ifndef CONFIG_USER_ONLY
129 for (i = 0; i < 16; i++) {
130 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
131 if ((i % 4) == 3) {
132 cpu_fprintf(f, "\n");
133 } else {
134 cpu_fprintf(f, " ");
135 }
136 }
137 #endif
138
139 #ifdef DEBUG_INLINE_BRANCHES
140 for (i = 0; i < CC_OP_MAX; i++) {
141 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
142 inline_branch_miss[i], inline_branch_hit[i]);
143 }
144 #endif
145
146 cpu_fprintf(f, "\n");
147 }
148
149 static TCGv_i64 psw_addr;
150 static TCGv_i64 psw_mask;
151
152 static TCGv_i32 cc_op;
153 static TCGv_i64 cc_src;
154 static TCGv_i64 cc_dst;
155 static TCGv_i64 cc_vr;
156
157 static char cpu_reg_names[32][4];
158 static TCGv_i64 regs[16];
159 static TCGv_i64 fregs[16];
160
161 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
162
163 void s390x_translate_init(void)
164 {
165 int i;
166
167 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
168 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
169 offsetof(CPUS390XState, psw.addr),
170 "psw_addr");
171 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
172 offsetof(CPUS390XState, psw.mask),
173 "psw_mask");
174
175 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
176 "cc_op");
177 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
178 "cc_src");
179 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
180 "cc_dst");
181 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
182 "cc_vr");
183
184 for (i = 0; i < 16; i++) {
185 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
186 regs[i] = tcg_global_mem_new(TCG_AREG0,
187 offsetof(CPUS390XState, regs[i]),
188 cpu_reg_names[i]);
189 }
190
191 for (i = 0; i < 16; i++) {
192 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
193 fregs[i] = tcg_global_mem_new(TCG_AREG0,
194 offsetof(CPUS390XState, fregs[i].d),
195 cpu_reg_names[i + 16]);
196 }
197
198 /* register helpers */
199 #define GEN_HELPER 2
200 #include "helper.h"
201 }
202
203 static inline TCGv_i64 load_reg(int reg)
204 {
205 TCGv_i64 r = tcg_temp_new_i64();
206 tcg_gen_mov_i64(r, regs[reg]);
207 return r;
208 }
209
210 static inline TCGv_i64 load_freg(int reg)
211 {
212 TCGv_i64 r = tcg_temp_new_i64();
213 tcg_gen_mov_i64(r, fregs[reg]);
214 return r;
215 }
216
217 static inline TCGv_i32 load_freg32(int reg)
218 {
219 TCGv_i32 r = tcg_temp_new_i32();
220 #if HOST_LONG_BITS == 32
221 tcg_gen_mov_i32(r, TCGV_HIGH(fregs[reg]));
222 #else
223 tcg_gen_shri_i64(MAKE_TCGV_I64(GET_TCGV_I32(r)), fregs[reg], 32);
224 #endif
225 return r;
226 }
227
228 static inline TCGv_i64 load_freg32_i64(int reg)
229 {
230 TCGv_i64 r = tcg_temp_new_i64();
231 tcg_gen_shri_i64(r, fregs[reg], 32);
232 return r;
233 }
234
235 static inline TCGv_i32 load_reg32(int reg)
236 {
237 TCGv_i32 r = tcg_temp_new_i32();
238 tcg_gen_trunc_i64_i32(r, regs[reg]);
239 return r;
240 }
241
242 static inline TCGv_i64 load_reg32_i64(int reg)
243 {
244 TCGv_i64 r = tcg_temp_new_i64();
245 tcg_gen_ext32s_i64(r, regs[reg]);
246 return r;
247 }
248
249 static inline void store_reg(int reg, TCGv_i64 v)
250 {
251 tcg_gen_mov_i64(regs[reg], v);
252 }
253
254 static inline void store_freg(int reg, TCGv_i64 v)
255 {
256 tcg_gen_mov_i64(fregs[reg], v);
257 }
258
259 static inline void store_reg32(int reg, TCGv_i32 v)
260 {
261 /* 32 bit register writes keep the upper half */
262 #if HOST_LONG_BITS == 32
263 tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
264 #else
265 tcg_gen_deposit_i64(regs[reg], regs[reg],
266 MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 32);
267 #endif
268 }
269
270 static inline void store_reg32_i64(int reg, TCGv_i64 v)
271 {
272 /* 32 bit register writes keep the upper half */
273 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
274 }
275
276 static inline void store_reg32h_i64(int reg, TCGv_i64 v)
277 {
278 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
279 }
280
281 static inline void store_freg32(int reg, TCGv_i32 v)
282 {
283 /* 32 bit register writes keep the lower half */
284 #if HOST_LONG_BITS == 32
285 tcg_gen_mov_i32(TCGV_HIGH(fregs[reg]), v);
286 #else
287 tcg_gen_deposit_i64(fregs[reg], fregs[reg],
288 MAKE_TCGV_I64(GET_TCGV_I32(v)), 32, 32);
289 #endif
290 }
291
292 static inline void store_freg32_i64(int reg, TCGv_i64 v)
293 {
294 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
295 }
296
297 static inline void return_low128(TCGv_i64 dest)
298 {
299 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
300 }
301
302 static inline void update_psw_addr(DisasContext *s)
303 {
304 /* psw.addr */
305 tcg_gen_movi_i64(psw_addr, s->pc);
306 }
307
308 static inline void potential_page_fault(DisasContext *s)
309 {
310 #ifndef CONFIG_USER_ONLY
311 update_psw_addr(s);
312 gen_op_calc_cc(s);
313 #endif
314 }
315
316 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
317 {
318 return (uint64_t)cpu_lduw_code(env, pc);
319 }
320
321 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
322 {
323 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
324 }
325
326 static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
327 {
328 return (ld_code2(env, pc) << 32) | ld_code4(env, pc + 2);
329 }
330
331 static inline int get_mem_index(DisasContext *s)
332 {
333 switch (s->tb->flags & FLAG_MASK_ASC) {
334 case PSW_ASC_PRIMARY >> 32:
335 return 0;
336 case PSW_ASC_SECONDARY >> 32:
337 return 1;
338 case PSW_ASC_HOME >> 32:
339 return 2;
340 default:
341 tcg_abort();
342 break;
343 }
344 }
345
346 static void gen_exception(int excp)
347 {
348 TCGv_i32 tmp = tcg_const_i32(excp);
349 gen_helper_exception(cpu_env, tmp);
350 tcg_temp_free_i32(tmp);
351 }
352
353 static void gen_program_exception(DisasContext *s, int code)
354 {
355 TCGv_i32 tmp;
356
357 /* Remember what pgm exeption this was. */
358 tmp = tcg_const_i32(code);
359 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
360 tcg_temp_free_i32(tmp);
361
362 tmp = tcg_const_i32(s->next_pc - s->pc);
363 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
364 tcg_temp_free_i32(tmp);
365
366 /* Advance past instruction. */
367 s->pc = s->next_pc;
368 update_psw_addr(s);
369
370 /* Save off cc. */
371 gen_op_calc_cc(s);
372
373 /* Trigger exception. */
374 gen_exception(EXCP_PGM);
375
376 /* End TB here. */
377 s->is_jmp = DISAS_EXCP;
378 }
379
380 static inline void gen_illegal_opcode(DisasContext *s)
381 {
382 gen_program_exception(s, PGM_SPECIFICATION);
383 }
384
385 static inline void check_privileged(DisasContext *s)
386 {
387 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
388 gen_program_exception(s, PGM_PRIVILEGED);
389 }
390 }
391
392 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
393 {
394 TCGv_i64 tmp;
395
396 /* 31-bitify the immediate part; register contents are dealt with below */
397 if (!(s->tb->flags & FLAG_MASK_64)) {
398 d2 &= 0x7fffffffUL;
399 }
400
401 if (x2) {
402 if (d2) {
403 tmp = tcg_const_i64(d2);
404 tcg_gen_add_i64(tmp, tmp, regs[x2]);
405 } else {
406 tmp = load_reg(x2);
407 }
408 if (b2) {
409 tcg_gen_add_i64(tmp, tmp, regs[b2]);
410 }
411 } else if (b2) {
412 if (d2) {
413 tmp = tcg_const_i64(d2);
414 tcg_gen_add_i64(tmp, tmp, regs[b2]);
415 } else {
416 tmp = load_reg(b2);
417 }
418 } else {
419 tmp = tcg_const_i64(d2);
420 }
421
422 /* 31-bit mode mask if there are values loaded from registers */
423 if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
424 tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
425 }
426
427 return tmp;
428 }
429
430 static void gen_op_movi_cc(DisasContext *s, uint32_t val)
431 {
432 s->cc_op = CC_OP_CONST0 + val;
433 }
434
435 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
436 {
437 tcg_gen_discard_i64(cc_src);
438 tcg_gen_mov_i64(cc_dst, dst);
439 tcg_gen_discard_i64(cc_vr);
440 s->cc_op = op;
441 }
442
443 static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
444 {
445 tcg_gen_discard_i64(cc_src);
446 tcg_gen_extu_i32_i64(cc_dst, dst);
447 tcg_gen_discard_i64(cc_vr);
448 s->cc_op = op;
449 }
450
451 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
452 TCGv_i64 dst)
453 {
454 tcg_gen_mov_i64(cc_src, src);
455 tcg_gen_mov_i64(cc_dst, dst);
456 tcg_gen_discard_i64(cc_vr);
457 s->cc_op = op;
458 }
459
460 static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
461 TCGv_i32 dst)
462 {
463 tcg_gen_extu_i32_i64(cc_src, src);
464 tcg_gen_extu_i32_i64(cc_dst, dst);
465 tcg_gen_discard_i64(cc_vr);
466 s->cc_op = op;
467 }
468
469 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
470 TCGv_i64 dst, TCGv_i64 vr)
471 {
472 tcg_gen_mov_i64(cc_src, src);
473 tcg_gen_mov_i64(cc_dst, dst);
474 tcg_gen_mov_i64(cc_vr, vr);
475 s->cc_op = op;
476 }
477
478 static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
479 {
480 gen_op_update1_cc_i32(s, CC_OP_NZ, val);
481 }
482
483 static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
484 {
485 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
486 }
487
488 static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
489 enum cc_op cond)
490 {
491 gen_op_update2_cc_i32(s, cond, v1, v2);
492 }
493
494 static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
495 enum cc_op cond)
496 {
497 gen_op_update2_cc_i64(s, cond, v1, v2);
498 }
499
500 static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
501 {
502 cmp_32(s, v1, v2, CC_OP_LTGT_32);
503 }
504
505 static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
506 {
507 cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
508 }
509
510 static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
511 {
512 /* XXX optimize for the constant? put it in s? */
513 TCGv_i32 tmp = tcg_const_i32(v2);
514 cmp_32(s, v1, tmp, CC_OP_LTGT_32);
515 tcg_temp_free_i32(tmp);
516 }
517
518 static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
519 {
520 TCGv_i32 tmp = tcg_const_i32(v2);
521 cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
522 tcg_temp_free_i32(tmp);
523 }
524
525 static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
526 {
527 cmp_64(s, v1, v2, CC_OP_LTGT_64);
528 }
529
530 static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
531 {
532 cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
533 }
534
535 static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
536 {
537 TCGv_i64 tmp = tcg_const_i64(v2);
538 cmp_s64(s, v1, tmp);
539 tcg_temp_free_i64(tmp);
540 }
541
542 static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
543 {
544 TCGv_i64 tmp = tcg_const_i64(v2);
545 cmp_u64(s, v1, tmp);
546 tcg_temp_free_i64(tmp);
547 }
548
549 static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
550 {
551 gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
552 }
553
554 static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
555 {
556 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
557 }
558
559 /* CC value is in env->cc_op */
560 static inline void set_cc_static(DisasContext *s)
561 {
562 tcg_gen_discard_i64(cc_src);
563 tcg_gen_discard_i64(cc_dst);
564 tcg_gen_discard_i64(cc_vr);
565 s->cc_op = CC_OP_STATIC;
566 }
567
568 static inline void gen_op_set_cc_op(DisasContext *s)
569 {
570 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
571 tcg_gen_movi_i32(cc_op, s->cc_op);
572 }
573 }
574
575 static inline void gen_update_cc_op(DisasContext *s)
576 {
577 gen_op_set_cc_op(s);
578 }
579
580 /* calculates cc into cc_op */
581 static void gen_op_calc_cc(DisasContext *s)
582 {
583 TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
584 TCGv_i64 dummy = tcg_const_i64(0);
585
586 switch (s->cc_op) {
587 case CC_OP_CONST0:
588 case CC_OP_CONST1:
589 case CC_OP_CONST2:
590 case CC_OP_CONST3:
591 /* s->cc_op is the cc value */
592 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
593 break;
594 case CC_OP_STATIC:
595 /* env->cc_op already is the cc value */
596 break;
597 case CC_OP_NZ:
598 case CC_OP_ABS_64:
599 case CC_OP_NABS_64:
600 case CC_OP_ABS_32:
601 case CC_OP_NABS_32:
602 case CC_OP_LTGT0_32:
603 case CC_OP_LTGT0_64:
604 case CC_OP_COMP_32:
605 case CC_OP_COMP_64:
606 case CC_OP_NZ_F32:
607 case CC_OP_NZ_F64:
608 /* 1 argument */
609 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
610 break;
611 case CC_OP_ICM:
612 case CC_OP_LTGT_32:
613 case CC_OP_LTGT_64:
614 case CC_OP_LTUGTU_32:
615 case CC_OP_LTUGTU_64:
616 case CC_OP_TM_32:
617 case CC_OP_TM_64:
618 case CC_OP_SLA_32:
619 case CC_OP_SLA_64:
620 case CC_OP_NZ_F128:
621 /* 2 arguments */
622 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
623 break;
624 case CC_OP_ADD_64:
625 case CC_OP_ADDU_64:
626 case CC_OP_ADDC_64:
627 case CC_OP_SUB_64:
628 case CC_OP_SUBU_64:
629 case CC_OP_SUBB_64:
630 case CC_OP_ADD_32:
631 case CC_OP_ADDU_32:
632 case CC_OP_ADDC_32:
633 case CC_OP_SUB_32:
634 case CC_OP_SUBU_32:
635 case CC_OP_SUBB_32:
636 /* 3 arguments */
637 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
638 break;
639 case CC_OP_DYNAMIC:
640 /* unknown operation - assume 3 arguments and cc_op in env */
641 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
642 break;
643 default:
644 tcg_abort();
645 }
646
647 tcg_temp_free_i32(local_cc_op);
648 tcg_temp_free_i64(dummy);
649
650 /* We now have cc in cc_op as constant */
651 set_cc_static(s);
652 }
653
654 static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
655 {
656 debug_insn(insn);
657
658 *r1 = (insn >> 4) & 0xf;
659 *r2 = insn & 0xf;
660 }
661
662 static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
663 int *x2, int *b2, int *d2)
664 {
665 debug_insn(insn);
666
667 *r1 = (insn >> 20) & 0xf;
668 *x2 = (insn >> 16) & 0xf;
669 *b2 = (insn >> 12) & 0xf;
670 *d2 = insn & 0xfff;
671
672 return get_address(s, *x2, *b2, *d2);
673 }
674
675 static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
676 int *b2, int *d2)
677 {
678 debug_insn(insn);
679
680 *r1 = (insn >> 20) & 0xf;
681 /* aka m3 */
682 *r3 = (insn >> 16) & 0xf;
683 *b2 = (insn >> 12) & 0xf;
684 *d2 = insn & 0xfff;
685 }
686
687 static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
688 int *b1, int *d1)
689 {
690 debug_insn(insn);
691
692 *i2 = (insn >> 16) & 0xff;
693 *b1 = (insn >> 12) & 0xf;
694 *d1 = insn & 0xfff;
695
696 return get_address(s, 0, *b1, *d1);
697 }
698
699 static int use_goto_tb(DisasContext *s, uint64_t dest)
700 {
701 /* NOTE: we handle the case where the TB spans two pages here */
702 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
703 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
704 && !s->singlestep_enabled
705 && !(s->tb->cflags & CF_LAST_IO));
706 }
707
708 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
709 {
710 gen_update_cc_op(s);
711
712 if (use_goto_tb(s, pc)) {
713 tcg_gen_goto_tb(tb_num);
714 tcg_gen_movi_i64(psw_addr, pc);
715 tcg_gen_exit_tb((tcg_target_long)s->tb + tb_num);
716 } else {
717 /* jump to another page: currently not optimized */
718 tcg_gen_movi_i64(psw_addr, pc);
719 tcg_gen_exit_tb(0);
720 }
721 }
722
723 static inline void account_noninline_branch(DisasContext *s, int cc_op)
724 {
725 #ifdef DEBUG_INLINE_BRANCHES
726 inline_branch_miss[cc_op]++;
727 #endif
728 }
729
730 static inline void account_inline_branch(DisasContext *s, int cc_op)
731 {
732 #ifdef DEBUG_INLINE_BRANCHES
733 inline_branch_hit[cc_op]++;
734 #endif
735 }
736
737 /* Table of mask values to comparison codes, given a comparison as input.
738 For a true comparison CC=3 will never be set, but we treat this
739 conservatively for possible use when CC=3 indicates overflow. */
740 static const TCGCond ltgt_cond[16] = {
741 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
742 TCG_COND_GT, TCG_COND_NEVER, /* | | GT | x */
743 TCG_COND_LT, TCG_COND_NEVER, /* | LT | | x */
744 TCG_COND_NE, TCG_COND_NEVER, /* | LT | GT | x */
745 TCG_COND_EQ, TCG_COND_NEVER, /* EQ | | | x */
746 TCG_COND_GE, TCG_COND_NEVER, /* EQ | | GT | x */
747 TCG_COND_LE, TCG_COND_NEVER, /* EQ | LT | | x */
748 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
749 };
750
751 /* Table of mask values to comparison codes, given a logic op as input.
752 For such, only CC=0 and CC=1 should be possible. */
753 static const TCGCond nz_cond[16] = {
754 /* | | x | x */
755 TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER, TCG_COND_NEVER,
756 /* | NE | x | x */
757 TCG_COND_NE, TCG_COND_NE, TCG_COND_NE, TCG_COND_NE,
758 /* EQ | | x | x */
759 TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ, TCG_COND_EQ,
760 /* EQ | NE | x | x */
761 TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS, TCG_COND_ALWAYS,
762 };
763
764 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
765 details required to generate a TCG comparison. */
766 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
767 {
768 TCGCond cond;
769 enum cc_op old_cc_op = s->cc_op;
770
771 if (mask == 15 || mask == 0) {
772 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
773 c->u.s32.a = cc_op;
774 c->u.s32.b = cc_op;
775 c->g1 = c->g2 = true;
776 c->is_64 = false;
777 return;
778 }
779
780 /* Find the TCG condition for the mask + cc op. */
781 switch (old_cc_op) {
782 case CC_OP_LTGT0_32:
783 case CC_OP_LTGT0_64:
784 case CC_OP_LTGT_32:
785 case CC_OP_LTGT_64:
786 cond = ltgt_cond[mask];
787 if (cond == TCG_COND_NEVER) {
788 goto do_dynamic;
789 }
790 account_inline_branch(s, old_cc_op);
791 break;
792
793 case CC_OP_LTUGTU_32:
794 case CC_OP_LTUGTU_64:
795 cond = tcg_unsigned_cond(ltgt_cond[mask]);
796 if (cond == TCG_COND_NEVER) {
797 goto do_dynamic;
798 }
799 account_inline_branch(s, old_cc_op);
800 break;
801
802 case CC_OP_NZ:
803 cond = nz_cond[mask];
804 if (cond == TCG_COND_NEVER) {
805 goto do_dynamic;
806 }
807 account_inline_branch(s, old_cc_op);
808 break;
809
810 case CC_OP_TM_32:
811 case CC_OP_TM_64:
812 switch (mask) {
813 case 8:
814 cond = TCG_COND_EQ;
815 break;
816 case 4 | 2 | 1:
817 cond = TCG_COND_NE;
818 break;
819 default:
820 goto do_dynamic;
821 }
822 account_inline_branch(s, old_cc_op);
823 break;
824
825 case CC_OP_ICM:
826 switch (mask) {
827 case 8:
828 cond = TCG_COND_EQ;
829 break;
830 case 4 | 2 | 1:
831 case 4 | 2:
832 cond = TCG_COND_NE;
833 break;
834 default:
835 goto do_dynamic;
836 }
837 account_inline_branch(s, old_cc_op);
838 break;
839
840 default:
841 do_dynamic:
842 /* Calculate cc value. */
843 gen_op_calc_cc(s);
844 /* FALLTHRU */
845
846 case CC_OP_STATIC:
847 /* Jump based on CC. We'll load up the real cond below;
848 the assignment here merely avoids a compiler warning. */
849 account_noninline_branch(s, old_cc_op);
850 old_cc_op = CC_OP_STATIC;
851 cond = TCG_COND_NEVER;
852 break;
853 }
854
855 /* Load up the arguments of the comparison. */
856 c->is_64 = true;
857 c->g1 = c->g2 = false;
858 switch (old_cc_op) {
859 case CC_OP_LTGT0_32:
860 c->is_64 = false;
861 c->u.s32.a = tcg_temp_new_i32();
862 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
863 c->u.s32.b = tcg_const_i32(0);
864 break;
865 case CC_OP_LTGT_32:
866 case CC_OP_LTUGTU_32:
867 c->is_64 = false;
868 c->u.s32.a = tcg_temp_new_i32();
869 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
870 c->u.s32.b = tcg_temp_new_i32();
871 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
872 break;
873
874 case CC_OP_LTGT0_64:
875 case CC_OP_NZ:
876 c->u.s64.a = cc_dst;
877 c->u.s64.b = tcg_const_i64(0);
878 c->g1 = true;
879 break;
880 case CC_OP_LTGT_64:
881 case CC_OP_LTUGTU_64:
882 c->u.s64.a = cc_src;
883 c->u.s64.b = cc_dst;
884 c->g1 = c->g2 = true;
885 break;
886
887 case CC_OP_TM_32:
888 case CC_OP_TM_64:
889 case CC_OP_ICM:
890 c->u.s64.a = tcg_temp_new_i64();
891 c->u.s64.b = tcg_const_i64(0);
892 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
893 break;
894
895 case CC_OP_STATIC:
896 c->is_64 = false;
897 c->u.s32.a = cc_op;
898 c->g1 = true;
899 switch (mask) {
900 case 0x8 | 0x4 | 0x2: /* cc != 3 */
901 cond = TCG_COND_NE;
902 c->u.s32.b = tcg_const_i32(3);
903 break;
904 case 0x8 | 0x4 | 0x1: /* cc != 2 */
905 cond = TCG_COND_NE;
906 c->u.s32.b = tcg_const_i32(2);
907 break;
908 case 0x8 | 0x2 | 0x1: /* cc != 1 */
909 cond = TCG_COND_NE;
910 c->u.s32.b = tcg_const_i32(1);
911 break;
912 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
913 cond = TCG_COND_EQ;
914 c->g1 = false;
915 c->u.s32.a = tcg_temp_new_i32();
916 c->u.s32.b = tcg_const_i32(0);
917 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
918 break;
919 case 0x8 | 0x4: /* cc < 2 */
920 cond = TCG_COND_LTU;
921 c->u.s32.b = tcg_const_i32(2);
922 break;
923 case 0x8: /* cc == 0 */
924 cond = TCG_COND_EQ;
925 c->u.s32.b = tcg_const_i32(0);
926 break;
927 case 0x4 | 0x2 | 0x1: /* cc != 0 */
928 cond = TCG_COND_NE;
929 c->u.s32.b = tcg_const_i32(0);
930 break;
931 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
932 cond = TCG_COND_NE;
933 c->g1 = false;
934 c->u.s32.a = tcg_temp_new_i32();
935 c->u.s32.b = tcg_const_i32(0);
936 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
937 break;
938 case 0x4: /* cc == 1 */
939 cond = TCG_COND_EQ;
940 c->u.s32.b = tcg_const_i32(1);
941 break;
942 case 0x2 | 0x1: /* cc > 1 */
943 cond = TCG_COND_GTU;
944 c->u.s32.b = tcg_const_i32(1);
945 break;
946 case 0x2: /* cc == 2 */
947 cond = TCG_COND_EQ;
948 c->u.s32.b = tcg_const_i32(2);
949 break;
950 case 0x1: /* cc == 3 */
951 cond = TCG_COND_EQ;
952 c->u.s32.b = tcg_const_i32(3);
953 break;
954 default:
955 /* CC is masked by something else: (8 >> cc) & mask. */
956 cond = TCG_COND_NE;
957 c->g1 = false;
958 c->u.s32.a = tcg_const_i32(8);
959 c->u.s32.b = tcg_const_i32(0);
960 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
961 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
962 break;
963 }
964 break;
965
966 default:
967 abort();
968 }
969 c->cond = cond;
970 }
971
972 static void free_compare(DisasCompare *c)
973 {
974 if (!c->g1) {
975 if (c->is_64) {
976 tcg_temp_free_i64(c->u.s64.a);
977 } else {
978 tcg_temp_free_i32(c->u.s32.a);
979 }
980 }
981 if (!c->g2) {
982 if (c->is_64) {
983 tcg_temp_free_i64(c->u.s64.b);
984 } else {
985 tcg_temp_free_i32(c->u.s32.b);
986 }
987 }
988 }
989
990 static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,
991 int x2, int b2, int d2, int r1b)
992 {
993 TCGv_i32 tmp_r1, tmp32;
994 TCGv_i64 addr, tmp;
995 addr = get_address(s, x2, b2, d2);
996 tmp_r1 = tcg_const_i32(r1);
997 switch (op) {
998 case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
999 tmp = tcg_temp_new_i64();
1000 tmp32 = tcg_temp_new_i32();
1001 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1002 tcg_gen_trunc_i64_i32(tmp32, tmp);
1003 gen_helper_deb(cpu_env, tmp_r1, tmp32);
1004 tcg_temp_free_i64(tmp);
1005 tcg_temp_free_i32(tmp32);
1006 break;
1007 case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
1008 potential_page_fault(s);
1009 gen_helper_tceb(cc_op, cpu_env, tmp_r1, addr);
1010 set_cc_static(s);
1011 break;
1012 case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
1013 potential_page_fault(s);
1014 gen_helper_tcdb(cc_op, cpu_env, tmp_r1, addr);
1015 set_cc_static(s);
1016 break;
1017 case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
1018 potential_page_fault(s);
1019 gen_helper_tcxb(cc_op, cpu_env, tmp_r1, addr);
1020 set_cc_static(s);
1021 break;
1022 case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
1023 tmp = tcg_temp_new_i64();
1024 tmp32 = tcg_temp_new_i32();
1025 tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
1026 tcg_gen_trunc_i64_i32(tmp32, tmp);
1027 gen_helper_meeb(cpu_env, tmp_r1, tmp32);
1028 tcg_temp_free_i64(tmp);
1029 tcg_temp_free_i32(tmp32);
1030 break;
1031 case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
1032 potential_page_fault(s);
1033 gen_helper_mdb(cpu_env, tmp_r1, addr);
1034 break;
1035 case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
1036 potential_page_fault(s);
1037 gen_helper_ddb(cpu_env, tmp_r1, addr);
1038 break;
1039 case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
1040 /* for RXF insns, r1 is R3 and r1b is R1 */
1041 tmp32 = tcg_const_i32(r1b);
1042 potential_page_fault(s);
1043 gen_helper_madb(cpu_env, tmp32, addr, tmp_r1);
1044 tcg_temp_free_i32(tmp32);
1045 break;
1046 default:
1047 LOG_DISAS("illegal ed operation 0x%x\n", op);
1048 gen_illegal_opcode(s);
1049 return;
1050 }
1051 tcg_temp_free_i32(tmp_r1);
1052 tcg_temp_free_i64(addr);
1053 }
1054
1055 static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
1056 uint32_t insn)
1057 {
1058 TCGv_i64 tmp, tmp2, tmp3;
1059 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1060 int r1, r2;
1061 #ifndef CONFIG_USER_ONLY
1062 int r3, d2, b2;
1063 #endif
1064
1065 r1 = (insn >> 4) & 0xf;
1066 r2 = insn & 0xf;
1067
1068 LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1069
1070 switch (op) {
1071 case 0x22: /* IPM R1 [RRE] */
1072 tmp32_1 = tcg_const_i32(r1);
1073 gen_op_calc_cc(s);
1074 gen_helper_ipm(cpu_env, cc_op, tmp32_1);
1075 tcg_temp_free_i32(tmp32_1);
1076 break;
1077 case 0x41: /* CKSM R1,R2 [RRE] */
1078 tmp32_1 = tcg_const_i32(r1);
1079 tmp32_2 = tcg_const_i32(r2);
1080 potential_page_fault(s);
1081 gen_helper_cksm(cpu_env, tmp32_1, tmp32_2);
1082 tcg_temp_free_i32(tmp32_1);
1083 tcg_temp_free_i32(tmp32_2);
1084 gen_op_movi_cc(s, 0);
1085 break;
1086 case 0x4e: /* SAR R1,R2 [RRE] */
1087 tmp32_1 = load_reg32(r2);
1088 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
1089 tcg_temp_free_i32(tmp32_1);
1090 break;
1091 case 0x4f: /* EAR R1,R2 [RRE] */
1092 tmp32_1 = tcg_temp_new_i32();
1093 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
1094 store_reg32(r1, tmp32_1);
1095 tcg_temp_free_i32(tmp32_1);
1096 break;
1097 case 0x54: /* MVPG R1,R2 [RRE] */
1098 tmp = load_reg(0);
1099 tmp2 = load_reg(r1);
1100 tmp3 = load_reg(r2);
1101 potential_page_fault(s);
1102 gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
1103 tcg_temp_free_i64(tmp);
1104 tcg_temp_free_i64(tmp2);
1105 tcg_temp_free_i64(tmp3);
1106 /* XXX check CCO bit and set CC accordingly */
1107 gen_op_movi_cc(s, 0);
1108 break;
1109 case 0x55: /* MVST R1,R2 [RRE] */
1110 tmp32_1 = load_reg32(0);
1111 tmp32_2 = tcg_const_i32(r1);
1112 tmp32_3 = tcg_const_i32(r2);
1113 potential_page_fault(s);
1114 gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
1115 tcg_temp_free_i32(tmp32_1);
1116 tcg_temp_free_i32(tmp32_2);
1117 tcg_temp_free_i32(tmp32_3);
1118 gen_op_movi_cc(s, 1);
1119 break;
1120 case 0x5d: /* CLST R1,R2 [RRE] */
1121 tmp32_1 = load_reg32(0);
1122 tmp32_2 = tcg_const_i32(r1);
1123 tmp32_3 = tcg_const_i32(r2);
1124 potential_page_fault(s);
1125 gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1126 set_cc_static(s);
1127 tcg_temp_free_i32(tmp32_1);
1128 tcg_temp_free_i32(tmp32_2);
1129 tcg_temp_free_i32(tmp32_3);
1130 break;
1131 case 0x5e: /* SRST R1,R2 [RRE] */
1132 tmp32_1 = load_reg32(0);
1133 tmp32_2 = tcg_const_i32(r1);
1134 tmp32_3 = tcg_const_i32(r2);
1135 potential_page_fault(s);
1136 gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1137 set_cc_static(s);
1138 tcg_temp_free_i32(tmp32_1);
1139 tcg_temp_free_i32(tmp32_2);
1140 tcg_temp_free_i32(tmp32_3);
1141 break;
1142
1143 #ifndef CONFIG_USER_ONLY
1144 case 0x02: /* STIDP D2(B2) [S] */
1145 /* Store CPU ID */
1146 check_privileged(s);
1147 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1148 tmp = get_address(s, 0, b2, d2);
1149 potential_page_fault(s);
1150 gen_helper_stidp(cpu_env, tmp);
1151 tcg_temp_free_i64(tmp);
1152 break;
1153 case 0x04: /* SCK D2(B2) [S] */
1154 /* Set Clock */
1155 check_privileged(s);
1156 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1157 tmp = get_address(s, 0, b2, d2);
1158 potential_page_fault(s);
1159 gen_helper_sck(cc_op, tmp);
1160 set_cc_static(s);
1161 tcg_temp_free_i64(tmp);
1162 break;
1163 case 0x05: /* STCK D2(B2) [S] */
1164 /* Store Clock */
1165 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1166 tmp = get_address(s, 0, b2, d2);
1167 potential_page_fault(s);
1168 gen_helper_stck(cc_op, cpu_env, tmp);
1169 set_cc_static(s);
1170 tcg_temp_free_i64(tmp);
1171 break;
1172 case 0x06: /* SCKC D2(B2) [S] */
1173 /* Set Clock Comparator */
1174 check_privileged(s);
1175 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1176 tmp = get_address(s, 0, b2, d2);
1177 potential_page_fault(s);
1178 gen_helper_sckc(cpu_env, tmp);
1179 tcg_temp_free_i64(tmp);
1180 break;
1181 case 0x07: /* STCKC D2(B2) [S] */
1182 /* Store Clock Comparator */
1183 check_privileged(s);
1184 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1185 tmp = get_address(s, 0, b2, d2);
1186 potential_page_fault(s);
1187 gen_helper_stckc(cpu_env, tmp);
1188 tcg_temp_free_i64(tmp);
1189 break;
1190 case 0x08: /* SPT D2(B2) [S] */
1191 /* Set CPU Timer */
1192 check_privileged(s);
1193 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1194 tmp = get_address(s, 0, b2, d2);
1195 potential_page_fault(s);
1196 gen_helper_spt(cpu_env, tmp);
1197 tcg_temp_free_i64(tmp);
1198 break;
1199 case 0x09: /* STPT D2(B2) [S] */
1200 /* Store CPU Timer */
1201 check_privileged(s);
1202 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1203 tmp = get_address(s, 0, b2, d2);
1204 potential_page_fault(s);
1205 gen_helper_stpt(cpu_env, tmp);
1206 tcg_temp_free_i64(tmp);
1207 break;
1208 case 0x0a: /* SPKA D2(B2) [S] */
1209 /* Set PSW Key from Address */
1210 check_privileged(s);
1211 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1212 tmp = get_address(s, 0, b2, d2);
1213 tmp2 = tcg_temp_new_i64();
1214 tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
1215 tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
1216 tcg_gen_or_i64(psw_mask, tmp2, tmp);
1217 tcg_temp_free_i64(tmp2);
1218 tcg_temp_free_i64(tmp);
1219 break;
1220 case 0x0d: /* PTLB [S] */
1221 /* Purge TLB */
1222 check_privileged(s);
1223 gen_helper_ptlb(cpu_env);
1224 break;
1225 case 0x10: /* SPX D2(B2) [S] */
1226 /* Set Prefix Register */
1227 check_privileged(s);
1228 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1229 tmp = get_address(s, 0, b2, d2);
1230 potential_page_fault(s);
1231 gen_helper_spx(cpu_env, tmp);
1232 tcg_temp_free_i64(tmp);
1233 break;
1234 case 0x11: /* STPX D2(B2) [S] */
1235 /* Store Prefix */
1236 check_privileged(s);
1237 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1238 tmp = get_address(s, 0, b2, d2);
1239 tmp2 = tcg_temp_new_i64();
1240 tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
1241 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1242 tcg_temp_free_i64(tmp);
1243 tcg_temp_free_i64(tmp2);
1244 break;
1245 case 0x12: /* STAP D2(B2) [S] */
1246 /* Store CPU Address */
1247 check_privileged(s);
1248 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1249 tmp = get_address(s, 0, b2, d2);
1250 tmp2 = tcg_temp_new_i64();
1251 tmp32_1 = tcg_temp_new_i32();
1252 tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
1253 tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1254 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1255 tcg_temp_free_i64(tmp);
1256 tcg_temp_free_i64(tmp2);
1257 tcg_temp_free_i32(tmp32_1);
1258 break;
1259 case 0x21: /* IPTE R1,R2 [RRE] */
1260 /* Invalidate PTE */
1261 check_privileged(s);
1262 r1 = (insn >> 4) & 0xf;
1263 r2 = insn & 0xf;
1264 tmp = load_reg(r1);
1265 tmp2 = load_reg(r2);
1266 gen_helper_ipte(cpu_env, tmp, tmp2);
1267 tcg_temp_free_i64(tmp);
1268 tcg_temp_free_i64(tmp2);
1269 break;
1270 case 0x29: /* ISKE R1,R2 [RRE] */
1271 /* Insert Storage Key Extended */
1272 check_privileged(s);
1273 r1 = (insn >> 4) & 0xf;
1274 r2 = insn & 0xf;
1275 tmp = load_reg(r2);
1276 tmp2 = tcg_temp_new_i64();
1277 gen_helper_iske(tmp2, cpu_env, tmp);
1278 store_reg(r1, tmp2);
1279 tcg_temp_free_i64(tmp);
1280 tcg_temp_free_i64(tmp2);
1281 break;
1282 case 0x2a: /* RRBE R1,R2 [RRE] */
1283 /* Set Storage Key Extended */
1284 check_privileged(s);
1285 r1 = (insn >> 4) & 0xf;
1286 r2 = insn & 0xf;
1287 tmp32_1 = load_reg32(r1);
1288 tmp = load_reg(r2);
1289 gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
1290 set_cc_static(s);
1291 tcg_temp_free_i32(tmp32_1);
1292 tcg_temp_free_i64(tmp);
1293 break;
1294 case 0x2b: /* SSKE R1,R2 [RRE] */
1295 /* Set Storage Key Extended */
1296 check_privileged(s);
1297 r1 = (insn >> 4) & 0xf;
1298 r2 = insn & 0xf;
1299 tmp32_1 = load_reg32(r1);
1300 tmp = load_reg(r2);
1301 gen_helper_sske(cpu_env, tmp32_1, tmp);
1302 tcg_temp_free_i32(tmp32_1);
1303 tcg_temp_free_i64(tmp);
1304 break;
1305 case 0x34: /* STCH ? */
1306 /* Store Subchannel */
1307 check_privileged(s);
1308 gen_op_movi_cc(s, 3);
1309 break;
1310 case 0x46: /* STURA R1,R2 [RRE] */
1311 /* Store Using Real Address */
1312 check_privileged(s);
1313 r1 = (insn >> 4) & 0xf;
1314 r2 = insn & 0xf;
1315 tmp32_1 = load_reg32(r1);
1316 tmp = load_reg(r2);
1317 potential_page_fault(s);
1318 gen_helper_stura(cpu_env, tmp, tmp32_1);
1319 tcg_temp_free_i32(tmp32_1);
1320 tcg_temp_free_i64(tmp);
1321 break;
1322 case 0x50: /* CSP R1,R2 [RRE] */
1323 /* Compare And Swap And Purge */
1324 check_privileged(s);
1325 r1 = (insn >> 4) & 0xf;
1326 r2 = insn & 0xf;
1327 tmp32_1 = tcg_const_i32(r1);
1328 tmp32_2 = tcg_const_i32(r2);
1329 gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
1330 set_cc_static(s);
1331 tcg_temp_free_i32(tmp32_1);
1332 tcg_temp_free_i32(tmp32_2);
1333 break;
1334 case 0x5f: /* CHSC ? */
1335 /* Channel Subsystem Call */
1336 check_privileged(s);
1337 gen_op_movi_cc(s, 3);
1338 break;
1339 case 0x78: /* STCKE D2(B2) [S] */
1340 /* Store Clock Extended */
1341 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1342 tmp = get_address(s, 0, b2, d2);
1343 potential_page_fault(s);
1344 gen_helper_stcke(cc_op, cpu_env, tmp);
1345 set_cc_static(s);
1346 tcg_temp_free_i64(tmp);
1347 break;
1348 case 0x79: /* SACF D2(B2) [S] */
1349 /* Set Address Space Control Fast */
1350 check_privileged(s);
1351 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1352 tmp = get_address(s, 0, b2, d2);
1353 potential_page_fault(s);
1354 gen_helper_sacf(cpu_env, tmp);
1355 tcg_temp_free_i64(tmp);
1356 /* addressing mode has changed, so end the block */
1357 s->pc = s->next_pc;
1358 update_psw_addr(s);
1359 s->is_jmp = DISAS_JUMP;
1360 break;
1361 case 0x7d: /* STSI D2,(B2) [S] */
1362 check_privileged(s);
1363 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1364 tmp = get_address(s, 0, b2, d2);
1365 tmp32_1 = load_reg32(0);
1366 tmp32_2 = load_reg32(1);
1367 potential_page_fault(s);
1368 gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
1369 set_cc_static(s);
1370 tcg_temp_free_i64(tmp);
1371 tcg_temp_free_i32(tmp32_1);
1372 tcg_temp_free_i32(tmp32_2);
1373 break;
1374 case 0x9d: /* LFPC D2(B2) [S] */
1375 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1376 tmp = get_address(s, 0, b2, d2);
1377 tmp2 = tcg_temp_new_i64();
1378 tmp32_1 = tcg_temp_new_i32();
1379 tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
1380 tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1381 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1382 tcg_temp_free_i64(tmp);
1383 tcg_temp_free_i64(tmp2);
1384 tcg_temp_free_i32(tmp32_1);
1385 break;
1386 case 0xb1: /* STFL D2(B2) [S] */
1387 /* Store Facility List (CPU features) at 200 */
1388 check_privileged(s);
1389 tmp2 = tcg_const_i64(0xc0000000);
1390 tmp = tcg_const_i64(200);
1391 tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
1392 tcg_temp_free_i64(tmp2);
1393 tcg_temp_free_i64(tmp);
1394 break;
1395 case 0xb2: /* LPSWE D2(B2) [S] */
1396 /* Load PSW Extended */
1397 check_privileged(s);
1398 decode_rs(s, insn, &r1, &r3, &b2, &d2);
1399 tmp = get_address(s, 0, b2, d2);
1400 tmp2 = tcg_temp_new_i64();
1401 tmp3 = tcg_temp_new_i64();
1402 tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
1403 tcg_gen_addi_i64(tmp, tmp, 8);
1404 tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
1405 gen_helper_load_psw(cpu_env, tmp2, tmp3);
1406 /* we need to keep cc_op intact */
1407 s->is_jmp = DISAS_JUMP;
1408 tcg_temp_free_i64(tmp);
1409 tcg_temp_free_i64(tmp2);
1410 tcg_temp_free_i64(tmp3);
1411 break;
1412 case 0x20: /* SERVC R1,R2 [RRE] */
1413 /* SCLP Service call (PV hypercall) */
1414 check_privileged(s);
1415 potential_page_fault(s);
1416 tmp32_1 = load_reg32(r2);
1417 tmp = load_reg(r1);
1418 gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
1419 set_cc_static(s);
1420 tcg_temp_free_i32(tmp32_1);
1421 tcg_temp_free_i64(tmp);
1422 break;
1423 #endif
1424 default:
1425 LOG_DISAS("illegal b2 operation 0x%x\n", op);
1426 gen_illegal_opcode(s);
1427 break;
1428 }
1429 }
1430
1431 static void disas_b3(CPUS390XState *env, DisasContext *s, int op, int m3,
1432 int r1, int r2)
1433 {
1434 TCGv_i64 tmp;
1435 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1436 LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2);
1437 #define FP_HELPER(i) \
1438 tmp32_1 = tcg_const_i32(r1); \
1439 tmp32_2 = tcg_const_i32(r2); \
1440 gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
1441 tcg_temp_free_i32(tmp32_1); \
1442 tcg_temp_free_i32(tmp32_2);
1443
1444 #define FP_HELPER_CC(i) \
1445 tmp32_1 = tcg_const_i32(r1); \
1446 tmp32_2 = tcg_const_i32(r2); \
1447 gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
1448 set_cc_static(s); \
1449 tcg_temp_free_i32(tmp32_1); \
1450 tcg_temp_free_i32(tmp32_2);
1451
1452 switch (op) {
1453 case 0x0: /* LPEBR R1,R2 [RRE] */
1454 FP_HELPER_CC(lpebr);
1455 break;
1456 case 0x3: /* LCEBR R1,R2 [RRE] */
1457 FP_HELPER_CC(lcebr);
1458 break;
1459 case 0xd: /* DEBR R1,R2 [RRE] */
1460 FP_HELPER(debr);
1461 break;
1462 case 0x10: /* LPDBR R1,R2 [RRE] */
1463 FP_HELPER_CC(lpdbr);
1464 break;
1465 case 0x13: /* LCDBR R1,R2 [RRE] */
1466 FP_HELPER_CC(lcdbr);
1467 break;
1468 case 0x15: /* SQBDR R1,R2 [RRE] */
1469 FP_HELPER(sqdbr);
1470 break;
1471 case 0x17: /* MEEBR R1,R2 [RRE] */
1472 FP_HELPER(meebr);
1473 break;
1474 case 0x1c: /* MDBR R1,R2 [RRE] */
1475 FP_HELPER(mdbr);
1476 break;
1477 case 0x1d: /* DDBR R1,R2 [RRE] */
1478 FP_HELPER(ddbr);
1479 break;
1480 case 0xe: /* MAEBR R1,R3,R2 [RRF] */
1481 case 0x1e: /* MADBR R1,R3,R2 [RRF] */
1482 case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
1483 /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
1484 tmp32_1 = tcg_const_i32(m3);
1485 tmp32_2 = tcg_const_i32(r2);
1486 tmp32_3 = tcg_const_i32(r1);
1487 switch (op) {
1488 case 0xe:
1489 gen_helper_maebr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1490 break;
1491 case 0x1e:
1492 gen_helper_madbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1493 break;
1494 case 0x1f:
1495 gen_helper_msdbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
1496 break;
1497 default:
1498 tcg_abort();
1499 }
1500 tcg_temp_free_i32(tmp32_1);
1501 tcg_temp_free_i32(tmp32_2);
1502 tcg_temp_free_i32(tmp32_3);
1503 break;
1504 case 0x40: /* LPXBR R1,R2 [RRE] */
1505 FP_HELPER_CC(lpxbr);
1506 break;
1507 case 0x43: /* LCXBR R1,R2 [RRE] */
1508 FP_HELPER_CC(lcxbr);
1509 break;
1510 case 0x4c: /* MXBR R1,R2 [RRE] */
1511 FP_HELPER(mxbr);
1512 break;
1513 case 0x4d: /* DXBR R1,R2 [RRE] */
1514 FP_HELPER(dxbr);
1515 break;
1516 case 0x65: /* LXR R1,R2 [RRE] */
1517 tmp = load_freg(r2);
1518 store_freg(r1, tmp);
1519 tcg_temp_free_i64(tmp);
1520 tmp = load_freg(r2 + 2);
1521 store_freg(r1 + 2, tmp);
1522 tcg_temp_free_i64(tmp);
1523 break;
1524 case 0x74: /* LZER R1 [RRE] */
1525 tmp32_1 = tcg_const_i32(r1);
1526 gen_helper_lzer(cpu_env, tmp32_1);
1527 tcg_temp_free_i32(tmp32_1);
1528 break;
1529 case 0x75: /* LZDR R1 [RRE] */
1530 tmp32_1 = tcg_const_i32(r1);
1531 gen_helper_lzdr(cpu_env, tmp32_1);
1532 tcg_temp_free_i32(tmp32_1);
1533 break;
1534 case 0x76: /* LZXR R1 [RRE] */
1535 tmp32_1 = tcg_const_i32(r1);
1536 gen_helper_lzxr(cpu_env, tmp32_1);
1537 tcg_temp_free_i32(tmp32_1);
1538 break;
1539 case 0x84: /* SFPC R1 [RRE] */
1540 tmp32_1 = load_reg32(r1);
1541 tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
1542 tcg_temp_free_i32(tmp32_1);
1543 break;
1544 case 0x94: /* CEFBR R1,R2 [RRE] */
1545 case 0x95: /* CDFBR R1,R2 [RRE] */
1546 case 0x96: /* CXFBR R1,R2 [RRE] */
1547 tmp32_1 = tcg_const_i32(r1);
1548 tmp32_2 = load_reg32(r2);
1549 switch (op) {
1550 case 0x94:
1551 gen_helper_cefbr(cpu_env, tmp32_1, tmp32_2);
1552 break;
1553 case 0x95:
1554 gen_helper_cdfbr(cpu_env, tmp32_1, tmp32_2);
1555 break;
1556 case 0x96:
1557 gen_helper_cxfbr(cpu_env, tmp32_1, tmp32_2);
1558 break;
1559 default:
1560 tcg_abort();
1561 }
1562 tcg_temp_free_i32(tmp32_1);
1563 tcg_temp_free_i32(tmp32_2);
1564 break;
1565 case 0x98: /* CFEBR R1,R2 [RRE] */
1566 case 0x99: /* CFDBR R1,R2 [RRE] */
1567 case 0x9a: /* CFXBR R1,R2 [RRE] */
1568 tmp32_1 = tcg_const_i32(r1);
1569 tmp32_2 = tcg_const_i32(r2);
1570 tmp32_3 = tcg_const_i32(m3);
1571 switch (op) {
1572 case 0x98:
1573 gen_helper_cfebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1574 break;
1575 case 0x99:
1576 gen_helper_cfdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1577 break;
1578 case 0x9a:
1579 gen_helper_cfxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1580 break;
1581 default:
1582 tcg_abort();
1583 }
1584 set_cc_static(s);
1585 tcg_temp_free_i32(tmp32_1);
1586 tcg_temp_free_i32(tmp32_2);
1587 tcg_temp_free_i32(tmp32_3);
1588 break;
1589 case 0xa4: /* CEGBR R1,R2 [RRE] */
1590 case 0xa5: /* CDGBR R1,R2 [RRE] */
1591 tmp32_1 = tcg_const_i32(r1);
1592 tmp = load_reg(r2);
1593 switch (op) {
1594 case 0xa4:
1595 gen_helper_cegbr(cpu_env, tmp32_1, tmp);
1596 break;
1597 case 0xa5:
1598 gen_helper_cdgbr(cpu_env, tmp32_1, tmp);
1599 break;
1600 default:
1601 tcg_abort();
1602 }
1603 tcg_temp_free_i32(tmp32_1);
1604 tcg_temp_free_i64(tmp);
1605 break;
1606 case 0xa6: /* CXGBR R1,R2 [RRE] */
1607 tmp32_1 = tcg_const_i32(r1);
1608 tmp = load_reg(r2);
1609 gen_helper_cxgbr(cpu_env, tmp32_1, tmp);
1610 tcg_temp_free_i32(tmp32_1);
1611 tcg_temp_free_i64(tmp);
1612 break;
1613 case 0xa8: /* CGEBR R1,R2 [RRE] */
1614 tmp32_1 = tcg_const_i32(r1);
1615 tmp32_2 = tcg_const_i32(r2);
1616 tmp32_3 = tcg_const_i32(m3);
1617 gen_helper_cgebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1618 set_cc_static(s);
1619 tcg_temp_free_i32(tmp32_1);
1620 tcg_temp_free_i32(tmp32_2);
1621 tcg_temp_free_i32(tmp32_3);
1622 break;
1623 case 0xa9: /* CGDBR R1,R2 [RRE] */
1624 tmp32_1 = tcg_const_i32(r1);
1625 tmp32_2 = tcg_const_i32(r2);
1626 tmp32_3 = tcg_const_i32(m3);
1627 gen_helper_cgdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1628 set_cc_static(s);
1629 tcg_temp_free_i32(tmp32_1);
1630 tcg_temp_free_i32(tmp32_2);
1631 tcg_temp_free_i32(tmp32_3);
1632 break;
1633 case 0xaa: /* CGXBR R1,R2 [RRE] */
1634 tmp32_1 = tcg_const_i32(r1);
1635 tmp32_2 = tcg_const_i32(r2);
1636 tmp32_3 = tcg_const_i32(m3);
1637 gen_helper_cgxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
1638 set_cc_static(s);
1639 tcg_temp_free_i32(tmp32_1);
1640 tcg_temp_free_i32(tmp32_2);
1641 tcg_temp_free_i32(tmp32_3);
1642 break;
1643 default:
1644 LOG_DISAS("illegal b3 operation 0x%x\n", op);
1645 gen_illegal_opcode(s);
1646 break;
1647 }
1648
1649 #undef FP_HELPER_CC
1650 #undef FP_HELPER
1651 }
1652
1653 static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
1654 int r2)
1655 {
1656 TCGv_i64 tmp;
1657 TCGv_i32 tmp32_1;
1658
1659 LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2);
1660 switch (op) {
1661 case 0x83: /* FLOGR R1,R2 [RRE] */
1662 tmp = load_reg(r2);
1663 tmp32_1 = tcg_const_i32(r1);
1664 gen_helper_flogr(cc_op, cpu_env, tmp32_1, tmp);
1665 set_cc_static(s);
1666 tcg_temp_free_i64(tmp);
1667 tcg_temp_free_i32(tmp32_1);
1668 break;
1669 default:
1670 LOG_DISAS("illegal b9 operation 0x%x\n", op);
1671 gen_illegal_opcode(s);
1672 break;
1673 }
1674 }
1675
1676 static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
1677 {
1678 unsigned char opc;
1679 uint64_t insn;
1680 int op, r1, r2, r3, d2, x2, b2, r1b;
1681
1682 opc = cpu_ldub_code(env, s->pc);
1683 LOG_DISAS("opc 0x%x\n", opc);
1684
1685 switch (opc) {
1686 case 0xb2:
1687 insn = ld_code4(env, s->pc);
1688 op = (insn >> 16) & 0xff;
1689 disas_b2(env, s, op, insn);
1690 break;
1691 case 0xb3:
1692 insn = ld_code4(env, s->pc);
1693 op = (insn >> 16) & 0xff;
1694 r3 = (insn >> 12) & 0xf; /* aka m3 */
1695 r1 = (insn >> 4) & 0xf;
1696 r2 = insn & 0xf;
1697 disas_b3(env, s, op, r3, r1, r2);
1698 break;
1699 case 0xb9:
1700 insn = ld_code4(env, s->pc);
1701 r1 = (insn >> 4) & 0xf;
1702 r2 = insn & 0xf;
1703 op = (insn >> 16) & 0xff;
1704 disas_b9(env, s, op, r1, r2);
1705 break;
1706 case 0xed:
1707 insn = ld_code6(env, s->pc);
1708 debug_insn(insn);
1709 op = insn & 0xff;
1710 r1 = (insn >> 36) & 0xf;
1711 x2 = (insn >> 32) & 0xf;
1712 b2 = (insn >> 28) & 0xf;
1713 d2 = (short)((insn >> 16) & 0xfff);
1714 r1b = (insn >> 12) & 0xf;
1715 disas_ed(env, s, op, r1, x2, b2, d2, r1b);
1716 break;
1717 default:
1718 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
1719 gen_illegal_opcode(s);
1720 break;
1721 }
1722 }
1723
1724 /* ====================================================================== */
1725 /* Define the insn format enumeration. */
1726 #define F0(N) FMT_##N,
1727 #define F1(N, X1) F0(N)
1728 #define F2(N, X1, X2) F0(N)
1729 #define F3(N, X1, X2, X3) F0(N)
1730 #define F4(N, X1, X2, X3, X4) F0(N)
1731 #define F5(N, X1, X2, X3, X4, X5) F0(N)
1732
1733 typedef enum {
1734 #include "insn-format.def"
1735 } DisasFormat;
1736
1737 #undef F0
1738 #undef F1
1739 #undef F2
1740 #undef F3
1741 #undef F4
1742 #undef F5
1743
1744 /* Define a structure to hold the decoded fields. We'll store each inside
1745 an array indexed by an enum. In order to conserve memory, we'll arrange
1746 for fields that do not exist at the same time to overlap, thus the "C"
1747 for compact. For checking purposes there is an "O" for original index
1748 as well that will be applied to availability bitmaps. */
1749
1750 enum DisasFieldIndexO {
1751 FLD_O_r1,
1752 FLD_O_r2,
1753 FLD_O_r3,
1754 FLD_O_m1,
1755 FLD_O_m3,
1756 FLD_O_m4,
1757 FLD_O_b1,
1758 FLD_O_b2,
1759 FLD_O_b4,
1760 FLD_O_d1,
1761 FLD_O_d2,
1762 FLD_O_d4,
1763 FLD_O_x2,
1764 FLD_O_l1,
1765 FLD_O_l2,
1766 FLD_O_i1,
1767 FLD_O_i2,
1768 FLD_O_i3,
1769 FLD_O_i4,
1770 FLD_O_i5
1771 };
1772
1773 enum DisasFieldIndexC {
1774 FLD_C_r1 = 0,
1775 FLD_C_m1 = 0,
1776 FLD_C_b1 = 0,
1777 FLD_C_i1 = 0,
1778
1779 FLD_C_r2 = 1,
1780 FLD_C_b2 = 1,
1781 FLD_C_i2 = 1,
1782
1783 FLD_C_r3 = 2,
1784 FLD_C_m3 = 2,
1785 FLD_C_i3 = 2,
1786
1787 FLD_C_m4 = 3,
1788 FLD_C_b4 = 3,
1789 FLD_C_i4 = 3,
1790 FLD_C_l1 = 3,
1791
1792 FLD_C_i5 = 4,
1793 FLD_C_d1 = 4,
1794
1795 FLD_C_d2 = 5,
1796
1797 FLD_C_d4 = 6,
1798 FLD_C_x2 = 6,
1799 FLD_C_l2 = 6,
1800
1801 NUM_C_FIELD = 7
1802 };
1803
1804 struct DisasFields {
1805 unsigned op:8;
1806 unsigned op2:8;
1807 unsigned presentC:16;
1808 unsigned int presentO;
1809 int c[NUM_C_FIELD];
1810 };
1811
1812 /* This is the way fields are to be accessed out of DisasFields. */
1813 #define have_field(S, F) have_field1((S), FLD_O_##F)
1814 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1815
1816 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1817 {
1818 return (f->presentO >> c) & 1;
1819 }
1820
1821 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1822 enum DisasFieldIndexC c)
1823 {
1824 assert(have_field1(f, o));
1825 return f->c[c];
1826 }
1827
1828 /* Describe the layout of each field in each format. */
1829 typedef struct DisasField {
1830 unsigned int beg:8;
1831 unsigned int size:8;
1832 unsigned int type:2;
1833 unsigned int indexC:6;
1834 enum DisasFieldIndexO indexO:8;
1835 } DisasField;
1836
1837 typedef struct DisasFormatInfo {
1838 DisasField op[NUM_C_FIELD];
1839 } DisasFormatInfo;
1840
1841 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1842 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1843 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1844 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1845 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1846 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1847 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1848 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1849 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1850 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1851 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1852 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1853 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1854 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1855
1856 #define F0(N) { { } },
1857 #define F1(N, X1) { { X1 } },
1858 #define F2(N, X1, X2) { { X1, X2 } },
1859 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1860 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1861 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1862
1863 static const DisasFormatInfo format_info[] = {
1864 #include "insn-format.def"
1865 };
1866
1867 #undef F0
1868 #undef F1
1869 #undef F2
1870 #undef F3
1871 #undef F4
1872 #undef F5
1873 #undef R
1874 #undef M
1875 #undef BD
1876 #undef BXD
1877 #undef BDL
1878 #undef BXDL
1879 #undef I
1880 #undef L
1881
1882 /* Generally, we'll extract operands into this structures, operate upon
1883 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1884 of routines below for more details. */
1885 typedef struct {
1886 bool g_out, g_out2, g_in1, g_in2;
1887 TCGv_i64 out, out2, in1, in2;
1888 TCGv_i64 addr1;
1889 } DisasOps;
1890
1891 /* Return values from translate_one, indicating the state of the TB. */
1892 typedef enum {
1893 /* Continue the TB. */
1894 NO_EXIT,
1895 /* We have emitted one or more goto_tb. No fixup required. */
1896 EXIT_GOTO_TB,
1897 /* We are not using a goto_tb (for whatever reason), but have updated
1898 the PC (for whatever reason), so there's no need to do it again on
1899 exiting the TB. */
1900 EXIT_PC_UPDATED,
1901 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1902 updated the PC for the next instruction to be executed. */
1903 EXIT_PC_STALE,
1904 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1905 No following code will be executed. */
1906 EXIT_NORETURN,
1907 } ExitStatus;
1908
1909 typedef enum DisasFacility {
1910 FAC_Z, /* zarch (default) */
1911 FAC_CASS, /* compare and swap and store */
1912 FAC_CASS2, /* compare and swap and store 2*/
1913 FAC_DFP, /* decimal floating point */
1914 FAC_DFPR, /* decimal floating point rounding */
1915 FAC_DO, /* distinct operands */
1916 FAC_EE, /* execute extensions */
1917 FAC_EI, /* extended immediate */
1918 FAC_FPE, /* floating point extension */
1919 FAC_FPSSH, /* floating point support sign handling */
1920 FAC_FPRGR, /* FPR-GR transfer */
1921 FAC_GIE, /* general instructions extension */
1922 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1923 FAC_HW, /* high-word */
1924 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1925 FAC_LOC, /* load/store on condition */
1926 FAC_LD, /* long displacement */
1927 FAC_PC, /* population count */
1928 FAC_SCF, /* store clock fast */
1929 FAC_SFLE, /* store facility list extended */
1930 } DisasFacility;
1931
1932 struct DisasInsn {
1933 unsigned opc:16;
1934 DisasFormat fmt:6;
1935 DisasFacility fac:6;
1936
1937 const char *name;
1938
1939 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1940 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1941 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1942 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1943 void (*help_cout)(DisasContext *, DisasOps *);
1944 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1945
1946 uint64_t data;
1947 };
1948
1949 /* ====================================================================== */
1950 /* Miscelaneous helpers, used by several operations. */
1951
1952 static void help_l2_shift(DisasContext *s, DisasFields *f,
1953 DisasOps *o, int mask)
1954 {
1955 int b2 = get_field(f, b2);
1956 int d2 = get_field(f, d2);
1957
1958 if (b2 == 0) {
1959 o->in2 = tcg_const_i64(d2 & mask);
1960 } else {
1961 o->in2 = get_address(s, 0, b2, d2);
1962 tcg_gen_andi_i64(o->in2, o->in2, mask);
1963 }
1964 }
1965
1966 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1967 {
1968 if (dest == s->next_pc) {
1969 return NO_EXIT;
1970 }
1971 if (use_goto_tb(s, dest)) {
1972 gen_update_cc_op(s);
1973 tcg_gen_goto_tb(0);
1974 tcg_gen_movi_i64(psw_addr, dest);
1975 tcg_gen_exit_tb((tcg_target_long)s->tb);
1976 return EXIT_GOTO_TB;
1977 } else {
1978 tcg_gen_movi_i64(psw_addr, dest);
1979 return EXIT_PC_UPDATED;
1980 }
1981 }
1982
1983 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1984 bool is_imm, int imm, TCGv_i64 cdest)
1985 {
1986 ExitStatus ret;
1987 uint64_t dest = s->pc + 2 * imm;
1988 int lab;
1989
1990 /* Take care of the special cases first. */
1991 if (c->cond == TCG_COND_NEVER) {
1992 ret = NO_EXIT;
1993 goto egress;
1994 }
1995 if (is_imm) {
1996 if (dest == s->next_pc) {
1997 /* Branch to next. */
1998 ret = NO_EXIT;
1999 goto egress;
2000 }
2001 if (c->cond == TCG_COND_ALWAYS) {
2002 ret = help_goto_direct(s, dest);
2003 goto egress;
2004 }
2005 } else {
2006 if (TCGV_IS_UNUSED_I64(cdest)) {
2007 /* E.g. bcr %r0 -> no branch. */
2008 ret = NO_EXIT;
2009 goto egress;
2010 }
2011 if (c->cond == TCG_COND_ALWAYS) {
2012 tcg_gen_mov_i64(psw_addr, cdest);
2013 ret = EXIT_PC_UPDATED;
2014 goto egress;
2015 }
2016 }
2017
2018 if (use_goto_tb(s, s->next_pc)) {
2019 if (is_imm && use_goto_tb(s, dest)) {
2020 /* Both exits can use goto_tb. */
2021 gen_update_cc_op(s);
2022
2023 lab = gen_new_label();
2024 if (c->is_64) {
2025 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2026 } else {
2027 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2028 }
2029
2030 /* Branch not taken. */
2031 tcg_gen_goto_tb(0);
2032 tcg_gen_movi_i64(psw_addr, s->next_pc);
2033 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2034
2035 /* Branch taken. */
2036 gen_set_label(lab);
2037 tcg_gen_goto_tb(1);
2038 tcg_gen_movi_i64(psw_addr, dest);
2039 tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
2040
2041 ret = EXIT_GOTO_TB;
2042 } else {
2043 /* Fallthru can use goto_tb, but taken branch cannot. */
2044 /* Store taken branch destination before the brcond. This
2045 avoids having to allocate a new local temp to hold it.
2046 We'll overwrite this in the not taken case anyway. */
2047 if (!is_imm) {
2048 tcg_gen_mov_i64(psw_addr, cdest);
2049 }
2050
2051 lab = gen_new_label();
2052 if (c->is_64) {
2053 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
2054 } else {
2055 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
2056 }
2057
2058 /* Branch not taken. */
2059 gen_update_cc_op(s);
2060 tcg_gen_goto_tb(0);
2061 tcg_gen_movi_i64(psw_addr, s->next_pc);
2062 tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
2063
2064 gen_set_label(lab);
2065 if (is_imm) {
2066 tcg_gen_movi_i64(psw_addr, dest);
2067 }
2068 ret = EXIT_PC_UPDATED;
2069 }
2070 } else {
2071 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
2072 Most commonly we're single-stepping or some other condition that
2073 disables all use of goto_tb. Just update the PC and exit. */
2074
2075 TCGv_i64 next = tcg_const_i64(s->next_pc);
2076 if (is_imm) {
2077 cdest = tcg_const_i64(dest);
2078 }
2079
2080 if (c->is_64) {
2081 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
2082 cdest, next);
2083 } else {
2084 TCGv_i32 t0 = tcg_temp_new_i32();
2085 TCGv_i64 t1 = tcg_temp_new_i64();
2086 TCGv_i64 z = tcg_const_i64(0);
2087 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
2088 tcg_gen_extu_i32_i64(t1, t0);
2089 tcg_temp_free_i32(t0);
2090 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
2091 tcg_temp_free_i64(t1);
2092 tcg_temp_free_i64(z);
2093 }
2094
2095 if (is_imm) {
2096 tcg_temp_free_i64(cdest);
2097 }
2098 tcg_temp_free_i64(next);
2099
2100 ret = EXIT_PC_UPDATED;
2101 }
2102
2103 egress:
2104 free_compare(c);
2105 return ret;
2106 }
2107
2108 /* ====================================================================== */
2109 /* The operations. These perform the bulk of the work for any insn,
2110 usually after the operands have been loaded and output initialized. */
2111
2112 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
2113 {
2114 gen_helper_abs_i64(o->out, o->in2);
2115 return NO_EXIT;
2116 }
2117
2118 static ExitStatus op_add(DisasContext *s, DisasOps *o)
2119 {
2120 tcg_gen_add_i64(o->out, o->in1, o->in2);
2121 return NO_EXIT;
2122 }
2123
2124 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
2125 {
2126 TCGv_i64 cc;
2127
2128 tcg_gen_add_i64(o->out, o->in1, o->in2);
2129
2130 /* XXX possible optimization point */
2131 gen_op_calc_cc(s);
2132 cc = tcg_temp_new_i64();
2133 tcg_gen_extu_i32_i64(cc, cc_op);
2134 tcg_gen_shri_i64(cc, cc, 1);
2135
2136 tcg_gen_add_i64(o->out, o->out, cc);
2137 tcg_temp_free_i64(cc);
2138 return NO_EXIT;
2139 }
2140
2141 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
2142 {
2143 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
2144 return NO_EXIT;
2145 }
2146
2147 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
2148 {
2149 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
2150 return NO_EXIT;
2151 }
2152
2153 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
2154 {
2155 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2156 return_low128(o->out2);
2157 return NO_EXIT;
2158 }
2159
2160 static ExitStatus op_and(DisasContext *s, DisasOps *o)
2161 {
2162 tcg_gen_and_i64(o->out, o->in1, o->in2);
2163 return NO_EXIT;
2164 }
2165
2166 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
2167 {
2168 int shift = s->insn->data & 0xff;
2169 int size = s->insn->data >> 8;
2170 uint64_t mask = ((1ull << size) - 1) << shift;
2171
2172 assert(!o->g_in2);
2173 tcg_gen_shli_i64(o->in2, o->in2, shift);
2174 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2175 tcg_gen_and_i64(o->out, o->in1, o->in2);
2176
2177 /* Produce the CC from only the bits manipulated. */
2178 tcg_gen_andi_i64(cc_dst, o->out, mask);
2179 set_cc_nz_u64(s, cc_dst);
2180 return NO_EXIT;
2181 }
2182
2183 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
2184 {
2185 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2186 if (!TCGV_IS_UNUSED_I64(o->in2)) {
2187 tcg_gen_mov_i64(psw_addr, o->in2);
2188 return EXIT_PC_UPDATED;
2189 } else {
2190 return NO_EXIT;
2191 }
2192 }
2193
2194 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
2195 {
2196 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
2197 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
2198 }
2199
2200 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
2201 {
2202 int m1 = get_field(s->fields, m1);
2203 bool is_imm = have_field(s->fields, i2);
2204 int imm = is_imm ? get_field(s->fields, i2) : 0;
2205 DisasCompare c;
2206
2207 disas_jcc(s, &c, m1);
2208 return help_branch(s, &c, is_imm, imm, o->in2);
2209 }
2210
2211 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
2212 {
2213 int r1 = get_field(s->fields, r1);
2214 bool is_imm = have_field(s->fields, i2);
2215 int imm = is_imm ? get_field(s->fields, i2) : 0;
2216 DisasCompare c;
2217 TCGv_i64 t;
2218
2219 c.cond = TCG_COND_NE;
2220 c.is_64 = false;
2221 c.g1 = false;
2222 c.g2 = false;
2223
2224 t = tcg_temp_new_i64();
2225 tcg_gen_subi_i64(t, regs[r1], 1);
2226 store_reg32_i64(r1, t);
2227 c.u.s32.a = tcg_temp_new_i32();
2228 c.u.s32.b = tcg_const_i32(0);
2229 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
2230 tcg_temp_free_i64(t);
2231
2232 return help_branch(s, &c, is_imm, imm, o->in2);
2233 }
2234
2235 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
2236 {
2237 int r1 = get_field(s->fields, r1);
2238 bool is_imm = have_field(s->fields, i2);
2239 int imm = is_imm ? get_field(s->fields, i2) : 0;
2240 DisasCompare c;
2241
2242 c.cond = TCG_COND_NE;
2243 c.is_64 = true;
2244 c.g1 = true;
2245 c.g2 = false;
2246
2247 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
2248 c.u.s64.a = regs[r1];
2249 c.u.s64.b = tcg_const_i64(0);
2250
2251 return help_branch(s, &c, is_imm, imm, o->in2);
2252 }
2253
2254 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
2255 {
2256 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
2257 set_cc_static(s);
2258 return NO_EXIT;
2259 }
2260
2261 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
2262 {
2263 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
2264 set_cc_static(s);
2265 return NO_EXIT;
2266 }
2267
2268 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
2269 {
2270 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
2271 set_cc_static(s);
2272 return NO_EXIT;
2273 }
2274
2275 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
2276 {
2277 int l = get_field(s->fields, l1);
2278 TCGv_i32 vl;
2279
2280 switch (l + 1) {
2281 case 1:
2282 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
2283 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
2284 break;
2285 case 2:
2286 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
2287 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
2288 break;
2289 case 4:
2290 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
2291 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
2292 break;
2293 case 8:
2294 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
2295 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
2296 break;
2297 default:
2298 potential_page_fault(s);
2299 vl = tcg_const_i32(l);
2300 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
2301 tcg_temp_free_i32(vl);
2302 set_cc_static(s);
2303 return NO_EXIT;
2304 }
2305 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
2306 return NO_EXIT;
2307 }
2308
2309 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
2310 {
2311 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2312 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2313 potential_page_fault(s);
2314 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
2315 tcg_temp_free_i32(r1);
2316 tcg_temp_free_i32(r3);
2317 set_cc_static(s);
2318 return NO_EXIT;
2319 }
2320
2321 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
2322 {
2323 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
2324 TCGv_i32 t1 = tcg_temp_new_i32();
2325 tcg_gen_trunc_i64_i32(t1, o->in1);
2326 potential_page_fault(s);
2327 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
2328 set_cc_static(s);
2329 tcg_temp_free_i32(t1);
2330 tcg_temp_free_i32(m3);
2331 return NO_EXIT;
2332 }
2333
2334 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
2335 {
2336 int r3 = get_field(s->fields, r3);
2337 potential_page_fault(s);
2338 gen_helper_cs(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2339 set_cc_static(s);
2340 return NO_EXIT;
2341 }
2342
2343 static ExitStatus op_csg(DisasContext *s, DisasOps *o)
2344 {
2345 int r3 = get_field(s->fields, r3);
2346 potential_page_fault(s);
2347 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, regs[r3]);
2348 set_cc_static(s);
2349 return NO_EXIT;
2350 }
2351
2352 static ExitStatus op_cds(DisasContext *s, DisasOps *o)
2353 {
2354 int r3 = get_field(s->fields, r3);
2355 TCGv_i64 in3 = tcg_temp_new_i64();
2356 tcg_gen_deposit_i64(in3, regs[r3 + 1], regs[r3], 32, 32);
2357 potential_page_fault(s);
2358 gen_helper_csg(o->out, cpu_env, o->in1, o->in2, in3);
2359 tcg_temp_free_i64(in3);
2360 set_cc_static(s);
2361 return NO_EXIT;
2362 }
2363
2364 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
2365 {
2366 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2367 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2368 potential_page_fault(s);
2369 /* XXX rewrite in tcg */
2370 gen_helper_cdsg(cc_op, cpu_env, r1, o->in2, r3);
2371 set_cc_static(s);
2372 return NO_EXIT;
2373 }
2374
2375 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
2376 {
2377 TCGv_i64 t1 = tcg_temp_new_i64();
2378 TCGv_i32 t2 = tcg_temp_new_i32();
2379 tcg_gen_trunc_i64_i32(t2, o->in1);
2380 gen_helper_cvd(t1, t2);
2381 tcg_temp_free_i32(t2);
2382 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
2383 tcg_temp_free_i64(t1);
2384 return NO_EXIT;
2385 }
2386
2387 #ifndef CONFIG_USER_ONLY
2388 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
2389 {
2390 TCGv_i32 tmp;
2391
2392 check_privileged(s);
2393 potential_page_fault(s);
2394
2395 /* We pretend the format is RX_a so that D2 is the field we want. */
2396 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
2397 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
2398 tcg_temp_free_i32(tmp);
2399 return NO_EXIT;
2400 }
2401 #endif
2402
2403 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2404 {
2405 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2406 return_low128(o->out);
2407 return NO_EXIT;
2408 }
2409
2410 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2411 {
2412 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2413 return_low128(o->out);
2414 return NO_EXIT;
2415 }
2416
2417 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2418 {
2419 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2420 return_low128(o->out);
2421 return NO_EXIT;
2422 }
2423
2424 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2425 {
2426 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2427 return_low128(o->out);
2428 return NO_EXIT;
2429 }
2430
2431 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2432 {
2433 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2434 return NO_EXIT;
2435 }
2436
2437 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2438 {
2439 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2440 tb->flags, (ab)use the tb->cs_base field as the address of
2441 the template in memory, and grab 8 bits of tb->flags/cflags for
2442 the contents of the register. We would then recognize all this
2443 in gen_intermediate_code_internal, generating code for exactly
2444 one instruction. This new TB then gets executed normally.
2445
2446 On the other hand, this seems to be mostly used for modifying
2447 MVC inside of memcpy, which needs a helper call anyway. So
2448 perhaps this doesn't bear thinking about any further. */
2449
2450 TCGv_i64 tmp;
2451
2452 update_psw_addr(s);
2453 gen_op_calc_cc(s);
2454
2455 tmp = tcg_const_i64(s->next_pc);
2456 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2457 tcg_temp_free_i64(tmp);
2458
2459 set_cc_static(s);
2460 return NO_EXIT;
2461 }
2462
2463 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2464 {
2465 int m3 = get_field(s->fields, m3);
2466 int pos, len, base = s->insn->data;
2467 TCGv_i64 tmp = tcg_temp_new_i64();
2468 uint64_t ccm;
2469
2470 switch (m3) {
2471 case 0xf:
2472 /* Effectively a 32-bit load. */
2473 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2474 len = 32;
2475 goto one_insert;
2476
2477 case 0xc:
2478 case 0x6:
2479 case 0x3:
2480 /* Effectively a 16-bit load. */
2481 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2482 len = 16;
2483 goto one_insert;
2484
2485 case 0x8:
2486 case 0x4:
2487 case 0x2:
2488 case 0x1:
2489 /* Effectively an 8-bit load. */
2490 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2491 len = 8;
2492 goto one_insert;
2493
2494 one_insert:
2495 pos = base + ctz32(m3) * 8;
2496 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2497 ccm = ((1ull << len) - 1) << pos;
2498 break;
2499
2500 default:
2501 /* This is going to be a sequence of loads and inserts. */
2502 pos = base + 32 - 8;
2503 ccm = 0;
2504 while (m3) {
2505 if (m3 & 0x8) {
2506 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2507 tcg_gen_addi_i64(o->in2, o->in2, 1);
2508 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2509 ccm |= 0xff << pos;
2510 }
2511 m3 = (m3 << 1) & 0xf;
2512 pos -= 8;
2513 }
2514 break;
2515 }
2516
2517 tcg_gen_movi_i64(tmp, ccm);
2518 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2519 tcg_temp_free_i64(tmp);
2520 return NO_EXIT;
2521 }
2522
2523 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2524 {
2525 int shift = s->insn->data & 0xff;
2526 int size = s->insn->data >> 8;
2527 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2528 return NO_EXIT;
2529 }
2530
2531 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2532 {
2533 gen_helper_ldeb(o->out, cpu_env, o->in2);
2534 return NO_EXIT;
2535 }
2536
2537 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2538 {
2539 gen_helper_ledb(o->out, cpu_env, o->in2);
2540 return NO_EXIT;
2541 }
2542
2543 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2544 {
2545 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2546 return NO_EXIT;
2547 }
2548
2549 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2550 {
2551 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2552 return NO_EXIT;
2553 }
2554
2555 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2556 {
2557 gen_helper_lxdb(o->out, cpu_env, o->in2);
2558 return_low128(o->out2);
2559 return NO_EXIT;
2560 }
2561
2562 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2563 {
2564 gen_helper_lxeb(o->out, cpu_env, o->in2);
2565 return_low128(o->out2);
2566 return NO_EXIT;
2567 }
2568
2569 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2570 {
2571 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2572 return NO_EXIT;
2573 }
2574
2575 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2576 {
2577 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2578 return NO_EXIT;
2579 }
2580
2581 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2582 {
2583 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2584 return NO_EXIT;
2585 }
2586
2587 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2588 {
2589 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2590 return NO_EXIT;
2591 }
2592
2593 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2594 {
2595 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2596 return NO_EXIT;
2597 }
2598
2599 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2600 {
2601 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2602 return NO_EXIT;
2603 }
2604
2605 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2606 {
2607 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2608 return NO_EXIT;
2609 }
2610
2611 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2612 {
2613 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2614 return NO_EXIT;
2615 }
2616
2617 #ifndef CONFIG_USER_ONLY
2618 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2619 {
2620 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2621 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2622 check_privileged(s);
2623 potential_page_fault(s);
2624 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2625 tcg_temp_free_i32(r1);
2626 tcg_temp_free_i32(r3);
2627 return NO_EXIT;
2628 }
2629
2630 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2631 {
2632 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2633 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2634 check_privileged(s);
2635 potential_page_fault(s);
2636 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2637 tcg_temp_free_i32(r1);
2638 tcg_temp_free_i32(r3);
2639 return NO_EXIT;
2640 }
2641 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2642 {
2643 check_privileged(s);
2644 potential_page_fault(s);
2645 gen_helper_lra(o->out, cpu_env, o->in2);
2646 set_cc_static(s);
2647 return NO_EXIT;
2648 }
2649
2650 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2651 {
2652 TCGv_i64 t1, t2;
2653
2654 check_privileged(s);
2655
2656 t1 = tcg_temp_new_i64();
2657 t2 = tcg_temp_new_i64();
2658 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2659 tcg_gen_addi_i64(o->in2, o->in2, 4);
2660 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2661 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2662 tcg_gen_shli_i64(t1, t1, 32);
2663 gen_helper_load_psw(cpu_env, t1, t2);
2664 tcg_temp_free_i64(t1);
2665 tcg_temp_free_i64(t2);
2666 return EXIT_NORETURN;
2667 }
2668 #endif
2669
2670 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2671 {
2672 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2673 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2674 potential_page_fault(s);
2675 gen_helper_lam(cpu_env, r1, o->in2, r3);
2676 tcg_temp_free_i32(r1);
2677 tcg_temp_free_i32(r3);
2678 return NO_EXIT;
2679 }
2680
2681 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2682 {
2683 int r1 = get_field(s->fields, r1);
2684 int r3 = get_field(s->fields, r3);
2685 TCGv_i64 t = tcg_temp_new_i64();
2686 TCGv_i64 t4 = tcg_const_i64(4);
2687
2688 while (1) {
2689 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2690 store_reg32_i64(r1, t);
2691 if (r1 == r3) {
2692 break;
2693 }
2694 tcg_gen_add_i64(o->in2, o->in2, t4);
2695 r1 = (r1 + 1) & 15;
2696 }
2697
2698 tcg_temp_free_i64(t);
2699 tcg_temp_free_i64(t4);
2700 return NO_EXIT;
2701 }
2702
2703 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2704 {
2705 int r1 = get_field(s->fields, r1);
2706 int r3 = get_field(s->fields, r3);
2707 TCGv_i64 t = tcg_temp_new_i64();
2708 TCGv_i64 t4 = tcg_const_i64(4);
2709
2710 while (1) {
2711 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2712 store_reg32h_i64(r1, t);
2713 if (r1 == r3) {
2714 break;
2715 }
2716 tcg_gen_add_i64(o->in2, o->in2, t4);
2717 r1 = (r1 + 1) & 15;
2718 }
2719
2720 tcg_temp_free_i64(t);
2721 tcg_temp_free_i64(t4);
2722 return NO_EXIT;
2723 }
2724
2725 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2726 {
2727 int r1 = get_field(s->fields, r1);
2728 int r3 = get_field(s->fields, r3);
2729 TCGv_i64 t8 = tcg_const_i64(8);
2730
2731 while (1) {
2732 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2733 if (r1 == r3) {
2734 break;
2735 }
2736 tcg_gen_add_i64(o->in2, o->in2, t8);
2737 r1 = (r1 + 1) & 15;
2738 }
2739
2740 tcg_temp_free_i64(t8);
2741 return NO_EXIT;
2742 }
2743
2744 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2745 {
2746 o->out = o->in2;
2747 o->g_out = o->g_in2;
2748 TCGV_UNUSED_I64(o->in2);
2749 o->g_in2 = false;
2750 return NO_EXIT;
2751 }
2752
2753 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2754 {
2755 o->out = o->in1;
2756 o->out2 = o->in2;
2757 o->g_out = o->g_in1;
2758 o->g_out2 = o->g_in2;
2759 TCGV_UNUSED_I64(o->in1);
2760 TCGV_UNUSED_I64(o->in2);
2761 o->g_in1 = o->g_in2 = false;
2762 return NO_EXIT;
2763 }
2764
2765 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2766 {
2767 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2768 potential_page_fault(s);
2769 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2770 tcg_temp_free_i32(l);
2771 return NO_EXIT;
2772 }
2773
2774 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2775 {
2776 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2777 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2778 potential_page_fault(s);
2779 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2780 tcg_temp_free_i32(r1);
2781 tcg_temp_free_i32(r2);
2782 set_cc_static(s);
2783 return NO_EXIT;
2784 }
2785
2786 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2787 {
2788 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2789 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2790 potential_page_fault(s);
2791 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2792 tcg_temp_free_i32(r1);
2793 tcg_temp_free_i32(r3);
2794 set_cc_static(s);
2795 return NO_EXIT;
2796 }
2797
2798 #ifndef CONFIG_USER_ONLY
2799 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2800 {
2801 int r1 = get_field(s->fields, l1);
2802 check_privileged(s);
2803 potential_page_fault(s);
2804 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2805 set_cc_static(s);
2806 return NO_EXIT;
2807 }
2808
2809 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2810 {
2811 int r1 = get_field(s->fields, l1);
2812 check_privileged(s);
2813 potential_page_fault(s);
2814 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2815 set_cc_static(s);
2816 return NO_EXIT;
2817 }
2818 #endif
2819
2820 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2821 {
2822 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2823 return NO_EXIT;
2824 }
2825
2826 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2827 {
2828 gen_helper_mul128(o->out, cpu_env, o->in1, o->in2);
2829 return_low128(o->out2);
2830 return NO_EXIT;
2831 }
2832
2833 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2834 {
2835 gen_helper_nabs_i64(o->out, o->in2);
2836 return NO_EXIT;
2837 }
2838
2839 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2840 {
2841 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2842 potential_page_fault(s);
2843 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2844 tcg_temp_free_i32(l);
2845 set_cc_static(s);
2846 return NO_EXIT;
2847 }
2848
2849 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2850 {
2851 tcg_gen_neg_i64(o->out, o->in2);
2852 return NO_EXIT;
2853 }
2854
2855 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2856 {
2857 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2858 potential_page_fault(s);
2859 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2860 tcg_temp_free_i32(l);
2861 set_cc_static(s);
2862 return NO_EXIT;
2863 }
2864
2865 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2866 {
2867 tcg_gen_or_i64(o->out, o->in1, o->in2);
2868 return NO_EXIT;
2869 }
2870
2871 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2872 {
2873 int shift = s->insn->data & 0xff;
2874 int size = s->insn->data >> 8;
2875 uint64_t mask = ((1ull << size) - 1) << shift;
2876
2877 assert(!o->g_in2);
2878 tcg_gen_shli_i64(o->in2, o->in2, shift);
2879 tcg_gen_or_i64(o->out, o->in1, o->in2);
2880
2881 /* Produce the CC from only the bits manipulated. */
2882 tcg_gen_andi_i64(cc_dst, o->out, mask);
2883 set_cc_nz_u64(s, cc_dst);
2884 return NO_EXIT;
2885 }
2886
2887 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2888 {
2889 tcg_gen_bswap16_i64(o->out, o->in2);
2890 return NO_EXIT;
2891 }
2892
2893 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2894 {
2895 tcg_gen_bswap32_i64(o->out, o->in2);
2896 return NO_EXIT;
2897 }
2898
2899 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2900 {
2901 tcg_gen_bswap64_i64(o->out, o->in2);
2902 return NO_EXIT;
2903 }
2904
2905 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2906 {
2907 TCGv_i32 t1 = tcg_temp_new_i32();
2908 TCGv_i32 t2 = tcg_temp_new_i32();
2909 TCGv_i32 to = tcg_temp_new_i32();
2910 tcg_gen_trunc_i64_i32(t1, o->in1);
2911 tcg_gen_trunc_i64_i32(t2, o->in2);
2912 tcg_gen_rotl_i32(to, t1, t2);
2913 tcg_gen_extu_i32_i64(o->out, to);
2914 tcg_temp_free_i32(t1);
2915 tcg_temp_free_i32(t2);
2916 tcg_temp_free_i32(to);
2917 return NO_EXIT;
2918 }
2919
2920 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2921 {
2922 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2923 return NO_EXIT;
2924 }
2925
2926 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
2927 {
2928 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
2929 return NO_EXIT;
2930 }
2931
2932 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
2933 {
2934 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
2935 return NO_EXIT;
2936 }
2937
2938 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
2939 {
2940 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2941 return_low128(o->out2);
2942 return NO_EXIT;
2943 }
2944
2945 #ifndef CONFIG_USER_ONLY
2946 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
2947 {
2948 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2949 check_privileged(s);
2950 potential_page_fault(s);
2951 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
2952 tcg_temp_free_i32(r1);
2953 return NO_EXIT;
2954 }
2955 #endif
2956
2957 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
2958 {
2959 uint64_t sign = 1ull << s->insn->data;
2960 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
2961 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
2962 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2963 /* The arithmetic left shift is curious in that it does not affect
2964 the sign bit. Copy that over from the source unchanged. */
2965 tcg_gen_andi_i64(o->out, o->out, ~sign);
2966 tcg_gen_andi_i64(o->in1, o->in1, sign);
2967 tcg_gen_or_i64(o->out, o->out, o->in1);
2968 return NO_EXIT;
2969 }
2970
2971 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
2972 {
2973 tcg_gen_shl_i64(o->out, o->in1, o->in2);
2974 return NO_EXIT;
2975 }
2976
2977 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
2978 {
2979 tcg_gen_sar_i64(o->out, o->in1, o->in2);
2980 return NO_EXIT;
2981 }
2982
2983 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
2984 {
2985 tcg_gen_shr_i64(o->out, o->in1, o->in2);
2986 return NO_EXIT;
2987 }
2988
2989 #ifndef CONFIG_USER_ONLY
2990 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
2991 {
2992 check_privileged(s);
2993 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
2994 return NO_EXIT;
2995 }
2996
2997 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
2998 {
2999 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3000 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3001 check_privileged(s);
3002 potential_page_fault(s);
3003 gen_helper_stctg(cpu_env, r1, o->in2, r3);
3004 tcg_temp_free_i32(r1);
3005 tcg_temp_free_i32(r3);
3006 return NO_EXIT;
3007 }
3008
3009 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
3010 {
3011 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3012 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3013 check_privileged(s);
3014 potential_page_fault(s);
3015 gen_helper_stctl(cpu_env, r1, o->in2, r3);
3016 tcg_temp_free_i32(r1);
3017 tcg_temp_free_i32(r3);
3018 return NO_EXIT;
3019 }
3020
3021 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3022 {
3023 uint64_t i2 = get_field(s->fields, i2);
3024 TCGv_i64 t;
3025
3026 check_privileged(s);
3027
3028 /* It is important to do what the instruction name says: STORE THEN.
3029 If we let the output hook perform the store then if we fault and
3030 restart, we'll have the wrong SYSTEM MASK in place. */
3031 t = tcg_temp_new_i64();
3032 tcg_gen_shri_i64(t, psw_mask, 56);
3033 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3034 tcg_temp_free_i64(t);
3035
3036 if (s->fields->op == 0xac) {
3037 tcg_gen_andi_i64(psw_mask, psw_mask,
3038 (i2 << 56) | 0x00ffffffffffffffull);
3039 } else {
3040 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3041 }
3042 return NO_EXIT;
3043 }
3044 #endif
3045
3046 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3047 {
3048 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3049 return NO_EXIT;
3050 }
3051
3052 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3053 {
3054 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3055 return NO_EXIT;
3056 }
3057
3058 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3059 {
3060 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3061 return NO_EXIT;
3062 }
3063
3064 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3065 {
3066 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3067 return NO_EXIT;
3068 }
3069
3070 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3071 {
3072 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3073 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3074 potential_page_fault(s);
3075 gen_helper_stam(cpu_env, r1, o->in2, r3);
3076 tcg_temp_free_i32(r1);
3077 tcg_temp_free_i32(r3);
3078 return NO_EXIT;
3079 }
3080
3081 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3082 {
3083 int m3 = get_field(s->fields, m3);
3084 int pos, base = s->insn->data;
3085 TCGv_i64 tmp = tcg_temp_new_i64();
3086
3087 pos = base + ctz32(m3) * 8;
3088 switch (m3) {
3089 case 0xf:
3090 /* Effectively a 32-bit store. */
3091 tcg_gen_shri_i64(tmp, o->in1, pos);
3092 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3093 break;
3094
3095 case 0xc:
3096 case 0x6:
3097 case 0x3:
3098 /* Effectively a 16-bit store. */
3099 tcg_gen_shri_i64(tmp, o->in1, pos);
3100 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3101 break;
3102
3103 case 0x8:
3104 case 0x4:
3105 case 0x2:
3106 case 0x1:
3107 /* Effectively an 8-bit store. */
3108 tcg_gen_shri_i64(tmp, o->in1, pos);
3109 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3110 break;
3111
3112 default:
3113 /* This is going to be a sequence of shifts and stores. */
3114 pos = base + 32 - 8;
3115 while (m3) {
3116 if (m3 & 0x8) {
3117 tcg_gen_shri_i64(tmp, o->in1, pos);
3118 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3119 tcg_gen_addi_i64(o->in2, o->in2, 1);
3120 }
3121 m3 = (m3 << 1) & 0xf;
3122 pos -= 8;
3123 }
3124 break;
3125 }
3126 tcg_temp_free_i64(tmp);
3127 return NO_EXIT;
3128 }
3129
3130 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3131 {
3132 int r1 = get_field(s->fields, r1);
3133 int r3 = get_field(s->fields, r3);
3134 int size = s->insn->data;
3135 TCGv_i64 tsize = tcg_const_i64(size);
3136
3137 while (1) {
3138 if (size == 8) {
3139 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3140 } else {
3141 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3142 }
3143 if (r1 == r3) {
3144 break;
3145 }
3146 tcg_gen_add_i64(o->in2, o->in2, tsize);
3147 r1 = (r1 + 1) & 15;
3148 }
3149
3150 tcg_temp_free_i64(tsize);
3151 return NO_EXIT;
3152 }
3153
3154 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3155 {
3156 int r1 = get_field(s->fields, r1);
3157 int r3 = get_field(s->fields, r3);
3158 TCGv_i64 t = tcg_temp_new_i64();
3159 TCGv_i64 t4 = tcg_const_i64(4);
3160 TCGv_i64 t32 = tcg_const_i64(32);
3161
3162 while (1) {
3163 tcg_gen_shl_i64(t, regs[r1], t32);
3164 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3165 if (r1 == r3) {
3166 break;
3167 }
3168 tcg_gen_add_i64(o->in2, o->in2, t4);
3169 r1 = (r1 + 1) & 15;
3170 }
3171
3172 tcg_temp_free_i64(t);
3173 tcg_temp_free_i64(t4);
3174 tcg_temp_free_i64(t32);
3175 return NO_EXIT;
3176 }
3177
3178 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3179 {
3180 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3181 return NO_EXIT;
3182 }
3183
3184 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3185 {
3186 TCGv_i64 cc;
3187
3188 assert(!o->g_in2);
3189 tcg_gen_not_i64(o->in2, o->in2);
3190 tcg_gen_add_i64(o->out, o->in1, o->in2);
3191
3192 /* XXX possible optimization point */
3193 gen_op_calc_cc(s);
3194 cc = tcg_temp_new_i64();
3195 tcg_gen_extu_i32_i64(cc, cc_op);
3196 tcg_gen_shri_i64(cc, cc, 1);
3197 tcg_gen_add_i64(o->out, o->out, cc);
3198 tcg_temp_free_i64(cc);
3199 return NO_EXIT;
3200 }
3201
3202 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3203 {
3204 TCGv_i32 t;
3205
3206 update_psw_addr(s);
3207 gen_op_calc_cc(s);
3208
3209 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3210 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3211 tcg_temp_free_i32(t);
3212
3213 t = tcg_const_i32(s->next_pc - s->pc);
3214 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3215 tcg_temp_free_i32(t);
3216
3217 gen_exception(EXCP_SVC);
3218 return EXIT_NORETURN;
3219 }
3220
3221 #ifndef CONFIG_USER_ONLY
3222 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3223 {
3224 potential_page_fault(s);
3225 gen_helper_tprot(cc_op, o->addr1, o->in2);
3226 set_cc_static(s);
3227 return NO_EXIT;
3228 }
3229 #endif
3230
3231 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3232 {
3233 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3234 potential_page_fault(s);
3235 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3236 tcg_temp_free_i32(l);
3237 set_cc_static(s);
3238 return NO_EXIT;
3239 }
3240
3241 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3242 {
3243 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3244 potential_page_fault(s);
3245 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3246 tcg_temp_free_i32(l);
3247 return NO_EXIT;
3248 }
3249
3250 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3251 {
3252 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3253 potential_page_fault(s);
3254 gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2);
3255 tcg_temp_free_i32(l);
3256 set_cc_static(s);
3257 return NO_EXIT;
3258 }
3259
3260 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3261 {
3262 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3263 return NO_EXIT;
3264 }
3265
3266 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3267 {
3268 int shift = s->insn->data & 0xff;
3269 int size = s->insn->data >> 8;
3270 uint64_t mask = ((1ull << size) - 1) << shift;
3271
3272 assert(!o->g_in2);
3273 tcg_gen_shli_i64(o->in2, o->in2, shift);
3274 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3275
3276 /* Produce the CC from only the bits manipulated. */
3277 tcg_gen_andi_i64(cc_dst, o->out, mask);
3278 set_cc_nz_u64(s, cc_dst);
3279 return NO_EXIT;
3280 }
3281
3282 /* ====================================================================== */
3283 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3284 the original inputs), update the various cc data structures in order to
3285 be able to compute the new condition code. */
3286
3287 static void cout_abs32(DisasContext *s, DisasOps *o)
3288 {
3289 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3290 }
3291
3292 static void cout_abs64(DisasContext *s, DisasOps *o)
3293 {
3294 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3295 }
3296
3297 static void cout_adds32(DisasContext *s, DisasOps *o)
3298 {
3299 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3300 }
3301
3302 static void cout_adds64(DisasContext *s, DisasOps *o)
3303 {
3304 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3305 }
3306
3307 static void cout_addu32(DisasContext *s, DisasOps *o)
3308 {
3309 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3310 }
3311
3312 static void cout_addu64(DisasContext *s, DisasOps *o)
3313 {
3314 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3315 }
3316
3317 static void cout_addc32(DisasContext *s, DisasOps *o)
3318 {
3319 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3320 }
3321
3322 static void cout_addc64(DisasContext *s, DisasOps *o)
3323 {
3324 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3325 }
3326
3327 static void cout_cmps32(DisasContext *s, DisasOps *o)
3328 {
3329 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3330 }
3331
3332 static void cout_cmps64(DisasContext *s, DisasOps *o)
3333 {
3334 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3335 }
3336
3337 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3338 {
3339 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3340 }
3341
3342 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3343 {
3344 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3345 }
3346
3347 static void cout_f32(DisasContext *s, DisasOps *o)
3348 {
3349 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3350 }
3351
3352 static void cout_f64(DisasContext *s, DisasOps *o)
3353 {
3354 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3355 }
3356
3357 static void cout_f128(DisasContext *s, DisasOps *o)
3358 {
3359 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3360 }
3361
3362 static void cout_nabs32(DisasContext *s, DisasOps *o)
3363 {
3364 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3365 }
3366
3367 static void cout_nabs64(DisasContext *s, DisasOps *o)
3368 {
3369 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3370 }
3371
3372 static void cout_neg32(DisasContext *s, DisasOps *o)
3373 {
3374 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3375 }
3376
3377 static void cout_neg64(DisasContext *s, DisasOps *o)
3378 {
3379 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3380 }
3381
3382 static void cout_nz32(DisasContext *s, DisasOps *o)
3383 {
3384 tcg_gen_ext32u_i64(cc_dst, o->out);
3385 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3386 }
3387
3388 static void cout_nz64(DisasContext *s, DisasOps *o)
3389 {
3390 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3391 }
3392
3393 static void cout_s32(DisasContext *s, DisasOps *o)
3394 {
3395 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3396 }
3397
3398 static void cout_s64(DisasContext *s, DisasOps *o)
3399 {
3400 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3401 }
3402
3403 static void cout_subs32(DisasContext *s, DisasOps *o)
3404 {
3405 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3406 }
3407
3408 static void cout_subs64(DisasContext *s, DisasOps *o)
3409 {
3410 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3411 }
3412
3413 static void cout_subu32(DisasContext *s, DisasOps *o)
3414 {
3415 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3416 }
3417
3418 static void cout_subu64(DisasContext *s, DisasOps *o)
3419 {
3420 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3421 }
3422
3423 static void cout_subb32(DisasContext *s, DisasOps *o)
3424 {
3425 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3426 }
3427
3428 static void cout_subb64(DisasContext *s, DisasOps *o)
3429 {
3430 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3431 }
3432
3433 static void cout_tm32(DisasContext *s, DisasOps *o)
3434 {
3435 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3436 }
3437
3438 static void cout_tm64(DisasContext *s, DisasOps *o)
3439 {
3440 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3441 }
3442
3443 /* ====================================================================== */
3444 /* The "PREPeration" generators. These initialize the DisasOps.OUT fields
3445 with the TCG register to which we will write. Used in combination with
3446 the "wout" generators, in some cases we need a new temporary, and in
3447 some cases we can write to a TCG global. */
3448
3449 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3450 {
3451 o->out = tcg_temp_new_i64();
3452 }
3453
3454 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3455 {
3456 o->out = tcg_temp_new_i64();
3457 o->out2 = tcg_temp_new_i64();
3458 }
3459
3460 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3461 {
3462 o->out = regs[get_field(f, r1)];
3463 o->g_out = true;
3464 }
3465
3466 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3467 {
3468 /* ??? Specification exception: r1 must be even. */
3469 int r1 = get_field(f, r1);
3470 o->out = regs[r1];
3471 o->out2 = regs[(r1 + 1) & 15];
3472 o->g_out = o->g_out2 = true;
3473 }
3474
3475 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3476 {
3477 o->out = fregs[get_field(f, r1)];
3478 o->g_out = true;
3479 }
3480
3481 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3482 {
3483 /* ??? Specification exception: r1 must be < 14. */
3484 int r1 = get_field(f, r1);
3485 o->out = fregs[r1];
3486 o->out2 = fregs[(r1 + 2) & 15];
3487 o->g_out = o->g_out2 = true;
3488 }
3489
3490 /* ====================================================================== */
3491 /* The "Write OUTput" generators. These generally perform some non-trivial
3492 copy of data to TCG globals, or to main memory. The trivial cases are
3493 generally handled by having a "prep" generator install the TCG global
3494 as the destination of the operation. */
3495
3496 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3497 {
3498 store_reg(get_field(f, r1), o->out);
3499 }
3500
3501 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3502 {
3503 int r1 = get_field(f, r1);
3504 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3505 }
3506
3507 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3508 {
3509 int r1 = get_field(f, r1);
3510 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3511 }
3512
3513 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3514 {
3515 store_reg32_i64(get_field(f, r1), o->out);
3516 }
3517
3518 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3519 {
3520 /* ??? Specification exception: r1 must be even. */
3521 int r1 = get_field(f, r1);
3522 store_reg32_i64(r1, o->out);
3523 store_reg32_i64((r1 + 1) & 15, o->out2);
3524 }
3525
3526 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3527 {
3528 /* ??? Specification exception: r1 must be even. */
3529 int r1 = get_field(f, r1);
3530 store_reg32_i64((r1 + 1) & 15, o->out);
3531 tcg_gen_shri_i64(o->out, o->out, 32);
3532 store_reg32_i64(r1, o->out);
3533 }
3534
3535 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3536 {
3537 store_freg32_i64(get_field(f, r1), o->out);
3538 }
3539
3540 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3541 {
3542 store_freg(get_field(f, r1), o->out);
3543 }
3544
3545 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3546 {
3547 /* ??? Specification exception: r1 must be < 14. */
3548 int f1 = get_field(s->fields, r1);
3549 store_freg(f1, o->out);
3550 store_freg((f1 + 2) & 15, o->out2);
3551 }
3552
3553 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3554 {
3555 if (get_field(f, r1) != get_field(f, r2)) {
3556 store_reg32_i64(get_field(f, r1), o->out);
3557 }
3558 }
3559
3560 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
3561 {
3562 if (get_field(f, r1) != get_field(f, r2)) {
3563 store_freg32_i64(get_field(f, r1), o->out);
3564 }
3565 }
3566
3567 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3568 {
3569 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
3570 }
3571
3572 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3573 {
3574 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
3575 }
3576
3577 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3578 {
3579 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
3580 }
3581
3582 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3583 {
3584 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
3585 }
3586
3587 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
3588 {
3589 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
3590 }
3591
3592 /* ====================================================================== */
3593 /* The "INput 1" generators. These load the first operand to an insn. */
3594
3595 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3596 {
3597 o->in1 = load_reg(get_field(f, r1));
3598 }
3599
3600 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3601 {
3602 o->in1 = regs[get_field(f, r1)];
3603 o->g_in1 = true;
3604 }
3605
3606 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3607 {
3608 o->in1 = tcg_temp_new_i64();
3609 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
3610 }
3611
3612 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3613 {
3614 o->in1 = tcg_temp_new_i64();
3615 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
3616 }
3617
3618 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
3619 {
3620 o->in1 = tcg_temp_new_i64();
3621 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
3622 }
3623
3624 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
3625 {
3626 /* ??? Specification exception: r1 must be even. */
3627 int r1 = get_field(f, r1);
3628 o->in1 = load_reg((r1 + 1) & 15);
3629 }
3630
3631 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3632 {
3633 /* ??? Specification exception: r1 must be even. */
3634 int r1 = get_field(f, r1);
3635 o->in1 = tcg_temp_new_i64();
3636 tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
3637 }
3638
3639 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3640 {
3641 /* ??? Specification exception: r1 must be even. */
3642 int r1 = get_field(f, r1);
3643 o->in1 = tcg_temp_new_i64();
3644 tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
3645 }
3646
3647 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
3648 {
3649 /* ??? Specification exception: r1 must be even. */
3650 int r1 = get_field(f, r1);
3651 o->in1 = tcg_temp_new_i64();
3652 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
3653 }
3654
3655 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3656 {
3657 o->in1 = load_reg(get_field(f, r2));
3658 }
3659
3660 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3661 {
3662 o->in1 = load_reg(get_field(f, r3));
3663 }
3664
3665 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
3666 {
3667 o->in1 = regs[get_field(f, r3)];
3668 o->g_in1 = true;
3669 }
3670
3671 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3672 {
3673 o->in1 = tcg_temp_new_i64();
3674 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
3675 }
3676
3677 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3678 {
3679 o->in1 = tcg_temp_new_i64();
3680 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
3681 }
3682
3683 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
3684 {
3685 o->in1 = load_freg32_i64(get_field(f, r1));
3686 }
3687
3688 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3689 {
3690 o->in1 = fregs[get_field(f, r1)];
3691 o->g_in1 = true;
3692 }
3693
3694 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3695 {
3696 /* ??? Specification exception: r1 must be < 14. */
3697 int r1 = get_field(f, r1);
3698 o->out = fregs[r1];
3699 o->out2 = fregs[(r1 + 2) & 15];
3700 o->g_out = o->g_out2 = true;
3701 }
3702
3703 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
3704 {
3705 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
3706 }
3707
3708 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
3709 {
3710 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3711 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3712 }
3713
3714 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3715 {
3716 in1_la1(s, f, o);
3717 o->in1 = tcg_temp_new_i64();
3718 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
3719 }
3720
3721 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3722 {
3723 in1_la1(s, f, o);
3724 o->in1 = tcg_temp_new_i64();
3725 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
3726 }
3727
3728 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3729 {
3730 in1_la1(s, f, o);
3731 o->in1 = tcg_temp_new_i64();
3732 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
3733 }
3734
3735 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3736 {
3737 in1_la1(s, f, o);
3738 o->in1 = tcg_temp_new_i64();
3739 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
3740 }
3741
3742 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3743 {
3744 in1_la1(s, f, o);
3745 o->in1 = tcg_temp_new_i64();
3746 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
3747 }
3748
3749 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
3750 {
3751 in1_la1(s, f, o);
3752 o->in1 = tcg_temp_new_i64();
3753 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
3754 }
3755
3756 /* ====================================================================== */
3757 /* The "INput 2" generators. These load the second operand to an insn. */
3758
3759 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
3760 {
3761 o->in2 = regs[get_field(f, r1)];
3762 o->g_in2 = true;
3763 }
3764
3765 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3766 {
3767 o->in2 = tcg_temp_new_i64();
3768 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
3769 }
3770
3771 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3772 {
3773 o->in2 = tcg_temp_new_i64();
3774 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
3775 }
3776
3777 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
3778 {
3779 o->in2 = load_reg(get_field(f, r2));
3780 }
3781
3782 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3783 {
3784 o->in2 = regs[get_field(f, r2)];
3785 o->g_in2 = true;
3786 }
3787
3788 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
3789 {
3790 int r2 = get_field(f, r2);
3791 if (r2 != 0) {
3792 o->in2 = load_reg(r2);
3793 }
3794 }
3795
3796 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
3797 {
3798 o->in2 = tcg_temp_new_i64();
3799 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
3800 }
3801
3802 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3803 {
3804 o->in2 = tcg_temp_new_i64();
3805 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
3806 }
3807
3808 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3809 {
3810 o->in2 = tcg_temp_new_i64();
3811 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
3812 }
3813
3814 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3815 {
3816 o->in2 = tcg_temp_new_i64();
3817 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
3818 }
3819
3820 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
3821 {
3822 o->in2 = load_reg(get_field(f, r3));
3823 }
3824
3825 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3826 {
3827 o->in2 = tcg_temp_new_i64();
3828 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
3829 }
3830
3831 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3832 {
3833 o->in2 = tcg_temp_new_i64();
3834 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
3835 }
3836
3837 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
3838 {
3839 o->in2 = load_freg32_i64(get_field(f, r2));
3840 }
3841
3842 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3843 {
3844 o->in2 = fregs[get_field(f, r2)];
3845 o->g_in2 = true;
3846 }
3847
3848 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
3849 {
3850 /* ??? Specification exception: r1 must be < 14. */
3851 int r2 = get_field(f, r2);
3852 o->in1 = fregs[r2];
3853 o->in2 = fregs[(r2 + 2) & 15];
3854 o->g_in1 = o->g_in2 = true;
3855 }
3856
3857 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
3858 {
3859 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
3860 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
3861 }
3862
3863 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
3864 {
3865 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
3866 }
3867
3868 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
3869 {
3870 help_l2_shift(s, f, o, 31);
3871 }
3872
3873 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
3874 {
3875 help_l2_shift(s, f, o, 63);
3876 }
3877
3878 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3879 {
3880 in2_a2(s, f, o);
3881 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
3882 }
3883
3884 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
3885 {
3886 in2_a2(s, f, o);
3887 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
3888 }
3889
3890 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3891 {
3892 in2_a2(s, f, o);
3893 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3894 }
3895
3896 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3897 {
3898 in2_a2(s, f, o);
3899 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3900 }
3901
3902 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3903 {
3904 in2_a2(s, f, o);
3905 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3906 }
3907
3908 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3909 {
3910 in2_a2(s, f, o);
3911 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3912 }
3913
3914 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3915 {
3916 in2_ri2(s, f, o);
3917 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
3918 }
3919
3920 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
3921 {
3922 in2_ri2(s, f, o);
3923 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
3924 }
3925
3926 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3927 {
3928 in2_ri2(s, f, o);
3929 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
3930 }
3931
3932 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
3933 {
3934 in2_ri2(s, f, o);
3935 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
3936 }
3937
3938 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
3939 {
3940 o->in2 = tcg_const_i64(get_field(f, i2));
3941 }
3942
3943 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
3946 }
3947
3948 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
3949 {
3950 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
3951 }
3952
3953 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
3954 {
3955 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
3956 }
3957
3958 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3959 {
3960 uint64_t i2 = (uint16_t)get_field(f, i2);
3961 o->in2 = tcg_const_i64(i2 << s->insn->data);
3962 }
3963
3964 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
3965 {
3966 uint64_t i2 = (uint32_t)get_field(f, i2);
3967 o->in2 = tcg_const_i64(i2 << s->insn->data);
3968 }
3969
3970 /* ====================================================================== */
3971
3972 /* Find opc within the table of insns. This is formulated as a switch
3973 statement so that (1) we get compile-time notice of cut-paste errors
3974 for duplicated opcodes, and (2) the compiler generates the binary
3975 search tree, rather than us having to post-process the table. */
3976
3977 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
3978 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
3979
3980 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
3981
3982 enum DisasInsnEnum {
3983 #include "insn-data.def"
3984 };
3985
3986 #undef D
3987 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
3988 .opc = OPC, \
3989 .fmt = FMT_##FT, \
3990 .fac = FAC_##FC, \
3991 .name = #NM, \
3992 .help_in1 = in1_##I1, \
3993 .help_in2 = in2_##I2, \
3994 .help_prep = prep_##P, \
3995 .help_wout = wout_##W, \
3996 .help_cout = cout_##CC, \
3997 .help_op = op_##OP, \
3998 .data = D \
3999 },
4000
4001 /* Allow 0 to be used for NULL in the table below. */
4002 #define in1_0 NULL
4003 #define in2_0 NULL
4004 #define prep_0 NULL
4005 #define wout_0 NULL
4006 #define cout_0 NULL
4007 #define op_0 NULL
4008
4009 static const DisasInsn insn_info[] = {
4010 #include "insn-data.def"
4011 };
4012
4013 #undef D
4014 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4015 case OPC: return &insn_info[insn_ ## NM];
4016
4017 static const DisasInsn *lookup_opc(uint16_t opc)
4018 {
4019 switch (opc) {
4020 #include "insn-data.def"
4021 default:
4022 return NULL;
4023 }
4024 }
4025
4026 #undef D
4027 #undef C
4028
4029 /* Extract a field from the insn. The INSN should be left-aligned in
4030 the uint64_t so that we can more easily utilize the big-bit-endian
4031 definitions we extract from the Principals of Operation. */
4032
4033 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4034 {
4035 uint32_t r, m;
4036
4037 if (f->size == 0) {
4038 return;
4039 }
4040
4041 /* Zero extract the field from the insn. */
4042 r = (insn << f->beg) >> (64 - f->size);
4043
4044 /* Sign-extend, or un-swap the field as necessary. */
4045 switch (f->type) {
4046 case 0: /* unsigned */
4047 break;
4048 case 1: /* signed */
4049 assert(f->size <= 32);
4050 m = 1u << (f->size - 1);
4051 r = (r ^ m) - m;
4052 break;
4053 case 2: /* dl+dh split, signed 20 bit. */
4054 r = ((int8_t)r << 12) | (r >> 8);
4055 break;
4056 default:
4057 abort();
4058 }
4059
4060 /* Validate that the "compressed" encoding we selected above is valid.
4061 I.e. we havn't make two different original fields overlap. */
4062 assert(((o->presentC >> f->indexC) & 1) == 0);
4063 o->presentC |= 1 << f->indexC;
4064 o->presentO |= 1 << f->indexO;
4065
4066 o->c[f->indexC] = r;
4067 }
4068
4069 /* Lookup the insn at the current PC, extracting the operands into O and
4070 returning the info struct for the insn. Returns NULL for invalid insn. */
4071
4072 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4073 DisasFields *f)
4074 {
4075 uint64_t insn, pc = s->pc;
4076 int op, op2, ilen;
4077 const DisasInsn *info;
4078
4079 insn = ld_code2(env, pc);
4080 op = (insn >> 8) & 0xff;
4081 ilen = get_ilen(op);
4082 s->next_pc = s->pc + ilen;
4083
4084 switch (ilen) {
4085 case 2:
4086 insn = insn << 48;
4087 break;
4088 case 4:
4089 insn = ld_code4(env, pc) << 32;
4090 break;
4091 case 6:
4092 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4093 break;
4094 default:
4095 abort();
4096 }
4097
4098 /* We can't actually determine the insn format until we've looked up
4099 the full insn opcode. Which we can't do without locating the
4100 secondary opcode. Assume by default that OP2 is at bit 40; for
4101 those smaller insns that don't actually have a secondary opcode
4102 this will correctly result in OP2 = 0. */
4103 switch (op) {
4104 case 0x01: /* E */
4105 case 0x80: /* S */
4106 case 0x82: /* S */
4107 case 0x93: /* S */
4108 case 0xb2: /* S, RRF, RRE */
4109 case 0xb3: /* RRE, RRD, RRF */
4110 case 0xb9: /* RRE, RRF */
4111 case 0xe5: /* SSE, SIL */
4112 op2 = (insn << 8) >> 56;
4113 break;
4114 case 0xa5: /* RI */
4115 case 0xa7: /* RI */
4116 case 0xc0: /* RIL */
4117 case 0xc2: /* RIL */
4118 case 0xc4: /* RIL */
4119 case 0xc6: /* RIL */
4120 case 0xc8: /* SSF */
4121 case 0xcc: /* RIL */
4122 op2 = (insn << 12) >> 60;
4123 break;
4124 case 0xd0 ... 0xdf: /* SS */
4125 case 0xe1: /* SS */
4126 case 0xe2: /* SS */
4127 case 0xe8: /* SS */
4128 case 0xe9: /* SS */
4129 case 0xea: /* SS */
4130 case 0xee ... 0xf3: /* SS */
4131 case 0xf8 ... 0xfd: /* SS */
4132 op2 = 0;
4133 break;
4134 default:
4135 op2 = (insn << 40) >> 56;
4136 break;
4137 }
4138
4139 memset(f, 0, sizeof(*f));
4140 f->op = op;
4141 f->op2 = op2;
4142
4143 /* Lookup the instruction. */
4144 info = lookup_opc(op << 8 | op2);
4145
4146 /* If we found it, extract the operands. */
4147 if (info != NULL) {
4148 DisasFormat fmt = info->fmt;
4149 int i;
4150
4151 for (i = 0; i < NUM_C_FIELD; ++i) {
4152 extract_field(f, &format_info[fmt].op[i], insn);
4153 }
4154 }
4155 return info;
4156 }
4157
4158 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4159 {
4160 const DisasInsn *insn;
4161 ExitStatus ret = NO_EXIT;
4162 DisasFields f;
4163 DisasOps o;
4164
4165 insn = extract_insn(env, s, &f);
4166
4167 /* If not found, try the old interpreter. This includes ILLOPC. */
4168 if (insn == NULL) {
4169 disas_s390_insn(env, s);
4170 switch (s->is_jmp) {
4171 case DISAS_NEXT:
4172 ret = NO_EXIT;
4173 break;
4174 case DISAS_TB_JUMP:
4175 ret = EXIT_GOTO_TB;
4176 break;
4177 case DISAS_JUMP:
4178 ret = EXIT_PC_UPDATED;
4179 break;
4180 case DISAS_EXCP:
4181 ret = EXIT_NORETURN;
4182 break;
4183 default:
4184 abort();
4185 }
4186
4187 s->pc = s->next_pc;
4188 return ret;
4189 }
4190
4191 /* Set up the strutures we use to communicate with the helpers. */
4192 s->insn = insn;
4193 s->fields = &f;
4194 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4195 TCGV_UNUSED_I64(o.out);
4196 TCGV_UNUSED_I64(o.out2);
4197 TCGV_UNUSED_I64(o.in1);
4198 TCGV_UNUSED_I64(o.in2);
4199 TCGV_UNUSED_I64(o.addr1);
4200
4201 /* Implement the instruction. */
4202 if (insn->help_in1) {
4203 insn->help_in1(s, &f, &o);
4204 }
4205 if (insn->help_in2) {
4206 insn->help_in2(s, &f, &o);
4207 }
4208 if (insn->help_prep) {
4209 insn->help_prep(s, &f, &o);
4210 }
4211 if (insn->help_op) {
4212 ret = insn->help_op(s, &o);
4213 }
4214 if (insn->help_wout) {
4215 insn->help_wout(s, &f, &o);
4216 }
4217 if (insn->help_cout) {
4218 insn->help_cout(s, &o);
4219 }
4220
4221 /* Free any temporaries created by the helpers. */
4222 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4223 tcg_temp_free_i64(o.out);
4224 }
4225 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4226 tcg_temp_free_i64(o.out2);
4227 }
4228 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4229 tcg_temp_free_i64(o.in1);
4230 }
4231 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4232 tcg_temp_free_i64(o.in2);
4233 }
4234 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4235 tcg_temp_free_i64(o.addr1);
4236 }
4237
4238 /* Advance to the next instruction. */
4239 s->pc = s->next_pc;
4240 return ret;
4241 }
4242
4243 static inline void gen_intermediate_code_internal(CPUS390XState *env,
4244 TranslationBlock *tb,
4245 int search_pc)
4246 {
4247 DisasContext dc;
4248 target_ulong pc_start;
4249 uint64_t next_page_start;
4250 uint16_t *gen_opc_end;
4251 int j, lj = -1;
4252 int num_insns, max_insns;
4253 CPUBreakpoint *bp;
4254 ExitStatus status;
4255 bool do_debug;
4256
4257 pc_start = tb->pc;
4258
4259 /* 31-bit mode */
4260 if (!(tb->flags & FLAG_MASK_64)) {
4261 pc_start &= 0x7fffffff;
4262 }
4263
4264 dc.tb = tb;
4265 dc.pc = pc_start;
4266 dc.cc_op = CC_OP_DYNAMIC;
4267 do_debug = dc.singlestep_enabled = env->singlestep_enabled;
4268 dc.is_jmp = DISAS_NEXT;
4269
4270 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4271
4272 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4273
4274 num_insns = 0;
4275 max_insns = tb->cflags & CF_COUNT_MASK;
4276 if (max_insns == 0) {
4277 max_insns = CF_COUNT_MASK;
4278 }
4279
4280 gen_icount_start();
4281
4282 do {
4283 if (search_pc) {
4284 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4285 if (lj < j) {
4286 lj++;
4287 while (lj < j) {
4288 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4289 }
4290 }
4291 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4292 gen_opc_cc_op[lj] = dc.cc_op;
4293 tcg_ctx.gen_opc_instr_start[lj] = 1;
4294 tcg_ctx.gen_opc_icount[lj] = num_insns;
4295 }
4296 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4297 gen_io_start();
4298 }
4299
4300 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4301 tcg_gen_debug_insn_start(dc.pc);
4302 }
4303
4304 status = NO_EXIT;
4305 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
4306 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4307 if (bp->pc == dc.pc) {
4308 status = EXIT_PC_STALE;
4309 do_debug = true;
4310 break;
4311 }
4312 }
4313 }
4314 if (status == NO_EXIT) {
4315 status = translate_one(env, &dc);
4316 }
4317
4318 /* If we reach a page boundary, are single stepping,
4319 or exhaust instruction count, stop generation. */
4320 if (status == NO_EXIT
4321 && (dc.pc >= next_page_start
4322 || tcg_ctx.gen_opc_ptr >= gen_opc_end
4323 || num_insns >= max_insns
4324 || singlestep
4325 || env->singlestep_enabled)) {
4326 status = EXIT_PC_STALE;
4327 }
4328 } while (status == NO_EXIT);
4329
4330 if (tb->cflags & CF_LAST_IO) {
4331 gen_io_end();
4332 }
4333
4334 switch (status) {
4335 case EXIT_GOTO_TB:
4336 case EXIT_NORETURN:
4337 break;
4338 case EXIT_PC_STALE:
4339 update_psw_addr(&dc);
4340 /* FALLTHRU */
4341 case EXIT_PC_UPDATED:
4342 if (singlestep && dc.cc_op != CC_OP_DYNAMIC) {
4343 gen_op_calc_cc(&dc);
4344 } else {
4345 /* Next TB starts off with CC_OP_DYNAMIC,
4346 so make sure the cc op type is in env */
4347 gen_op_set_cc_op(&dc);
4348 }
4349 if (do_debug) {
4350 gen_exception(EXCP_DEBUG);
4351 } else {
4352 /* Generate the return instruction */
4353 tcg_gen_exit_tb(0);
4354 }
4355 break;
4356 default:
4357 abort();
4358 }
4359
4360 gen_icount_end(tb, num_insns);
4361 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4362 if (search_pc) {
4363 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4364 lj++;
4365 while (lj <= j) {
4366 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4367 }
4368 } else {
4369 tb->size = dc.pc - pc_start;
4370 tb->icount = num_insns;
4371 }
4372
4373 #if defined(S390X_DEBUG_DISAS)
4374 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4375 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4376 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4377 qemu_log("\n");
4378 }
4379 #endif
4380 }
4381
4382 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
4383 {
4384 gen_intermediate_code_internal(env, tb, 0);
4385 }
4386
4387 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
4388 {
4389 gen_intermediate_code_internal(env, tb, 1);
4390 }
4391
4392 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
4393 {
4394 int cc_op;
4395 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
4396 cc_op = gen_opc_cc_op[pc_pos];
4397 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
4398 env->cc_op = cc_op;
4399 }
4400 }
QEMU modified to work with kvm