target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         env->pstate = PSTATE_MODE_EL1h;
 117         env->pc = cpu->rvbar;
 118 #endif
 119     } else {
 120 #if defined(CONFIG_USER_ONLY)
 121         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 122         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 123 #endif
 124     }
 125
 126 #if defined(CONFIG_USER_ONLY)
 127     env->uncached_cpsr = ARM_CPU_MODE_USR;
 128     /* For user mode we must enable access to coprocessors */
 129     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 130     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 131         env->cp15.c15_cpar = 3;
 132     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 133         env->cp15.c15_cpar = 1;
 134     }
 135 #else
 136     /* SVC mode with interrupts disabled.  */
 137     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 138     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 139     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 140      * clear at reset. Initial SP and PC are loaded from ROM.
 141      */
 142     if (IS_M(env)) {
 143         uint32_t initial_msp; /* Loaded from 0x0 */
 144         uint32_t initial_pc; /* Loaded from 0x4 */
 145         uint8_t *rom;
 146
 147         env->daif &= ~PSTATE_I;
 148         rom = rom_ptr(0);
 149         if (rom) {
 150             /* Address zero is covered by ROM which hasn't yet been
 151              * copied into physical memory.
 152              */
 153             initial_msp = ldl_p(rom);
 154             initial_pc = ldl_p(rom + 4);
 155         } else {
 156             /* Address zero not covered by a ROM blob, or the ROM blob
 157              * is in non-modifiable memory and this is a second reset after
 158              * it got copied into memory. In the latter case, rom_ptr
 159              * will return a NULL pointer and we should use ldl_phys instead.
 160              */
 161             initial_msp = ldl_phys(s->as, 0);
 162             initial_pc = ldl_phys(s->as, 4);
 163         }
 164
 165         env->regs[13] = initial_msp & 0xFFFFFFFC;
 166         env->regs[15] = initial_pc & ~1;
 167         env->thumb = initial_pc & 1;
 168     }
 169
 170     if (env->cp15.c1_sys & SCTLR_V) {
 171         env->regs[15] = 0xFFFF0000;
 172     }
 173
 174     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 175 #endif
 176     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 177     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 178     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 179     set_float_detect_tininess(float_tininess_before_rounding,
 180                               &env->vfp.fp_status);
 181     set_float_detect_tininess(float_tininess_before_rounding,
 182                               &env->vfp.standard_fp_status);
 183     tlb_flush(s, 1);
 184
 185 #ifndef CONFIG_USER_ONLY
 186     if (kvm_enabled()) {
 187         kvm_arm_reset_vcpu(cpu);
 188     }
 189 #endif
 190
 191     hw_breakpoint_update_all(cpu);
 192     hw_watchpoint_update_all(cpu);
 193 }
 194
 195 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 196 {
 197     CPUClass *cc = CPU_GET_CLASS(cs);
 198     bool ret = false;
 199
 200     if (interrupt_request & CPU_INTERRUPT_FIQ
 201         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 202         cs->exception_index = EXCP_FIQ;
 203         cc->do_interrupt(cs);
 204         ret = true;
 205     }
 206     /* ARMv7-M interrupt return works by loading a magic value
 207        into the PC.  On real hardware the load causes the
 208        return to occur.  The qemu implementation performs the
 209        jump normally, then does the exception return when the
 210        CPU tries to execute code at the magic address.
 211        This will cause the magic PC value to be pushed to
 212        the stack if an interrupt occurred at the wrong time.
 213        We avoid this by disabling interrupts when
 214        pc contains a magic address.  */
 215     if (interrupt_request & CPU_INTERRUPT_HARD
 216         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 217         cs->exception_index = EXCP_IRQ;
 218         cc->do_interrupt(cs);
 219         ret = true;
 220     }
 221     if (interrupt_request & CPU_INTERRUPT_VIRQ
 222         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 223         cs->exception_index = EXCP_VIRQ;
 224         cc->do_interrupt(cs);
 225         ret = true;
 226     }
 227     if (interrupt_request & CPU_INTERRUPT_VFIQ
 228         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 229         cs->exception_index = EXCP_VFIQ;
 230         cc->do_interrupt(cs);
 231         ret = true;
 232     }
 233
 234     return ret;
 235 }
 236
 237 #ifndef CONFIG_USER_ONLY
 238 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 239 {
 240     ARMCPU *cpu = opaque;
 241     CPUARMState *env = &cpu->env;
 242     CPUState *cs = CPU(cpu);
 243     static const int mask[] = {
 244         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 245         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 246         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 247         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 248     };
 249
 250     switch (irq) {
 251     case ARM_CPU_VIRQ:
 252     case ARM_CPU_VFIQ:
 253         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 254             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 255                      __func__, irq);
 256         }
 257         /* fall through */
 258     case ARM_CPU_IRQ:
 259     case ARM_CPU_FIQ:
 260         if (level) {
 261             cpu_interrupt(cs, mask[irq]);
 262         } else {
 263             cpu_reset_interrupt(cs, mask[irq]);
 264         }
 265         break;
 266     default:
 267         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 268     }
 269 }
 270
 271 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 272 {
 273 #ifdef CONFIG_KVM
 274     ARMCPU *cpu = opaque;
 275     CPUState *cs = CPU(cpu);
 276     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 277
 278     switch (irq) {
 279     case ARM_CPU_IRQ:
 280         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 281         break;
 282     case ARM_CPU_FIQ:
 283         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 284         break;
 285     default:
 286         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 287     }
 288     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 289     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 290 #endif
 291 }
 292 #endif
 293
 294 static inline void set_feature(CPUARMState *env, int feature)
 295 {
 296     env->features |= 1ULL << feature;
 297 }
 298
 299 static void arm_cpu_initfn(Object *obj)
 300 {
 301     CPUState *cs = CPU(obj);
 302     ARMCPU *cpu = ARM_CPU(obj);
 303     static bool inited;
 304
 305     cs->env_ptr = &cpu->env;
 306     cpu_exec_init(&cpu->env);
 307     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 308                                          g_free, g_free);
 309
 310 #ifndef CONFIG_USER_ONLY
 311     /* Our inbound IRQ and FIQ lines */
 312     if (kvm_enabled()) {
 313         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 314          * the same interface as non-KVM CPUs.
 315          */
 316         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 317     } else {
 318         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 319     }
 320
 321     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 322                                                 arm_gt_ptimer_cb, cpu);
 323     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 324                                                 arm_gt_vtimer_cb, cpu);
 325     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 326                        ARRAY_SIZE(cpu->gt_timer_outputs));
 327 #endif
 328
 329     /* DTB consumers generally don't in fact care what the 'compatible'
 330      * string is, so always provide some string and trust that a hypothetical
 331      * picky DTB consumer will also provide a helpful error message.
 332      */
 333     cpu->dtb_compatible = "qemu,unknown";
 334     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 335     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 336
 337     if (tcg_enabled()) {
 338         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 339         if (!inited) {
 340             inited = true;
 341             arm_translate_init();
 342         }
 343     }
 344 }
 345
 346 static Property arm_cpu_reset_cbar_property =
 347             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 348
 349 static Property arm_cpu_reset_hivecs_property =
 350             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 351
 352 static Property arm_cpu_rvbar_property =
 353             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 354
 355 static void arm_cpu_post_init(Object *obj)
 356 {
 357     ARMCPU *cpu = ARM_CPU(obj);
 358
 359     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 360         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 361         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 362                                  &error_abort);
 363     }
 364
 365     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 366         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 367                                  &error_abort);
 368     }
 369
 370     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 371         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 372                                  &error_abort);
 373     }
 374 }
 375
 376 static void arm_cpu_finalizefn(Object *obj)
 377 {
 378     ARMCPU *cpu = ARM_CPU(obj);
 379     g_hash_table_destroy(cpu->cp_regs);
 380 }
 381
 382 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 383 {
 384     CPUState *cs = CPU(dev);
 385     ARMCPU *cpu = ARM_CPU(dev);
 386     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 387     CPUARMState *env = &cpu->env;
 388
 389     /* Some features automatically imply others: */
 390     if (arm_feature(env, ARM_FEATURE_V8)) {
 391         set_feature(env, ARM_FEATURE_V7);
 392         set_feature(env, ARM_FEATURE_ARM_DIV);
 393         set_feature(env, ARM_FEATURE_LPAE);
 394     }
 395     if (arm_feature(env, ARM_FEATURE_V7)) {
 396         set_feature(env, ARM_FEATURE_VAPA);
 397         set_feature(env, ARM_FEATURE_THUMB2);
 398         set_feature(env, ARM_FEATURE_MPIDR);
 399         if (!arm_feature(env, ARM_FEATURE_M)) {
 400             set_feature(env, ARM_FEATURE_V6K);
 401         } else {
 402             set_feature(env, ARM_FEATURE_V6);
 403         }
 404     }
 405     if (arm_feature(env, ARM_FEATURE_V6K)) {
 406         set_feature(env, ARM_FEATURE_V6);
 407         set_feature(env, ARM_FEATURE_MVFR);
 408     }
 409     if (arm_feature(env, ARM_FEATURE_V6)) {
 410         set_feature(env, ARM_FEATURE_V5);
 411         if (!arm_feature(env, ARM_FEATURE_M)) {
 412             set_feature(env, ARM_FEATURE_AUXCR);
 413         }
 414     }
 415     if (arm_feature(env, ARM_FEATURE_V5)) {
 416         set_feature(env, ARM_FEATURE_V4T);
 417     }
 418     if (arm_feature(env, ARM_FEATURE_M)) {
 419         set_feature(env, ARM_FEATURE_THUMB_DIV);
 420     }
 421     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 422         set_feature(env, ARM_FEATURE_THUMB_DIV);
 423     }
 424     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 425         set_feature(env, ARM_FEATURE_VFP3);
 426         set_feature(env, ARM_FEATURE_VFP_FP16);
 427     }
 428     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 429         set_feature(env, ARM_FEATURE_VFP);
 430     }
 431     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 432         set_feature(env, ARM_FEATURE_V7MP);
 433         set_feature(env, ARM_FEATURE_PXN);
 434     }
 435     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 436         set_feature(env, ARM_FEATURE_CBAR);
 437     }
 438
 439     if (cpu->reset_hivecs) {
 440             cpu->reset_sctlr |= (1 << 13);
 441     }
 442
 443     register_cp_regs_for_features(cpu);
 444     arm_cpu_register_gdb_regs_for_features(cpu);
 445
 446     init_cpreg_list(cpu);
 447
 448     qemu_init_vcpu(cs);
 449     cpu_reset(cs);
 450
 451     acc->parent_realize(dev, errp);
 452 }
 453
 454 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 455 {
 456     ObjectClass *oc;
 457     char *typename;
 458
 459     if (!cpu_model) {
 460         return NULL;
 461     }
 462
 463     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 464     oc = object_class_by_name(typename);
 465     g_free(typename);
 466     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 467         object_class_is_abstract(oc)) {
 468         return NULL;
 469     }
 470     return oc;
 471 }
 472
 473 /* CPU models. These are not needed for the AArch64 linux-user build. */
 474 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 475
 476 static void arm926_initfn(Object *obj)
 477 {
 478     ARMCPU *cpu = ARM_CPU(obj);
 479
 480     cpu->dtb_compatible = "arm,arm926";
 481     set_feature(&cpu->env, ARM_FEATURE_V5);
 482     set_feature(&cpu->env, ARM_FEATURE_VFP);
 483     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 484     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 485     cpu->midr = 0x41069265;
 486     cpu->reset_fpsid = 0x41011090;
 487     cpu->ctr = 0x1dd20d2;
 488     cpu->reset_sctlr = 0x00090078;
 489 }
 490
 491 static void arm946_initfn(Object *obj)
 492 {
 493     ARMCPU *cpu = ARM_CPU(obj);
 494
 495     cpu->dtb_compatible = "arm,arm946";
 496     set_feature(&cpu->env, ARM_FEATURE_V5);
 497     set_feature(&cpu->env, ARM_FEATURE_MPU);
 498     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 499     cpu->midr = 0x41059461;
 500     cpu->ctr = 0x0f004006;
 501     cpu->reset_sctlr = 0x00000078;
 502 }
 503
 504 static void arm1026_initfn(Object *obj)
 505 {
 506     ARMCPU *cpu = ARM_CPU(obj);
 507
 508     cpu->dtb_compatible = "arm,arm1026";
 509     set_feature(&cpu->env, ARM_FEATURE_V5);
 510     set_feature(&cpu->env, ARM_FEATURE_VFP);
 511     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 512     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 513     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 514     cpu->midr = 0x4106a262;
 515     cpu->reset_fpsid = 0x410110a0;
 516     cpu->ctr = 0x1dd20d2;
 517     cpu->reset_sctlr = 0x00090078;
 518     cpu->reset_auxcr = 1;
 519     {
 520         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 521         ARMCPRegInfo ifar = {
 522             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 523             .access = PL1_RW,
 524             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 525             .resetvalue = 0
 526         };
 527         define_one_arm_cp_reg(cpu, &ifar);
 528     }
 529 }
 530
 531 static void arm1136_r2_initfn(Object *obj)
 532 {
 533     ARMCPU *cpu = ARM_CPU(obj);
 534     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 535      * older core than plain "arm1136". In particular this does not
 536      * have the v6K features.
 537      * These ID register values are correct for 1136 but may be wrong
 538      * for 1136_r2 (in particular r0p2 does not actually implement most
 539      * of the ID registers).
 540      */
 541
 542     cpu->dtb_compatible = "arm,arm1136";
 543     set_feature(&cpu->env, ARM_FEATURE_V6);
 544     set_feature(&cpu->env, ARM_FEATURE_VFP);
 545     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 546     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 547     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 548     cpu->midr = 0x4107b362;
 549     cpu->reset_fpsid = 0x410120b4;
 550     cpu->mvfr0 = 0x11111111;
 551     cpu->mvfr1 = 0x00000000;
 552     cpu->ctr = 0x1dd20d2;
 553     cpu->reset_sctlr = 0x00050078;
 554     cpu->id_pfr0 = 0x111;
 555     cpu->id_pfr1 = 0x1;
 556     cpu->id_dfr0 = 0x2;
 557     cpu->id_afr0 = 0x3;
 558     cpu->id_mmfr0 = 0x01130003;
 559     cpu->id_mmfr1 = 0x10030302;
 560     cpu->id_mmfr2 = 0x01222110;
 561     cpu->id_isar0 = 0x00140011;
 562     cpu->id_isar1 = 0x12002111;
 563     cpu->id_isar2 = 0x11231111;
 564     cpu->id_isar3 = 0x01102131;
 565     cpu->id_isar4 = 0x141;
 566     cpu->reset_auxcr = 7;
 567 }
 568
 569 static void arm1136_initfn(Object *obj)
 570 {
 571     ARMCPU *cpu = ARM_CPU(obj);
 572
 573     cpu->dtb_compatible = "arm,arm1136";
 574     set_feature(&cpu->env, ARM_FEATURE_V6K);
 575     set_feature(&cpu->env, ARM_FEATURE_V6);
 576     set_feature(&cpu->env, ARM_FEATURE_VFP);
 577     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 578     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 579     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 580     cpu->midr = 0x4117b363;
 581     cpu->reset_fpsid = 0x410120b4;
 582     cpu->mvfr0 = 0x11111111;
 583     cpu->mvfr1 = 0x00000000;
 584     cpu->ctr = 0x1dd20d2;
 585     cpu->reset_sctlr = 0x00050078;
 586     cpu->id_pfr0 = 0x111;
 587     cpu->id_pfr1 = 0x1;
 588     cpu->id_dfr0 = 0x2;
 589     cpu->id_afr0 = 0x3;
 590     cpu->id_mmfr0 = 0x01130003;
 591     cpu->id_mmfr1 = 0x10030302;
 592     cpu->id_mmfr2 = 0x01222110;
 593     cpu->id_isar0 = 0x00140011;
 594     cpu->id_isar1 = 0x12002111;
 595     cpu->id_isar2 = 0x11231111;
 596     cpu->id_isar3 = 0x01102131;
 597     cpu->id_isar4 = 0x141;
 598     cpu->reset_auxcr = 7;
 599 }
 600
 601 static void arm1176_initfn(Object *obj)
 602 {
 603     ARMCPU *cpu = ARM_CPU(obj);
 604
 605     cpu->dtb_compatible = "arm,arm1176";
 606     set_feature(&cpu->env, ARM_FEATURE_V6K);
 607     set_feature(&cpu->env, ARM_FEATURE_VFP);
 608     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 609     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 610     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 611     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 612     cpu->midr = 0x410fb767;
 613     cpu->reset_fpsid = 0x410120b5;
 614     cpu->mvfr0 = 0x11111111;
 615     cpu->mvfr1 = 0x00000000;
 616     cpu->ctr = 0x1dd20d2;
 617     cpu->reset_sctlr = 0x00050078;
 618     cpu->id_pfr0 = 0x111;
 619     cpu->id_pfr1 = 0x11;
 620     cpu->id_dfr0 = 0x33;
 621     cpu->id_afr0 = 0;
 622     cpu->id_mmfr0 = 0x01130003;
 623     cpu->id_mmfr1 = 0x10030302;
 624     cpu->id_mmfr2 = 0x01222100;
 625     cpu->id_isar0 = 0x0140011;
 626     cpu->id_isar1 = 0x12002111;
 627     cpu->id_isar2 = 0x11231121;
 628     cpu->id_isar3 = 0x01102131;
 629     cpu->id_isar4 = 0x01141;
 630     cpu->reset_auxcr = 7;
 631 }
 632
 633 static void arm11mpcore_initfn(Object *obj)
 634 {
 635     ARMCPU *cpu = ARM_CPU(obj);
 636
 637     cpu->dtb_compatible = "arm,arm11mpcore";
 638     set_feature(&cpu->env, ARM_FEATURE_V6K);
 639     set_feature(&cpu->env, ARM_FEATURE_VFP);
 640     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 641     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 642     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 643     cpu->midr = 0x410fb022;
 644     cpu->reset_fpsid = 0x410120b4;
 645     cpu->mvfr0 = 0x11111111;
 646     cpu->mvfr1 = 0x00000000;
 647     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 648     cpu->id_pfr0 = 0x111;
 649     cpu->id_pfr1 = 0x1;
 650     cpu->id_dfr0 = 0;
 651     cpu->id_afr0 = 0x2;
 652     cpu->id_mmfr0 = 0x01100103;
 653     cpu->id_mmfr1 = 0x10020302;
 654     cpu->id_mmfr2 = 0x01222000;
 655     cpu->id_isar0 = 0x00100011;
 656     cpu->id_isar1 = 0x12002111;
 657     cpu->id_isar2 = 0x11221011;
 658     cpu->id_isar3 = 0x01102131;
 659     cpu->id_isar4 = 0x141;
 660     cpu->reset_auxcr = 1;
 661 }
 662
 663 static void cortex_m3_initfn(Object *obj)
 664 {
 665     ARMCPU *cpu = ARM_CPU(obj);
 666     set_feature(&cpu->env, ARM_FEATURE_V7);
 667     set_feature(&cpu->env, ARM_FEATURE_M);
 668     cpu->midr = 0x410fc231;
 669 }
 670
 671 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 672 {
 673 #ifndef CONFIG_USER_ONLY
 674     CPUClass *cc = CPU_CLASS(oc);
 675
 676     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 677 #endif
 678 }
 679
 680 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 681     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 682       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 683     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 684       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 685     REGINFO_SENTINEL
 686 };
 687
 688 static void cortex_a8_initfn(Object *obj)
 689 {
 690     ARMCPU *cpu = ARM_CPU(obj);
 691
 692     cpu->dtb_compatible = "arm,cortex-a8";
 693     set_feature(&cpu->env, ARM_FEATURE_V7);
 694     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 695     set_feature(&cpu->env, ARM_FEATURE_NEON);
 696     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 697     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 698     cpu->midr = 0x410fc080;
 699     cpu->reset_fpsid = 0x410330c0;
 700     cpu->mvfr0 = 0x11110222;
 701     cpu->mvfr1 = 0x00011100;
 702     cpu->ctr = 0x82048004;
 703     cpu->reset_sctlr = 0x00c50078;
 704     cpu->id_pfr0 = 0x1031;
 705     cpu->id_pfr1 = 0x11;
 706     cpu->id_dfr0 = 0x400;
 707     cpu->id_afr0 = 0;
 708     cpu->id_mmfr0 = 0x31100003;
 709     cpu->id_mmfr1 = 0x20000000;
 710     cpu->id_mmfr2 = 0x01202000;
 711     cpu->id_mmfr3 = 0x11;
 712     cpu->id_isar0 = 0x00101111;
 713     cpu->id_isar1 = 0x12112111;
 714     cpu->id_isar2 = 0x21232031;
 715     cpu->id_isar3 = 0x11112131;
 716     cpu->id_isar4 = 0x00111142;
 717     cpu->dbgdidr = 0x15141000;
 718     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 719     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 720     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 721     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 722     cpu->reset_auxcr = 2;
 723     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 724 }
 725
 726 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 727     /* power_control should be set to maximum latency. Again,
 728      * default to 0 and set by private hook
 729      */
 730     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 731       .access = PL1_RW, .resetvalue = 0,
 732       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 733     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 734       .access = PL1_RW, .resetvalue = 0,
 735       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 736     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 737       .access = PL1_RW, .resetvalue = 0,
 738       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 739     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 740       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 741     /* TLB lockdown control */
 742     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 743       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 744     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 745       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 746     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 747       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 748     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 749       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 750     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 751       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 752     REGINFO_SENTINEL
 753 };
 754
 755 static void cortex_a9_initfn(Object *obj)
 756 {
 757     ARMCPU *cpu = ARM_CPU(obj);
 758
 759     cpu->dtb_compatible = "arm,cortex-a9";
 760     set_feature(&cpu->env, ARM_FEATURE_V7);
 761     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 762     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 763     set_feature(&cpu->env, ARM_FEATURE_NEON);
 764     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 765     /* Note that A9 supports the MP extensions even for
 766      * A9UP and single-core A9MP (which are both different
 767      * and valid configurations; we don't model A9UP).
 768      */
 769     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 770     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 771     cpu->midr = 0x410fc090;
 772     cpu->reset_fpsid = 0x41033090;
 773     cpu->mvfr0 = 0x11110222;
 774     cpu->mvfr1 = 0x01111111;
 775     cpu->ctr = 0x80038003;
 776     cpu->reset_sctlr = 0x00c50078;
 777     cpu->id_pfr0 = 0x1031;
 778     cpu->id_pfr1 = 0x11;
 779     cpu->id_dfr0 = 0x000;
 780     cpu->id_afr0 = 0;
 781     cpu->id_mmfr0 = 0x00100103;
 782     cpu->id_mmfr1 = 0x20000000;
 783     cpu->id_mmfr2 = 0x01230000;
 784     cpu->id_mmfr3 = 0x00002111;
 785     cpu->id_isar0 = 0x00101111;
 786     cpu->id_isar1 = 0x13112111;
 787     cpu->id_isar2 = 0x21232041;
 788     cpu->id_isar3 = 0x11112131;
 789     cpu->id_isar4 = 0x00111142;
 790     cpu->dbgdidr = 0x35141000;
 791     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 792     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 793     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 794     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 795 }
 796
 797 #ifndef CONFIG_USER_ONLY
 798 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 799 {
 800     /* Linux wants the number of processors from here.
 801      * Might as well set the interrupt-controller bit too.
 802      */
 803     return ((smp_cpus - 1) << 24) | (1 << 23);
 804 }
 805 #endif
 806
 807 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 808 #ifndef CONFIG_USER_ONLY
 809     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 810       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 811       .writefn = arm_cp_write_ignore, },
 812 #endif
 813     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 814       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 815     REGINFO_SENTINEL
 816 };
 817
 818 static void cortex_a15_initfn(Object *obj)
 819 {
 820     ARMCPU *cpu = ARM_CPU(obj);
 821
 822     cpu->dtb_compatible = "arm,cortex-a15";
 823     set_feature(&cpu->env, ARM_FEATURE_V7);
 824     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 825     set_feature(&cpu->env, ARM_FEATURE_NEON);
 826     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 827     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 828     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 829     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 830     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 831     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 832     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 833     cpu->midr = 0x412fc0f1;
 834     cpu->reset_fpsid = 0x410430f0;
 835     cpu->mvfr0 = 0x10110222;
 836     cpu->mvfr1 = 0x11111111;
 837     cpu->ctr = 0x8444c004;
 838     cpu->reset_sctlr = 0x00c50078;
 839     cpu->id_pfr0 = 0x00001131;
 840     cpu->id_pfr1 = 0x00011011;
 841     cpu->id_dfr0 = 0x02010555;
 842     cpu->id_afr0 = 0x00000000;
 843     cpu->id_mmfr0 = 0x10201105;
 844     cpu->id_mmfr1 = 0x20000000;
 845     cpu->id_mmfr2 = 0x01240000;
 846     cpu->id_mmfr3 = 0x02102211;
 847     cpu->id_isar0 = 0x02101110;
 848     cpu->id_isar1 = 0x13112111;
 849     cpu->id_isar2 = 0x21232041;
 850     cpu->id_isar3 = 0x11112131;
 851     cpu->id_isar4 = 0x10011142;
 852     cpu->dbgdidr = 0x3515f021;
 853     cpu->clidr = 0x0a200023;
 854     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 855     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 856     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 857     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 858 }
 859
 860 static void ti925t_initfn(Object *obj)
 861 {
 862     ARMCPU *cpu = ARM_CPU(obj);
 863     set_feature(&cpu->env, ARM_FEATURE_V4T);
 864     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 865     cpu->midr = ARM_CPUID_TI925T;
 866     cpu->ctr = 0x5109149;
 867     cpu->reset_sctlr = 0x00000070;
 868 }
 869
 870 static void sa1100_initfn(Object *obj)
 871 {
 872     ARMCPU *cpu = ARM_CPU(obj);
 873
 874     cpu->dtb_compatible = "intel,sa1100";
 875     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 876     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 877     cpu->midr = 0x4401A11B;
 878     cpu->reset_sctlr = 0x00000070;
 879 }
 880
 881 static void sa1110_initfn(Object *obj)
 882 {
 883     ARMCPU *cpu = ARM_CPU(obj);
 884     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 885     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 886     cpu->midr = 0x6901B119;
 887     cpu->reset_sctlr = 0x00000070;
 888 }
 889
 890 static void pxa250_initfn(Object *obj)
 891 {
 892     ARMCPU *cpu = ARM_CPU(obj);
 893
 894     cpu->dtb_compatible = "marvell,xscale";
 895     set_feature(&cpu->env, ARM_FEATURE_V5);
 896     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 897     cpu->midr = 0x69052100;
 898     cpu->ctr = 0xd172172;
 899     cpu->reset_sctlr = 0x00000078;
 900 }
 901
 902 static void pxa255_initfn(Object *obj)
 903 {
 904     ARMCPU *cpu = ARM_CPU(obj);
 905
 906     cpu->dtb_compatible = "marvell,xscale";
 907     set_feature(&cpu->env, ARM_FEATURE_V5);
 908     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 909     cpu->midr = 0x69052d00;
 910     cpu->ctr = 0xd172172;
 911     cpu->reset_sctlr = 0x00000078;
 912 }
 913
 914 static void pxa260_initfn(Object *obj)
 915 {
 916     ARMCPU *cpu = ARM_CPU(obj);
 917
 918     cpu->dtb_compatible = "marvell,xscale";
 919     set_feature(&cpu->env, ARM_FEATURE_V5);
 920     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 921     cpu->midr = 0x69052903;
 922     cpu->ctr = 0xd172172;
 923     cpu->reset_sctlr = 0x00000078;
 924 }
 925
 926 static void pxa261_initfn(Object *obj)
 927 {
 928     ARMCPU *cpu = ARM_CPU(obj);
 929
 930     cpu->dtb_compatible = "marvell,xscale";
 931     set_feature(&cpu->env, ARM_FEATURE_V5);
 932     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 933     cpu->midr = 0x69052d05;
 934     cpu->ctr = 0xd172172;
 935     cpu->reset_sctlr = 0x00000078;
 936 }
 937
 938 static void pxa262_initfn(Object *obj)
 939 {
 940     ARMCPU *cpu = ARM_CPU(obj);
 941
 942     cpu->dtb_compatible = "marvell,xscale";
 943     set_feature(&cpu->env, ARM_FEATURE_V5);
 944     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 945     cpu->midr = 0x69052d06;
 946     cpu->ctr = 0xd172172;
 947     cpu->reset_sctlr = 0x00000078;
 948 }
 949
 950 static void pxa270a0_initfn(Object *obj)
 951 {
 952     ARMCPU *cpu = ARM_CPU(obj);
 953
 954     cpu->dtb_compatible = "marvell,xscale";
 955     set_feature(&cpu->env, ARM_FEATURE_V5);
 956     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 957     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 958     cpu->midr = 0x69054110;
 959     cpu->ctr = 0xd172172;
 960     cpu->reset_sctlr = 0x00000078;
 961 }
 962
 963 static void pxa270a1_initfn(Object *obj)
 964 {
 965     ARMCPU *cpu = ARM_CPU(obj);
 966
 967     cpu->dtb_compatible = "marvell,xscale";
 968     set_feature(&cpu->env, ARM_FEATURE_V5);
 969     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 970     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 971     cpu->midr = 0x69054111;
 972     cpu->ctr = 0xd172172;
 973     cpu->reset_sctlr = 0x00000078;
 974 }
 975
 976 static void pxa270b0_initfn(Object *obj)
 977 {
 978     ARMCPU *cpu = ARM_CPU(obj);
 979
 980     cpu->dtb_compatible = "marvell,xscale";
 981     set_feature(&cpu->env, ARM_FEATURE_V5);
 982     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 983     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 984     cpu->midr = 0x69054112;
 985     cpu->ctr = 0xd172172;
 986     cpu->reset_sctlr = 0x00000078;
 987 }
 988
 989 static void pxa270b1_initfn(Object *obj)
 990 {
 991     ARMCPU *cpu = ARM_CPU(obj);
 992
 993     cpu->dtb_compatible = "marvell,xscale";
 994     set_feature(&cpu->env, ARM_FEATURE_V5);
 995     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 996     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 997     cpu->midr = 0x69054113;
 998     cpu->ctr = 0xd172172;
 999     cpu->reset_sctlr = 0x00000078;
1000 }
1001
1002 static void pxa270c0_initfn(Object *obj)
1003 {
1004     ARMCPU *cpu = ARM_CPU(obj);
1005
1006     cpu->dtb_compatible = "marvell,xscale";
1007     set_feature(&cpu->env, ARM_FEATURE_V5);
1008     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1009     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1010     cpu->midr = 0x69054114;
1011     cpu->ctr = 0xd172172;
1012     cpu->reset_sctlr = 0x00000078;
1013 }
1014
1015 static void pxa270c5_initfn(Object *obj)
1016 {
1017     ARMCPU *cpu = ARM_CPU(obj);
1018
1019     cpu->dtb_compatible = "marvell,xscale";
1020     set_feature(&cpu->env, ARM_FEATURE_V5);
1021     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1022     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1023     cpu->midr = 0x69054117;
1024     cpu->ctr = 0xd172172;
1025     cpu->reset_sctlr = 0x00000078;
1026 }
1027
1028 #ifdef CONFIG_USER_ONLY
1029 static void arm_any_initfn(Object *obj)
1030 {
1031     ARMCPU *cpu = ARM_CPU(obj);
1032     set_feature(&cpu->env, ARM_FEATURE_V8);
1033     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1034     set_feature(&cpu->env, ARM_FEATURE_NEON);
1035     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1036     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1037     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1038     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1039     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1040     set_feature(&cpu->env, ARM_FEATURE_CRC);
1041     cpu->midr = 0xffffffff;
1042 }
1043 #endif
1044
1045 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1046
1047 typedef struct ARMCPUInfo {
1048     const char *name;
1049     void (*initfn)(Object *obj);
1050     void (*class_init)(ObjectClass *oc, void *data);
1051 } ARMCPUInfo;
1052
1053 static const ARMCPUInfo arm_cpus[] = {
1054 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1055     { .name = "arm926",      .initfn = arm926_initfn },
1056     { .name = "arm946",      .initfn = arm946_initfn },
1057     { .name = "arm1026",     .initfn = arm1026_initfn },
1058     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1059      * older core than plain "arm1136". In particular this does not
1060      * have the v6K features.
1061      */
1062     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1063     { .name = "arm1136",     .initfn = arm1136_initfn },
1064     { .name = "arm1176",     .initfn = arm1176_initfn },
1065     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1066     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1067                              .class_init = arm_v7m_class_init },
1068     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1069     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1070     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1071     { .name = "ti925t",      .initfn = ti925t_initfn },
1072     { .name = "sa1100",      .initfn = sa1100_initfn },
1073     { .name = "sa1110",      .initfn = sa1110_initfn },
1074     { .name = "pxa250",      .initfn = pxa250_initfn },
1075     { .name = "pxa255",      .initfn = pxa255_initfn },
1076     { .name = "pxa260",      .initfn = pxa260_initfn },
1077     { .name = "pxa261",      .initfn = pxa261_initfn },
1078     { .name = "pxa262",      .initfn = pxa262_initfn },
1079     /* "pxa270" is an alias for "pxa270-a0" */
1080     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1081     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1082     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1083     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1084     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1085     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1086     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1087 #ifdef CONFIG_USER_ONLY
1088     { .name = "any",         .initfn = arm_any_initfn },
1089 #endif
1090 #endif
1091     { .name = NULL }
1092 };
1093
1094 static Property arm_cpu_properties[] = {
1095     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1096     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1097     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1098     DEFINE_PROP_END_OF_LIST()
1099 };
1100
1101 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1102 {
1103     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1104     CPUClass *cc = CPU_CLASS(acc);
1105     DeviceClass *dc = DEVICE_CLASS(oc);
1106
1107     acc->parent_realize = dc->realize;
1108     dc->realize = arm_cpu_realizefn;
1109     dc->props = arm_cpu_properties;
1110
1111     acc->parent_reset = cc->reset;
1112     cc->reset = arm_cpu_reset;
1113
1114     cc->class_by_name = arm_cpu_class_by_name;
1115     cc->has_work = arm_cpu_has_work;
1116     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1117     cc->dump_state = arm_cpu_dump_state;
1118     cc->set_pc = arm_cpu_set_pc;
1119     cc->gdb_read_register = arm_cpu_gdb_read_register;
1120     cc->gdb_write_register = arm_cpu_gdb_write_register;
1121 #ifdef CONFIG_USER_ONLY
1122     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1123 #else
1124     cc->do_interrupt = arm_cpu_do_interrupt;
1125     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1126     cc->vmsd = &vmstate_arm_cpu;
1127 #endif
1128     cc->gdb_num_core_regs = 26;
1129     cc->gdb_core_xml_file = "arm-core.xml";
1130     cc->gdb_stop_before_watchpoint = true;
1131     cc->debug_excp_handler = arm_debug_excp_handler;
1132 }
1133
1134 static void cpu_register(const ARMCPUInfo *info)
1135 {
1136     TypeInfo type_info = {
1137         .parent = TYPE_ARM_CPU,
1138         .instance_size = sizeof(ARMCPU),
1139         .instance_init = info->initfn,
1140         .class_size = sizeof(ARMCPUClass),
1141         .class_init = info->class_init,
1142     };
1143
1144     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1145     type_register(&type_info);
1146     g_free((void *)type_info.name);
1147 }
1148
1149 static const TypeInfo arm_cpu_type_info = {
1150     .name = TYPE_ARM_CPU,
1151     .parent = TYPE_CPU,
1152     .instance_size = sizeof(ARMCPU),
1153     .instance_init = arm_cpu_initfn,
1154     .instance_post_init = arm_cpu_post_init,
1155     .instance_finalize = arm_cpu_finalizefn,
1156     .abstract = true,
1157     .class_size = sizeof(ARMCPUClass),
1158     .class_init = arm_cpu_class_init,
1159 };
1160
1161 static void arm_cpu_register_types(void)
1162 {
1163     const ARMCPUInfo *info = arm_cpus;
1164
1165     type_register_static(&arm_cpu_type_info);
1166
1167     while (info->name) {
1168         cpu_register(info);
1169         info++;
1170     }
1171 }
1172
1173 type_init(arm_cpu_register_types)