4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include <hw/sysbus.h>
32 #include "cpu-common.h"
34 #include <hw/ide/pci.h>
35 #include <hw/ide/ahci.h>
37 /* #define DEBUG_AHCI */
40 #define DPRINTF(port, fmt, ...) \
41 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \
42 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
44 #define DPRINTF(port, fmt, ...) do {} while(0)
47 static void check_cmd(AHCIState
*s
, int port
);
48 static int handle_cmd(AHCIState
*s
,int port
,int slot
);
49 static void ahci_reset_port(AHCIState
*s
, int port
);
50 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
);
51 static void ahci_init_d2h(AHCIDevice
*ad
);
53 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
57 pr
= &s
->dev
[port
].port_regs
;
63 case PORT_LST_ADDR_HI
:
64 val
= pr
->lst_addr_hi
;
69 case PORT_FIS_ADDR_HI
:
70 val
= pr
->fis_addr_hi
;
82 val
= ((uint16_t)s
->dev
[port
].port
.ifs
[0].error
<< 8) |
83 s
->dev
[port
].port
.ifs
[0].status
;
89 if (s
->dev
[port
].port
.ifs
[0].bs
) {
90 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
91 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
93 val
= SATA_SCR_SSTATUS_DET_NODEV
;
103 pr
->scr_act
&= ~s
->dev
[port
].finished
;
104 s
->dev
[port
].finished
= 0;
114 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
119 static void ahci_irq_raise(AHCIState
*s
, AHCIDevice
*dev
)
121 struct AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
123 DPRINTF(0, "raise irq\n");
125 if (msi_enabled(&d
->card
)) {
126 msi_notify(&d
->card
, 0);
128 qemu_irq_raise(s
->irq
);
132 static void ahci_irq_lower(AHCIState
*s
, AHCIDevice
*dev
)
134 struct AHCIPCIState
*d
= container_of(s
, AHCIPCIState
, ahci
);
136 DPRINTF(0, "lower irq\n");
138 if (!msi_enabled(&d
->card
)) {
139 qemu_irq_lower(s
->irq
);
143 static void ahci_check_irq(AHCIState
*s
)
147 DPRINTF(-1, "check irq %#x\n", s
->control_regs
.irqstatus
);
149 s
->control_regs
.irqstatus
= 0;
150 for (i
= 0; i
< s
->ports
; i
++) {
151 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
152 if (pr
->irq_stat
& pr
->irq_mask
) {
153 s
->control_regs
.irqstatus
|= (1 << i
);
157 if (s
->control_regs
.irqstatus
&&
158 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
159 ahci_irq_raise(s
, NULL
);
161 ahci_irq_lower(s
, NULL
);
165 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
168 DPRINTF(d
->port_no
, "trigger irq %#x -> %x\n",
169 irq_type
, d
->port_regs
.irq_mask
& irq_type
);
171 d
->port_regs
.irq_stat
|= irq_type
;
175 static void map_page(uint8_t **ptr
, uint64_t addr
, uint32_t wanted
)
177 target_phys_addr_t len
= wanted
;
180 cpu_physical_memory_unmap(*ptr
, len
, 1, len
);
183 *ptr
= cpu_physical_memory_map(addr
, &len
, 1);
185 cpu_physical_memory_unmap(*ptr
, len
, 1, len
);
190 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
192 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
194 DPRINTF(port
, "offset: 0x%x val: 0x%x\n", offset
, val
);
198 map_page(&s
->dev
[port
].lst
,
199 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
200 s
->dev
[port
].cur_cmd
= NULL
;
202 case PORT_LST_ADDR_HI
:
203 pr
->lst_addr_hi
= val
;
204 map_page(&s
->dev
[port
].lst
,
205 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
206 s
->dev
[port
].cur_cmd
= NULL
;
210 map_page(&s
->dev
[port
].res_fis
,
211 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
213 case PORT_FIS_ADDR_HI
:
214 pr
->fis_addr_hi
= val
;
215 map_page(&s
->dev
[port
].res_fis
,
216 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
219 pr
->irq_stat
&= ~val
;
223 pr
->irq_mask
= val
& 0xfdc000ff;
227 pr
->cmd
= val
& ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
229 if (pr
->cmd
& PORT_CMD_START
) {
230 pr
->cmd
|= PORT_CMD_LIST_ON
;
233 if (pr
->cmd
& PORT_CMD_FIS_RX
) {
234 pr
->cmd
|= PORT_CMD_FIS_ON
;
237 /* XXX usually the FIS would be pending on the bus here and
238 issuing deferred until the OS enables FIS receival.
239 Instead, we only submit it once - which works in most
240 cases, but is a hack. */
241 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
242 !s
->dev
[port
].init_d2h_sent
) {
243 ahci_init_d2h(&s
->dev
[port
]);
244 s
->dev
[port
].init_d2h_sent
= 1;
250 s
->dev
[port
].port
.ifs
[0].error
= (val
>> 8) & 0xff;
251 s
->dev
[port
].port
.ifs
[0].status
= val
& 0xff;
260 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
261 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
262 ahci_reset_port(s
, port
);
274 pr
->cmd_issue
|= val
;
282 static uint64_t ahci_mem_read(void *opaque
, target_phys_addr_t addr
,
285 AHCIState
*s
= opaque
;
288 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
291 val
= s
->control_regs
.cap
;
294 val
= s
->control_regs
.ghc
;
297 val
= s
->control_regs
.irqstatus
;
299 case HOST_PORTS_IMPL
:
300 val
= s
->control_regs
.impl
;
303 val
= s
->control_regs
.version
;
307 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr
, val
);
308 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
309 (addr
< (AHCI_PORT_REGS_START_ADDR
+
310 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
311 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
312 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
320 static void ahci_mem_write(void *opaque
, target_phys_addr_t addr
,
321 uint64_t val
, unsigned size
)
323 AHCIState
*s
= opaque
;
325 /* Only aligned reads are allowed on AHCI */
327 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
328 TARGET_FMT_plx
"\n", addr
);
332 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
333 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64
"\n", (unsigned) addr
, val
);
336 case HOST_CAP
: /* R/WO, RO */
337 /* FIXME handle R/WO */
339 case HOST_CTL
: /* R/W */
340 if (val
& HOST_CTL_RESET
) {
341 DPRINTF(-1, "HBA Reset\n");
344 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
348 case HOST_IRQ_STAT
: /* R/WC, RO */
349 s
->control_regs
.irqstatus
&= ~val
;
352 case HOST_PORTS_IMPL
: /* R/WO, RO */
353 /* FIXME handle R/WO */
355 case HOST_VERSION
: /* RO */
356 /* FIXME report write? */
359 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr
);
361 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
362 (addr
< (AHCI_PORT_REGS_START_ADDR
+
363 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
364 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
365 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
370 static const MemoryRegionOps ahci_mem_ops
= {
371 .read
= ahci_mem_read
,
372 .write
= ahci_mem_write
,
373 .endianness
= DEVICE_LITTLE_ENDIAN
,
376 static uint64_t ahci_idp_read(void *opaque
, target_phys_addr_t addr
,
379 AHCIState
*s
= opaque
;
381 if (addr
== s
->idp_offset
) {
384 } else if (addr
== s
->idp_offset
+ 4) {
385 /* data register - do memory read at location selected by index */
386 return ahci_mem_read(opaque
, s
->idp_index
, size
);
392 static void ahci_idp_write(void *opaque
, target_phys_addr_t addr
,
393 uint64_t val
, unsigned size
)
395 AHCIState
*s
= opaque
;
397 if (addr
== s
->idp_offset
) {
398 /* index register - mask off reserved bits */
399 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
400 } else if (addr
== s
->idp_offset
+ 4) {
401 /* data register - do memory write at location selected by index */
402 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
406 static const MemoryRegionOps ahci_idp_ops
= {
407 .read
= ahci_idp_read
,
408 .write
= ahci_idp_write
,
409 .endianness
= DEVICE_LITTLE_ENDIAN
,
413 static void ahci_reg_init(AHCIState
*s
)
417 s
->control_regs
.cap
= (s
->ports
- 1) |
418 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
419 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
420 HOST_CAP_NCQ
| HOST_CAP_AHCI
;
422 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
424 s
->control_regs
.version
= AHCI_VERSION_1_0
;
426 for (i
= 0; i
< s
->ports
; i
++) {
427 s
->dev
[i
].port_state
= STATE_RUN
;
431 static void check_cmd(AHCIState
*s
, int port
)
433 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
436 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
437 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
438 if ((pr
->cmd_issue
& (1 << slot
)) &&
439 !handle_cmd(s
, port
, slot
)) {
440 pr
->cmd_issue
&= ~(1 << slot
);
446 static void ahci_check_cmd_bh(void *opaque
)
448 AHCIDevice
*ad
= opaque
;
450 qemu_bh_delete(ad
->check_bh
);
453 if ((ad
->busy_slot
!= -1) &&
454 !(ad
->port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
))) {
456 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
460 check_cmd(ad
->hba
, ad
->port_no
);
463 static void ahci_init_d2h(AHCIDevice
*ad
)
465 uint8_t init_fis
[20];
466 IDEState
*ide_state
= &ad
->port
.ifs
[0];
468 memset(init_fis
, 0, sizeof(init_fis
));
473 if (ide_state
->drive_kind
== IDE_CD
) {
474 init_fis
[5] = ide_state
->lcyl
;
475 init_fis
[6] = ide_state
->hcyl
;
478 ahci_write_fis_d2h(ad
, init_fis
);
481 static void ahci_reset_port(AHCIState
*s
, int port
)
483 AHCIDevice
*d
= &s
->dev
[port
];
484 AHCIPortRegs
*pr
= &d
->port_regs
;
485 IDEState
*ide_state
= &d
->port
.ifs
[0];
488 DPRINTF(port
, "reset port\n");
490 ide_bus_reset(&d
->port
);
491 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
497 d
->init_d2h_sent
= 0;
499 ide_state
= &s
->dev
[port
].port
.ifs
[0];
500 if (!ide_state
->bs
) {
504 /* reset ncq queue */
505 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
506 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
507 if (!ncq_tfs
->used
) {
511 if (ncq_tfs
->aiocb
) {
512 bdrv_aio_cancel(ncq_tfs
->aiocb
);
513 ncq_tfs
->aiocb
= NULL
;
516 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */
517 if (!ncq_tfs
->used
) {
521 qemu_sglist_destroy(&ncq_tfs
->sglist
);
525 s
->dev
[port
].port_state
= STATE_RUN
;
526 if (!ide_state
->bs
) {
527 s
->dev
[port
].port_regs
.sig
= 0;
528 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
529 } else if (ide_state
->drive_kind
== IDE_CD
) {
530 s
->dev
[port
].port_regs
.sig
= SATA_SIGNATURE_CDROM
;
531 ide_state
->lcyl
= 0x14;
532 ide_state
->hcyl
= 0xeb;
533 DPRINTF(port
, "set lcyl = %d\n", ide_state
->lcyl
);
534 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
536 s
->dev
[port
].port_regs
.sig
= SATA_SIGNATURE_DISK
;
537 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
540 ide_state
->error
= 1;
544 static void debug_print_fis(uint8_t *fis
, int cmd_len
)
549 fprintf(stderr
, "fis:");
550 for (i
= 0; i
< cmd_len
; i
++) {
551 if ((i
& 0xf) == 0) {
552 fprintf(stderr
, "\n%02x:",i
);
554 fprintf(stderr
, "%02x ",fis
[i
]);
556 fprintf(stderr
, "\n");
560 static void ahci_write_fis_sdb(AHCIState
*s
, int port
, uint32_t finished
)
562 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
566 if (!s
->dev
[port
].res_fis
||
567 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
571 sdb_fis
= &s
->dev
[port
].res_fis
[RES_FIS_SDBFIS
];
572 ide_state
= &s
->dev
[port
].port
.ifs
[0];
575 *(uint32_t*)sdb_fis
= 0;
578 sdb_fis
[0] = ide_state
->error
;
579 sdb_fis
[2] = ide_state
->status
& 0x77;
580 s
->dev
[port
].finished
|= finished
;
581 *(uint32_t*)(sdb_fis
+ 4) = cpu_to_le32(s
->dev
[port
].finished
);
583 ahci_trigger_irq(s
, &s
->dev
[port
], PORT_IRQ_STAT_SDBS
);
586 static void ahci_write_fis_d2h(AHCIDevice
*ad
, uint8_t *cmd_fis
)
588 AHCIPortRegs
*pr
= &ad
->port_regs
;
591 dma_addr_t cmd_len
= 0x80;
594 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
600 uint64_t tbl_addr
= le64_to_cpu(ad
->cur_cmd
->tbl_addr
);
601 cmd_fis
= dma_memory_map(ad
->hba
->dma
, tbl_addr
, &cmd_len
,
602 DMA_DIRECTION_TO_DEVICE
);
606 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
609 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
610 d2h_fis
[2] = ad
->port
.ifs
[0].status
;
611 d2h_fis
[3] = ad
->port
.ifs
[0].error
;
613 d2h_fis
[4] = cmd_fis
[4];
614 d2h_fis
[5] = cmd_fis
[5];
615 d2h_fis
[6] = cmd_fis
[6];
616 d2h_fis
[7] = cmd_fis
[7];
617 d2h_fis
[8] = cmd_fis
[8];
618 d2h_fis
[9] = cmd_fis
[9];
619 d2h_fis
[10] = cmd_fis
[10];
620 d2h_fis
[11] = cmd_fis
[11];
621 d2h_fis
[12] = cmd_fis
[12];
622 d2h_fis
[13] = cmd_fis
[13];
623 for (i
= 14; i
< 20; i
++) {
627 if (d2h_fis
[2] & ERR_STAT
) {
628 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_TFES
);
631 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_D2H_REG_FIS
);
634 dma_memory_unmap(ad
->hba
->dma
, cmd_fis
, cmd_len
,
635 DMA_DIRECTION_TO_DEVICE
, cmd_len
);
639 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
)
641 AHCICmdHdr
*cmd
= ad
->cur_cmd
;
642 uint32_t opts
= le32_to_cpu(cmd
->opts
);
643 uint64_t prdt_addr
= le64_to_cpu(cmd
->tbl_addr
) + 0x80;
644 int sglist_alloc_hint
= opts
>> AHCI_CMD_HDR_PRDT_LEN
;
645 dma_addr_t prdt_len
= (sglist_alloc_hint
* sizeof(AHCI_SG
));
646 dma_addr_t real_prdt_len
= prdt_len
;
651 if (!sglist_alloc_hint
) {
652 DPRINTF(ad
->port_no
, "no sg list given by guest: 0x%08x\n", opts
);
657 if (!(prdt
= dma_memory_map(ad
->hba
->dma
, prdt_addr
, &prdt_len
,
658 DMA_DIRECTION_TO_DEVICE
))){
659 DPRINTF(ad
->port_no
, "map failed\n");
663 if (prdt_len
< real_prdt_len
) {
664 DPRINTF(ad
->port_no
, "mapped less than expected\n");
669 /* Get entries in the PRDT, init a qemu sglist accordingly */
670 if (sglist_alloc_hint
> 0) {
671 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
673 qemu_sglist_init(sglist
, sglist_alloc_hint
, ad
->hba
->dma
);
674 for (i
= 0; i
< sglist_alloc_hint
; i
++) {
675 /* flags_size is zero-based */
676 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
677 le32_to_cpu(tbl
[i
].flags_size
) + 1);
682 dma_memory_unmap(ad
->hba
->dma
, prdt
, prdt_len
,
683 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
687 static void ncq_cb(void *opaque
, int ret
)
689 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
690 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
692 /* Clear bit for this tag in SActive */
693 ncq_tfs
->drive
->port_regs
.scr_act
&= ~(1 << ncq_tfs
->tag
);
697 ide_state
->error
= ABRT_ERR
;
698 ide_state
->status
= READY_STAT
| ERR_STAT
;
699 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
701 ide_state
->status
= READY_STAT
| SEEK_STAT
;
704 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
705 (1 << ncq_tfs
->tag
));
707 DPRINTF(ncq_tfs
->drive
->port_no
, "NCQ transfer tag %d finished\n",
710 bdrv_acct_done(ncq_tfs
->drive
->port
.ifs
[0].bs
, &ncq_tfs
->acct
);
711 qemu_sglist_destroy(&ncq_tfs
->sglist
);
715 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
718 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
719 uint8_t tag
= ncq_fis
->tag
>> 3;
720 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[tag
];
723 /* error - already in use */
724 fprintf(stderr
, "%s: tag %d already used\n", __FUNCTION__
, tag
);
729 ncq_tfs
->drive
= &s
->dev
[port
];
730 ncq_tfs
->slot
= slot
;
731 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
732 ((uint64_t)ncq_fis
->lba4
<< 32) |
733 ((uint64_t)ncq_fis
->lba3
<< 24) |
734 ((uint64_t)ncq_fis
->lba2
<< 16) |
735 ((uint64_t)ncq_fis
->lba1
<< 8) |
736 (uint64_t)ncq_fis
->lba0
;
738 /* Note: We calculate the sector count, but don't currently rely on it.
739 * The total size of the DMA buffer tells us the transfer size instead. */
740 ncq_tfs
->sector_count
= ((uint16_t)ncq_fis
->sector_count_high
<< 8) |
741 ncq_fis
->sector_count_low
;
743 DPRINTF(port
, "NCQ transfer LBA from %"PRId64
" to %"PRId64
", "
744 "drive max %"PRId64
"\n",
745 ncq_tfs
->lba
, ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 2,
746 s
->dev
[port
].port
.ifs
[0].nb_sectors
- 1);
748 ahci_populate_sglist(&s
->dev
[port
], &ncq_tfs
->sglist
);
751 switch(ncq_fis
->command
) {
752 case READ_FPDMA_QUEUED
:
753 DPRINTF(port
, "NCQ reading %d sectors from LBA %"PRId64
", "
755 ncq_tfs
->sector_count
-1, ncq_tfs
->lba
, ncq_tfs
->tag
);
757 DPRINTF(port
, "tag %d aio read %"PRId64
"\n",
758 ncq_tfs
->tag
, ncq_tfs
->lba
);
760 dma_acct_start(ncq_tfs
->drive
->port
.ifs
[0].bs
, &ncq_tfs
->acct
,
761 &ncq_tfs
->sglist
, BDRV_ACCT_READ
);
762 ncq_tfs
->aiocb
= dma_bdrv_read(ncq_tfs
->drive
->port
.ifs
[0].bs
,
763 &ncq_tfs
->sglist
, ncq_tfs
->lba
,
766 case WRITE_FPDMA_QUEUED
:
767 DPRINTF(port
, "NCQ writing %d sectors to LBA %"PRId64
", tag %d\n",
768 ncq_tfs
->sector_count
-1, ncq_tfs
->lba
, ncq_tfs
->tag
);
770 DPRINTF(port
, "tag %d aio write %"PRId64
"\n",
771 ncq_tfs
->tag
, ncq_tfs
->lba
);
773 dma_acct_start(ncq_tfs
->drive
->port
.ifs
[0].bs
, &ncq_tfs
->acct
,
774 &ncq_tfs
->sglist
, BDRV_ACCT_WRITE
);
775 ncq_tfs
->aiocb
= dma_bdrv_write(ncq_tfs
->drive
->port
.ifs
[0].bs
,
776 &ncq_tfs
->sglist
, ncq_tfs
->lba
,
780 DPRINTF(port
, "error: tried to process non-NCQ command as NCQ\n");
781 qemu_sglist_destroy(&ncq_tfs
->sglist
);
786 static int handle_cmd(AHCIState
*s
, int port
, int slot
)
795 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
796 /* Engine currently busy, try again later */
797 DPRINTF(port
, "engine busy\n");
801 cmd
= &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
];
803 if (!s
->dev
[port
].lst
) {
804 DPRINTF(port
, "error: lst not given but cmd handled");
808 /* remember current slot handle for later */
809 s
->dev
[port
].cur_cmd
= cmd
;
811 opts
= le32_to_cpu(cmd
->opts
);
812 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
815 cmd_fis
= dma_memory_map(s
->dma
, tbl_addr
, &cmd_len
,
816 DMA_DIRECTION_FROM_DEVICE
);
819 DPRINTF(port
, "error: guest passed us an invalid cmd fis\n");
823 /* The device we are working for */
824 ide_state
= &s
->dev
[port
].port
.ifs
[0];
826 if (!ide_state
->bs
) {
827 DPRINTF(port
, "error: guest accessed unused port");
831 debug_print_fis(cmd_fis
, 0x90);
832 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4);
834 switch (cmd_fis
[0]) {
835 case SATA_FIS_TYPE_REGISTER_H2D
:
838 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
839 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
845 switch (cmd_fis
[1]) {
846 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
:
851 DPRINTF(port
, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
852 "cmd_fis[2]=%02x\n", cmd_fis
[0], cmd_fis
[1],
858 switch (s
->dev
[port
].port_state
) {
860 if (cmd_fis
[15] & ATA_SRST
) {
861 s
->dev
[port
].port_state
= STATE_RESET
;
865 if (!(cmd_fis
[15] & ATA_SRST
)) {
866 ahci_reset_port(s
, port
);
871 if (cmd_fis
[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
) {
873 /* Check for NCQ command */
874 if ((cmd_fis
[2] == READ_FPDMA_QUEUED
) ||
875 (cmd_fis
[2] == WRITE_FPDMA_QUEUED
)) {
876 process_ncq_command(s
, port
, cmd_fis
, slot
);
880 /* Decompose the FIS */
881 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
882 ide_state
->feature
= cmd_fis
[3];
883 if (!ide_state
->nsector
) {
884 ide_state
->nsector
= 256;
887 if (ide_state
->drive_kind
!= IDE_CD
) {
889 * We set the sector depending on the sector defined in the FIS.
890 * Unfortunately, the spec isn't exactly obvious on this one.
892 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the
893 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for
896 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a
897 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such
900 * Since the spec doesn't explicitly state what each field should
901 * do, I simply assume non-used fields as reserved and OR everything
902 * together, independent of the command.
904 ide_set_sector(ide_state
, ((uint64_t)cmd_fis
[10] << 40)
905 | ((uint64_t)cmd_fis
[9] << 32)
906 /* This is used for LBA48 commands */
907 | ((uint64_t)cmd_fis
[8] << 24)
908 /* This is used for non-LBA48 commands */
909 | ((uint64_t)(cmd_fis
[7] & 0xf) << 24)
910 | ((uint64_t)cmd_fis
[6] << 16)
911 | ((uint64_t)cmd_fis
[5] << 8)
915 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
916 * table to ide_state->io_buffer
918 if (opts
& AHCI_CMD_ATAPI
) {
919 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
920 ide_state
->lcyl
= 0x14;
921 ide_state
->hcyl
= 0xeb;
922 debug_print_fis(ide_state
->io_buffer
, 0x10);
923 ide_state
->feature
= IDE_FEATURE_DMA
;
924 s
->dev
[port
].done_atapi_packet
= 0;
925 /* XXX send PIO setup FIS */
928 ide_state
->error
= 0;
930 /* Reset transferred byte counter */
933 /* We're ready to process the command in FIS byte 2. */
934 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
936 if (s
->dev
[port
].port
.ifs
[0].status
& READY_STAT
) {
937 ahci_write_fis_d2h(&s
->dev
[port
], cmd_fis
);
942 dma_memory_unmap(s
->dma
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
945 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
946 /* async command, complete later */
947 s
->dev
[port
].busy_slot
= slot
;
951 /* done handling the command */
955 /* DMA dev <-> ram */
956 static int ahci_start_transfer(IDEDMA
*dma
)
958 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
959 IDEState
*s
= &ad
->port
.ifs
[0];
960 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
961 /* write == ram -> device */
962 uint32_t opts
= le32_to_cpu(ad
->cur_cmd
->opts
);
963 int is_write
= opts
& AHCI_CMD_WRITE
;
964 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
967 if (is_atapi
&& !ad
->done_atapi_packet
) {
968 /* already prepopulated iobuffer */
969 ad
->done_atapi_packet
= 1;
973 if (!ahci_populate_sglist(ad
, &s
->sg
)) {
977 DPRINTF(ad
->port_no
, "%sing %d bytes on %s w/%s sglist\n",
978 is_write
? "writ" : "read", size
, is_atapi
? "atapi" : "ata",
979 has_sglist
? "" : "o");
981 if (has_sglist
&& size
) {
983 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
985 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
989 /* update number of transferred bytes */
990 ad
->cur_cmd
->status
= cpu_to_le32(le32_to_cpu(ad
->cur_cmd
->status
) + size
);
993 /* declare that we processed everything */
994 s
->data_ptr
= s
->data_end
;
997 qemu_sglist_destroy(&s
->sg
);
1000 s
->end_transfer_func(s
);
1002 if (!(s
->status
& DRQ_STAT
)) {
1004 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_DSS
);
1010 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1011 BlockDriverCompletionFunc
*dma_cb
)
1013 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1015 DPRINTF(ad
->port_no
, "\n");
1016 ad
->dma_cb
= dma_cb
;
1017 ad
->dma_status
|= BM_STATUS_DMAING
;
1021 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int is_write
)
1023 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1024 IDEState
*s
= &ad
->port
.ifs
[0];
1026 ahci_populate_sglist(ad
, &s
->sg
);
1027 s
->io_buffer_size
= s
->sg
.size
;
1029 DPRINTF(ad
->port_no
, "len=%#x\n", s
->io_buffer_size
);
1030 return s
->io_buffer_size
!= 0;
1033 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1035 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1036 IDEState
*s
= &ad
->port
.ifs
[0];
1037 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1038 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1040 if (ahci_populate_sglist(ad
, &s
->sg
)) {
1045 dma_buf_read(p
, l
, &s
->sg
);
1047 dma_buf_write(p
, l
, &s
->sg
);
1050 /* update number of transferred bytes */
1051 ad
->cur_cmd
->status
= cpu_to_le32(le32_to_cpu(ad
->cur_cmd
->status
) + l
);
1052 s
->io_buffer_index
+= l
;
1054 DPRINTF(ad
->port_no
, "len=%#x\n", l
);
1059 static int ahci_dma_set_unit(IDEDMA
*dma
, int unit
)
1061 /* only a single unit per link */
1065 static int ahci_dma_add_status(IDEDMA
*dma
, int status
)
1067 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1068 ad
->dma_status
|= status
;
1069 DPRINTF(ad
->port_no
, "set status: %x\n", status
);
1071 if (status
& BM_STATUS_INT
) {
1072 ahci_trigger_irq(ad
->hba
, ad
, PORT_IRQ_STAT_DSS
);
1078 static int ahci_dma_set_inactive(IDEDMA
*dma
)
1080 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1082 DPRINTF(ad
->port_no
, "dma done\n");
1084 /* update d2h status */
1085 ahci_write_fis_d2h(ad
, NULL
);
1089 if (!ad
->check_bh
) {
1090 /* maybe we still have something to process, check later */
1091 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1092 qemu_bh_schedule(ad
->check_bh
);
1098 static void ahci_irq_set(void *opaque
, int n
, int level
)
1102 static void ahci_dma_restart_cb(void *opaque
, int running
, RunState state
)
1106 static int ahci_dma_reset(IDEDMA
*dma
)
1111 static const IDEDMAOps ahci_dma_ops
= {
1112 .start_dma
= ahci_start_dma
,
1113 .start_transfer
= ahci_start_transfer
,
1114 .prepare_buf
= ahci_dma_prepare_buf
,
1115 .rw_buf
= ahci_dma_rw_buf
,
1116 .set_unit
= ahci_dma_set_unit
,
1117 .add_status
= ahci_dma_add_status
,
1118 .set_inactive
= ahci_dma_set_inactive
,
1119 .restart_cb
= ahci_dma_restart_cb
,
1120 .reset
= ahci_dma_reset
,
1123 void ahci_init(AHCIState
*s
, DeviceState
*qdev
, DMAContext
*dma
, int ports
)
1130 s
->dev
= g_malloc0(sizeof(AHCIDevice
) * ports
);
1132 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1133 memory_region_init_io(&s
->mem
, &ahci_mem_ops
, s
, "ahci", AHCI_MEM_BAR_SIZE
);
1134 memory_region_init_io(&s
->idp
, &ahci_idp_ops
, s
, "ahci-idp", 32);
1136 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1138 for (i
= 0; i
< s
->ports
; i
++) {
1139 AHCIDevice
*ad
= &s
->dev
[i
];
1141 ide_bus_new(&ad
->port
, qdev
, i
);
1142 ide_init2(&ad
->port
, irqs
[i
]);
1146 ad
->port
.dma
= &ad
->dma
;
1147 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1148 ad
->port_regs
.cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1152 void ahci_uninit(AHCIState
*s
)
1154 memory_region_destroy(&s
->mem
);
1155 memory_region_destroy(&s
->idp
);
1159 void ahci_reset(AHCIState
*s
)
1164 s
->control_regs
.irqstatus
= 0;
1165 s
->control_regs
.ghc
= 0;
1167 for (i
= 0; i
< s
->ports
; i
++) {
1168 pr
= &s
->dev
[i
].port_regs
;
1172 ahci_reset_port(s
, i
);
1176 typedef struct SysbusAHCIState
{
1177 SysBusDevice busdev
;
1182 static const VMStateDescription vmstate_sysbus_ahci
= {
1183 .name
= "sysbus-ahci",
1187 static void sysbus_ahci_reset(DeviceState
*dev
)
1189 SysbusAHCIState
*s
= DO_UPCAST(SysbusAHCIState
, busdev
.qdev
, dev
);
1191 ahci_reset(&s
->ahci
);
1194 static int sysbus_ahci_init(SysBusDevice
*dev
)
1196 SysbusAHCIState
*s
= FROM_SYSBUS(SysbusAHCIState
, dev
);
1197 ahci_init(&s
->ahci
, &dev
->qdev
, NULL
, s
->num_ports
);
1199 sysbus_init_mmio(dev
, &s
->ahci
.mem
);
1200 sysbus_init_irq(dev
, &s
->ahci
.irq
);
1204 static Property sysbus_ahci_properties
[] = {
1205 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1206 DEFINE_PROP_END_OF_LIST(),
1209 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1211 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
1212 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1214 sbc
->init
= sysbus_ahci_init
;
1215 dc
->vmsd
= &vmstate_sysbus_ahci
;
1216 dc
->props
= sysbus_ahci_properties
;
1217 dc
->reset
= sysbus_ahci_reset
;
1220 static TypeInfo sysbus_ahci_info
= {
1221 .name
= "sysbus-ahci",
1222 .parent
= TYPE_SYS_BUS_DEVICE
,
1223 .instance_size
= sizeof(SysbusAHCIState
),
1224 .class_init
= sysbus_ahci_class_init
,
1227 static void sysbus_ahci_register_types(void)
1229 type_register_static(&sysbus_ahci_info
);
1232 type_init(sysbus_ahci_register_types
)