hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw.h"
  22 #include "pc.h"
  23 #include "apm.h"
  24 #include "pm_smbus.h"
  25 #include "pci.h"
  26 #include "acpi.h"
  27 #include "sysemu.h"
  28 #include "range.h"
  29 #include "ioport.h"
  30
  31 //#define DEBUG
  32
  33 #ifdef DEBUG
  34 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  35 #else
  36 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  37 #endif
  38
  39 #define ACPI_DBG_IO_ADDR  0xb044
  40
  41 #define GPE_BASE 0xafe0
  42 #define PROC_BASE 0xaf00
  43 #define GPE_LEN 4
  44 #define PCI_UP_BASE 0xae00
  45 #define PCI_DOWN_BASE 0xae04
  46 #define PCI_EJ_BASE 0xae08
  47 #define PCI_RMV_BASE 0xae0c
  48
  49 #define PIIX4_CPU_HOTPLUG_STATUS 4
  50 #define PIIX4_PCI_HOTPLUG_STATUS 2
  51
  52 struct gpe_regs {
  53     uint8_t cpus_sts[32];
  54 };
  55
  56 struct pci_status {
  57     uint32_t up; /* deprecated, maintained for migration compatibility */
  58     uint32_t down;
  59 };
  60
  61 typedef struct PIIX4PMState {
  62     PCIDevice dev;
  63     IORange ioport;
  64     ACPIREGS ar;
  65
  66     APMState apm;
  67
  68     PMSMBus smb;
  69     uint32_t smb_io_base;
  70
  71     qemu_irq irq;
  72     qemu_irq smi_irq;
  73     int kvm_enabled;
  74     Notifier machine_ready;
  75
  76     /* for pci hotplug */
  77     struct gpe_regs gpe_cpu;
  78     struct pci_status pci0_status;
  79     uint32_t pci0_hotplug_enable;
  80     uint32_t pci0_slot_device_present;
  81 } PIIX4PMState;
  82
  83 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  84
  85 #define ACPI_ENABLE 0xf1
  86 #define ACPI_DISABLE 0xf0
  87
  88 static void pm_update_sci(PIIX4PMState *s)
  89 {
  90     int sci_level, pmsts;
  91
  92     pmsts = acpi_pm1_evt_get_sts(&s->ar);
  93     sci_level = (((pmsts & s->ar.pm1.evt.en) &
  94                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  95                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  96                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  97                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  98         (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
  99           & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 100
 101     qemu_set_irq(s->irq, sci_level);
 102     /* schedule a timer interruption if needed */
 103     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 104                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 105 }
 106
 107 static void pm_tmr_timer(ACPIREGS *ar)
 108 {
 109     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 110     pm_update_sci(s);
 111 }
 112
 113 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 114                             uint64_t val)
 115 {
 116     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 117
 118     if (width != 2) {
 119         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 120                       (unsigned)addr, width, (unsigned)val);
 121     }
 122
 123     switch(addr) {
 124     case 0x00:
 125         acpi_pm1_evt_write_sts(&s->ar, val);
 126         pm_update_sci(s);
 127         break;
 128     case 0x02:
 129         acpi_pm1_evt_write_en(&s->ar, val);
 130         pm_update_sci(s);
 131         break;
 132     case 0x04:
 133         acpi_pm1_cnt_write(&s->ar, val);
 134         break;
 135     default:
 136         break;
 137     }
 138     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 139                   (unsigned int)val);
 140 }
 141
 142 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 143                             uint64_t *data)
 144 {
 145     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 146     uint32_t val;
 147
 148     switch(addr) {
 149     case 0x00:
 150         val = acpi_pm1_evt_get_sts(&s->ar);
 151         break;
 152     case 0x02:
 153         val = s->ar.pm1.evt.en;
 154         break;
 155     case 0x04:
 156         val = s->ar.pm1.cnt.cnt;
 157         break;
 158     case 0x08:
 159         val = acpi_pm_tmr_get(&s->ar);
 160         break;
 161     default:
 162         val = 0;
 163         break;
 164     }
 165     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 166     *data = val;
 167 }
 168
 169 static const IORangeOps pm_iorange_ops = {
 170     .read = pm_ioport_read,
 171     .write = pm_ioport_write,
 172 };
 173
 174 static void apm_ctrl_changed(uint32_t val, void *arg)
 175 {
 176     PIIX4PMState *s = arg;
 177
 178     /* ACPI specs 3.0, 4.7.2.5 */
 179     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 180
 181     if (s->dev.config[0x5b] & (1 << 1)) {
 182         if (s->smi_irq) {
 183             qemu_irq_raise(s->smi_irq);
 184         }
 185     }
 186 }
 187
 188 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 189 {
 190     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 191 }
 192
 193 static void pm_io_space_update(PIIX4PMState *s)
 194 {
 195     uint32_t pm_io_base;
 196
 197     if (s->dev.config[0x80] & 1) {
 198         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 199         pm_io_base &= 0xffc0;
 200
 201         /* XXX: need to improve memory and ioport allocation */
 202         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 203         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 204         ioport_register(&s->ioport);
 205     }
 206 }
 207
 208 static void pm_write_config(PCIDevice *d,
 209                             uint32_t address, uint32_t val, int len)
 210 {
 211     pci_default_write_config(d, address, val, len);
 212     if (range_covers_byte(address, len, 0x80))
 213         pm_io_space_update((PIIX4PMState *)d);
 214 }
 215
 216 static void vmstate_pci_status_pre_save(void *opaque)
 217 {
 218     struct pci_status *pci0_status = opaque;
 219     PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
 220
 221     /* We no longer track up, so build a safe value for migrating
 222      * to a version that still does... of course these might get lost
 223      * by an old buggy implementation, but we try. */
 224     pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 225 }
 226
 227 static int vmstate_acpi_post_load(void *opaque, int version_id)
 228 {
 229     PIIX4PMState *s = opaque;
 230
 231     pm_io_space_update(s);
 232     return 0;
 233 }
 234
 235 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 236  {                                                                   \
 237      .name       = (stringify(_field)),                              \
 238      .version_id = 0,                                                \
 239      .info       = &vmstate_info_uint16,                             \
 240      .size       = sizeof(uint16_t),                                 \
 241      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 242      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 243  }
 244
 245 static const VMStateDescription vmstate_gpe = {
 246     .name = "gpe",
 247     .version_id = 1,
 248     .minimum_version_id = 1,
 249     .minimum_version_id_old = 1,
 250     .fields      = (VMStateField []) {
 251         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 252         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 253         VMSTATE_END_OF_LIST()
 254     }
 255 };
 256
 257 static const VMStateDescription vmstate_pci_status = {
 258     .name = "pci_status",
 259     .version_id = 1,
 260     .minimum_version_id = 1,
 261     .minimum_version_id_old = 1,
 262     .pre_save = vmstate_pci_status_pre_save,
 263     .fields      = (VMStateField []) {
 264         VMSTATE_UINT32(up, struct pci_status),
 265         VMSTATE_UINT32(down, struct pci_status),
 266         VMSTATE_END_OF_LIST()
 267     }
 268 };
 269
 270 static const VMStateDescription vmstate_acpi = {
 271     .name = "piix4_pm",
 272     .version_id = 2,
 273     .minimum_version_id = 1,
 274     .minimum_version_id_old = 1,
 275     .post_load = vmstate_acpi_post_load,
 276     .fields      = (VMStateField []) {
 277         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 278         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 279         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 280         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 281         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 282         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 283         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 284         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 285         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 286                        struct pci_status),
 287         VMSTATE_END_OF_LIST()
 288     }
 289 };
 290
 291 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
 292 {
 293     DeviceState *qdev, *next;
 294     BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
 295     int slot = ffs(slots) - 1;
 296     bool slot_free = true;
 297
 298     /* Mark request as complete */
 299     s->pci0_status.down &= ~(1U << slot);
 300
 301     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 302         PCIDevice *dev = PCI_DEVICE(qdev);
 303         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 304         if (PCI_SLOT(dev->devfn) == slot) {
 305             if (pc->no_hotplug) {
 306                 slot_free = false;
 307             } else {
 308                 object_unparent(OBJECT(dev));
 309                 qdev_free(qdev);
 310             }
 311         }
 312     }
 313     if (slot_free) {
 314         s->pci0_slot_device_present &= ~(1U << slot);
 315     }
 316 }
 317
 318 static void piix4_update_hotplug(PIIX4PMState *s)
 319 {
 320     PCIDevice *dev = &s->dev;
 321     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 322     DeviceState *qdev, *next;
 323
 324     /* Execute any pending removes during reset */
 325     while (s->pci0_status.down) {
 326         acpi_piix_eject_slot(s, s->pci0_status.down);
 327     }
 328
 329     s->pci0_hotplug_enable = ~0;
 330     s->pci0_slot_device_present = 0;
 331
 332     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 333         PCIDevice *pdev = PCI_DEVICE(qdev);
 334         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 335         int slot = PCI_SLOT(pdev->devfn);
 336
 337         if (pc->no_hotplug) {
 338             s->pci0_hotplug_enable &= ~(1U << slot);
 339         }
 340
 341         s->pci0_slot_device_present |= (1U << slot);
 342     }
 343 }
 344
 345 static void piix4_reset(void *opaque)
 346 {
 347     PIIX4PMState *s = opaque;
 348     uint8_t *pci_conf = s->dev.config;
 349
 350     pci_conf[0x58] = 0;
 351     pci_conf[0x59] = 0;
 352     pci_conf[0x5a] = 0;
 353     pci_conf[0x5b] = 0;
 354
 355     if (s->kvm_enabled) {
 356         /* Mark SMM as already inited (until KVM supports SMM). */
 357         pci_conf[0x5B] = 0x02;
 358     }
 359     piix4_update_hotplug(s);
 360 }
 361
 362 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 363 {
 364     PIIX4PMState *s = opaque;
 365
 366     assert(s != NULL);
 367     acpi_pm1_evt_power_down(&s->ar);
 368 }
 369
 370 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 371 {
 372     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 373     uint8_t *pci_conf;
 374
 375     pci_conf = s->dev.config;
 376     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 377     pci_conf[0x63] = 0x60;
 378     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 379         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 380
 381 }
 382
 383 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 384
 385 static int piix4_pm_initfn(PCIDevice *dev)
 386 {
 387     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 388     uint8_t *pci_conf;
 389
 390     /* for cpu hotadd */
 391     global_piix4_pm_state = s;
 392
 393     pci_conf = s->dev.config;
 394     pci_conf[0x06] = 0x80;
 395     pci_conf[0x07] = 0x02;
 396     pci_conf[0x09] = 0x00;
 397     pci_conf[0x3d] = 0x01; // interrupt pin 1
 398
 399     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 400
 401     /* APM */
 402     apm_init(&s->apm, apm_ctrl_changed, s);
 403
 404     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 405
 406     if (s->kvm_enabled) {
 407         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 408          * support SMM mode. */
 409         pci_conf[0x5B] = 0x02;
 410     }
 411
 412     /* XXX: which specification is used ? The i82731AB has different
 413        mappings */
 414     pci_conf[0x90] = s->smb_io_base | 1;
 415     pci_conf[0x91] = s->smb_io_base >> 8;
 416     pci_conf[0xd2] = 0x09;
 417     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 418     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 419
 420     acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
 421     acpi_gpe_init(&s->ar, GPE_LEN);
 422
 423     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 424
 425     pm_smbus_init(&s->dev.qdev, &s->smb);
 426     s->machine_ready.notify = piix4_pm_machine_ready;
 427     qemu_add_machine_init_done_notifier(&s->machine_ready);
 428     qemu_register_reset(piix4_reset, s);
 429     piix4_acpi_system_hot_add_init(dev->bus, s);
 430
 431     return 0;
 432 }
 433
 434 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 435                        qemu_irq sci_irq, qemu_irq smi_irq,
 436                        int kvm_enabled)
 437 {
 438     PCIDevice *dev;
 439     PIIX4PMState *s;
 440
 441     dev = pci_create(bus, devfn, "PIIX4_PM");
 442     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 443
 444     s = DO_UPCAST(PIIX4PMState, dev, dev);
 445     s->irq = sci_irq;
 446     acpi_pm1_cnt_init(&s->ar);
 447     s->smi_irq = smi_irq;
 448     s->kvm_enabled = kvm_enabled;
 449
 450     qdev_init_nofail(&dev->qdev);
 451
 452     return s->smb.smbus;
 453 }
 454
 455 static Property piix4_pm_properties[] = {
 456     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 457     DEFINE_PROP_END_OF_LIST(),
 458 };
 459
 460 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 461 {
 462     DeviceClass *dc = DEVICE_CLASS(klass);
 463     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 464
 465     k->no_hotplug = 1;
 466     k->init = piix4_pm_initfn;
 467     k->config_write = pm_write_config;
 468     k->vendor_id = PCI_VENDOR_ID_INTEL;
 469     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 470     k->revision = 0x03;
 471     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 472     dc->desc = "PM";
 473     dc->no_user = 1;
 474     dc->vmsd = &vmstate_acpi;
 475     dc->props = piix4_pm_properties;
 476 }
 477
 478 static TypeInfo piix4_pm_info = {
 479     .name          = "PIIX4_PM",
 480     .parent        = TYPE_PCI_DEVICE,
 481     .instance_size = sizeof(PIIX4PMState),
 482     .class_init    = piix4_pm_class_init,
 483 };
 484
 485 static void piix4_pm_register_types(void)
 486 {
 487     type_register_static(&piix4_pm_info);
 488 }
 489
 490 type_init(piix4_pm_register_types)
 491
 492 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 493 {
 494     PIIX4PMState *s = opaque;
 495     uint32_t val = 0;
 496     struct gpe_regs *g = &s->gpe_cpu;
 497
 498     switch (addr) {
 499         case PROC_BASE ... PROC_BASE+31:
 500             val = g->cpus_sts[addr - PROC_BASE];
 501             break;
 502         default:
 503             val = acpi_gpe_ioport_readb(&s->ar, addr);
 504     }
 505
 506     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 507     return val;
 508 }
 509
 510 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 511 {
 512     PIIX4PMState *s = opaque;
 513
 514     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 515     pm_update_sci(s);
 516
 517     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 518 }
 519
 520 static uint32_t pci_up_read(void *opaque, uint32_t addr)
 521 {
 522     PIIX4PMState *s = opaque;
 523     uint32_t val;
 524
 525     /* Manufacture an "up" value to cause a device check on any hotplug
 526      * slot with a device.  Extra device checks are harmless. */
 527     val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 528
 529     PIIX4_DPRINTF("pci_up_read %x\n", val);
 530     return val;
 531 }
 532
 533 static uint32_t pci_down_read(void *opaque, uint32_t addr)
 534 {
 535     PIIX4PMState *s = opaque;
 536     uint32_t val = s->pci0_status.down;
 537
 538     PIIX4_DPRINTF("pci_down_read %x\n", val);
 539     return val;
 540 }
 541
 542 static uint32_t pci_features_read(void *opaque, uint32_t addr)
 543 {
 544     /* No feature defined yet */
 545     PIIX4_DPRINTF("pci_features_read %x\n", 0);
 546     return 0;
 547 }
 548
 549 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 550 {
 551     acpi_piix_eject_slot(opaque, val);
 552
 553     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 554 }
 555
 556 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 557 {
 558     PIIX4PMState *s = opaque;
 559
 560     return s->pci0_hotplug_enable;
 561 }
 562
 563 extern const char *global_cpu_model;
 564
 565 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 566                                 PCIHotplugState state);
 567
 568 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 569 {
 570     int i = 0, cpus = smp_cpus;
 571
 572     while (cpus > 0) {
 573         s->gpe_cpu.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 574         cpus -= 8;
 575     }
 576
 577     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 578     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 579     acpi_gpe_blk(&s->ar, GPE_BASE);
 580
 581     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 582     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 583
 584     register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
 585     register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
 586
 587     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
 588     register_ioport_read(PCI_EJ_BASE, 4, 4,  pci_features_read, s);
 589
 590     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 591
 592     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 593 }
 594
 595 #if defined(TARGET_I386)
 596 static void enable_processor(PIIX4PMState *s, int cpu)
 597 {
 598     struct gpe_regs *g = &s->gpe_cpu;
 599     ACPIGPE *gpe = &s->ar.gpe;
 600
 601     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 602     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 603 }
 604
 605 static void disable_processor(PIIX4PMState *s, int cpu)
 606 {
 607     struct gpe_regs *g = &s->gpe_cpu;
 608     ACPIGPE *gpe = &s->ar.gpe;
 609
 610     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 611     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 612 }
 613
 614 void qemu_system_cpu_hot_add(int cpu, int state)
 615 {
 616     X86CPU *env;
 617     PIIX4PMState *s = global_piix4_pm_state;
 618
 619     if (state && !qemu_get_cpu(cpu)) {
 620         env = pc_new_cpu(global_cpu_model);
 621         if (!env) {
 622             fprintf(stderr, "cpu %d creation failed\n", cpu);
 623             return;
 624         }
 625         env->env.cpuid_apic_id = cpu;
 626     }
 627
 628     if (state)
 629         enable_processor(s, cpu);
 630     else
 631         disable_processor(s, cpu);
 632
 633     pm_update_sci(s);
 634 }
 635 #endif
 636
 637 static void enable_device(PIIX4PMState *s, int slot)
 638 {
 639     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 640     s->pci0_slot_device_present |= (1U << slot);
 641 }
 642
 643 static void disable_device(PIIX4PMState *s, int slot)
 644 {
 645     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 646     s->pci0_status.down |= (1U << slot);
 647 }
 648
 649 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 650                                 PCIHotplugState state)
 651 {
 652     int slot = PCI_SLOT(dev->devfn);
 653     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 654                                 PCI_DEVICE(qdev));
 655
 656     /* Don't send event when device is enabled during qemu machine creation:
 657      * it is present on boot, no hotplug event is necessary. We do send an
 658      * event when the device is disabled later. */
 659     if (state == PCI_COLDPLUG_ENABLED) {
 660         s->pci0_slot_device_present |= (1U << slot);
 661         return 0;
 662     }
 663
 664     if (state == PCI_HOTPLUG_ENABLED) {
 665         enable_device(s, slot);
 666     } else {
 667         disable_device(s, slot);
 668     }
 669
 670     pm_update_sci(s);
 671
 672     return 0;
 673 }