4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39 #define PREFIX_VEX 0x20
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
64 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
65 static TCGv_i32 cpu_cc_op
;
66 static TCGv cpu_regs
[CPU_NB_REGS
];
69 /* local register indexes (only used inside old micro ops) */
70 static TCGv cpu_tmp0
, cpu_tmp4
;
71 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
72 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
73 static TCGv_i64 cpu_tmp1_i64
;
75 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
77 #include "exec/gen-icount.h"
80 static int x86_64_hregs
;
83 typedef struct DisasContext
{
84 /* current insn context */
85 int override
; /* -1 if no override */
89 target_ulong pc
; /* pc = eip + cs_base */
90 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
91 static state change (stop translation) */
92 /* current block context */
93 target_ulong cs_base
; /* base of CS segment */
94 int pe
; /* protected mode */
95 int code32
; /* 32 bit code segment */
97 int lma
; /* long mode active */
98 int code64
; /* 64 bit code segment */
101 int vex_l
; /* vex vector length */
102 int vex_v
; /* vex vvvv register, without 1's compliment. */
103 int ss32
; /* 32 bit stack segment */
104 CCOp cc_op
; /* current CC operation */
106 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
107 int f_st
; /* currently unused */
108 int vm86
; /* vm86 mode */
111 int tf
; /* TF cpu flag */
112 int singlestep_enabled
; /* "hardware" single step enabled */
113 int jmp_opt
; /* use direct block chaining for direct jumps */
114 int mem_index
; /* select memory access functions */
115 uint64_t flags
; /* all execution flags */
116 struct TranslationBlock
*tb
;
117 int popl_esp_hack
; /* for correct popl with esp base handling */
118 int rip_offset
; /* only used in x86_64, but left for simplicity */
120 int cpuid_ext_features
;
121 int cpuid_ext2_features
;
122 int cpuid_ext3_features
;
123 int cpuid_7_0_ebx_features
;
126 static void gen_eob(DisasContext
*s
);
127 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
128 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
129 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
);
131 /* i386 arith/logic operations */
151 OP_SHL1
, /* undocumented */
167 /* I386 int registers */
168 OR_EAX
, /* MUST be even numbered */
177 OR_TMP0
= 16, /* temporary operand register */
179 OR_A0
, /* temporary register used when doing address evaluation */
189 /* Bit set if the global variable is live after setting CC_OP to X. */
190 static const uint8_t cc_op_live
[CC_OP_NB
] = {
191 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
192 [CC_OP_EFLAGS
] = USES_CC_SRC
,
193 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
194 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
196 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
197 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
198 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
199 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
206 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
210 static void set_cc_op(DisasContext
*s
, CCOp op
)
214 if (s
->cc_op
== op
) {
218 /* Discard CC computation that will no longer be used. */
219 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
220 if (dead
& USES_CC_DST
) {
221 tcg_gen_discard_tl(cpu_cc_dst
);
223 if (dead
& USES_CC_SRC
) {
224 tcg_gen_discard_tl(cpu_cc_src
);
226 if (dead
& USES_CC_SRC2
) {
227 tcg_gen_discard_tl(cpu_cc_src2
);
229 if (dead
& USES_CC_SRCT
) {
230 tcg_gen_discard_tl(cpu_cc_srcT
);
233 if (op
== CC_OP_DYNAMIC
) {
234 /* The DYNAMIC setting is translator only, and should never be
235 stored. Thus we always consider it clean. */
236 s
->cc_op_dirty
= false;
238 /* Discard any computed CC_OP value (see shifts). */
239 if (s
->cc_op
== CC_OP_DYNAMIC
) {
240 tcg_gen_discard_i32(cpu_cc_op
);
242 s
->cc_op_dirty
= true;
247 static void gen_update_cc_op(DisasContext
*s
)
249 if (s
->cc_op_dirty
) {
250 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
251 s
->cc_op_dirty
= false;
257 #define NB_OP_SIZES 4
259 #else /* !TARGET_X86_64 */
261 #define NB_OP_SIZES 3
263 #endif /* !TARGET_X86_64 */
265 #if defined(HOST_WORDS_BIGENDIAN)
266 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
267 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
268 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
269 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
270 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
272 #define REG_B_OFFSET 0
273 #define REG_H_OFFSET 1
274 #define REG_W_OFFSET 0
275 #define REG_L_OFFSET 0
276 #define REG_LH_OFFSET 4
279 /* In instruction encodings for byte register accesses the
280 * register number usually indicates "low 8 bits of register N";
281 * however there are some special cases where N 4..7 indicates
282 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
283 * true for this special case, false otherwise.
285 static inline bool byte_reg_is_xH(int reg
)
291 if (reg
>= 8 || x86_64_hregs
) {
298 /* Select the size of a push/pop operation. */
299 static inline TCGMemOp
mo_pushpop(DisasContext
*s
, TCGMemOp ot
)
302 return ot
== MO_16
? MO_16
: MO_64
;
308 /* Select only size 64 else 32. Used for SSE operand sizes. */
309 static inline TCGMemOp
mo_64_32(TCGMemOp ot
)
312 return ot
== MO_64
? MO_64
: MO_32
;
318 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
319 byte vs word opcodes. */
320 static inline TCGMemOp
mo_b_d(int b
, TCGMemOp ot
)
322 return b
& 1 ? ot
: MO_8
;
325 /* Select size 8 if lsb of B is clear, else OT capped at 32.
326 Used for decoding operand size of port opcodes. */
327 static inline TCGMemOp
mo_b_d32(int b
, TCGMemOp ot
)
329 return b
& 1 ? (ot
== MO_16
? MO_16
: MO_32
) : MO_8
;
332 static void gen_op_mov_reg_v(TCGMemOp ot
, int reg
, TCGv t0
)
336 if (!byte_reg_is_xH(reg
)) {
337 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
339 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
343 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
346 /* For x86_64, this sets the higher half of register to zero.
347 For i386, this is equivalent to a mov. */
348 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
352 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
360 static inline void gen_op_mov_v_reg(TCGMemOp ot
, TCGv t0
, int reg
)
362 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
363 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
364 tcg_gen_ext8u_tl(t0
, t0
);
366 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
370 static inline void gen_op_movl_A0_reg(int reg
)
372 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
375 static inline void gen_op_addl_A0_im(int32_t val
)
377 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
379 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
384 static inline void gen_op_addq_A0_im(int64_t val
)
386 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
390 static void gen_add_A0_im(DisasContext
*s
, int val
)
394 gen_op_addq_A0_im(val
);
397 gen_op_addl_A0_im(val
);
400 static inline void gen_op_jmp_v(TCGv dest
)
402 tcg_gen_st_tl(dest
, cpu_env
, offsetof(CPUX86State
, eip
));
405 static inline void gen_op_add_reg_im(TCGMemOp size
, int reg
, int32_t val
)
407 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
408 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
411 static inline void gen_op_add_reg_T0(TCGMemOp size
, int reg
)
413 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
414 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
417 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
419 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
421 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
422 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
423 /* For x86_64, this sets the higher half of register to zero.
424 For i386, this is equivalent to a nop. */
425 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
428 static inline void gen_op_movl_A0_seg(int reg
)
430 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
433 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
435 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
438 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
439 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
441 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
442 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
445 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
450 static inline void gen_op_movq_A0_seg(int reg
)
452 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
455 static inline void gen_op_addq_A0_seg(int reg
)
457 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
458 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
461 static inline void gen_op_movq_A0_reg(int reg
)
463 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
466 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
468 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
470 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
471 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
475 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
477 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
480 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
482 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
485 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
488 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
490 gen_op_mov_reg_v(idx
, d
, cpu_T
[0]);
494 static inline void gen_jmp_im(target_ulong pc
)
496 tcg_gen_movi_tl(cpu_tmp0
, pc
);
497 gen_op_jmp_v(cpu_tmp0
);
500 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
504 override
= s
->override
;
509 gen_op_movq_A0_seg(override
);
510 gen_op_addq_A0_reg_sN(0, R_ESI
);
512 gen_op_movq_A0_reg(R_ESI
);
518 if (s
->addseg
&& override
< 0)
521 gen_op_movl_A0_seg(override
);
522 gen_op_addl_A0_reg_sN(0, R_ESI
);
524 gen_op_movl_A0_reg(R_ESI
);
528 /* 16 address, always override */
531 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESI
]);
532 gen_op_addl_A0_seg(s
, override
);
539 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
544 gen_op_movq_A0_reg(R_EDI
);
549 gen_op_movl_A0_seg(R_ES
);
550 gen_op_addl_A0_reg_sN(0, R_EDI
);
552 gen_op_movl_A0_reg(R_EDI
);
556 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_EDI
]);
557 gen_op_addl_A0_seg(s
, R_ES
);
564 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot
)
566 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
567 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
570 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, TCGMemOp size
, bool sign
)
575 tcg_gen_ext8s_tl(dst
, src
);
577 tcg_gen_ext8u_tl(dst
, src
);
582 tcg_gen_ext16s_tl(dst
, src
);
584 tcg_gen_ext16u_tl(dst
, src
);
590 tcg_gen_ext32s_tl(dst
, src
);
592 tcg_gen_ext32u_tl(dst
, src
);
601 static void gen_extu(TCGMemOp ot
, TCGv reg
)
603 gen_ext_tl(reg
, reg
, ot
, false);
606 static void gen_exts(TCGMemOp ot
, TCGv reg
)
608 gen_ext_tl(reg
, reg
, ot
, true);
611 static inline void gen_op_jnz_ecx(TCGMemOp size
, int label1
)
613 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
614 gen_extu(size
, cpu_tmp0
);
615 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
618 static inline void gen_op_jz_ecx(TCGMemOp size
, int label1
)
620 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
621 gen_extu(size
, cpu_tmp0
);
622 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
625 static void gen_helper_in_func(TCGMemOp ot
, TCGv v
, TCGv_i32 n
)
629 gen_helper_inb(v
, n
);
632 gen_helper_inw(v
, n
);
635 gen_helper_inl(v
, n
);
642 static void gen_helper_out_func(TCGMemOp ot
, TCGv_i32 v
, TCGv_i32 n
)
646 gen_helper_outb(v
, n
);
649 gen_helper_outw(v
, n
);
652 gen_helper_outl(v
, n
);
659 static void gen_check_io(DisasContext
*s
, TCGMemOp ot
, target_ulong cur_eip
,
663 target_ulong next_eip
;
666 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
670 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
673 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
676 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
679 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
685 if(s
->flags
& HF_SVMI_MASK
) {
690 svm_flags
|= (1 << (4 + ot
));
691 next_eip
= s
->pc
- s
->cs_base
;
692 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
693 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
694 tcg_const_i32(svm_flags
),
695 tcg_const_i32(next_eip
- cur_eip
));
699 static inline void gen_movs(DisasContext
*s
, TCGMemOp ot
)
701 gen_string_movl_A0_ESI(s
);
702 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
703 gen_string_movl_A0_EDI(s
);
704 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
705 gen_op_movl_T0_Dshift(ot
);
706 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
707 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
710 static void gen_op_update1_cc(void)
712 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
715 static void gen_op_update2_cc(void)
717 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
718 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
721 static void gen_op_update3_cc(TCGv reg
)
723 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
724 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
725 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
728 static inline void gen_op_testl_T0_T1_cc(void)
730 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
733 static void gen_op_update_neg_cc(void)
735 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
736 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
737 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
740 /* compute all eflags to cc_src */
741 static void gen_compute_eflags(DisasContext
*s
)
743 TCGv zero
, dst
, src1
, src2
;
746 if (s
->cc_op
== CC_OP_EFLAGS
) {
749 if (s
->cc_op
== CC_OP_CLR
) {
750 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
| CC_P
);
751 set_cc_op(s
, CC_OP_EFLAGS
);
760 /* Take care to not read values that are not live. */
761 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
762 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
764 zero
= tcg_const_tl(0);
765 if (dead
& USES_CC_DST
) {
768 if (dead
& USES_CC_SRC
) {
771 if (dead
& USES_CC_SRC2
) {
777 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
778 set_cc_op(s
, CC_OP_EFLAGS
);
785 typedef struct CCPrepare
{
795 /* compute eflags.C to reg */
796 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
802 case CC_OP_SUBB
... CC_OP_SUBQ
:
803 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
804 size
= s
->cc_op
- CC_OP_SUBB
;
805 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
806 /* If no temporary was used, be careful not to alias t1 and t0. */
807 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
808 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
812 case CC_OP_ADDB
... CC_OP_ADDQ
:
813 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
814 size
= s
->cc_op
- CC_OP_ADDB
;
815 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
816 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
818 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
819 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
821 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
823 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
825 case CC_OP_INCB
... CC_OP_INCQ
:
826 case CC_OP_DECB
... CC_OP_DECQ
:
827 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
828 .mask
= -1, .no_setcond
= true };
830 case CC_OP_SHLB
... CC_OP_SHLQ
:
831 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
832 size
= s
->cc_op
- CC_OP_SHLB
;
833 shift
= (8 << size
) - 1;
834 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
835 .mask
= (target_ulong
)1 << shift
};
837 case CC_OP_MULB
... CC_OP_MULQ
:
838 return (CCPrepare
) { .cond
= TCG_COND_NE
,
839 .reg
= cpu_cc_src
, .mask
= -1 };
841 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
842 size
= s
->cc_op
- CC_OP_BMILGB
;
843 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
844 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
848 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
849 .mask
= -1, .no_setcond
= true };
852 case CC_OP_SARB
... CC_OP_SARQ
:
854 return (CCPrepare
) { .cond
= TCG_COND_NE
,
855 .reg
= cpu_cc_src
, .mask
= CC_C
};
858 /* The need to compute only C from CC_OP_DYNAMIC is important
859 in efficiently implementing e.g. INC at the start of a TB. */
861 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
862 cpu_cc_src2
, cpu_cc_op
);
863 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
864 .mask
= -1, .no_setcond
= true };
868 /* compute eflags.P to reg */
869 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
871 gen_compute_eflags(s
);
872 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
876 /* compute eflags.S to reg */
877 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
881 gen_compute_eflags(s
);
887 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
890 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
893 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
894 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
895 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
900 /* compute eflags.O to reg */
901 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
906 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
907 .mask
= -1, .no_setcond
= true };
909 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
911 gen_compute_eflags(s
);
912 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
917 /* compute eflags.Z to reg */
918 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
922 gen_compute_eflags(s
);
928 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
931 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
934 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
935 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
936 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
941 /* perform a conditional store into register 'reg' according to jump opcode
942 value 'b'. In the fast case, T0 is guaranted not to be used. */
943 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
945 int inv
, jcc_op
, cond
;
951 jcc_op
= (b
>> 1) & 7;
954 case CC_OP_SUBB
... CC_OP_SUBQ
:
955 /* We optimize relational operators for the cmp/jcc case. */
956 size
= s
->cc_op
- CC_OP_SUBB
;
959 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
960 gen_extu(size
, cpu_tmp4
);
961 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
962 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
963 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
972 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
973 gen_exts(size
, cpu_tmp4
);
974 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
975 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
976 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
986 /* This actually generates good code for JC, JZ and JS. */
989 cc
= gen_prepare_eflags_o(s
, reg
);
992 cc
= gen_prepare_eflags_c(s
, reg
);
995 cc
= gen_prepare_eflags_z(s
, reg
);
998 gen_compute_eflags(s
);
999 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1000 .mask
= CC_Z
| CC_C
};
1003 cc
= gen_prepare_eflags_s(s
, reg
);
1006 cc
= gen_prepare_eflags_p(s
, reg
);
1009 gen_compute_eflags(s
);
1010 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1013 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1014 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1015 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1020 gen_compute_eflags(s
);
1021 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1024 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1025 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1026 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1027 .mask
= CC_S
| CC_Z
};
1034 cc
.cond
= tcg_invert_cond(cc
.cond
);
1039 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1041 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1043 if (cc
.no_setcond
) {
1044 if (cc
.cond
== TCG_COND_EQ
) {
1045 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1047 tcg_gen_mov_tl(reg
, cc
.reg
);
1052 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1053 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1054 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1055 tcg_gen_andi_tl(reg
, reg
, 1);
1058 if (cc
.mask
!= -1) {
1059 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1063 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1065 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1069 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1071 gen_setcc1(s
, JCC_B
<< 1, reg
);
1074 /* generate a conditional jump to label 'l1' according to jump opcode
1075 value 'b'. In the fast case, T0 is guaranted not to be used. */
1076 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1078 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1080 if (cc
.mask
!= -1) {
1081 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1085 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1087 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1091 /* Generate a conditional jump to label 'l1' according to jump opcode
1092 value 'b'. In the fast case, T0 is guaranted not to be used.
1093 A translation block must end soon. */
1094 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1096 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1098 gen_update_cc_op(s
);
1099 if (cc
.mask
!= -1) {
1100 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1103 set_cc_op(s
, CC_OP_DYNAMIC
);
1105 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1107 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1111 /* XXX: does not work with gdbstub "ice" single step - not a
1113 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1117 l1
= gen_new_label();
1118 l2
= gen_new_label();
1119 gen_op_jnz_ecx(s
->aflag
, l1
);
1121 gen_jmp_tb(s
, next_eip
, 1);
1126 static inline void gen_stos(DisasContext
*s
, TCGMemOp ot
)
1128 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
1129 gen_string_movl_A0_EDI(s
);
1130 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1131 gen_op_movl_T0_Dshift(ot
);
1132 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1135 static inline void gen_lods(DisasContext
*s
, TCGMemOp ot
)
1137 gen_string_movl_A0_ESI(s
);
1138 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1139 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
1140 gen_op_movl_T0_Dshift(ot
);
1141 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1144 static inline void gen_scas(DisasContext
*s
, TCGMemOp ot
)
1146 gen_string_movl_A0_EDI(s
);
1147 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1148 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1149 gen_op_movl_T0_Dshift(ot
);
1150 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1153 static inline void gen_cmps(DisasContext
*s
, TCGMemOp ot
)
1155 gen_string_movl_A0_EDI(s
);
1156 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1157 gen_string_movl_A0_ESI(s
);
1158 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1159 gen_op_movl_T0_Dshift(ot
);
1160 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1161 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1164 static inline void gen_ins(DisasContext
*s
, TCGMemOp ot
)
1168 gen_string_movl_A0_EDI(s
);
1169 /* Note: we must do this dummy write first to be restartable in
1170 case of page fault. */
1171 tcg_gen_movi_tl(cpu_T
[0], 0);
1172 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1173 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1174 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1175 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1176 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1177 gen_op_movl_T0_Dshift(ot
);
1178 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1183 static inline void gen_outs(DisasContext
*s
, TCGMemOp ot
)
1187 gen_string_movl_A0_ESI(s
);
1188 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1190 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1191 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1192 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1193 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1195 gen_op_movl_T0_Dshift(ot
);
1196 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1201 /* same method as Valgrind : we generate jumps to current or next
1203 #define GEN_REPZ(op) \
1204 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1205 target_ulong cur_eip, target_ulong next_eip) \
1208 gen_update_cc_op(s); \
1209 l2 = gen_jz_ecx_string(s, next_eip); \
1210 gen_ ## op(s, ot); \
1211 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1212 /* a loop would cause two single step exceptions if ECX = 1 \
1213 before rep string_insn */ \
1215 gen_op_jz_ecx(s->aflag, l2); \
1216 gen_jmp(s, cur_eip); \
1219 #define GEN_REPZ2(op) \
1220 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1221 target_ulong cur_eip, \
1222 target_ulong next_eip, \
1226 gen_update_cc_op(s); \
1227 l2 = gen_jz_ecx_string(s, next_eip); \
1228 gen_ ## op(s, ot); \
1229 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1230 gen_update_cc_op(s); \
1231 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1233 gen_op_jz_ecx(s->aflag, l2); \
1234 gen_jmp(s, cur_eip); \
1245 static void gen_helper_fp_arith_ST0_FT0(int op
)
1249 gen_helper_fadd_ST0_FT0(cpu_env
);
1252 gen_helper_fmul_ST0_FT0(cpu_env
);
1255 gen_helper_fcom_ST0_FT0(cpu_env
);
1258 gen_helper_fcom_ST0_FT0(cpu_env
);
1261 gen_helper_fsub_ST0_FT0(cpu_env
);
1264 gen_helper_fsubr_ST0_FT0(cpu_env
);
1267 gen_helper_fdiv_ST0_FT0(cpu_env
);
1270 gen_helper_fdivr_ST0_FT0(cpu_env
);
1275 /* NOTE the exception in "r" op ordering */
1276 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1278 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1281 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1284 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1287 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1290 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1293 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1296 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1301 /* if d == OR_TMP0, it means memory operand (address in A0) */
1302 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
)
1305 gen_op_mov_v_reg(ot
, cpu_T
[0], d
);
1307 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1311 gen_compute_eflags_c(s1
, cpu_tmp4
);
1312 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1313 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1314 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1315 gen_op_update3_cc(cpu_tmp4
);
1316 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1319 gen_compute_eflags_c(s1
, cpu_tmp4
);
1320 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1321 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1322 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1323 gen_op_update3_cc(cpu_tmp4
);
1324 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1327 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1328 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1329 gen_op_update2_cc();
1330 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1333 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1334 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1335 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1336 gen_op_update2_cc();
1337 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1341 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1342 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1343 gen_op_update1_cc();
1344 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1347 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1348 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1349 gen_op_update1_cc();
1350 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1353 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1354 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1355 gen_op_update1_cc();
1356 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1359 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1360 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1361 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1362 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1367 /* if d == OR_TMP0, it means memory operand (address in A0) */
1368 static void gen_inc(DisasContext
*s1
, TCGMemOp ot
, int d
, int c
)
1371 gen_op_mov_v_reg(ot
, cpu_T
[0], d
);
1373 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1375 gen_compute_eflags_c(s1
, cpu_cc_src
);
1377 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1378 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1380 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1381 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1383 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1384 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1387 static void gen_shift_flags(DisasContext
*s
, TCGMemOp ot
, TCGv result
,
1388 TCGv shm1
, TCGv count
, bool is_right
)
1390 TCGv_i32 z32
, s32
, oldop
;
1393 /* Store the results into the CC variables. If we know that the
1394 variable must be dead, store unconditionally. Otherwise we'll
1395 need to not disrupt the current contents. */
1396 z_tl
= tcg_const_tl(0);
1397 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1398 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1399 result
, cpu_cc_dst
);
1401 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1403 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1404 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1407 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1409 tcg_temp_free(z_tl
);
1411 /* Get the two potential CC_OP values into temporaries. */
1412 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1413 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1416 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1417 oldop
= cpu_tmp3_i32
;
1420 /* Conditionally store the CC_OP value. */
1421 z32
= tcg_const_i32(0);
1422 s32
= tcg_temp_new_i32();
1423 tcg_gen_trunc_tl_i32(s32
, count
);
1424 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1425 tcg_temp_free_i32(z32
);
1426 tcg_temp_free_i32(s32
);
1428 /* The CC_OP value is no longer predictable. */
1429 set_cc_op(s
, CC_OP_DYNAMIC
);
1432 static void gen_shift_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1433 int is_right
, int is_arith
)
1435 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1438 if (op1
== OR_TMP0
) {
1439 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1441 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1444 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1445 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1449 gen_exts(ot
, cpu_T
[0]);
1450 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1451 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1453 gen_extu(ot
, cpu_T
[0]);
1454 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1455 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1458 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1459 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1463 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1465 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1468 static void gen_shift_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1469 int is_right
, int is_arith
)
1471 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1475 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1477 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1483 gen_exts(ot
, cpu_T
[0]);
1484 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1485 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1487 gen_extu(ot
, cpu_T
[0]);
1488 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1489 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1492 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1493 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1498 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1500 /* update eflags if non zero shift */
1502 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1503 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1504 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1508 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1511 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1513 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1516 static void gen_rot_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
, int is_right
)
1518 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1522 if (op1
== OR_TMP0
) {
1523 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1525 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1528 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1532 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1533 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1534 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1537 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1538 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1541 #ifdef TARGET_X86_64
1543 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1544 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1546 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1548 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1550 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1555 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1557 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1563 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1565 /* We'll need the flags computed into CC_SRC. */
1566 gen_compute_eflags(s
);
1568 /* The value that was "rotated out" is now present at the other end
1569 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1570 since we've computed the flags into CC_SRC, these variables are
1573 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1574 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1575 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1577 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1578 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1580 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1581 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1583 /* Now conditionally store the new CC_OP value. If the shift count
1584 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1585 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1586 exactly as we computed above. */
1587 t0
= tcg_const_i32(0);
1588 t1
= tcg_temp_new_i32();
1589 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1590 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1591 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1592 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1593 cpu_tmp2_i32
, cpu_tmp3_i32
);
1594 tcg_temp_free_i32(t0
);
1595 tcg_temp_free_i32(t1
);
1597 /* The CC_OP value is no longer predictable. */
1598 set_cc_op(s
, CC_OP_DYNAMIC
);
1601 static void gen_rot_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1604 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1608 if (op1
== OR_TMP0
) {
1609 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1611 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1617 #ifdef TARGET_X86_64
1619 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1621 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1623 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1625 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1630 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1632 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1643 shift
= mask
+ 1 - shift
;
1645 gen_extu(ot
, cpu_T
[0]);
1646 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1647 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1648 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1654 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1657 /* Compute the flags into CC_SRC. */
1658 gen_compute_eflags(s
);
1660 /* The value that was "rotated out" is now present at the other end
1661 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1662 since we've computed the flags into CC_SRC, these variables are
1665 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1666 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1667 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1669 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1670 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1672 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1673 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1674 set_cc_op(s
, CC_OP_ADCOX
);
1678 /* XXX: add faster immediate = 1 case */
1679 static void gen_rotc_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1682 gen_compute_eflags(s
);
1683 assert(s
->cc_op
== CC_OP_EFLAGS
);
1687 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1689 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1694 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1697 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1700 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1702 #ifdef TARGET_X86_64
1704 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1713 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1716 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1719 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1721 #ifdef TARGET_X86_64
1723 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1731 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1734 /* XXX: add faster immediate case */
1735 static void gen_shiftd_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1736 bool is_right
, TCGv count_in
)
1738 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1742 if (op1
== OR_TMP0
) {
1743 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1745 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1748 count
= tcg_temp_new();
1749 tcg_gen_andi_tl(count
, count_in
, mask
);
1753 /* Note: we implement the Intel behaviour for shift count > 16.
1754 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1755 portion by constructing it as a 32-bit value. */
1757 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1758 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1759 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1761 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1764 #ifdef TARGET_X86_64
1766 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1767 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1769 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1770 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1771 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1773 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1774 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1775 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1776 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1777 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1782 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1784 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1786 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1787 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1788 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1790 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1792 /* Only needed if count > 16, for Intel behaviour. */
1793 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1794 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1795 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1798 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1799 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1800 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1802 tcg_gen_movi_tl(cpu_tmp4
, 0);
1803 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1804 cpu_tmp4
, cpu_T
[1]);
1805 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1810 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1812 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1813 tcg_temp_free(count
);
1816 static void gen_shift(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int s
)
1819 gen_op_mov_v_reg(ot
, cpu_T
[1], s
);
1822 gen_rot_rm_T1(s1
, ot
, d
, 0);
1825 gen_rot_rm_T1(s1
, ot
, d
, 1);
1829 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1832 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1835 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1838 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1841 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1846 static void gen_shifti(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int c
)
1850 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1853 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1857 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1860 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1863 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1866 /* currently not optimized */
1867 tcg_gen_movi_tl(cpu_T
[1], c
);
1868 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1873 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1880 int mod
, rm
, code
, override
, must_add_seg
;
1883 override
= s
->override
;
1884 must_add_seg
= s
->addseg
;
1887 mod
= (modrm
>> 6) & 3;
1900 code
= cpu_ldub_code(env
, s
->pc
++);
1901 scale
= (code
>> 6) & 3;
1902 index
= ((code
>> 3) & 7) | REX_X(s
);
1904 index
= -1; /* no index */
1912 if ((base
& 7) == 5) {
1914 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1916 if (CODE64(s
) && !havesib
) {
1917 disp
+= s
->pc
+ s
->rip_offset
;
1924 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1928 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1933 /* For correct popl handling with esp. */
1934 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1935 disp
+= s
->popl_esp_hack
;
1938 /* Compute the address, with a minimum number of TCG ops. */
1942 sum
= cpu_regs
[index
];
1944 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1948 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1951 } else if (base
>= 0) {
1952 sum
= cpu_regs
[base
];
1954 if (TCGV_IS_UNUSED(sum
)) {
1955 tcg_gen_movi_tl(cpu_A0
, disp
);
1957 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
1962 if (base
== R_EBP
|| base
== R_ESP
) {
1969 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
1970 offsetof(CPUX86State
, segs
[override
].base
));
1972 if (s
->aflag
== MO_32
) {
1973 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1975 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1979 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1982 if (s
->aflag
== MO_32
) {
1983 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1991 disp
= cpu_lduw_code(env
, s
->pc
);
1993 tcg_gen_movi_tl(cpu_A0
, disp
);
1994 rm
= 0; /* avoid SS override */
2001 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2005 disp
= (int16_t)cpu_lduw_code(env
, s
->pc
);
2013 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_ESI
]);
2016 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_EDI
]);
2019 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_ESI
]);
2022 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_EDI
]);
2025 sum
= cpu_regs
[R_ESI
];
2028 sum
= cpu_regs
[R_EDI
];
2031 sum
= cpu_regs
[R_EBP
];
2035 sum
= cpu_regs
[R_EBX
];
2038 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2039 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2043 if (rm
== 2 || rm
== 3 || rm
== 6) {
2049 gen_op_addl_A0_seg(s
, override
);
2058 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2060 int mod
, rm
, base
, code
;
2062 mod
= (modrm
>> 6) & 3;
2073 code
= cpu_ldub_code(env
, s
->pc
++);
2115 /* used for LEA and MOV AX, mem */
2116 static void gen_add_A0_ds_seg(DisasContext
*s
)
2118 int override
, must_add_seg
;
2119 must_add_seg
= s
->addseg
;
2121 if (s
->override
>= 0) {
2122 override
= s
->override
;
2126 #ifdef TARGET_X86_64
2128 gen_op_addq_A0_seg(override
);
2132 gen_op_addl_A0_seg(s
, override
);
2137 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2139 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2140 TCGMemOp ot
, int reg
, int is_store
)
2144 mod
= (modrm
>> 6) & 3;
2145 rm
= (modrm
& 7) | REX_B(s
);
2149 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
2150 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
2152 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
2154 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2157 gen_lea_modrm(env
, s
, modrm
);
2160 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
2161 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2163 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2165 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2170 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
)
2176 ret
= cpu_ldub_code(env
, s
->pc
);
2180 ret
= cpu_lduw_code(env
, s
->pc
);
2184 #ifdef TARGET_X86_64
2187 ret
= cpu_ldl_code(env
, s
->pc
);
2196 static inline int insn_const_size(TCGMemOp ot
)
2205 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2207 TranslationBlock
*tb
;
2210 pc
= s
->cs_base
+ eip
;
2212 /* NOTE: we handle the case where the TB spans two pages here */
2213 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2214 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2215 /* jump to same page: we can use a direct jump */
2216 tcg_gen_goto_tb(tb_num
);
2218 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2220 /* jump to another page: currently not optimized */
2226 static inline void gen_jcc(DisasContext
*s
, int b
,
2227 target_ulong val
, target_ulong next_eip
)
2232 l1
= gen_new_label();
2235 gen_goto_tb(s
, 0, next_eip
);
2238 gen_goto_tb(s
, 1, val
);
2239 s
->is_jmp
= DISAS_TB_JUMP
;
2241 l1
= gen_new_label();
2242 l2
= gen_new_label();
2245 gen_jmp_im(next_eip
);
2255 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
, int b
,
2260 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2262 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2263 if (cc
.mask
!= -1) {
2264 TCGv t0
= tcg_temp_new();
2265 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2269 cc
.reg2
= tcg_const_tl(cc
.imm
);
2272 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2273 cpu_T
[0], cpu_regs
[reg
]);
2274 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2276 if (cc
.mask
!= -1) {
2277 tcg_temp_free(cc
.reg
);
2280 tcg_temp_free(cc
.reg2
);
2284 static inline void gen_op_movl_T0_seg(int seg_reg
)
2286 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2287 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2290 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2292 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2293 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2294 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2295 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2296 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2297 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2300 /* move T0 to seg_reg and compute if the CPU state may change. Never
2301 call this function with seg_reg == R_CS */
2302 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2304 if (s
->pe
&& !s
->vm86
) {
2305 /* XXX: optimize by finding processor state dynamically */
2306 gen_update_cc_op(s
);
2307 gen_jmp_im(cur_eip
);
2308 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2309 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2310 /* abort translation because the addseg value may change or
2311 because ss32 may change. For R_SS, translation must always
2312 stop as a special handling must be done to disable hardware
2313 interrupts for the next instruction */
2314 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2315 s
->is_jmp
= DISAS_TB_JUMP
;
2317 gen_op_movl_seg_T0_vm(seg_reg
);
2318 if (seg_reg
== R_SS
)
2319 s
->is_jmp
= DISAS_TB_JUMP
;
2323 static inline int svm_is_rep(int prefixes
)
2325 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2329 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2330 uint32_t type
, uint64_t param
)
2332 /* no SVM activated; fast case */
2333 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2335 gen_update_cc_op(s
);
2336 gen_jmp_im(pc_start
- s
->cs_base
);
2337 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2338 tcg_const_i64(param
));
2342 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2344 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2347 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2349 #ifdef TARGET_X86_64
2351 gen_op_add_reg_im(MO_64
, R_ESP
, addend
);
2355 gen_op_add_reg_im(MO_32
, R_ESP
, addend
);
2357 gen_op_add_reg_im(MO_16
, R_ESP
, addend
);
2361 /* Generate a push. It depends on ss32, addseg and dflag. */
2362 static void gen_push_v(DisasContext
*s
, TCGv val
)
2364 TCGMemOp a_ot
, d_ot
= mo_pushpop(s
, s
->dflag
);
2365 int size
= 1 << d_ot
;
2366 TCGv new_esp
= cpu_A0
;
2368 tcg_gen_subi_tl(cpu_A0
, cpu_regs
[R_ESP
], size
);
2372 } else if (s
->ss32
) {
2376 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2377 gen_op_addl_A0_seg(s
, R_SS
);
2379 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2384 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2385 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2386 gen_op_addl_A0_seg(s
, R_SS
);
2389 gen_op_st_v(s
, d_ot
, val
, cpu_A0
);
2390 gen_op_mov_reg_v(a_ot
, R_ESP
, new_esp
);
2393 /* two step pop is necessary for precise exceptions */
2394 static TCGMemOp
gen_pop_T0(DisasContext
*s
)
2396 TCGMemOp d_ot
= mo_pushpop(s
, s
->dflag
);
2400 addr
= cpu_regs
[R_ESP
];
2401 } else if (!s
->ss32
) {
2402 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2403 gen_op_addl_A0_seg(s
, R_SS
);
2404 } else if (s
->addseg
) {
2405 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2406 gen_op_addl_A0_seg(s
, R_SS
);
2408 tcg_gen_ext32u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2411 gen_op_ld_v(s
, d_ot
, cpu_T
[0], addr
);
2415 static void gen_pop_update(DisasContext
*s
, TCGMemOp ot
)
2417 gen_stack_update(s
, 1 << ot
);
2420 static void gen_stack_A0(DisasContext
*s
)
2422 gen_op_movl_A0_reg(R_ESP
);
2424 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2425 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2427 gen_op_addl_A0_seg(s
, R_SS
);
2430 /* NOTE: wrap around in 16 bit not fully handled */
2431 static void gen_pusha(DisasContext
*s
)
2434 gen_op_movl_A0_reg(R_ESP
);
2435 gen_op_addl_A0_im(-8 << s
->dflag
);
2437 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2438 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2440 gen_op_addl_A0_seg(s
, R_SS
);
2441 for(i
= 0;i
< 8; i
++) {
2442 gen_op_mov_v_reg(MO_32
, cpu_T
[0], 7 - i
);
2443 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2444 gen_op_addl_A0_im(1 << s
->dflag
);
2446 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2449 /* NOTE: wrap around in 16 bit not fully handled */
2450 static void gen_popa(DisasContext
*s
)
2453 gen_op_movl_A0_reg(R_ESP
);
2455 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2456 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2457 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 8 << s
->dflag
);
2459 gen_op_addl_A0_seg(s
, R_SS
);
2460 for(i
= 0;i
< 8; i
++) {
2461 /* ESP is not reloaded */
2463 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2464 gen_op_mov_reg_v(s
->dflag
, 7 - i
, cpu_T
[0]);
2466 gen_op_addl_A0_im(1 << s
->dflag
);
2468 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2471 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2473 TCGMemOp ot
= mo_pushpop(s
, s
->dflag
);
2474 int opsize
= 1 << ot
;
2477 #ifdef TARGET_X86_64
2479 gen_op_movl_A0_reg(R_ESP
);
2480 gen_op_addq_A0_im(-opsize
);
2481 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2484 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
2485 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2487 /* XXX: must save state */
2488 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2489 tcg_const_i32((ot
== MO_64
)),
2492 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2493 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2494 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[1]);
2498 gen_op_movl_A0_reg(R_ESP
);
2499 gen_op_addl_A0_im(-opsize
);
2501 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2502 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2504 gen_op_addl_A0_seg(s
, R_SS
);
2506 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
2507 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2509 /* XXX: must save state */
2510 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2511 tcg_const_i32(s
->dflag
- 1),
2514 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2515 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2516 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2520 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2522 gen_update_cc_op(s
);
2523 gen_jmp_im(cur_eip
);
2524 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2525 s
->is_jmp
= DISAS_TB_JUMP
;
2528 /* an interrupt is different from an exception because of the
2530 static void gen_interrupt(DisasContext
*s
, int intno
,
2531 target_ulong cur_eip
, target_ulong next_eip
)
2533 gen_update_cc_op(s
);
2534 gen_jmp_im(cur_eip
);
2535 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2536 tcg_const_i32(next_eip
- cur_eip
));
2537 s
->is_jmp
= DISAS_TB_JUMP
;
2540 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2542 gen_update_cc_op(s
);
2543 gen_jmp_im(cur_eip
);
2544 gen_helper_debug(cpu_env
);
2545 s
->is_jmp
= DISAS_TB_JUMP
;
2548 /* generate a generic end of block. Trace exception is also generated
2550 static void gen_eob(DisasContext
*s
)
2552 gen_update_cc_op(s
);
2553 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2554 gen_helper_reset_inhibit_irq(cpu_env
);
2556 if (s
->tb
->flags
& HF_RF_MASK
) {
2557 gen_helper_reset_rf(cpu_env
);
2559 if (s
->singlestep_enabled
) {
2560 gen_helper_debug(cpu_env
);
2562 gen_helper_single_step(cpu_env
);
2566 s
->is_jmp
= DISAS_TB_JUMP
;
2569 /* generate a jump to eip. No segment change must happen before as a
2570 direct call to the next block may occur */
2571 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2573 gen_update_cc_op(s
);
2574 set_cc_op(s
, CC_OP_DYNAMIC
);
2576 gen_goto_tb(s
, tb_num
, eip
);
2577 s
->is_jmp
= DISAS_TB_JUMP
;
2584 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2586 gen_jmp_tb(s
, eip
, 0);
2589 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2591 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2592 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2595 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2597 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2598 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2601 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2603 int mem_index
= s
->mem_index
;
2604 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2605 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2606 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2607 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2608 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2611 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2613 int mem_index
= s
->mem_index
;
2614 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2615 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2616 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2617 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2618 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2621 static inline void gen_op_movo(int d_offset
, int s_offset
)
2623 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2624 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2625 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2626 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2629 static inline void gen_op_movq(int d_offset
, int s_offset
)
2631 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2632 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2635 static inline void gen_op_movl(int d_offset
, int s_offset
)
2637 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2638 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2641 static inline void gen_op_movq_env_0(int d_offset
)
2643 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2644 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2647 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2648 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2649 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2650 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2651 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2652 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2654 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2655 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2658 #define SSE_SPECIAL ((void *)1)
2659 #define SSE_DUMMY ((void *)2)
2661 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2662 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2663 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2665 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2666 /* 3DNow! extensions */
2667 [0x0e] = { SSE_DUMMY
}, /* femms */
2668 [0x0f] = { SSE_DUMMY
}, /* pf... */
2669 /* pure SSE operations */
2670 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2671 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2672 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2673 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2674 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2675 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2676 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2677 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2679 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2680 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2681 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2682 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2683 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2684 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2685 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2686 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2687 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2688 [0x51] = SSE_FOP(sqrt
),
2689 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2690 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2691 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2692 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2693 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2694 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2695 [0x58] = SSE_FOP(add
),
2696 [0x59] = SSE_FOP(mul
),
2697 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2698 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2699 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2700 [0x5c] = SSE_FOP(sub
),
2701 [0x5d] = SSE_FOP(min
),
2702 [0x5e] = SSE_FOP(div
),
2703 [0x5f] = SSE_FOP(max
),
2705 [0xc2] = SSE_FOP(cmpeq
),
2706 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2707 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2709 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2710 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2711 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2713 /* MMX ops and their SSE extensions */
2714 [0x60] = MMX_OP2(punpcklbw
),
2715 [0x61] = MMX_OP2(punpcklwd
),
2716 [0x62] = MMX_OP2(punpckldq
),
2717 [0x63] = MMX_OP2(packsswb
),
2718 [0x64] = MMX_OP2(pcmpgtb
),
2719 [0x65] = MMX_OP2(pcmpgtw
),
2720 [0x66] = MMX_OP2(pcmpgtl
),
2721 [0x67] = MMX_OP2(packuswb
),
2722 [0x68] = MMX_OP2(punpckhbw
),
2723 [0x69] = MMX_OP2(punpckhwd
),
2724 [0x6a] = MMX_OP2(punpckhdq
),
2725 [0x6b] = MMX_OP2(packssdw
),
2726 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2727 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2728 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2729 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2730 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2731 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2732 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2733 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2734 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2735 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2736 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2737 [0x74] = MMX_OP2(pcmpeqb
),
2738 [0x75] = MMX_OP2(pcmpeqw
),
2739 [0x76] = MMX_OP2(pcmpeql
),
2740 [0x77] = { SSE_DUMMY
}, /* emms */
2741 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2742 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2743 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2744 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2745 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2746 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2747 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2748 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2749 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2750 [0xd1] = MMX_OP2(psrlw
),
2751 [0xd2] = MMX_OP2(psrld
),
2752 [0xd3] = MMX_OP2(psrlq
),
2753 [0xd4] = MMX_OP2(paddq
),
2754 [0xd5] = MMX_OP2(pmullw
),
2755 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2756 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2757 [0xd8] = MMX_OP2(psubusb
),
2758 [0xd9] = MMX_OP2(psubusw
),
2759 [0xda] = MMX_OP2(pminub
),
2760 [0xdb] = MMX_OP2(pand
),
2761 [0xdc] = MMX_OP2(paddusb
),
2762 [0xdd] = MMX_OP2(paddusw
),
2763 [0xde] = MMX_OP2(pmaxub
),
2764 [0xdf] = MMX_OP2(pandn
),
2765 [0xe0] = MMX_OP2(pavgb
),
2766 [0xe1] = MMX_OP2(psraw
),
2767 [0xe2] = MMX_OP2(psrad
),
2768 [0xe3] = MMX_OP2(pavgw
),
2769 [0xe4] = MMX_OP2(pmulhuw
),
2770 [0xe5] = MMX_OP2(pmulhw
),
2771 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2772 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2773 [0xe8] = MMX_OP2(psubsb
),
2774 [0xe9] = MMX_OP2(psubsw
),
2775 [0xea] = MMX_OP2(pminsw
),
2776 [0xeb] = MMX_OP2(por
),
2777 [0xec] = MMX_OP2(paddsb
),
2778 [0xed] = MMX_OP2(paddsw
),
2779 [0xee] = MMX_OP2(pmaxsw
),
2780 [0xef] = MMX_OP2(pxor
),
2781 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2782 [0xf1] = MMX_OP2(psllw
),
2783 [0xf2] = MMX_OP2(pslld
),
2784 [0xf3] = MMX_OP2(psllq
),
2785 [0xf4] = MMX_OP2(pmuludq
),
2786 [0xf5] = MMX_OP2(pmaddwd
),
2787 [0xf6] = MMX_OP2(psadbw
),
2788 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2789 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2790 [0xf8] = MMX_OP2(psubb
),
2791 [0xf9] = MMX_OP2(psubw
),
2792 [0xfa] = MMX_OP2(psubl
),
2793 [0xfb] = MMX_OP2(psubq
),
2794 [0xfc] = MMX_OP2(paddb
),
2795 [0xfd] = MMX_OP2(paddw
),
2796 [0xfe] = MMX_OP2(paddl
),
2799 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2800 [0 + 2] = MMX_OP2(psrlw
),
2801 [0 + 4] = MMX_OP2(psraw
),
2802 [0 + 6] = MMX_OP2(psllw
),
2803 [8 + 2] = MMX_OP2(psrld
),
2804 [8 + 4] = MMX_OP2(psrad
),
2805 [8 + 6] = MMX_OP2(pslld
),
2806 [16 + 2] = MMX_OP2(psrlq
),
2807 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2808 [16 + 6] = MMX_OP2(psllq
),
2809 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2812 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2813 gen_helper_cvtsi2ss
,
2817 #ifdef TARGET_X86_64
2818 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2819 gen_helper_cvtsq2ss
,
2824 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2825 gen_helper_cvttss2si
,
2826 gen_helper_cvtss2si
,
2827 gen_helper_cvttsd2si
,
2831 #ifdef TARGET_X86_64
2832 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2833 gen_helper_cvttss2sq
,
2834 gen_helper_cvtss2sq
,
2835 gen_helper_cvttsd2sq
,
2840 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2851 static const SSEFunc_0_epp sse_op_table5
[256] = {
2852 [0x0c] = gen_helper_pi2fw
,
2853 [0x0d] = gen_helper_pi2fd
,
2854 [0x1c] = gen_helper_pf2iw
,
2855 [0x1d] = gen_helper_pf2id
,
2856 [0x8a] = gen_helper_pfnacc
,
2857 [0x8e] = gen_helper_pfpnacc
,
2858 [0x90] = gen_helper_pfcmpge
,
2859 [0x94] = gen_helper_pfmin
,
2860 [0x96] = gen_helper_pfrcp
,
2861 [0x97] = gen_helper_pfrsqrt
,
2862 [0x9a] = gen_helper_pfsub
,
2863 [0x9e] = gen_helper_pfadd
,
2864 [0xa0] = gen_helper_pfcmpgt
,
2865 [0xa4] = gen_helper_pfmax
,
2866 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2867 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2868 [0xaa] = gen_helper_pfsubr
,
2869 [0xae] = gen_helper_pfacc
,
2870 [0xb0] = gen_helper_pfcmpeq
,
2871 [0xb4] = gen_helper_pfmul
,
2872 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2873 [0xb7] = gen_helper_pmulhrw_mmx
,
2874 [0xbb] = gen_helper_pswapd
,
2875 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2878 struct SSEOpHelper_epp
{
2879 SSEFunc_0_epp op
[2];
2883 struct SSEOpHelper_eppi
{
2884 SSEFunc_0_eppi op
[2];
2888 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2889 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2890 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2891 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2892 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2893 CPUID_EXT_PCLMULQDQ }
2894 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2896 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2897 [0x00] = SSSE3_OP(pshufb
),
2898 [0x01] = SSSE3_OP(phaddw
),
2899 [0x02] = SSSE3_OP(phaddd
),
2900 [0x03] = SSSE3_OP(phaddsw
),
2901 [0x04] = SSSE3_OP(pmaddubsw
),
2902 [0x05] = SSSE3_OP(phsubw
),
2903 [0x06] = SSSE3_OP(phsubd
),
2904 [0x07] = SSSE3_OP(phsubsw
),
2905 [0x08] = SSSE3_OP(psignb
),
2906 [0x09] = SSSE3_OP(psignw
),
2907 [0x0a] = SSSE3_OP(psignd
),
2908 [0x0b] = SSSE3_OP(pmulhrsw
),
2909 [0x10] = SSE41_OP(pblendvb
),
2910 [0x14] = SSE41_OP(blendvps
),
2911 [0x15] = SSE41_OP(blendvpd
),
2912 [0x17] = SSE41_OP(ptest
),
2913 [0x1c] = SSSE3_OP(pabsb
),
2914 [0x1d] = SSSE3_OP(pabsw
),
2915 [0x1e] = SSSE3_OP(pabsd
),
2916 [0x20] = SSE41_OP(pmovsxbw
),
2917 [0x21] = SSE41_OP(pmovsxbd
),
2918 [0x22] = SSE41_OP(pmovsxbq
),
2919 [0x23] = SSE41_OP(pmovsxwd
),
2920 [0x24] = SSE41_OP(pmovsxwq
),
2921 [0x25] = SSE41_OP(pmovsxdq
),
2922 [0x28] = SSE41_OP(pmuldq
),
2923 [0x29] = SSE41_OP(pcmpeqq
),
2924 [0x2a] = SSE41_SPECIAL
, /* movntqda */
2925 [0x2b] = SSE41_OP(packusdw
),
2926 [0x30] = SSE41_OP(pmovzxbw
),
2927 [0x31] = SSE41_OP(pmovzxbd
),
2928 [0x32] = SSE41_OP(pmovzxbq
),
2929 [0x33] = SSE41_OP(pmovzxwd
),
2930 [0x34] = SSE41_OP(pmovzxwq
),
2931 [0x35] = SSE41_OP(pmovzxdq
),
2932 [0x37] = SSE42_OP(pcmpgtq
),
2933 [0x38] = SSE41_OP(pminsb
),
2934 [0x39] = SSE41_OP(pminsd
),
2935 [0x3a] = SSE41_OP(pminuw
),
2936 [0x3b] = SSE41_OP(pminud
),
2937 [0x3c] = SSE41_OP(pmaxsb
),
2938 [0x3d] = SSE41_OP(pmaxsd
),
2939 [0x3e] = SSE41_OP(pmaxuw
),
2940 [0x3f] = SSE41_OP(pmaxud
),
2941 [0x40] = SSE41_OP(pmulld
),
2942 [0x41] = SSE41_OP(phminposuw
),
2943 [0xdb] = AESNI_OP(aesimc
),
2944 [0xdc] = AESNI_OP(aesenc
),
2945 [0xdd] = AESNI_OP(aesenclast
),
2946 [0xde] = AESNI_OP(aesdec
),
2947 [0xdf] = AESNI_OP(aesdeclast
),
2950 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
2951 [0x08] = SSE41_OP(roundps
),
2952 [0x09] = SSE41_OP(roundpd
),
2953 [0x0a] = SSE41_OP(roundss
),
2954 [0x0b] = SSE41_OP(roundsd
),
2955 [0x0c] = SSE41_OP(blendps
),
2956 [0x0d] = SSE41_OP(blendpd
),
2957 [0x0e] = SSE41_OP(pblendw
),
2958 [0x0f] = SSSE3_OP(palignr
),
2959 [0x14] = SSE41_SPECIAL
, /* pextrb */
2960 [0x15] = SSE41_SPECIAL
, /* pextrw */
2961 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
2962 [0x17] = SSE41_SPECIAL
, /* extractps */
2963 [0x20] = SSE41_SPECIAL
, /* pinsrb */
2964 [0x21] = SSE41_SPECIAL
, /* insertps */
2965 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
2966 [0x40] = SSE41_OP(dpps
),
2967 [0x41] = SSE41_OP(dppd
),
2968 [0x42] = SSE41_OP(mpsadbw
),
2969 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
2970 [0x60] = SSE42_OP(pcmpestrm
),
2971 [0x61] = SSE42_OP(pcmpestri
),
2972 [0x62] = SSE42_OP(pcmpistrm
),
2973 [0x63] = SSE42_OP(pcmpistri
),
2974 [0xdf] = AESNI_OP(aeskeygenassist
),
2977 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
2978 target_ulong pc_start
, int rex_r
)
2980 int b1
, op1_offset
, op2_offset
, is_xmm
, val
;
2981 int modrm
, mod
, rm
, reg
;
2982 SSEFunc_0_epp sse_fn_epp
;
2983 SSEFunc_0_eppi sse_fn_eppi
;
2984 SSEFunc_0_ppi sse_fn_ppi
;
2985 SSEFunc_0_eppt sse_fn_eppt
;
2989 if (s
->prefix
& PREFIX_DATA
)
2991 else if (s
->prefix
& PREFIX_REPZ
)
2993 else if (s
->prefix
& PREFIX_REPNZ
)
2997 sse_fn_epp
= sse_op_table1
[b
][b1
];
3001 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3011 /* simple MMX/SSE operation */
3012 if (s
->flags
& HF_TS_MASK
) {
3013 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3016 if (s
->flags
& HF_EM_MASK
) {
3018 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3021 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3022 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3025 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3028 gen_helper_emms(cpu_env
);
3033 gen_helper_emms(cpu_env
);
3036 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3037 the static cpu state) */
3039 gen_helper_enter_mmx(cpu_env
);
3042 modrm
= cpu_ldub_code(env
, s
->pc
++);
3043 reg
= ((modrm
>> 3) & 7);
3046 mod
= (modrm
>> 6) & 3;
3047 if (sse_fn_epp
== SSE_SPECIAL
) {
3050 case 0x0e7: /* movntq */
3053 gen_lea_modrm(env
, s
, modrm
);
3054 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3056 case 0x1e7: /* movntdq */
3057 case 0x02b: /* movntps */
3058 case 0x12b: /* movntps */
3061 gen_lea_modrm(env
, s
, modrm
);
3062 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3064 case 0x3f0: /* lddqu */
3067 gen_lea_modrm(env
, s
, modrm
);
3068 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3070 case 0x22b: /* movntss */
3071 case 0x32b: /* movntsd */
3074 gen_lea_modrm(env
, s
, modrm
);
3076 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3078 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3079 xmm_regs
[reg
].XMM_L(0)));
3080 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3083 case 0x6e: /* movd mm, ea */
3084 #ifdef TARGET_X86_64
3085 if (s
->dflag
== MO_64
) {
3086 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3087 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3091 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3092 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3093 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3094 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3095 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3098 case 0x16e: /* movd xmm, ea */
3099 #ifdef TARGET_X86_64
3100 if (s
->dflag
== MO_64
) {
3101 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3102 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3103 offsetof(CPUX86State
,xmm_regs
[reg
]));
3104 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3108 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3109 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3110 offsetof(CPUX86State
,xmm_regs
[reg
]));
3111 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3112 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3115 case 0x6f: /* movq mm, ea */
3117 gen_lea_modrm(env
, s
, modrm
);
3118 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3121 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3122 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3123 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3124 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3127 case 0x010: /* movups */
3128 case 0x110: /* movupd */
3129 case 0x028: /* movaps */
3130 case 0x128: /* movapd */
3131 case 0x16f: /* movdqa xmm, ea */
3132 case 0x26f: /* movdqu xmm, ea */
3134 gen_lea_modrm(env
, s
, modrm
);
3135 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3137 rm
= (modrm
& 7) | REX_B(s
);
3138 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3139 offsetof(CPUX86State
,xmm_regs
[rm
]));
3142 case 0x210: /* movss xmm, ea */
3144 gen_lea_modrm(env
, s
, modrm
);
3145 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3146 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3147 tcg_gen_movi_tl(cpu_T
[0], 0);
3148 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3149 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3150 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3152 rm
= (modrm
& 7) | REX_B(s
);
3153 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3154 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3157 case 0x310: /* movsd xmm, ea */
3159 gen_lea_modrm(env
, s
, modrm
);
3160 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3161 xmm_regs
[reg
].XMM_Q(0)));
3162 tcg_gen_movi_tl(cpu_T
[0], 0);
3163 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3164 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3166 rm
= (modrm
& 7) | REX_B(s
);
3167 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3168 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3171 case 0x012: /* movlps */
3172 case 0x112: /* movlpd */
3174 gen_lea_modrm(env
, s
, modrm
);
3175 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3176 xmm_regs
[reg
].XMM_Q(0)));
3179 rm
= (modrm
& 7) | REX_B(s
);
3180 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3181 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3184 case 0x212: /* movsldup */
3186 gen_lea_modrm(env
, s
, modrm
);
3187 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3189 rm
= (modrm
& 7) | REX_B(s
);
3190 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3191 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3192 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3193 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3195 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3196 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3197 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3198 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3200 case 0x312: /* movddup */
3202 gen_lea_modrm(env
, s
, modrm
);
3203 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3204 xmm_regs
[reg
].XMM_Q(0)));
3206 rm
= (modrm
& 7) | REX_B(s
);
3207 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3208 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3210 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3211 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3213 case 0x016: /* movhps */
3214 case 0x116: /* movhpd */
3216 gen_lea_modrm(env
, s
, modrm
);
3217 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3218 xmm_regs
[reg
].XMM_Q(1)));
3221 rm
= (modrm
& 7) | REX_B(s
);
3222 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3223 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3226 case 0x216: /* movshdup */
3228 gen_lea_modrm(env
, s
, modrm
);
3229 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3231 rm
= (modrm
& 7) | REX_B(s
);
3232 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3233 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3234 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3235 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3237 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3238 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3239 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3240 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3245 int bit_index
, field_length
;
3247 if (b1
== 1 && reg
!= 0)
3249 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3250 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3251 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3252 offsetof(CPUX86State
,xmm_regs
[reg
]));
3254 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3255 tcg_const_i32(bit_index
),
3256 tcg_const_i32(field_length
));
3258 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3259 tcg_const_i32(bit_index
),
3260 tcg_const_i32(field_length
));
3263 case 0x7e: /* movd ea, mm */
3264 #ifdef TARGET_X86_64
3265 if (s
->dflag
== MO_64
) {
3266 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3267 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3268 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3272 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3273 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3274 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3277 case 0x17e: /* movd ea, xmm */
3278 #ifdef TARGET_X86_64
3279 if (s
->dflag
== MO_64
) {
3280 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3281 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3282 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3286 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3287 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3288 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3291 case 0x27e: /* movq xmm, ea */
3293 gen_lea_modrm(env
, s
, modrm
);
3294 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3295 xmm_regs
[reg
].XMM_Q(0)));
3297 rm
= (modrm
& 7) | REX_B(s
);
3298 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3299 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3301 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3303 case 0x7f: /* movq ea, mm */
3305 gen_lea_modrm(env
, s
, modrm
);
3306 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3309 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3310 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3313 case 0x011: /* movups */
3314 case 0x111: /* movupd */
3315 case 0x029: /* movaps */
3316 case 0x129: /* movapd */
3317 case 0x17f: /* movdqa ea, xmm */
3318 case 0x27f: /* movdqu ea, xmm */
3320 gen_lea_modrm(env
, s
, modrm
);
3321 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3323 rm
= (modrm
& 7) | REX_B(s
);
3324 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3325 offsetof(CPUX86State
,xmm_regs
[reg
]));
3328 case 0x211: /* movss ea, xmm */
3330 gen_lea_modrm(env
, s
, modrm
);
3331 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3332 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3334 rm
= (modrm
& 7) | REX_B(s
);
3335 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3336 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3339 case 0x311: /* movsd ea, xmm */
3341 gen_lea_modrm(env
, s
, modrm
);
3342 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3343 xmm_regs
[reg
].XMM_Q(0)));
3345 rm
= (modrm
& 7) | REX_B(s
);
3346 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3347 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3350 case 0x013: /* movlps */
3351 case 0x113: /* movlpd */
3353 gen_lea_modrm(env
, s
, modrm
);
3354 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3355 xmm_regs
[reg
].XMM_Q(0)));
3360 case 0x017: /* movhps */
3361 case 0x117: /* movhpd */
3363 gen_lea_modrm(env
, s
, modrm
);
3364 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3365 xmm_regs
[reg
].XMM_Q(1)));
3370 case 0x71: /* shift mm, im */
3373 case 0x171: /* shift xmm, im */
3379 val
= cpu_ldub_code(env
, s
->pc
++);
3381 tcg_gen_movi_tl(cpu_T
[0], val
);
3382 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3383 tcg_gen_movi_tl(cpu_T
[0], 0);
3384 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3385 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3387 tcg_gen_movi_tl(cpu_T
[0], val
);
3388 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3389 tcg_gen_movi_tl(cpu_T
[0], 0);
3390 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3391 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3393 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3394 (((modrm
>> 3)) & 7)][b1
];
3399 rm
= (modrm
& 7) | REX_B(s
);
3400 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3403 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3405 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3406 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3407 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3409 case 0x050: /* movmskps */
3410 rm
= (modrm
& 7) | REX_B(s
);
3411 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3412 offsetof(CPUX86State
,xmm_regs
[rm
]));
3413 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3414 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3416 case 0x150: /* movmskpd */
3417 rm
= (modrm
& 7) | REX_B(s
);
3418 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3419 offsetof(CPUX86State
,xmm_regs
[rm
]));
3420 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3421 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3423 case 0x02a: /* cvtpi2ps */
3424 case 0x12a: /* cvtpi2pd */
3425 gen_helper_enter_mmx(cpu_env
);
3427 gen_lea_modrm(env
, s
, modrm
);
3428 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3429 gen_ldq_env_A0(s
, op2_offset
);
3432 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3434 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3435 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3436 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3439 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3443 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3447 case 0x22a: /* cvtsi2ss */
3448 case 0x32a: /* cvtsi2sd */
3449 ot
= mo_64_32(s
->dflag
);
3450 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3451 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3452 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3454 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3455 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3456 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3458 #ifdef TARGET_X86_64
3459 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3460 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3466 case 0x02c: /* cvttps2pi */
3467 case 0x12c: /* cvttpd2pi */
3468 case 0x02d: /* cvtps2pi */
3469 case 0x12d: /* cvtpd2pi */
3470 gen_helper_enter_mmx(cpu_env
);
3472 gen_lea_modrm(env
, s
, modrm
);
3473 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3474 gen_ldo_env_A0(s
, op2_offset
);
3476 rm
= (modrm
& 7) | REX_B(s
);
3477 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3479 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3480 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3481 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3484 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3487 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3490 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3493 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3497 case 0x22c: /* cvttss2si */
3498 case 0x32c: /* cvttsd2si */
3499 case 0x22d: /* cvtss2si */
3500 case 0x32d: /* cvtsd2si */
3501 ot
= mo_64_32(s
->dflag
);
3503 gen_lea_modrm(env
, s
, modrm
);
3505 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3507 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3508 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3510 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3512 rm
= (modrm
& 7) | REX_B(s
);
3513 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3515 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3517 SSEFunc_i_ep sse_fn_i_ep
=
3518 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3519 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3520 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3522 #ifdef TARGET_X86_64
3523 SSEFunc_l_ep sse_fn_l_ep
=
3524 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3525 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3530 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3532 case 0xc4: /* pinsrw */
3535 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3536 val
= cpu_ldub_code(env
, s
->pc
++);
3539 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3540 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3543 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3544 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3547 case 0xc5: /* pextrw */
3551 ot
= mo_64_32(s
->dflag
);
3552 val
= cpu_ldub_code(env
, s
->pc
++);
3555 rm
= (modrm
& 7) | REX_B(s
);
3556 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3557 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3561 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3562 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3564 reg
= ((modrm
>> 3) & 7) | rex_r
;
3565 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3567 case 0x1d6: /* movq ea, xmm */
3569 gen_lea_modrm(env
, s
, modrm
);
3570 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3571 xmm_regs
[reg
].XMM_Q(0)));
3573 rm
= (modrm
& 7) | REX_B(s
);
3574 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3575 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3576 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3579 case 0x2d6: /* movq2dq */
3580 gen_helper_enter_mmx(cpu_env
);
3582 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3583 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3584 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3586 case 0x3d6: /* movdq2q */
3587 gen_helper_enter_mmx(cpu_env
);
3588 rm
= (modrm
& 7) | REX_B(s
);
3589 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3590 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3592 case 0xd7: /* pmovmskb */
3597 rm
= (modrm
& 7) | REX_B(s
);
3598 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3599 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3602 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3603 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3605 reg
= ((modrm
>> 3) & 7) | rex_r
;
3606 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3612 if ((b
& 0xf0) == 0xf0) {
3615 modrm
= cpu_ldub_code(env
, s
->pc
++);
3617 reg
= ((modrm
>> 3) & 7) | rex_r
;
3618 mod
= (modrm
>> 6) & 3;
3623 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3627 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3631 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3633 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3635 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3636 gen_lea_modrm(env
, s
, modrm
);
3638 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3639 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3640 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3641 gen_ldq_env_A0(s
, op2_offset
+
3642 offsetof(XMMReg
, XMM_Q(0)));
3644 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3645 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3646 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3647 s
->mem_index
, MO_LEUL
);
3648 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3649 offsetof(XMMReg
, XMM_L(0)));
3651 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3652 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3653 s
->mem_index
, MO_LEUW
);
3654 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3655 offsetof(XMMReg
, XMM_W(0)));
3657 case 0x2a: /* movntqda */
3658 gen_ldo_env_A0(s
, op1_offset
);
3661 gen_ldo_env_A0(s
, op2_offset
);
3665 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3667 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3669 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3670 gen_lea_modrm(env
, s
, modrm
);
3671 gen_ldq_env_A0(s
, op2_offset
);
3674 if (sse_fn_epp
== SSE_SPECIAL
) {
3678 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3679 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3680 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3683 set_cc_op(s
, CC_OP_EFLAGS
);
3690 /* Various integer extensions at 0f 38 f[0-f]. */
3691 b
= modrm
| (b1
<< 8);
3692 modrm
= cpu_ldub_code(env
, s
->pc
++);
3693 reg
= ((modrm
>> 3) & 7) | rex_r
;
3696 case 0x3f0: /* crc32 Gd,Eb */
3697 case 0x3f1: /* crc32 Gd,Ey */
3699 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3702 if ((b
& 0xff) == 0xf0) {
3704 } else if (s
->dflag
!= MO_64
) {
3705 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3710 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3711 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3712 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3713 cpu_T
[0], tcg_const_i32(8 << ot
));
3715 ot
= mo_64_32(s
->dflag
);
3716 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3719 case 0x1f0: /* crc32 or movbe */
3721 /* For these insns, the f3 prefix is supposed to have priority
3722 over the 66 prefix, but that's not what we implement above
3724 if (s
->prefix
& PREFIX_REPNZ
) {
3728 case 0x0f0: /* movbe Gy,My */
3729 case 0x0f1: /* movbe My,Gy */
3730 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3733 if (s
->dflag
!= MO_64
) {
3734 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3739 gen_lea_modrm(env
, s
, modrm
);
3741 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3742 s
->mem_index
, ot
| MO_BE
);
3743 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3745 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3746 s
->mem_index
, ot
| MO_BE
);
3750 case 0x0f2: /* andn Gy, By, Ey */
3751 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3752 || !(s
->prefix
& PREFIX_VEX
)
3756 ot
= mo_64_32(s
->dflag
);
3757 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3758 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3759 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3760 gen_op_update1_cc();
3761 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3764 case 0x0f7: /* bextr Gy, Ey, By */
3765 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3766 || !(s
->prefix
& PREFIX_VEX
)
3770 ot
= mo_64_32(s
->dflag
);
3774 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3775 /* Extract START, and shift the operand.
3776 Shifts larger than operand size get zeros. */
3777 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3778 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3780 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3781 zero
= tcg_const_tl(0);
3782 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3784 tcg_temp_free(zero
);
3786 /* Extract the LEN into a mask. Lengths larger than
3787 operand size get all ones. */
3788 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3789 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3790 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3792 tcg_temp_free(bound
);
3793 tcg_gen_movi_tl(cpu_T
[1], 1);
3794 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3795 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3796 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3798 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3799 gen_op_update1_cc();
3800 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3804 case 0x0f5: /* bzhi Gy, Ey, By */
3805 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3806 || !(s
->prefix
& PREFIX_VEX
)
3810 ot
= mo_64_32(s
->dflag
);
3811 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3812 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3814 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3815 /* Note that since we're using BMILG (in order to get O
3816 cleared) we need to store the inverse into C. */
3817 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3819 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3820 bound
, bound
, cpu_T
[1]);
3821 tcg_temp_free(bound
);
3823 tcg_gen_movi_tl(cpu_A0
, -1);
3824 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3825 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3826 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3827 gen_op_update1_cc();
3828 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3831 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3832 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3833 || !(s
->prefix
& PREFIX_VEX
)
3837 ot
= mo_64_32(s
->dflag
);
3838 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3841 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3842 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3843 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3844 cpu_tmp2_i32
, cpu_tmp3_i32
);
3845 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3846 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3848 #ifdef TARGET_X86_64
3850 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3851 cpu_T
[0], cpu_regs
[R_EDX
]);
3857 case 0x3f5: /* pdep Gy, By, Ey */
3858 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3859 || !(s
->prefix
& PREFIX_VEX
)
3863 ot
= mo_64_32(s
->dflag
);
3864 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3865 /* Note that by zero-extending the mask operand, we
3866 automatically handle zero-extending the result. */
3868 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3870 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3872 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3875 case 0x2f5: /* pext Gy, By, Ey */
3876 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3877 || !(s
->prefix
& PREFIX_VEX
)
3881 ot
= mo_64_32(s
->dflag
);
3882 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3883 /* Note that by zero-extending the mask operand, we
3884 automatically handle zero-extending the result. */
3886 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3888 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3890 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3893 case 0x1f6: /* adcx Gy, Ey */
3894 case 0x2f6: /* adox Gy, Ey */
3895 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3898 TCGv carry_in
, carry_out
, zero
;
3901 ot
= mo_64_32(s
->dflag
);
3902 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3904 /* Re-use the carry-out from a previous round. */
3905 TCGV_UNUSED(carry_in
);
3906 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
3910 carry_in
= cpu_cc_dst
;
3911 end_op
= CC_OP_ADCX
;
3913 end_op
= CC_OP_ADCOX
;
3918 end_op
= CC_OP_ADCOX
;
3920 carry_in
= cpu_cc_src2
;
3921 end_op
= CC_OP_ADOX
;
3925 end_op
= CC_OP_ADCOX
;
3926 carry_in
= carry_out
;
3929 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
3932 /* If we can't reuse carry-out, get it out of EFLAGS. */
3933 if (TCGV_IS_UNUSED(carry_in
)) {
3934 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
3935 gen_compute_eflags(s
);
3937 carry_in
= cpu_tmp0
;
3938 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
3939 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
3940 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
3944 #ifdef TARGET_X86_64
3946 /* If we know TL is 64-bit, and we want a 32-bit
3947 result, just do everything in 64-bit arithmetic. */
3948 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
3949 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
3950 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
3951 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
3952 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
3953 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
3957 /* Otherwise compute the carry-out in two steps. */
3958 zero
= tcg_const_tl(0);
3959 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
3962 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
3963 cpu_regs
[reg
], carry_out
,
3965 tcg_temp_free(zero
);
3968 set_cc_op(s
, end_op
);
3972 case 0x1f7: /* shlx Gy, Ey, By */
3973 case 0x2f7: /* sarx Gy, Ey, By */
3974 case 0x3f7: /* shrx Gy, Ey, By */
3975 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3976 || !(s
->prefix
& PREFIX_VEX
)
3980 ot
= mo_64_32(s
->dflag
);
3981 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3983 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
3985 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
3988 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3989 } else if (b
== 0x2f7) {
3991 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
3993 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3996 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
3998 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4000 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4006 case 0x3f3: /* Group 17 */
4007 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4008 || !(s
->prefix
& PREFIX_VEX
)
4012 ot
= mo_64_32(s
->dflag
);
4013 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4016 case 1: /* blsr By,Ey */
4017 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4018 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4019 gen_op_mov_reg_v(ot
, s
->vex_v
, cpu_T
[0]);
4020 gen_op_update2_cc();
4021 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4024 case 2: /* blsmsk By,Ey */
4025 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4026 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4027 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4028 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4029 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4032 case 3: /* blsi By, Ey */
4033 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4034 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4035 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4036 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4037 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4053 modrm
= cpu_ldub_code(env
, s
->pc
++);
4055 reg
= ((modrm
>> 3) & 7) | rex_r
;
4056 mod
= (modrm
>> 6) & 3;
4061 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4065 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4068 if (sse_fn_eppi
== SSE_SPECIAL
) {
4069 ot
= mo_64_32(s
->dflag
);
4070 rm
= (modrm
& 7) | REX_B(s
);
4072 gen_lea_modrm(env
, s
, modrm
);
4073 reg
= ((modrm
>> 3) & 7) | rex_r
;
4074 val
= cpu_ldub_code(env
, s
->pc
++);
4076 case 0x14: /* pextrb */
4077 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4078 xmm_regs
[reg
].XMM_B(val
& 15)));
4080 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4082 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4083 s
->mem_index
, MO_UB
);
4086 case 0x15: /* pextrw */
4087 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4088 xmm_regs
[reg
].XMM_W(val
& 7)));
4090 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4092 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4093 s
->mem_index
, MO_LEUW
);
4097 if (ot
== MO_32
) { /* pextrd */
4098 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4099 offsetof(CPUX86State
,
4100 xmm_regs
[reg
].XMM_L(val
& 3)));
4102 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4104 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4105 s
->mem_index
, MO_LEUL
);
4107 } else { /* pextrq */
4108 #ifdef TARGET_X86_64
4109 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4110 offsetof(CPUX86State
,
4111 xmm_regs
[reg
].XMM_Q(val
& 1)));
4113 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4115 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4116 s
->mem_index
, MO_LEQ
);
4123 case 0x17: /* extractps */
4124 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4125 xmm_regs
[reg
].XMM_L(val
& 3)));
4127 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4129 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4130 s
->mem_index
, MO_LEUL
);
4133 case 0x20: /* pinsrb */
4135 gen_op_mov_v_reg(MO_32
, cpu_T
[0], rm
);
4137 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4138 s
->mem_index
, MO_UB
);
4140 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4141 xmm_regs
[reg
].XMM_B(val
& 15)));
4143 case 0x21: /* insertps */
4145 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4146 offsetof(CPUX86State
,xmm_regs
[rm
]
4147 .XMM_L((val
>> 6) & 3)));
4149 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4150 s
->mem_index
, MO_LEUL
);
4152 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4153 offsetof(CPUX86State
,xmm_regs
[reg
]
4154 .XMM_L((val
>> 4) & 3)));
4156 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4157 cpu_env
, offsetof(CPUX86State
,
4158 xmm_regs
[reg
].XMM_L(0)));
4160 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4161 cpu_env
, offsetof(CPUX86State
,
4162 xmm_regs
[reg
].XMM_L(1)));
4164 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4165 cpu_env
, offsetof(CPUX86State
,
4166 xmm_regs
[reg
].XMM_L(2)));
4168 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4169 cpu_env
, offsetof(CPUX86State
,
4170 xmm_regs
[reg
].XMM_L(3)));
4173 if (ot
== MO_32
) { /* pinsrd */
4175 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4177 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4178 s
->mem_index
, MO_LEUL
);
4180 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4181 offsetof(CPUX86State
,
4182 xmm_regs
[reg
].XMM_L(val
& 3)));
4183 } else { /* pinsrq */
4184 #ifdef TARGET_X86_64
4186 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4188 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4189 s
->mem_index
, MO_LEQ
);
4191 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4192 offsetof(CPUX86State
,
4193 xmm_regs
[reg
].XMM_Q(val
& 1)));
4204 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4206 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4208 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4209 gen_lea_modrm(env
, s
, modrm
);
4210 gen_ldo_env_A0(s
, op2_offset
);
4213 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4215 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4217 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4218 gen_lea_modrm(env
, s
, modrm
);
4219 gen_ldq_env_A0(s
, op2_offset
);
4222 val
= cpu_ldub_code(env
, s
->pc
++);
4224 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4225 set_cc_op(s
, CC_OP_EFLAGS
);
4227 if (s
->dflag
== MO_64
) {
4228 /* The helper must use entire 64-bit gp registers */
4233 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4234 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4235 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4239 /* Various integer extensions at 0f 3a f[0-f]. */
4240 b
= modrm
| (b1
<< 8);
4241 modrm
= cpu_ldub_code(env
, s
->pc
++);
4242 reg
= ((modrm
>> 3) & 7) | rex_r
;
4245 case 0x3f0: /* rorx Gy,Ey, Ib */
4246 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4247 || !(s
->prefix
& PREFIX_VEX
)
4251 ot
= mo_64_32(s
->dflag
);
4252 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4253 b
= cpu_ldub_code(env
, s
->pc
++);
4255 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4257 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4258 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4259 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4261 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4273 /* generic MMX or SSE operation */
4275 case 0x70: /* pshufx insn */
4276 case 0xc6: /* pshufx insn */
4277 case 0xc2: /* compare insns */
4284 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4288 gen_lea_modrm(env
, s
, modrm
);
4289 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4295 /* Most sse scalar operations. */
4298 } else if (b1
== 3) {
4303 case 0x2e: /* ucomis[sd] */
4304 case 0x2f: /* comis[sd] */
4316 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4317 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
4318 offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4322 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_D(0)));
4325 /* 128 bit access */
4326 gen_ldo_env_A0(s
, op2_offset
);
4330 rm
= (modrm
& 7) | REX_B(s
);
4331 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4334 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4336 gen_lea_modrm(env
, s
, modrm
);
4337 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4338 gen_ldq_env_A0(s
, op2_offset
);
4341 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4345 case 0x0f: /* 3DNow! data insns */
4346 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4348 val
= cpu_ldub_code(env
, s
->pc
++);
4349 sse_fn_epp
= sse_op_table5
[val
];
4353 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4354 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4355 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4357 case 0x70: /* pshufx insn */
4358 case 0xc6: /* pshufx insn */
4359 val
= cpu_ldub_code(env
, s
->pc
++);
4360 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4361 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4362 /* XXX: introduce a new table? */
4363 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4364 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4368 val
= cpu_ldub_code(env
, s
->pc
++);
4371 sse_fn_epp
= sse_op_table4
[val
][b1
];
4373 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4374 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4375 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4378 /* maskmov : we must prepare A0 */
4381 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EDI
]);
4382 gen_extu(s
->aflag
, cpu_A0
);
4383 gen_add_A0_ds_seg(s
);
4385 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4386 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4387 /* XXX: introduce a new table? */
4388 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4389 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4392 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4393 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4394 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4397 if (b
== 0x2e || b
== 0x2f) {
4398 set_cc_op(s
, CC_OP_EFLAGS
);
4403 /* convert one instruction. s->is_jmp is set if the translation must
4404 be stopped. Return the next pc value */
4405 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4406 target_ulong pc_start
)
4410 TCGMemOp ot
, aflag
, dflag
;
4411 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4412 target_ulong next_eip
, tval
;
4415 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4416 tcg_gen_debug_insn_start(pc_start
);
4423 #ifdef TARGET_X86_64
4428 s
->rip_offset
= 0; /* for relative ip address */
4432 b
= cpu_ldub_code(env
, s
->pc
);
4434 /* Collect prefixes. */
4437 prefixes
|= PREFIX_REPZ
;
4440 prefixes
|= PREFIX_REPNZ
;
4443 prefixes
|= PREFIX_LOCK
;
4464 prefixes
|= PREFIX_DATA
;
4467 prefixes
|= PREFIX_ADR
;
4469 #ifdef TARGET_X86_64
4473 rex_w
= (b
>> 3) & 1;
4474 rex_r
= (b
& 0x4) << 1;
4475 s
->rex_x
= (b
& 0x2) << 2;
4476 REX_B(s
) = (b
& 0x1) << 3;
4477 x86_64_hregs
= 1; /* select uniform byte register addressing */
4482 case 0xc5: /* 2-byte VEX */
4483 case 0xc4: /* 3-byte VEX */
4484 /* VEX prefixes cannot be used except in 32-bit mode.
4485 Otherwise the instruction is LES or LDS. */
4486 if (s
->code32
&& !s
->vm86
) {
4487 static const int pp_prefix
[4] = {
4488 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4490 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4492 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4493 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4494 otherwise the instruction is LES or LDS. */
4499 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4500 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4501 | PREFIX_LOCK
| PREFIX_DATA
)) {
4504 #ifdef TARGET_X86_64
4509 rex_r
= (~vex2
>> 4) & 8;
4512 b
= cpu_ldub_code(env
, s
->pc
++);
4514 #ifdef TARGET_X86_64
4515 s
->rex_x
= (~vex2
>> 3) & 8;
4516 s
->rex_b
= (~vex2
>> 2) & 8;
4518 vex3
= cpu_ldub_code(env
, s
->pc
++);
4519 rex_w
= (vex3
>> 7) & 1;
4520 switch (vex2
& 0x1f) {
4521 case 0x01: /* Implied 0f leading opcode bytes. */
4522 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4524 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4527 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4530 default: /* Reserved for future use. */
4534 s
->vex_v
= (~vex3
>> 3) & 0xf;
4535 s
->vex_l
= (vex3
>> 2) & 1;
4536 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4541 /* Post-process prefixes. */
4543 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4544 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4545 over 0x66 if both are present. */
4546 dflag
= (rex_w
> 0 ? MO_64
: prefixes
& PREFIX_DATA
? MO_16
: MO_32
);
4547 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4548 aflag
= (prefixes
& PREFIX_ADR
? MO_32
: MO_64
);
4550 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4551 if (s
->code32
^ ((prefixes
& PREFIX_DATA
) != 0)) {
4556 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4557 if (s
->code32
^ ((prefixes
& PREFIX_ADR
) != 0)) {
4564 s
->prefix
= prefixes
;
4568 /* lock generation */
4569 if (prefixes
& PREFIX_LOCK
)
4572 /* now check op code */
4576 /**************************/
4577 /* extended op code */
4578 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4581 /**************************/
4596 ot
= mo_b_d(b
, dflag
);
4599 case 0: /* OP Ev, Gv */
4600 modrm
= cpu_ldub_code(env
, s
->pc
++);
4601 reg
= ((modrm
>> 3) & 7) | rex_r
;
4602 mod
= (modrm
>> 6) & 3;
4603 rm
= (modrm
& 7) | REX_B(s
);
4605 gen_lea_modrm(env
, s
, modrm
);
4607 } else if (op
== OP_XORL
&& rm
== reg
) {
4609 /* xor reg, reg optimisation */
4610 set_cc_op(s
, CC_OP_CLR
);
4611 tcg_gen_movi_tl(cpu_T
[0], 0);
4612 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4617 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
4618 gen_op(s
, op
, ot
, opreg
);
4620 case 1: /* OP Gv, Ev */
4621 modrm
= cpu_ldub_code(env
, s
->pc
++);
4622 mod
= (modrm
>> 6) & 3;
4623 reg
= ((modrm
>> 3) & 7) | rex_r
;
4624 rm
= (modrm
& 7) | REX_B(s
);
4626 gen_lea_modrm(env
, s
, modrm
);
4627 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4628 } else if (op
== OP_XORL
&& rm
== reg
) {
4631 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
4633 gen_op(s
, op
, ot
, reg
);
4635 case 2: /* OP A, Iv */
4636 val
= insn_get(env
, s
, ot
);
4637 tcg_gen_movi_tl(cpu_T
[1], val
);
4638 gen_op(s
, op
, ot
, OR_EAX
);
4647 case 0x80: /* GRP1 */
4653 ot
= mo_b_d(b
, dflag
);
4655 modrm
= cpu_ldub_code(env
, s
->pc
++);
4656 mod
= (modrm
>> 6) & 3;
4657 rm
= (modrm
& 7) | REX_B(s
);
4658 op
= (modrm
>> 3) & 7;
4664 s
->rip_offset
= insn_const_size(ot
);
4665 gen_lea_modrm(env
, s
, modrm
);
4676 val
= insn_get(env
, s
, ot
);
4679 val
= (int8_t)insn_get(env
, s
, MO_8
);
4682 tcg_gen_movi_tl(cpu_T
[1], val
);
4683 gen_op(s
, op
, ot
, opreg
);
4687 /**************************/
4688 /* inc, dec, and other misc arith */
4689 case 0x40 ... 0x47: /* inc Gv */
4691 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4693 case 0x48 ... 0x4f: /* dec Gv */
4695 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4697 case 0xf6: /* GRP3 */
4699 ot
= mo_b_d(b
, dflag
);
4701 modrm
= cpu_ldub_code(env
, s
->pc
++);
4702 mod
= (modrm
>> 6) & 3;
4703 rm
= (modrm
& 7) | REX_B(s
);
4704 op
= (modrm
>> 3) & 7;
4707 s
->rip_offset
= insn_const_size(ot
);
4708 gen_lea_modrm(env
, s
, modrm
);
4709 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4711 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
4716 val
= insn_get(env
, s
, ot
);
4717 tcg_gen_movi_tl(cpu_T
[1], val
);
4718 gen_op_testl_T0_T1_cc();
4719 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4722 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4724 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4726 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4730 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4732 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4734 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4736 gen_op_update_neg_cc();
4737 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4742 gen_op_mov_v_reg(MO_8
, cpu_T
[1], R_EAX
);
4743 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4744 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4745 /* XXX: use 32 bit mul which could be faster */
4746 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4747 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4748 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4749 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4750 set_cc_op(s
, CC_OP_MULB
);
4753 gen_op_mov_v_reg(MO_16
, cpu_T
[1], R_EAX
);
4754 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4755 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4756 /* XXX: use 32 bit mul which could be faster */
4757 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4758 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4759 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4760 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4761 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4762 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4763 set_cc_op(s
, CC_OP_MULW
);
4767 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4768 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4769 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4770 cpu_tmp2_i32
, cpu_tmp3_i32
);
4771 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4772 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4773 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4774 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4775 set_cc_op(s
, CC_OP_MULL
);
4777 #ifdef TARGET_X86_64
4779 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4780 cpu_T
[0], cpu_regs
[R_EAX
]);
4781 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4782 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4783 set_cc_op(s
, CC_OP_MULQ
);
4791 gen_op_mov_v_reg(MO_8
, cpu_T
[1], R_EAX
);
4792 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4793 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4794 /* XXX: use 32 bit mul which could be faster */
4795 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4796 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4797 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4798 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4799 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4800 set_cc_op(s
, CC_OP_MULB
);
4803 gen_op_mov_v_reg(MO_16
, cpu_T
[1], R_EAX
);
4804 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4805 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4806 /* XXX: use 32 bit mul which could be faster */
4807 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4808 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4809 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4810 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4811 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4812 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4813 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4814 set_cc_op(s
, CC_OP_MULW
);
4818 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4819 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4820 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4821 cpu_tmp2_i32
, cpu_tmp3_i32
);
4822 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4823 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4824 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4825 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4826 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4827 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4828 set_cc_op(s
, CC_OP_MULL
);
4830 #ifdef TARGET_X86_64
4832 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4833 cpu_T
[0], cpu_regs
[R_EAX
]);
4834 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4835 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4836 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4837 set_cc_op(s
, CC_OP_MULQ
);
4845 gen_jmp_im(pc_start
- s
->cs_base
);
4846 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4849 gen_jmp_im(pc_start
- s
->cs_base
);
4850 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4854 gen_jmp_im(pc_start
- s
->cs_base
);
4855 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4857 #ifdef TARGET_X86_64
4859 gen_jmp_im(pc_start
- s
->cs_base
);
4860 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4868 gen_jmp_im(pc_start
- s
->cs_base
);
4869 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4872 gen_jmp_im(pc_start
- s
->cs_base
);
4873 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4877 gen_jmp_im(pc_start
- s
->cs_base
);
4878 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4880 #ifdef TARGET_X86_64
4882 gen_jmp_im(pc_start
- s
->cs_base
);
4883 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4893 case 0xfe: /* GRP4 */
4894 case 0xff: /* GRP5 */
4895 ot
= mo_b_d(b
, dflag
);
4897 modrm
= cpu_ldub_code(env
, s
->pc
++);
4898 mod
= (modrm
>> 6) & 3;
4899 rm
= (modrm
& 7) | REX_B(s
);
4900 op
= (modrm
>> 3) & 7;
4901 if (op
>= 2 && b
== 0xfe) {
4905 if (op
== 2 || op
== 4) {
4906 /* operand size for jumps is 64 bit */
4908 } else if (op
== 3 || op
== 5) {
4909 ot
= dflag
!= MO_16
? MO_32
+ (rex_w
== 1) : MO_16
;
4910 } else if (op
== 6) {
4911 /* default push size is 64 bit */
4912 ot
= mo_pushpop(s
, dflag
);
4916 gen_lea_modrm(env
, s
, modrm
);
4917 if (op
>= 2 && op
!= 3 && op
!= 5)
4918 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4920 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
4924 case 0: /* inc Ev */
4929 gen_inc(s
, ot
, opreg
, 1);
4931 case 1: /* dec Ev */
4936 gen_inc(s
, ot
, opreg
, -1);
4938 case 2: /* call Ev */
4939 /* XXX: optimize if memory (no 'and' is necessary) */
4940 if (dflag
== MO_16
) {
4941 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4943 next_eip
= s
->pc
- s
->cs_base
;
4944 tcg_gen_movi_tl(cpu_T
[1], next_eip
);
4945 gen_push_v(s
, cpu_T
[1]);
4946 gen_op_jmp_v(cpu_T
[0]);
4949 case 3: /* lcall Ev */
4950 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4951 gen_add_A0_im(s
, 1 << ot
);
4952 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4954 if (s
->pe
&& !s
->vm86
) {
4955 gen_update_cc_op(s
);
4956 gen_jmp_im(pc_start
- s
->cs_base
);
4957 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4958 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4959 tcg_const_i32(dflag
- 1),
4960 tcg_const_i32(s
->pc
- pc_start
));
4962 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4963 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4964 tcg_const_i32(dflag
- 1),
4965 tcg_const_i32(s
->pc
- s
->cs_base
));
4969 case 4: /* jmp Ev */
4970 if (dflag
== MO_16
) {
4971 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4973 gen_op_jmp_v(cpu_T
[0]);
4976 case 5: /* ljmp Ev */
4977 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4978 gen_add_A0_im(s
, 1 << ot
);
4979 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4981 if (s
->pe
&& !s
->vm86
) {
4982 gen_update_cc_op(s
);
4983 gen_jmp_im(pc_start
- s
->cs_base
);
4984 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4985 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4986 tcg_const_i32(s
->pc
- pc_start
));
4988 gen_op_movl_seg_T0_vm(R_CS
);
4989 gen_op_jmp_v(cpu_T
[1]);
4993 case 6: /* push Ev */
4994 gen_push_v(s
, cpu_T
[0]);
5001 case 0x84: /* test Ev, Gv */
5003 ot
= mo_b_d(b
, dflag
);
5005 modrm
= cpu_ldub_code(env
, s
->pc
++);
5006 reg
= ((modrm
>> 3) & 7) | rex_r
;
5008 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5009 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5010 gen_op_testl_T0_T1_cc();
5011 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5014 case 0xa8: /* test eAX, Iv */
5016 ot
= mo_b_d(b
, dflag
);
5017 val
= insn_get(env
, s
, ot
);
5019 gen_op_mov_v_reg(ot
, cpu_T
[0], OR_EAX
);
5020 tcg_gen_movi_tl(cpu_T
[1], val
);
5021 gen_op_testl_T0_T1_cc();
5022 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5025 case 0x98: /* CWDE/CBW */
5027 #ifdef TARGET_X86_64
5029 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
5030 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5031 gen_op_mov_reg_v(MO_64
, R_EAX
, cpu_T
[0]);
5035 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EAX
);
5036 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5037 gen_op_mov_reg_v(MO_32
, R_EAX
, cpu_T
[0]);
5040 gen_op_mov_v_reg(MO_8
, cpu_T
[0], R_EAX
);
5041 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5042 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
5048 case 0x99: /* CDQ/CWD */
5050 #ifdef TARGET_X86_64
5052 gen_op_mov_v_reg(MO_64
, cpu_T
[0], R_EAX
);
5053 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5054 gen_op_mov_reg_v(MO_64
, R_EDX
, cpu_T
[0]);
5058 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
5059 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5060 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5061 gen_op_mov_reg_v(MO_32
, R_EDX
, cpu_T
[0]);
5064 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EAX
);
5065 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5066 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5067 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
5073 case 0x1af: /* imul Gv, Ev */
5074 case 0x69: /* imul Gv, Ev, I */
5077 modrm
= cpu_ldub_code(env
, s
->pc
++);
5078 reg
= ((modrm
>> 3) & 7) | rex_r
;
5080 s
->rip_offset
= insn_const_size(ot
);
5083 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5085 val
= insn_get(env
, s
, ot
);
5086 tcg_gen_movi_tl(cpu_T
[1], val
);
5087 } else if (b
== 0x6b) {
5088 val
= (int8_t)insn_get(env
, s
, MO_8
);
5089 tcg_gen_movi_tl(cpu_T
[1], val
);
5091 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5094 #ifdef TARGET_X86_64
5096 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5097 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5098 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5099 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5103 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5104 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5105 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5106 cpu_tmp2_i32
, cpu_tmp3_i32
);
5107 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5108 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5109 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5110 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5111 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5114 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5115 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5116 /* XXX: use 32 bit mul which could be faster */
5117 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5118 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5119 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5120 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5121 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5124 set_cc_op(s
, CC_OP_MULB
+ ot
);
5127 case 0x1c1: /* xadd Ev, Gv */
5128 ot
= mo_b_d(b
, dflag
);
5129 modrm
= cpu_ldub_code(env
, s
->pc
++);
5130 reg
= ((modrm
>> 3) & 7) | rex_r
;
5131 mod
= (modrm
>> 6) & 3;
5133 rm
= (modrm
& 7) | REX_B(s
);
5134 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5135 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
5136 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5137 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5138 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5140 gen_lea_modrm(env
, s
, modrm
);
5141 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5142 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5143 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5144 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5145 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5147 gen_op_update2_cc();
5148 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5151 case 0x1b1: /* cmpxchg Ev, Gv */
5154 TCGv t0
, t1
, t2
, a0
;
5156 ot
= mo_b_d(b
, dflag
);
5157 modrm
= cpu_ldub_code(env
, s
->pc
++);
5158 reg
= ((modrm
>> 3) & 7) | rex_r
;
5159 mod
= (modrm
>> 6) & 3;
5160 t0
= tcg_temp_local_new();
5161 t1
= tcg_temp_local_new();
5162 t2
= tcg_temp_local_new();
5163 a0
= tcg_temp_local_new();
5164 gen_op_mov_v_reg(ot
, t1
, reg
);
5166 rm
= (modrm
& 7) | REX_B(s
);
5167 gen_op_mov_v_reg(ot
, t0
, rm
);
5169 gen_lea_modrm(env
, s
, modrm
);
5170 tcg_gen_mov_tl(a0
, cpu_A0
);
5171 gen_op_ld_v(s
, ot
, t0
, a0
);
5172 rm
= 0; /* avoid warning */
5174 label1
= gen_new_label();
5175 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5178 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5179 label2
= gen_new_label();
5181 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5183 gen_set_label(label1
);
5184 gen_op_mov_reg_v(ot
, rm
, t1
);
5186 /* perform no-op store cycle like physical cpu; must be
5187 before changing accumulator to ensure idempotency if
5188 the store faults and the instruction is restarted */
5189 gen_op_st_v(s
, ot
, t0
, a0
);
5190 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5192 gen_set_label(label1
);
5193 gen_op_st_v(s
, ot
, t1
, a0
);
5195 gen_set_label(label2
);
5196 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5197 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5198 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5199 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5206 case 0x1c7: /* cmpxchg8b */
5207 modrm
= cpu_ldub_code(env
, s
->pc
++);
5208 mod
= (modrm
>> 6) & 3;
5209 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5211 #ifdef TARGET_X86_64
5212 if (dflag
== MO_64
) {
5213 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5215 gen_jmp_im(pc_start
- s
->cs_base
);
5216 gen_update_cc_op(s
);
5217 gen_lea_modrm(env
, s
, modrm
);
5218 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5222 if (!(s
->cpuid_features
& CPUID_CX8
))
5224 gen_jmp_im(pc_start
- s
->cs_base
);
5225 gen_update_cc_op(s
);
5226 gen_lea_modrm(env
, s
, modrm
);
5227 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5229 set_cc_op(s
, CC_OP_EFLAGS
);
5232 /**************************/
5234 case 0x50 ... 0x57: /* push */
5235 gen_op_mov_v_reg(MO_32
, cpu_T
[0], (b
& 7) | REX_B(s
));
5236 gen_push_v(s
, cpu_T
[0]);
5238 case 0x58 ... 0x5f: /* pop */
5240 /* NOTE: order is important for pop %sp */
5241 gen_pop_update(s
, ot
);
5242 gen_op_mov_reg_v(ot
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5244 case 0x60: /* pusha */
5249 case 0x61: /* popa */
5254 case 0x68: /* push Iv */
5256 ot
= mo_pushpop(s
, dflag
);
5258 val
= insn_get(env
, s
, ot
);
5260 val
= (int8_t)insn_get(env
, s
, MO_8
);
5261 tcg_gen_movi_tl(cpu_T
[0], val
);
5262 gen_push_v(s
, cpu_T
[0]);
5264 case 0x8f: /* pop Ev */
5265 modrm
= cpu_ldub_code(env
, s
->pc
++);
5266 mod
= (modrm
>> 6) & 3;
5269 /* NOTE: order is important for pop %sp */
5270 gen_pop_update(s
, ot
);
5271 rm
= (modrm
& 7) | REX_B(s
);
5272 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5274 /* NOTE: order is important too for MMU exceptions */
5275 s
->popl_esp_hack
= 1 << ot
;
5276 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5277 s
->popl_esp_hack
= 0;
5278 gen_pop_update(s
, ot
);
5281 case 0xc8: /* enter */
5284 val
= cpu_lduw_code(env
, s
->pc
);
5286 level
= cpu_ldub_code(env
, s
->pc
++);
5287 gen_enter(s
, val
, level
);
5290 case 0xc9: /* leave */
5291 /* XXX: exception not precise (ESP is updated before potential exception) */
5293 gen_op_mov_v_reg(MO_64
, cpu_T
[0], R_EBP
);
5294 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[0]);
5295 } else if (s
->ss32
) {
5296 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
5297 gen_op_mov_reg_v(MO_32
, R_ESP
, cpu_T
[0]);
5299 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EBP
);
5300 gen_op_mov_reg_v(MO_16
, R_ESP
, cpu_T
[0]);
5303 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[0]);
5304 gen_pop_update(s
, ot
);
5306 case 0x06: /* push es */
5307 case 0x0e: /* push cs */
5308 case 0x16: /* push ss */
5309 case 0x1e: /* push ds */
5312 gen_op_movl_T0_seg(b
>> 3);
5313 gen_push_v(s
, cpu_T
[0]);
5315 case 0x1a0: /* push fs */
5316 case 0x1a8: /* push gs */
5317 gen_op_movl_T0_seg((b
>> 3) & 7);
5318 gen_push_v(s
, cpu_T
[0]);
5320 case 0x07: /* pop es */
5321 case 0x17: /* pop ss */
5322 case 0x1f: /* pop ds */
5327 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5328 gen_pop_update(s
, ot
);
5330 /* if reg == SS, inhibit interrupts/trace. */
5331 /* If several instructions disable interrupts, only the
5333 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5334 gen_helper_set_inhibit_irq(cpu_env
);
5338 gen_jmp_im(s
->pc
- s
->cs_base
);
5342 case 0x1a1: /* pop fs */
5343 case 0x1a9: /* pop gs */
5345 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5346 gen_pop_update(s
, ot
);
5348 gen_jmp_im(s
->pc
- s
->cs_base
);
5353 /**************************/
5356 case 0x89: /* mov Gv, Ev */
5357 ot
= mo_b_d(b
, dflag
);
5358 modrm
= cpu_ldub_code(env
, s
->pc
++);
5359 reg
= ((modrm
>> 3) & 7) | rex_r
;
5361 /* generate a generic store */
5362 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5365 case 0xc7: /* mov Ev, Iv */
5366 ot
= mo_b_d(b
, dflag
);
5367 modrm
= cpu_ldub_code(env
, s
->pc
++);
5368 mod
= (modrm
>> 6) & 3;
5370 s
->rip_offset
= insn_const_size(ot
);
5371 gen_lea_modrm(env
, s
, modrm
);
5373 val
= insn_get(env
, s
, ot
);
5374 tcg_gen_movi_tl(cpu_T
[0], val
);
5376 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5378 gen_op_mov_reg_v(ot
, (modrm
& 7) | REX_B(s
), cpu_T
[0]);
5382 case 0x8b: /* mov Ev, Gv */
5383 ot
= mo_b_d(b
, dflag
);
5384 modrm
= cpu_ldub_code(env
, s
->pc
++);
5385 reg
= ((modrm
>> 3) & 7) | rex_r
;
5387 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5388 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5390 case 0x8e: /* mov seg, Gv */
5391 modrm
= cpu_ldub_code(env
, s
->pc
++);
5392 reg
= (modrm
>> 3) & 7;
5393 if (reg
>= 6 || reg
== R_CS
)
5395 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5396 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5398 /* if reg == SS, inhibit interrupts/trace */
5399 /* If several instructions disable interrupts, only the
5401 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5402 gen_helper_set_inhibit_irq(cpu_env
);
5406 gen_jmp_im(s
->pc
- s
->cs_base
);
5410 case 0x8c: /* mov Gv, seg */
5411 modrm
= cpu_ldub_code(env
, s
->pc
++);
5412 reg
= (modrm
>> 3) & 7;
5413 mod
= (modrm
>> 6) & 3;
5416 gen_op_movl_T0_seg(reg
);
5417 ot
= mod
== 3 ? dflag
: MO_16
;
5418 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5421 case 0x1b6: /* movzbS Gv, Eb */
5422 case 0x1b7: /* movzwS Gv, Eb */
5423 case 0x1be: /* movsbS Gv, Eb */
5424 case 0x1bf: /* movswS Gv, Eb */
5429 /* d_ot is the size of destination */
5431 /* ot is the size of source */
5432 ot
= (b
& 1) + MO_8
;
5433 /* s_ot is the sign+size of source */
5434 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5436 modrm
= cpu_ldub_code(env
, s
->pc
++);
5437 reg
= ((modrm
>> 3) & 7) | rex_r
;
5438 mod
= (modrm
>> 6) & 3;
5439 rm
= (modrm
& 7) | REX_B(s
);
5442 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
5445 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5448 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5451 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5455 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5458 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5460 gen_lea_modrm(env
, s
, modrm
);
5461 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5462 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5467 case 0x8d: /* lea */
5469 modrm
= cpu_ldub_code(env
, s
->pc
++);
5470 mod
= (modrm
>> 6) & 3;
5473 reg
= ((modrm
>> 3) & 7) | rex_r
;
5474 /* we must ensure that no segment is added */
5478 gen_lea_modrm(env
, s
, modrm
);
5480 gen_op_mov_reg_v(ot
, reg
, cpu_A0
);
5483 case 0xa0: /* mov EAX, Ov */
5485 case 0xa2: /* mov Ov, EAX */
5488 target_ulong offset_addr
;
5490 ot
= mo_b_d(b
, dflag
);
5492 #ifdef TARGET_X86_64
5494 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5499 offset_addr
= insn_get(env
, s
, s
->aflag
);
5502 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5503 gen_add_A0_ds_seg(s
);
5505 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5506 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
5508 gen_op_mov_v_reg(ot
, cpu_T
[0], R_EAX
);
5509 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5513 case 0xd7: /* xlat */
5514 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EBX
]);
5515 tcg_gen_ext8u_tl(cpu_T
[0], cpu_regs
[R_EAX
]);
5516 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5517 gen_extu(s
->aflag
, cpu_A0
);
5518 gen_add_A0_ds_seg(s
);
5519 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5520 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
5522 case 0xb0 ... 0xb7: /* mov R, Ib */
5523 val
= insn_get(env
, s
, MO_8
);
5524 tcg_gen_movi_tl(cpu_T
[0], val
);
5525 gen_op_mov_reg_v(MO_8
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5527 case 0xb8 ... 0xbf: /* mov R, Iv */
5528 #ifdef TARGET_X86_64
5529 if (dflag
== MO_64
) {
5532 tmp
= cpu_ldq_code(env
, s
->pc
);
5534 reg
= (b
& 7) | REX_B(s
);
5535 tcg_gen_movi_tl(cpu_T
[0], tmp
);
5536 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
5541 val
= insn_get(env
, s
, ot
);
5542 reg
= (b
& 7) | REX_B(s
);
5543 tcg_gen_movi_tl(cpu_T
[0], val
);
5544 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5548 case 0x91 ... 0x97: /* xchg R, EAX */
5551 reg
= (b
& 7) | REX_B(s
);
5555 case 0x87: /* xchg Ev, Gv */
5556 ot
= mo_b_d(b
, dflag
);
5557 modrm
= cpu_ldub_code(env
, s
->pc
++);
5558 reg
= ((modrm
>> 3) & 7) | rex_r
;
5559 mod
= (modrm
>> 6) & 3;
5561 rm
= (modrm
& 7) | REX_B(s
);
5563 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5564 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
5565 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5566 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5568 gen_lea_modrm(env
, s
, modrm
);
5569 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5570 /* for xchg, lock is implicit */
5571 if (!(prefixes
& PREFIX_LOCK
))
5573 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5574 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5575 if (!(prefixes
& PREFIX_LOCK
))
5576 gen_helper_unlock();
5577 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5580 case 0xc4: /* les Gv */
5581 /* In CODE64 this is VEX3; see above. */
5584 case 0xc5: /* lds Gv */
5585 /* In CODE64 this is VEX2; see above. */
5588 case 0x1b2: /* lss Gv */
5591 case 0x1b4: /* lfs Gv */
5594 case 0x1b5: /* lgs Gv */
5597 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
5598 modrm
= cpu_ldub_code(env
, s
->pc
++);
5599 reg
= ((modrm
>> 3) & 7) | rex_r
;
5600 mod
= (modrm
>> 6) & 3;
5603 gen_lea_modrm(env
, s
, modrm
);
5604 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5605 gen_add_A0_im(s
, 1 << ot
);
5606 /* load the segment first to handle exceptions properly */
5607 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5608 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5609 /* then put the data */
5610 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5612 gen_jmp_im(s
->pc
- s
->cs_base
);
5617 /************************/
5625 ot
= mo_b_d(b
, dflag
);
5626 modrm
= cpu_ldub_code(env
, s
->pc
++);
5627 mod
= (modrm
>> 6) & 3;
5628 op
= (modrm
>> 3) & 7;
5634 gen_lea_modrm(env
, s
, modrm
);
5637 opreg
= (modrm
& 7) | REX_B(s
);
5642 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5645 shift
= cpu_ldub_code(env
, s
->pc
++);
5647 gen_shifti(s
, op
, ot
, opreg
, shift
);
5662 case 0x1a4: /* shld imm */
5666 case 0x1a5: /* shld cl */
5670 case 0x1ac: /* shrd imm */
5674 case 0x1ad: /* shrd cl */
5679 modrm
= cpu_ldub_code(env
, s
->pc
++);
5680 mod
= (modrm
>> 6) & 3;
5681 rm
= (modrm
& 7) | REX_B(s
);
5682 reg
= ((modrm
>> 3) & 7) | rex_r
;
5684 gen_lea_modrm(env
, s
, modrm
);
5689 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5692 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5693 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5696 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5700 /************************/
5703 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5704 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5705 /* XXX: what to do if illegal op ? */
5706 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5709 modrm
= cpu_ldub_code(env
, s
->pc
++);
5710 mod
= (modrm
>> 6) & 3;
5712 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5715 gen_lea_modrm(env
, s
, modrm
);
5717 case 0x00 ... 0x07: /* fxxxs */
5718 case 0x10 ... 0x17: /* fixxxl */
5719 case 0x20 ... 0x27: /* fxxxl */
5720 case 0x30 ... 0x37: /* fixxx */
5727 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5728 s
->mem_index
, MO_LEUL
);
5729 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5732 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5733 s
->mem_index
, MO_LEUL
);
5734 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5737 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5738 s
->mem_index
, MO_LEQ
);
5739 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5743 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5744 s
->mem_index
, MO_LESW
);
5745 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5749 gen_helper_fp_arith_ST0_FT0(op1
);
5751 /* fcomp needs pop */
5752 gen_helper_fpop(cpu_env
);
5756 case 0x08: /* flds */
5757 case 0x0a: /* fsts */
5758 case 0x0b: /* fstps */
5759 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5760 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5761 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5766 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5767 s
->mem_index
, MO_LEUL
);
5768 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5771 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5772 s
->mem_index
, MO_LEUL
);
5773 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5776 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5777 s
->mem_index
, MO_LEQ
);
5778 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5782 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5783 s
->mem_index
, MO_LESW
);
5784 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5789 /* XXX: the corresponding CPUID bit must be tested ! */
5792 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5793 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5794 s
->mem_index
, MO_LEUL
);
5797 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5798 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5799 s
->mem_index
, MO_LEQ
);
5803 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5804 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5805 s
->mem_index
, MO_LEUW
);
5808 gen_helper_fpop(cpu_env
);
5813 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5814 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5815 s
->mem_index
, MO_LEUL
);
5818 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5819 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5820 s
->mem_index
, MO_LEUL
);
5823 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5824 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5825 s
->mem_index
, MO_LEQ
);
5829 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5830 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5831 s
->mem_index
, MO_LEUW
);
5835 gen_helper_fpop(cpu_env
);
5839 case 0x0c: /* fldenv mem */
5840 gen_update_cc_op(s
);
5841 gen_jmp_im(pc_start
- s
->cs_base
);
5842 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5844 case 0x0d: /* fldcw mem */
5845 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5846 s
->mem_index
, MO_LEUW
);
5847 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5849 case 0x0e: /* fnstenv mem */
5850 gen_update_cc_op(s
);
5851 gen_jmp_im(pc_start
- s
->cs_base
);
5852 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5854 case 0x0f: /* fnstcw mem */
5855 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5856 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5857 s
->mem_index
, MO_LEUW
);
5859 case 0x1d: /* fldt mem */
5860 gen_update_cc_op(s
);
5861 gen_jmp_im(pc_start
- s
->cs_base
);
5862 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5864 case 0x1f: /* fstpt mem */
5865 gen_update_cc_op(s
);
5866 gen_jmp_im(pc_start
- s
->cs_base
);
5867 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5868 gen_helper_fpop(cpu_env
);
5870 case 0x2c: /* frstor mem */
5871 gen_update_cc_op(s
);
5872 gen_jmp_im(pc_start
- s
->cs_base
);
5873 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5875 case 0x2e: /* fnsave mem */
5876 gen_update_cc_op(s
);
5877 gen_jmp_im(pc_start
- s
->cs_base
);
5878 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5880 case 0x2f: /* fnstsw mem */
5881 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5882 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5883 s
->mem_index
, MO_LEUW
);
5885 case 0x3c: /* fbld */
5886 gen_update_cc_op(s
);
5887 gen_jmp_im(pc_start
- s
->cs_base
);
5888 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5890 case 0x3e: /* fbstp */
5891 gen_update_cc_op(s
);
5892 gen_jmp_im(pc_start
- s
->cs_base
);
5893 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5894 gen_helper_fpop(cpu_env
);
5896 case 0x3d: /* fildll */
5897 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5898 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5900 case 0x3f: /* fistpll */
5901 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5902 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5903 gen_helper_fpop(cpu_env
);
5909 /* register float ops */
5913 case 0x08: /* fld sti */
5914 gen_helper_fpush(cpu_env
);
5915 gen_helper_fmov_ST0_STN(cpu_env
,
5916 tcg_const_i32((opreg
+ 1) & 7));
5918 case 0x09: /* fxchg sti */
5919 case 0x29: /* fxchg4 sti, undocumented op */
5920 case 0x39: /* fxchg7 sti, undocumented op */
5921 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5923 case 0x0a: /* grp d9/2 */
5926 /* check exceptions (FreeBSD FPU probe) */
5927 gen_update_cc_op(s
);
5928 gen_jmp_im(pc_start
- s
->cs_base
);
5929 gen_helper_fwait(cpu_env
);
5935 case 0x0c: /* grp d9/4 */
5938 gen_helper_fchs_ST0(cpu_env
);
5941 gen_helper_fabs_ST0(cpu_env
);
5944 gen_helper_fldz_FT0(cpu_env
);
5945 gen_helper_fcom_ST0_FT0(cpu_env
);
5948 gen_helper_fxam_ST0(cpu_env
);
5954 case 0x0d: /* grp d9/5 */
5958 gen_helper_fpush(cpu_env
);
5959 gen_helper_fld1_ST0(cpu_env
);
5962 gen_helper_fpush(cpu_env
);
5963 gen_helper_fldl2t_ST0(cpu_env
);
5966 gen_helper_fpush(cpu_env
);
5967 gen_helper_fldl2e_ST0(cpu_env
);
5970 gen_helper_fpush(cpu_env
);
5971 gen_helper_fldpi_ST0(cpu_env
);
5974 gen_helper_fpush(cpu_env
);
5975 gen_helper_fldlg2_ST0(cpu_env
);
5978 gen_helper_fpush(cpu_env
);
5979 gen_helper_fldln2_ST0(cpu_env
);
5982 gen_helper_fpush(cpu_env
);
5983 gen_helper_fldz_ST0(cpu_env
);
5990 case 0x0e: /* grp d9/6 */
5993 gen_helper_f2xm1(cpu_env
);
5996 gen_helper_fyl2x(cpu_env
);
5999 gen_helper_fptan(cpu_env
);
6001 case 3: /* fpatan */
6002 gen_helper_fpatan(cpu_env
);
6004 case 4: /* fxtract */
6005 gen_helper_fxtract(cpu_env
);
6007 case 5: /* fprem1 */
6008 gen_helper_fprem1(cpu_env
);
6010 case 6: /* fdecstp */
6011 gen_helper_fdecstp(cpu_env
);
6014 case 7: /* fincstp */
6015 gen_helper_fincstp(cpu_env
);
6019 case 0x0f: /* grp d9/7 */
6022 gen_helper_fprem(cpu_env
);
6024 case 1: /* fyl2xp1 */
6025 gen_helper_fyl2xp1(cpu_env
);
6028 gen_helper_fsqrt(cpu_env
);
6030 case 3: /* fsincos */
6031 gen_helper_fsincos(cpu_env
);
6033 case 5: /* fscale */
6034 gen_helper_fscale(cpu_env
);
6036 case 4: /* frndint */
6037 gen_helper_frndint(cpu_env
);
6040 gen_helper_fsin(cpu_env
);
6044 gen_helper_fcos(cpu_env
);
6048 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6049 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6050 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6056 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6058 gen_helper_fpop(cpu_env
);
6060 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6061 gen_helper_fp_arith_ST0_FT0(op1
);
6065 case 0x02: /* fcom */
6066 case 0x22: /* fcom2, undocumented op */
6067 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6068 gen_helper_fcom_ST0_FT0(cpu_env
);
6070 case 0x03: /* fcomp */
6071 case 0x23: /* fcomp3, undocumented op */
6072 case 0x32: /* fcomp5, undocumented op */
6073 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6074 gen_helper_fcom_ST0_FT0(cpu_env
);
6075 gen_helper_fpop(cpu_env
);
6077 case 0x15: /* da/5 */
6079 case 1: /* fucompp */
6080 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6081 gen_helper_fucom_ST0_FT0(cpu_env
);
6082 gen_helper_fpop(cpu_env
);
6083 gen_helper_fpop(cpu_env
);
6091 case 0: /* feni (287 only, just do nop here) */
6093 case 1: /* fdisi (287 only, just do nop here) */
6096 gen_helper_fclex(cpu_env
);
6098 case 3: /* fninit */
6099 gen_helper_fninit(cpu_env
);
6101 case 4: /* fsetpm (287 only, just do nop here) */
6107 case 0x1d: /* fucomi */
6108 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6111 gen_update_cc_op(s
);
6112 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6113 gen_helper_fucomi_ST0_FT0(cpu_env
);
6114 set_cc_op(s
, CC_OP_EFLAGS
);
6116 case 0x1e: /* fcomi */
6117 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6120 gen_update_cc_op(s
);
6121 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6122 gen_helper_fcomi_ST0_FT0(cpu_env
);
6123 set_cc_op(s
, CC_OP_EFLAGS
);
6125 case 0x28: /* ffree sti */
6126 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6128 case 0x2a: /* fst sti */
6129 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6131 case 0x2b: /* fstp sti */
6132 case 0x0b: /* fstp1 sti, undocumented op */
6133 case 0x3a: /* fstp8 sti, undocumented op */
6134 case 0x3b: /* fstp9 sti, undocumented op */
6135 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6136 gen_helper_fpop(cpu_env
);
6138 case 0x2c: /* fucom st(i) */
6139 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6140 gen_helper_fucom_ST0_FT0(cpu_env
);
6142 case 0x2d: /* fucomp st(i) */
6143 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6144 gen_helper_fucom_ST0_FT0(cpu_env
);
6145 gen_helper_fpop(cpu_env
);
6147 case 0x33: /* de/3 */
6149 case 1: /* fcompp */
6150 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6151 gen_helper_fcom_ST0_FT0(cpu_env
);
6152 gen_helper_fpop(cpu_env
);
6153 gen_helper_fpop(cpu_env
);
6159 case 0x38: /* ffreep sti, undocumented op */
6160 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6161 gen_helper_fpop(cpu_env
);
6163 case 0x3c: /* df/4 */
6166 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6167 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6168 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
6174 case 0x3d: /* fucomip */
6175 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6178 gen_update_cc_op(s
);
6179 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6180 gen_helper_fucomi_ST0_FT0(cpu_env
);
6181 gen_helper_fpop(cpu_env
);
6182 set_cc_op(s
, CC_OP_EFLAGS
);
6184 case 0x3e: /* fcomip */
6185 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6188 gen_update_cc_op(s
);
6189 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6190 gen_helper_fcomi_ST0_FT0(cpu_env
);
6191 gen_helper_fpop(cpu_env
);
6192 set_cc_op(s
, CC_OP_EFLAGS
);
6194 case 0x10 ... 0x13: /* fcmovxx */
6198 static const uint8_t fcmov_cc
[8] = {
6205 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6208 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6209 l1
= gen_new_label();
6210 gen_jcc1_noeob(s
, op1
, l1
);
6211 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6220 /************************/
6223 case 0xa4: /* movsS */
6225 ot
= mo_b_d(b
, dflag
);
6226 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6227 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6233 case 0xaa: /* stosS */
6235 ot
= mo_b_d(b
, dflag
);
6236 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6237 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6242 case 0xac: /* lodsS */
6244 ot
= mo_b_d(b
, dflag
);
6245 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6246 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6251 case 0xae: /* scasS */
6253 ot
= mo_b_d(b
, dflag
);
6254 if (prefixes
& PREFIX_REPNZ
) {
6255 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6256 } else if (prefixes
& PREFIX_REPZ
) {
6257 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6263 case 0xa6: /* cmpsS */
6265 ot
= mo_b_d(b
, dflag
);
6266 if (prefixes
& PREFIX_REPNZ
) {
6267 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6268 } else if (prefixes
& PREFIX_REPZ
) {
6269 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6274 case 0x6c: /* insS */
6276 ot
= mo_b_d32(b
, dflag
);
6277 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6278 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6279 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6280 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6281 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6285 gen_jmp(s
, s
->pc
- s
->cs_base
);
6289 case 0x6e: /* outsS */
6291 ot
= mo_b_d32(b
, dflag
);
6292 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6293 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6294 svm_is_rep(prefixes
) | 4);
6295 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6296 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6300 gen_jmp(s
, s
->pc
- s
->cs_base
);
6305 /************************/
6310 ot
= mo_b_d32(b
, dflag
);
6311 val
= cpu_ldub_code(env
, s
->pc
++);
6312 tcg_gen_movi_tl(cpu_T
[0], val
);
6313 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6314 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6317 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6318 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6319 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6322 gen_jmp(s
, s
->pc
- s
->cs_base
);
6327 ot
= mo_b_d32(b
, dflag
);
6328 val
= cpu_ldub_code(env
, s
->pc
++);
6329 tcg_gen_movi_tl(cpu_T
[0], val
);
6330 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6331 svm_is_rep(prefixes
));
6332 gen_op_mov_v_reg(ot
, cpu_T
[1], R_EAX
);
6336 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6337 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6338 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6341 gen_jmp(s
, s
->pc
- s
->cs_base
);
6346 ot
= mo_b_d32(b
, dflag
);
6347 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6348 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6349 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6352 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6353 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6354 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6357 gen_jmp(s
, s
->pc
- s
->cs_base
);
6362 ot
= mo_b_d32(b
, dflag
);
6363 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6364 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6365 svm_is_rep(prefixes
));
6366 gen_op_mov_v_reg(ot
, cpu_T
[1], R_EAX
);
6370 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6371 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6372 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6375 gen_jmp(s
, s
->pc
- s
->cs_base
);
6379 /************************/
6381 case 0xc2: /* ret im */
6382 val
= cpu_ldsw_code(env
, s
->pc
);
6385 gen_stack_update(s
, val
+ (1 << ot
));
6386 /* Note that gen_pop_T0 uses a zero-extending load. */
6387 gen_op_jmp_v(cpu_T
[0]);
6390 case 0xc3: /* ret */
6392 gen_pop_update(s
, ot
);
6393 /* Note that gen_pop_T0 uses a zero-extending load. */
6394 gen_op_jmp_v(cpu_T
[0]);
6397 case 0xca: /* lret im */
6398 val
= cpu_ldsw_code(env
, s
->pc
);
6401 if (s
->pe
&& !s
->vm86
) {
6402 gen_update_cc_op(s
);
6403 gen_jmp_im(pc_start
- s
->cs_base
);
6404 gen_helper_lret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6405 tcg_const_i32(val
));
6409 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6410 /* NOTE: keeping EIP updated is not a problem in case of
6412 gen_op_jmp_v(cpu_T
[0]);
6414 gen_op_addl_A0_im(1 << dflag
);
6415 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6416 gen_op_movl_seg_T0_vm(R_CS
);
6417 /* add stack offset */
6418 gen_stack_update(s
, val
+ (2 << dflag
));
6422 case 0xcb: /* lret */
6425 case 0xcf: /* iret */
6426 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6429 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6430 set_cc_op(s
, CC_OP_EFLAGS
);
6431 } else if (s
->vm86
) {
6433 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6435 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6436 set_cc_op(s
, CC_OP_EFLAGS
);
6439 gen_update_cc_op(s
);
6440 gen_jmp_im(pc_start
- s
->cs_base
);
6441 gen_helper_iret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6442 tcg_const_i32(s
->pc
- s
->cs_base
));
6443 set_cc_op(s
, CC_OP_EFLAGS
);
6447 case 0xe8: /* call im */
6449 if (dflag
!= MO_16
) {
6450 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6452 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6454 next_eip
= s
->pc
- s
->cs_base
;
6456 if (dflag
== MO_16
) {
6458 } else if (!CODE64(s
)) {
6461 tcg_gen_movi_tl(cpu_T
[0], next_eip
);
6462 gen_push_v(s
, cpu_T
[0]);
6466 case 0x9a: /* lcall im */
6468 unsigned int selector
, offset
;
6473 offset
= insn_get(env
, s
, ot
);
6474 selector
= insn_get(env
, s
, MO_16
);
6476 tcg_gen_movi_tl(cpu_T
[0], selector
);
6477 tcg_gen_movi_tl(cpu_T
[1], offset
);
6480 case 0xe9: /* jmp im */
6481 if (dflag
!= MO_16
) {
6482 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6484 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6486 tval
+= s
->pc
- s
->cs_base
;
6487 if (dflag
== MO_16
) {
6489 } else if (!CODE64(s
)) {
6494 case 0xea: /* ljmp im */
6496 unsigned int selector
, offset
;
6501 offset
= insn_get(env
, s
, ot
);
6502 selector
= insn_get(env
, s
, MO_16
);
6504 tcg_gen_movi_tl(cpu_T
[0], selector
);
6505 tcg_gen_movi_tl(cpu_T
[1], offset
);
6508 case 0xeb: /* jmp Jb */
6509 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6510 tval
+= s
->pc
- s
->cs_base
;
6511 if (dflag
== MO_16
) {
6516 case 0x70 ... 0x7f: /* jcc Jb */
6517 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6519 case 0x180 ... 0x18f: /* jcc Jv */
6520 if (dflag
!= MO_16
) {
6521 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6523 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6526 next_eip
= s
->pc
- s
->cs_base
;
6528 if (dflag
== MO_16
) {
6531 gen_jcc(s
, b
, tval
, next_eip
);
6534 case 0x190 ... 0x19f: /* setcc Gv */
6535 modrm
= cpu_ldub_code(env
, s
->pc
++);
6536 gen_setcc1(s
, b
, cpu_T
[0]);
6537 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6539 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6540 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6544 modrm
= cpu_ldub_code(env
, s
->pc
++);
6545 reg
= ((modrm
>> 3) & 7) | rex_r
;
6546 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6549 /************************/
6551 case 0x9c: /* pushf */
6552 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6553 if (s
->vm86
&& s
->iopl
!= 3) {
6554 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6556 gen_update_cc_op(s
);
6557 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6558 gen_push_v(s
, cpu_T
[0]);
6561 case 0x9d: /* popf */
6562 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6563 if (s
->vm86
&& s
->iopl
!= 3) {
6564 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6568 if (dflag
!= MO_16
) {
6569 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6570 tcg_const_i32((TF_MASK
| AC_MASK
|
6575 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6576 tcg_const_i32((TF_MASK
| AC_MASK
|
6578 IF_MASK
| IOPL_MASK
)
6582 if (s
->cpl
<= s
->iopl
) {
6583 if (dflag
!= MO_16
) {
6584 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6585 tcg_const_i32((TF_MASK
|
6591 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6592 tcg_const_i32((TF_MASK
|
6600 if (dflag
!= MO_16
) {
6601 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6602 tcg_const_i32((TF_MASK
| AC_MASK
|
6603 ID_MASK
| NT_MASK
)));
6605 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6606 tcg_const_i32((TF_MASK
| AC_MASK
|
6612 gen_pop_update(s
, ot
);
6613 set_cc_op(s
, CC_OP_EFLAGS
);
6614 /* abort translation because TF/AC flag may change */
6615 gen_jmp_im(s
->pc
- s
->cs_base
);
6619 case 0x9e: /* sahf */
6620 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6622 gen_op_mov_v_reg(MO_8
, cpu_T
[0], R_AH
);
6623 gen_compute_eflags(s
);
6624 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6625 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6626 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6628 case 0x9f: /* lahf */
6629 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6631 gen_compute_eflags(s
);
6632 /* Note: gen_compute_eflags() only gives the condition codes */
6633 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6634 gen_op_mov_reg_v(MO_8
, R_AH
, cpu_T
[0]);
6636 case 0xf5: /* cmc */
6637 gen_compute_eflags(s
);
6638 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6640 case 0xf8: /* clc */
6641 gen_compute_eflags(s
);
6642 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6644 case 0xf9: /* stc */
6645 gen_compute_eflags(s
);
6646 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6648 case 0xfc: /* cld */
6649 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6650 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6652 case 0xfd: /* std */
6653 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6654 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6657 /************************/
6658 /* bit operations */
6659 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6661 modrm
= cpu_ldub_code(env
, s
->pc
++);
6662 op
= (modrm
>> 3) & 7;
6663 mod
= (modrm
>> 6) & 3;
6664 rm
= (modrm
& 7) | REX_B(s
);
6667 gen_lea_modrm(env
, s
, modrm
);
6668 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6670 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
6673 val
= cpu_ldub_code(env
, s
->pc
++);
6674 tcg_gen_movi_tl(cpu_T
[1], val
);
6679 case 0x1a3: /* bt Gv, Ev */
6682 case 0x1ab: /* bts */
6685 case 0x1b3: /* btr */
6688 case 0x1bb: /* btc */
6692 modrm
= cpu_ldub_code(env
, s
->pc
++);
6693 reg
= ((modrm
>> 3) & 7) | rex_r
;
6694 mod
= (modrm
>> 6) & 3;
6695 rm
= (modrm
& 7) | REX_B(s
);
6696 gen_op_mov_v_reg(MO_32
, cpu_T
[1], reg
);
6698 gen_lea_modrm(env
, s
, modrm
);
6699 /* specific case: we need to add a displacement */
6700 gen_exts(ot
, cpu_T
[1]);
6701 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6702 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6703 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6704 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6706 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
6709 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6710 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6715 tcg_gen_movi_tl(cpu_tmp0
, 1);
6716 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6717 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6720 tcg_gen_movi_tl(cpu_tmp0
, 1);
6721 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6722 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6726 tcg_gen_movi_tl(cpu_tmp0
, 1);
6727 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6728 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6733 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6735 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
6739 /* Delay all CC updates until after the store above. Note that
6740 C is the result of the test, Z is unchanged, and the others
6741 are all undefined. */
6743 case CC_OP_MULB
... CC_OP_MULQ
:
6744 case CC_OP_ADDB
... CC_OP_ADDQ
:
6745 case CC_OP_ADCB
... CC_OP_ADCQ
:
6746 case CC_OP_SUBB
... CC_OP_SUBQ
:
6747 case CC_OP_SBBB
... CC_OP_SBBQ
:
6748 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
6749 case CC_OP_INCB
... CC_OP_INCQ
:
6750 case CC_OP_DECB
... CC_OP_DECQ
:
6751 case CC_OP_SHLB
... CC_OP_SHLQ
:
6752 case CC_OP_SARB
... CC_OP_SARQ
:
6753 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
6754 /* Z was going to be computed from the non-zero status of CC_DST.
6755 We can get that same Z value (and the new C value) by leaving
6756 CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
6758 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6759 set_cc_op(s
, ((s
->cc_op
- CC_OP_MULB
) & 3) + CC_OP_SARB
);
6762 /* Otherwise, generate EFLAGS and replace the C bit. */
6763 gen_compute_eflags(s
);
6764 tcg_gen_deposit_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp4
,
6769 case 0x1bc: /* bsf / tzcnt */
6770 case 0x1bd: /* bsr / lzcnt */
6772 modrm
= cpu_ldub_code(env
, s
->pc
++);
6773 reg
= ((modrm
>> 3) & 7) | rex_r
;
6774 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6775 gen_extu(ot
, cpu_T
[0]);
6777 /* Note that lzcnt and tzcnt are in different extensions. */
6778 if ((prefixes
& PREFIX_REPZ
)
6780 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6781 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6783 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6785 /* For lzcnt, reduce the target_ulong result by the
6786 number of zeros that we expect to find at the top. */
6787 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6788 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6790 /* For tzcnt, a zero input must return the operand size:
6791 force all bits outside the operand size to 1. */
6792 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6793 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6794 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6796 /* For lzcnt/tzcnt, C and Z bits are defined and are
6797 related to the result. */
6798 gen_op_update1_cc();
6799 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6801 /* For bsr/bsf, only the Z bit is defined and it is related
6802 to the input and not the result. */
6803 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6804 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6806 /* For bsr, return the bit index of the first 1 bit,
6807 not the count of leading zeros. */
6808 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6809 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6811 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6813 /* ??? The manual says that the output is undefined when the
6814 input is zero, but real hardware leaves it unchanged, and
6815 real programs appear to depend on that. */
6816 tcg_gen_movi_tl(cpu_tmp0
, 0);
6817 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6818 cpu_regs
[reg
], cpu_T
[0]);
6820 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
6822 /************************/
6824 case 0x27: /* daa */
6827 gen_update_cc_op(s
);
6828 gen_helper_daa(cpu_env
);
6829 set_cc_op(s
, CC_OP_EFLAGS
);
6831 case 0x2f: /* das */
6834 gen_update_cc_op(s
);
6835 gen_helper_das(cpu_env
);
6836 set_cc_op(s
, CC_OP_EFLAGS
);
6838 case 0x37: /* aaa */
6841 gen_update_cc_op(s
);
6842 gen_helper_aaa(cpu_env
);
6843 set_cc_op(s
, CC_OP_EFLAGS
);
6845 case 0x3f: /* aas */
6848 gen_update_cc_op(s
);
6849 gen_helper_aas(cpu_env
);
6850 set_cc_op(s
, CC_OP_EFLAGS
);
6852 case 0xd4: /* aam */
6855 val
= cpu_ldub_code(env
, s
->pc
++);
6857 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6859 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6860 set_cc_op(s
, CC_OP_LOGICB
);
6863 case 0xd5: /* aad */
6866 val
= cpu_ldub_code(env
, s
->pc
++);
6867 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6868 set_cc_op(s
, CC_OP_LOGICB
);
6870 /************************/
6872 case 0x90: /* nop */
6873 /* XXX: correct lock test for all insn */
6874 if (prefixes
& PREFIX_LOCK
) {
6877 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6879 goto do_xchg_reg_eax
;
6881 if (prefixes
& PREFIX_REPZ
) {
6882 gen_update_cc_op(s
);
6883 gen_jmp_im(pc_start
- s
->cs_base
);
6884 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6885 s
->is_jmp
= DISAS_TB_JUMP
;
6888 case 0x9b: /* fwait */
6889 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6890 (HF_MP_MASK
| HF_TS_MASK
)) {
6891 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6893 gen_update_cc_op(s
);
6894 gen_jmp_im(pc_start
- s
->cs_base
);
6895 gen_helper_fwait(cpu_env
);
6898 case 0xcc: /* int3 */
6899 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6901 case 0xcd: /* int N */
6902 val
= cpu_ldub_code(env
, s
->pc
++);
6903 if (s
->vm86
&& s
->iopl
!= 3) {
6904 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6906 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6909 case 0xce: /* into */
6912 gen_update_cc_op(s
);
6913 gen_jmp_im(pc_start
- s
->cs_base
);
6914 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6917 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6918 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6920 gen_debug(s
, pc_start
- s
->cs_base
);
6924 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6928 case 0xfa: /* cli */
6930 if (s
->cpl
<= s
->iopl
) {
6931 gen_helper_cli(cpu_env
);
6933 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6937 gen_helper_cli(cpu_env
);
6939 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6943 case 0xfb: /* sti */
6945 if (s
->cpl
<= s
->iopl
) {
6947 gen_helper_sti(cpu_env
);
6948 /* interruptions are enabled only the first insn after sti */
6949 /* If several instructions disable interrupts, only the
6951 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6952 gen_helper_set_inhibit_irq(cpu_env
);
6953 /* give a chance to handle pending irqs */
6954 gen_jmp_im(s
->pc
- s
->cs_base
);
6957 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6963 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6967 case 0x62: /* bound */
6971 modrm
= cpu_ldub_code(env
, s
->pc
++);
6972 reg
= (modrm
>> 3) & 7;
6973 mod
= (modrm
>> 6) & 3;
6976 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
6977 gen_lea_modrm(env
, s
, modrm
);
6978 gen_jmp_im(pc_start
- s
->cs_base
);
6979 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6981 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6983 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6986 case 0x1c8 ... 0x1cf: /* bswap reg */
6987 reg
= (b
& 7) | REX_B(s
);
6988 #ifdef TARGET_X86_64
6989 if (dflag
== MO_64
) {
6990 gen_op_mov_v_reg(MO_64
, cpu_T
[0], reg
);
6991 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6992 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
6996 gen_op_mov_v_reg(MO_32
, cpu_T
[0], reg
);
6997 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6998 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6999 gen_op_mov_reg_v(MO_32
, reg
, cpu_T
[0]);
7002 case 0xd6: /* salc */
7005 gen_compute_eflags_c(s
, cpu_T
[0]);
7006 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7007 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
7009 case 0xe0: /* loopnz */
7010 case 0xe1: /* loopz */
7011 case 0xe2: /* loop */
7012 case 0xe3: /* jecxz */
7016 tval
= (int8_t)insn_get(env
, s
, MO_8
);
7017 next_eip
= s
->pc
- s
->cs_base
;
7019 if (dflag
== MO_16
) {
7023 l1
= gen_new_label();
7024 l2
= gen_new_label();
7025 l3
= gen_new_label();
7028 case 0: /* loopnz */
7030 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7031 gen_op_jz_ecx(s
->aflag
, l3
);
7032 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7035 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7036 gen_op_jnz_ecx(s
->aflag
, l1
);
7040 gen_op_jz_ecx(s
->aflag
, l1
);
7045 gen_jmp_im(next_eip
);
7054 case 0x130: /* wrmsr */
7055 case 0x132: /* rdmsr */
7057 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7059 gen_update_cc_op(s
);
7060 gen_jmp_im(pc_start
- s
->cs_base
);
7062 gen_helper_rdmsr(cpu_env
);
7064 gen_helper_wrmsr(cpu_env
);
7068 case 0x131: /* rdtsc */
7069 gen_update_cc_op(s
);
7070 gen_jmp_im(pc_start
- s
->cs_base
);
7073 gen_helper_rdtsc(cpu_env
);
7076 gen_jmp(s
, s
->pc
- s
->cs_base
);
7079 case 0x133: /* rdpmc */
7080 gen_update_cc_op(s
);
7081 gen_jmp_im(pc_start
- s
->cs_base
);
7082 gen_helper_rdpmc(cpu_env
);
7084 case 0x134: /* sysenter */
7085 /* For Intel SYSENTER is valid on 64-bit */
7086 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7089 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7091 gen_update_cc_op(s
);
7092 gen_jmp_im(pc_start
- s
->cs_base
);
7093 gen_helper_sysenter(cpu_env
);
7097 case 0x135: /* sysexit */
7098 /* For Intel SYSEXIT is valid on 64-bit */
7099 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7102 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7104 gen_update_cc_op(s
);
7105 gen_jmp_im(pc_start
- s
->cs_base
);
7106 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
- 1));
7110 #ifdef TARGET_X86_64
7111 case 0x105: /* syscall */
7112 /* XXX: is it usable in real mode ? */
7113 gen_update_cc_op(s
);
7114 gen_jmp_im(pc_start
- s
->cs_base
);
7115 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7118 case 0x107: /* sysret */
7120 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7122 gen_update_cc_op(s
);
7123 gen_jmp_im(pc_start
- s
->cs_base
);
7124 gen_helper_sysret(cpu_env
, tcg_const_i32(dflag
- 1));
7125 /* condition codes are modified only in long mode */
7127 set_cc_op(s
, CC_OP_EFLAGS
);
7133 case 0x1a2: /* cpuid */
7134 gen_update_cc_op(s
);
7135 gen_jmp_im(pc_start
- s
->cs_base
);
7136 gen_helper_cpuid(cpu_env
);
7138 case 0xf4: /* hlt */
7140 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7142 gen_update_cc_op(s
);
7143 gen_jmp_im(pc_start
- s
->cs_base
);
7144 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7145 s
->is_jmp
= DISAS_TB_JUMP
;
7149 modrm
= cpu_ldub_code(env
, s
->pc
++);
7150 mod
= (modrm
>> 6) & 3;
7151 op
= (modrm
>> 3) & 7;
7154 if (!s
->pe
|| s
->vm86
)
7156 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7157 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7158 ot
= mod
== 3 ? dflag
: MO_16
;
7159 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7162 if (!s
->pe
|| s
->vm86
)
7165 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7167 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7168 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7169 gen_jmp_im(pc_start
- s
->cs_base
);
7170 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7171 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7175 if (!s
->pe
|| s
->vm86
)
7177 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7178 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7179 ot
= mod
== 3 ? dflag
: MO_16
;
7180 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7183 if (!s
->pe
|| s
->vm86
)
7186 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7188 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7189 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7190 gen_jmp_im(pc_start
- s
->cs_base
);
7191 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7192 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7197 if (!s
->pe
|| s
->vm86
)
7199 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7200 gen_update_cc_op(s
);
7202 gen_helper_verr(cpu_env
, cpu_T
[0]);
7204 gen_helper_verw(cpu_env
, cpu_T
[0]);
7206 set_cc_op(s
, CC_OP_EFLAGS
);
7213 modrm
= cpu_ldub_code(env
, s
->pc
++);
7214 mod
= (modrm
>> 6) & 3;
7215 op
= (modrm
>> 3) & 7;
7221 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7222 gen_lea_modrm(env
, s
, modrm
);
7223 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7224 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7225 gen_add_A0_im(s
, 2);
7226 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7227 if (dflag
== MO_16
) {
7228 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7230 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7235 case 0: /* monitor */
7236 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7239 gen_update_cc_op(s
);
7240 gen_jmp_im(pc_start
- s
->cs_base
);
7241 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EAX
]);
7242 gen_extu(s
->aflag
, cpu_A0
);
7243 gen_add_A0_ds_seg(s
);
7244 gen_helper_monitor(cpu_env
, cpu_A0
);
7247 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7250 gen_update_cc_op(s
);
7251 gen_jmp_im(pc_start
- s
->cs_base
);
7252 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7256 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7260 gen_helper_clac(cpu_env
);
7261 gen_jmp_im(s
->pc
- s
->cs_base
);
7265 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7269 gen_helper_stac(cpu_env
);
7270 gen_jmp_im(s
->pc
- s
->cs_base
);
7277 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7278 gen_lea_modrm(env
, s
, modrm
);
7279 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7280 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7281 gen_add_A0_im(s
, 2);
7282 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7283 if (dflag
== MO_16
) {
7284 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7286 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7292 gen_update_cc_op(s
);
7293 gen_jmp_im(pc_start
- s
->cs_base
);
7296 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7299 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7302 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
- 1),
7303 tcg_const_i32(s
->pc
- pc_start
));
7305 s
->is_jmp
= DISAS_TB_JUMP
;
7308 case 1: /* VMMCALL */
7309 if (!(s
->flags
& HF_SVME_MASK
))
7311 gen_helper_vmmcall(cpu_env
);
7313 case 2: /* VMLOAD */
7314 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7317 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7320 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7323 case 3: /* VMSAVE */
7324 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7327 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7330 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7334 if ((!(s
->flags
& HF_SVME_MASK
) &&
7335 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7339 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7342 gen_helper_stgi(cpu_env
);
7346 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7349 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7352 gen_helper_clgi(cpu_env
);
7355 case 6: /* SKINIT */
7356 if ((!(s
->flags
& HF_SVME_MASK
) &&
7357 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7360 gen_helper_skinit(cpu_env
);
7362 case 7: /* INVLPGA */
7363 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7366 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7369 gen_helper_invlpga(cpu_env
,
7370 tcg_const_i32(s
->aflag
- 1));
7376 } else if (s
->cpl
!= 0) {
7377 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7379 gen_svm_check_intercept(s
, pc_start
,
7380 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7381 gen_lea_modrm(env
, s
, modrm
);
7382 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7383 gen_add_A0_im(s
, 2);
7384 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7385 if (dflag
== MO_16
) {
7386 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7389 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7390 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7392 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7393 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7398 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7399 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7400 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7402 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7404 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7408 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7410 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7411 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7412 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7413 gen_jmp_im(s
->pc
- s
->cs_base
);
7418 if (mod
!= 3) { /* invlpg */
7420 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7422 gen_update_cc_op(s
);
7423 gen_jmp_im(pc_start
- s
->cs_base
);
7424 gen_lea_modrm(env
, s
, modrm
);
7425 gen_helper_invlpg(cpu_env
, cpu_A0
);
7426 gen_jmp_im(s
->pc
- s
->cs_base
);
7431 case 0: /* swapgs */
7432 #ifdef TARGET_X86_64
7435 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7437 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7438 offsetof(CPUX86State
,segs
[R_GS
].base
));
7439 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7440 offsetof(CPUX86State
,kernelgsbase
));
7441 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7442 offsetof(CPUX86State
,segs
[R_GS
].base
));
7443 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7444 offsetof(CPUX86State
,kernelgsbase
));
7452 case 1: /* rdtscp */
7453 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7455 gen_update_cc_op(s
);
7456 gen_jmp_im(pc_start
- s
->cs_base
);
7459 gen_helper_rdtscp(cpu_env
);
7462 gen_jmp(s
, s
->pc
- s
->cs_base
);
7474 case 0x108: /* invd */
7475 case 0x109: /* wbinvd */
7477 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7479 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7483 case 0x63: /* arpl or movslS (x86_64) */
7484 #ifdef TARGET_X86_64
7487 /* d_ot is the size of destination */
7490 modrm
= cpu_ldub_code(env
, s
->pc
++);
7491 reg
= ((modrm
>> 3) & 7) | rex_r
;
7492 mod
= (modrm
>> 6) & 3;
7493 rm
= (modrm
& 7) | REX_B(s
);
7496 gen_op_mov_v_reg(MO_32
, cpu_T
[0], rm
);
7498 if (d_ot
== MO_64
) {
7499 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7501 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7503 gen_lea_modrm(env
, s
, modrm
);
7504 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7505 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7511 TCGv t0
, t1
, t2
, a0
;
7513 if (!s
->pe
|| s
->vm86
)
7515 t0
= tcg_temp_local_new();
7516 t1
= tcg_temp_local_new();
7517 t2
= tcg_temp_local_new();
7519 modrm
= cpu_ldub_code(env
, s
->pc
++);
7520 reg
= (modrm
>> 3) & 7;
7521 mod
= (modrm
>> 6) & 3;
7524 gen_lea_modrm(env
, s
, modrm
);
7525 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7526 a0
= tcg_temp_local_new();
7527 tcg_gen_mov_tl(a0
, cpu_A0
);
7529 gen_op_mov_v_reg(ot
, t0
, rm
);
7532 gen_op_mov_v_reg(ot
, t1
, reg
);
7533 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7534 tcg_gen_andi_tl(t1
, t1
, 3);
7535 tcg_gen_movi_tl(t2
, 0);
7536 label1
= gen_new_label();
7537 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7538 tcg_gen_andi_tl(t0
, t0
, ~3);
7539 tcg_gen_or_tl(t0
, t0
, t1
);
7540 tcg_gen_movi_tl(t2
, CC_Z
);
7541 gen_set_label(label1
);
7543 gen_op_st_v(s
, ot
, t0
, a0
);
7546 gen_op_mov_reg_v(ot
, rm
, t0
);
7548 gen_compute_eflags(s
);
7549 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7550 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7556 case 0x102: /* lar */
7557 case 0x103: /* lsl */
7561 if (!s
->pe
|| s
->vm86
)
7563 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
7564 modrm
= cpu_ldub_code(env
, s
->pc
++);
7565 reg
= ((modrm
>> 3) & 7) | rex_r
;
7566 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7567 t0
= tcg_temp_local_new();
7568 gen_update_cc_op(s
);
7570 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7572 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7574 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7575 label1
= gen_new_label();
7576 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7577 gen_op_mov_reg_v(ot
, reg
, t0
);
7578 gen_set_label(label1
);
7579 set_cc_op(s
, CC_OP_EFLAGS
);
7584 modrm
= cpu_ldub_code(env
, s
->pc
++);
7585 mod
= (modrm
>> 6) & 3;
7586 op
= (modrm
>> 3) & 7;
7588 case 0: /* prefetchnta */
7589 case 1: /* prefetchnt0 */
7590 case 2: /* prefetchnt0 */
7591 case 3: /* prefetchnt0 */
7594 gen_lea_modrm(env
, s
, modrm
);
7595 /* nothing more to do */
7597 default: /* nop (multi byte) */
7598 gen_nop_modrm(env
, s
, modrm
);
7602 case 0x119 ... 0x11f: /* nop (multi byte) */
7603 modrm
= cpu_ldub_code(env
, s
->pc
++);
7604 gen_nop_modrm(env
, s
, modrm
);
7606 case 0x120: /* mov reg, crN */
7607 case 0x122: /* mov crN, reg */
7609 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7611 modrm
= cpu_ldub_code(env
, s
->pc
++);
7612 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7613 * AMD documentation (24594.pdf) and testing of
7614 * intel 386 and 486 processors all show that the mod bits
7615 * are assumed to be 1's, regardless of actual values.
7617 rm
= (modrm
& 7) | REX_B(s
);
7618 reg
= ((modrm
>> 3) & 7) | rex_r
;
7623 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7624 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7633 gen_update_cc_op(s
);
7634 gen_jmp_im(pc_start
- s
->cs_base
);
7636 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
7637 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7639 gen_jmp_im(s
->pc
- s
->cs_base
);
7642 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7643 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7651 case 0x121: /* mov reg, drN */
7652 case 0x123: /* mov drN, reg */
7654 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7656 modrm
= cpu_ldub_code(env
, s
->pc
++);
7657 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7658 * AMD documentation (24594.pdf) and testing of
7659 * intel 386 and 486 processors all show that the mod bits
7660 * are assumed to be 1's, regardless of actual values.
7662 rm
= (modrm
& 7) | REX_B(s
);
7663 reg
= ((modrm
>> 3) & 7) | rex_r
;
7668 /* XXX: do it dynamically with CR4.DE bit */
7669 if (reg
== 4 || reg
== 5 || reg
>= 8)
7672 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7673 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
7674 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7675 gen_jmp_im(s
->pc
- s
->cs_base
);
7678 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7679 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7680 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7684 case 0x106: /* clts */
7686 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7688 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7689 gen_helper_clts(cpu_env
);
7690 /* abort block because static cpu state changed */
7691 gen_jmp_im(s
->pc
- s
->cs_base
);
7695 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7696 case 0x1c3: /* MOVNTI reg, mem */
7697 if (!(s
->cpuid_features
& CPUID_SSE2
))
7699 ot
= mo_64_32(dflag
);
7700 modrm
= cpu_ldub_code(env
, s
->pc
++);
7701 mod
= (modrm
>> 6) & 3;
7704 reg
= ((modrm
>> 3) & 7) | rex_r
;
7705 /* generate a generic store */
7706 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7709 modrm
= cpu_ldub_code(env
, s
->pc
++);
7710 mod
= (modrm
>> 6) & 3;
7711 op
= (modrm
>> 3) & 7;
7713 case 0: /* fxsave */
7714 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7715 (s
->prefix
& PREFIX_LOCK
))
7717 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7718 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7721 gen_lea_modrm(env
, s
, modrm
);
7722 gen_update_cc_op(s
);
7723 gen_jmp_im(pc_start
- s
->cs_base
);
7724 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7726 case 1: /* fxrstor */
7727 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7728 (s
->prefix
& PREFIX_LOCK
))
7730 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7731 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7734 gen_lea_modrm(env
, s
, modrm
);
7735 gen_update_cc_op(s
);
7736 gen_jmp_im(pc_start
- s
->cs_base
);
7737 gen_helper_fxrstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7739 case 2: /* ldmxcsr */
7740 case 3: /* stmxcsr */
7741 if (s
->flags
& HF_TS_MASK
) {
7742 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7745 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7748 gen_lea_modrm(env
, s
, modrm
);
7750 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7751 s
->mem_index
, MO_LEUL
);
7752 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7754 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7755 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7758 case 5: /* lfence */
7759 case 6: /* mfence */
7760 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7763 case 7: /* sfence / clflush */
7764 if ((modrm
& 0xc7) == 0xc0) {
7766 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7767 if (!(s
->cpuid_features
& CPUID_SSE
))
7771 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7773 gen_lea_modrm(env
, s
, modrm
);
7780 case 0x10d: /* 3DNow! prefetch(w) */
7781 modrm
= cpu_ldub_code(env
, s
->pc
++);
7782 mod
= (modrm
>> 6) & 3;
7785 gen_lea_modrm(env
, s
, modrm
);
7786 /* ignore for now */
7788 case 0x1aa: /* rsm */
7789 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7790 if (!(s
->flags
& HF_SMM_MASK
))
7792 gen_update_cc_op(s
);
7793 gen_jmp_im(s
->pc
- s
->cs_base
);
7794 gen_helper_rsm(cpu_env
);
7797 case 0x1b8: /* SSE4.2 popcnt */
7798 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7801 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7804 modrm
= cpu_ldub_code(env
, s
->pc
++);
7805 reg
= ((modrm
>> 3) & 7) | rex_r
;
7807 if (s
->prefix
& PREFIX_DATA
) {
7810 ot
= mo_64_32(dflag
);
7813 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7814 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7815 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
7817 set_cc_op(s
, CC_OP_EFLAGS
);
7819 case 0x10e ... 0x10f:
7820 /* 3DNow! instructions, ignore prefixes */
7821 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7822 case 0x110 ... 0x117:
7823 case 0x128 ... 0x12f:
7824 case 0x138 ... 0x13a:
7825 case 0x150 ... 0x179:
7826 case 0x17c ... 0x17f:
7828 case 0x1c4 ... 0x1c6:
7829 case 0x1d0 ... 0x1fe:
7830 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7835 /* lock generation */
7836 if (s
->prefix
& PREFIX_LOCK
)
7837 gen_helper_unlock();
7840 if (s
->prefix
& PREFIX_LOCK
)
7841 gen_helper_unlock();
7842 /* XXX: ensure that no lock was generated */
7843 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7847 void optimize_flags_init(void)
7849 static const char reg_names
[CPU_NB_REGS
][4] = {
7850 #ifdef TARGET_X86_64
7880 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7881 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7882 offsetof(CPUX86State
, cc_op
), "cc_op");
7883 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7885 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7887 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
7890 for (i
= 0; i
< CPU_NB_REGS
; ++i
) {
7891 cpu_regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
7892 offsetof(CPUX86State
, regs
[i
]),
7897 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7898 basic block 'tb'. If search_pc is TRUE, also generate PC
7899 information for each intermediate instruction. */
7900 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
7901 TranslationBlock
*tb
,
7904 CPUState
*cs
= CPU(cpu
);
7905 CPUX86State
*env
= &cpu
->env
;
7906 DisasContext dc1
, *dc
= &dc1
;
7907 target_ulong pc_ptr
;
7908 uint16_t *gen_opc_end
;
7912 target_ulong pc_start
;
7913 target_ulong cs_base
;
7917 /* generate intermediate code */
7919 cs_base
= tb
->cs_base
;
7922 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7923 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7924 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7925 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7927 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7928 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7929 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7930 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7931 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
7932 dc
->cc_op
= CC_OP_DYNAMIC
;
7933 dc
->cc_op_dirty
= false;
7934 dc
->cs_base
= cs_base
;
7936 dc
->popl_esp_hack
= 0;
7937 /* select memory access functions */
7939 if (flags
& HF_SOFTMMU_MASK
) {
7940 dc
->mem_index
= cpu_mmu_index(env
);
7942 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
7943 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
7944 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
7945 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
7946 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
7947 #ifdef TARGET_X86_64
7948 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7949 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7952 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
7953 (flags
& HF_INHIBIT_IRQ_MASK
)
7954 #ifndef CONFIG_SOFTMMU
7955 || (flags
& HF_SOFTMMU_MASK
)
7959 /* check addseg logic */
7960 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7961 printf("ERROR addseg\n");
7964 cpu_T
[0] = tcg_temp_new();
7965 cpu_T
[1] = tcg_temp_new();
7966 cpu_A0
= tcg_temp_new();
7968 cpu_tmp0
= tcg_temp_new();
7969 cpu_tmp1_i64
= tcg_temp_new_i64();
7970 cpu_tmp2_i32
= tcg_temp_new_i32();
7971 cpu_tmp3_i32
= tcg_temp_new_i32();
7972 cpu_tmp4
= tcg_temp_new();
7973 cpu_ptr0
= tcg_temp_new_ptr();
7974 cpu_ptr1
= tcg_temp_new_ptr();
7975 cpu_cc_srcT
= tcg_temp_local_new();
7977 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7979 dc
->is_jmp
= DISAS_NEXT
;
7983 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7985 max_insns
= CF_COUNT_MASK
;
7989 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
7990 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
7991 if (bp
->pc
== pc_ptr
&&
7992 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7993 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7999 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8003 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8005 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8006 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8007 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8008 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8010 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8013 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8015 /* stop translation if indicated */
8018 /* if single step mode, we generate only one instruction and
8019 generate an exception */
8020 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8021 the flag and abort the translation to give the irqs a
8022 change to be happen */
8023 if (dc
->tf
|| dc
->singlestep_enabled
||
8024 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8025 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8029 /* if too long translation, stop generation too */
8030 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8031 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8032 num_insns
>= max_insns
) {
8033 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8038 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8043 if (tb
->cflags
& CF_LAST_IO
)
8045 gen_tb_end(tb
, num_insns
);
8046 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8047 /* we don't forget to fill the last values */
8049 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8052 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8056 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8058 qemu_log("----------------\n");
8059 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8060 #ifdef TARGET_X86_64
8065 disas_flags
= !dc
->code32
;
8066 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8072 tb
->size
= pc_ptr
- pc_start
;
8073 tb
->icount
= num_insns
;
8077 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8079 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8082 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8084 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8087 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8091 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8093 qemu_log("RESTORE:\n");
8094 for(i
= 0;i
<= pc_pos
; i
++) {
8095 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8096 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8097 tcg_ctx
.gen_opc_pc
[i
]);
8100 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8101 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8102 (uint32_t)tb
->cs_base
);
8105 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8106 cc_op
= gen_opc_cc_op
[pc_pos
];
8107 if (cc_op
!= CC_OP_DYNAMIC
)