4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
33 #include "qmp-commands.h"
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
41 # define PCI_DPRINTF(format, ...) do { } while (0)
44 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
45 static char *pcibus_get_dev_path(DeviceState
*dev
);
46 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
47 static int pcibus_reset(BusState
*qbus
);
49 struct BusInfo pci_bus_info
= {
51 .size
= sizeof(PCIBus
),
52 .print_dev
= pcibus_dev_print
,
53 .get_dev_path
= pcibus_get_dev_path
,
54 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
55 .reset
= pcibus_reset
,
56 .props
= (Property
[]) {
57 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
58 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
59 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
60 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
61 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
62 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
63 QEMU_PCI_CAP_SERR_BITNR
, true),
64 DEFINE_PROP_END_OF_LIST()
68 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
69 static void pci_update_mappings(PCIDevice
*d
);
70 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
71 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
72 static void pci_del_option_rom(PCIDevice
*pdev
);
74 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
75 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
80 QLIST_ENTRY(PCIHostBus
) next
;
82 static QLIST_HEAD(, PCIHostBus
) host_buses
;
84 static const VMStateDescription vmstate_pcibus
= {
87 .minimum_version_id
= 1,
88 .minimum_version_id_old
= 1,
89 .fields
= (VMStateField
[]) {
90 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
91 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
95 static int pci_bar(PCIDevice
*d
, int reg
)
99 if (reg
!= PCI_ROM_SLOT
)
100 return PCI_BASE_ADDRESS_0
+ reg
* 4;
102 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
103 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
106 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
108 return (d
->irq_state
>> irq_num
) & 0x1;
111 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
113 d
->irq_state
&= ~(0x1 << irq_num
);
114 d
->irq_state
|= level
<< irq_num
;
117 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
122 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
125 pci_dev
= bus
->parent_dev
;
127 bus
->irq_count
[irq_num
] += change
;
128 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
131 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
133 assert(irq_num
>= 0);
134 assert(irq_num
< bus
->nirq
);
135 return !!bus
->irq_count
[irq_num
];
138 /* Update interrupt status bit in config space on interrupt
140 static void pci_update_irq_status(PCIDevice
*dev
)
142 if (dev
->irq_state
) {
143 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
145 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
149 void pci_device_deassert_intx(PCIDevice
*dev
)
152 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
153 qemu_set_irq(dev
->irq
[i
], 0);
158 * This function is called on #RST and FLR.
159 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
161 void pci_device_reset(PCIDevice
*dev
)
165 qdev_reset_all(&dev
->qdev
);
168 pci_update_irq_status(dev
);
169 pci_device_deassert_intx(dev
);
170 /* Clear all writable bits */
171 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
172 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
173 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
174 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
175 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
176 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
177 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
178 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
179 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
180 PCIIORegion
*region
= &dev
->io_regions
[r
];
185 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
186 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
187 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
189 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
192 pci_update_mappings(dev
);
199 * Trigger pci bus reset under a given bus.
200 * To be called on RST# assert.
202 void pci_bus_reset(PCIBus
*bus
)
206 for (i
= 0; i
< bus
->nirq
; i
++) {
207 bus
->irq_count
[i
] = 0;
209 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
210 if (bus
->devices
[i
]) {
211 pci_device_reset(bus
->devices
[i
]);
216 static int pcibus_reset(BusState
*qbus
)
218 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
220 /* topology traverse is done by pci_bus_reset().
221 Tell qbus/qdev walker not to traverse the tree */
225 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
227 struct PCIHostBus
*host
;
228 host
= g_malloc0(sizeof(*host
));
229 host
->domain
= domain
;
231 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
234 PCIBus
*pci_find_root_bus(int domain
)
236 struct PCIHostBus
*host
;
238 QLIST_FOREACH(host
, &host_buses
, next
) {
239 if (host
->domain
== domain
) {
247 int pci_find_domain(const PCIBus
*bus
)
250 struct PCIHostBus
*host
;
252 /* obtain root bus */
253 while ((d
= bus
->parent_dev
) != NULL
) {
257 QLIST_FOREACH(host
, &host_buses
, next
) {
258 if (host
->bus
== bus
) {
263 abort(); /* should not be reached */
267 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
269 MemoryRegion
*address_space_mem
,
270 MemoryRegion
*address_space_io
,
273 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
274 assert(PCI_FUNC(devfn_min
) == 0);
275 bus
->devfn_min
= devfn_min
;
276 bus
->address_space_mem
= address_space_mem
;
277 bus
->address_space_io
= address_space_io
;
280 QLIST_INIT(&bus
->child
);
281 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
283 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
286 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
287 MemoryRegion
*address_space_mem
,
288 MemoryRegion
*address_space_io
,
293 bus
= g_malloc0(sizeof(*bus
));
294 bus
->qbus
.qdev_allocated
= 1;
295 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
296 address_space_io
, devfn_min
);
300 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
301 void *irq_opaque
, int nirq
)
303 bus
->set_irq
= set_irq
;
304 bus
->map_irq
= map_irq
;
305 bus
->irq_opaque
= irq_opaque
;
307 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
310 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
312 bus
->qbus
.allow_hotplug
= 1;
313 bus
->hotplug
= hotplug
;
314 bus
->hotplug_qdev
= qdev
;
317 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
318 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
320 MemoryRegion
*address_space_mem
,
321 MemoryRegion
*address_space_io
,
322 uint8_t devfn_min
, int nirq
)
326 bus
= pci_bus_new(parent
, name
, address_space_mem
,
327 address_space_io
, devfn_min
);
328 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
332 int pci_bus_num(PCIBus
*s
)
335 return 0; /* pci host bridge */
336 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
339 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
341 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
345 assert(size
== pci_config_size(s
));
346 config
= g_malloc(size
);
348 qemu_get_buffer(f
, config
, size
);
349 for (i
= 0; i
< size
; ++i
) {
350 if ((config
[i
] ^ s
->config
[i
]) &
351 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
356 memcpy(s
->config
, config
, size
);
358 pci_update_mappings(s
);
364 /* just put buffer */
365 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
367 const uint8_t **v
= pv
;
368 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
369 qemu_put_buffer(f
, *v
, size
);
372 static VMStateInfo vmstate_info_pci_config
= {
373 .name
= "pci config",
374 .get
= get_pci_config_device
,
375 .put
= put_pci_config_device
,
378 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
380 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
381 uint32_t irq_state
[PCI_NUM_PINS
];
383 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
384 irq_state
[i
] = qemu_get_be32(f
);
385 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
386 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
392 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
393 pci_set_irq_state(s
, i
, irq_state
[i
]);
399 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
402 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
404 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
405 qemu_put_be32(f
, pci_irq_state(s
, i
));
409 static VMStateInfo vmstate_info_pci_irq_state
= {
410 .name
= "pci irq state",
411 .get
= get_pci_irq_state
,
412 .put
= put_pci_irq_state
,
415 const VMStateDescription vmstate_pci_device
= {
418 .minimum_version_id
= 1,
419 .minimum_version_id_old
= 1,
420 .fields
= (VMStateField
[]) {
421 VMSTATE_INT32_LE(version_id
, PCIDevice
),
422 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
423 vmstate_info_pci_config
,
424 PCI_CONFIG_SPACE_SIZE
),
425 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
426 vmstate_info_pci_irq_state
,
427 PCI_NUM_PINS
* sizeof(int32_t)),
428 VMSTATE_END_OF_LIST()
432 const VMStateDescription vmstate_pcie_device
= {
435 .minimum_version_id
= 1,
436 .minimum_version_id_old
= 1,
437 .fields
= (VMStateField
[]) {
438 VMSTATE_INT32_LE(version_id
, PCIDevice
),
439 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
440 vmstate_info_pci_config
,
441 PCIE_CONFIG_SPACE_SIZE
),
442 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
443 vmstate_info_pci_irq_state
,
444 PCI_NUM_PINS
* sizeof(int32_t)),
445 VMSTATE_END_OF_LIST()
449 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
451 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
454 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
456 /* Clear interrupt status bit: it is implicit
457 * in irq_state which we are saving.
458 * This makes us compatible with old devices
459 * which never set or clear this bit. */
460 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
461 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
462 /* Restore the interrupt status bit. */
463 pci_update_irq_status(s
);
466 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
469 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
470 /* Restore the interrupt status bit. */
471 pci_update_irq_status(s
);
475 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
477 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
478 pci_default_sub_vendor_id
);
479 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
480 pci_default_sub_device_id
);
484 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
485 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
487 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
488 unsigned int *slotp
, unsigned int *funcp
)
493 unsigned long dom
= 0, bus
= 0;
494 unsigned int slot
= 0;
495 unsigned int func
= 0;
498 val
= strtoul(p
, &e
, 16);
504 val
= strtoul(p
, &e
, 16);
511 val
= strtoul(p
, &e
, 16);
524 val
= strtoul(p
, &e
, 16);
531 /* if funcp == NULL func is 0 */
532 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
546 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
549 /* strip legacy tag */
550 if (!strncmp(addr
, "pci_addr=", 9)) {
553 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
554 monitor_printf(mon
, "Invalid pci address\n");
560 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
567 return pci_find_bus_nr(pci_find_root_bus(0), 0);
570 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
574 *devfnp
= PCI_DEVFN(slot
, 0);
575 return pci_find_bus_nr(pci_find_root_bus(dom
), bus
);
578 static void pci_init_cmask(PCIDevice
*dev
)
580 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
581 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
582 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
583 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
584 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
585 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
586 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
587 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
590 static void pci_init_wmask(PCIDevice
*dev
)
592 int config_size
= pci_config_size(dev
);
594 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
595 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
596 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
597 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
598 PCI_COMMAND_INTX_DISABLE
);
599 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
600 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
603 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
604 config_size
- PCI_CONFIG_HEADER_SIZE
);
607 static void pci_init_w1cmask(PCIDevice
*dev
)
610 * Note: It's okay to set w1cmask even for readonly bits as
611 * long as their value is hardwired to 0.
613 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
614 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
615 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
616 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
619 static void pci_init_mask_bridge(PCIDevice
*d
)
621 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
622 PCI_SEC_LETENCY_TIMER */
623 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
626 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
627 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
628 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
629 PCI_MEMORY_RANGE_MASK
& 0xffff);
630 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
631 PCI_MEMORY_RANGE_MASK
& 0xffff);
632 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
633 PCI_PREF_RANGE_MASK
& 0xffff);
634 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
635 PCI_PREF_RANGE_MASK
& 0xffff);
637 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
638 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
640 /* Supported memory and i/o types */
641 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
642 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
643 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
644 PCI_PREF_RANGE_TYPE_64
);
645 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
646 PCI_PREF_RANGE_TYPE_64
);
648 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
649 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
650 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
651 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
652 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
653 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
654 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
655 PCI_BRIDGE_CTL_PARITY
|
656 PCI_BRIDGE_CTL_SERR
|
659 PCI_BRIDGE_CTL_VGA_16BIT
|
660 PCI_BRIDGE_CTL_MASTER_ABORT
|
661 PCI_BRIDGE_CTL_BUS_RESET
|
662 PCI_BRIDGE_CTL_FAST_BACK
|
663 PCI_BRIDGE_CTL_DISCARD
|
664 PCI_BRIDGE_CTL_SEC_DISCARD
|
665 PCI_BRIDGE_CTL_DISCARD_SERR
);
666 /* Below does not do anything as we never set this bit, put here for
668 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
669 PCI_BRIDGE_CTL_DISCARD_STATUS
);
670 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
671 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
672 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
673 PCI_PREF_RANGE_TYPE_MASK
);
674 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
675 PCI_PREF_RANGE_TYPE_MASK
);
678 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
680 uint8_t slot
= PCI_SLOT(dev
->devfn
);
683 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
684 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
688 * multifunction bit is interpreted in two ways as follows.
689 * - all functions must set the bit to 1.
691 * - function 0 must set the bit, but the rest function (> 0)
692 * is allowed to leave the bit to 0.
693 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
695 * So OS (at least Linux) checks the bit of only function 0,
696 * and doesn't see the bit of function > 0.
698 * The below check allows both interpretation.
700 if (PCI_FUNC(dev
->devfn
)) {
701 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
702 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
703 /* function 0 should set multifunction bit */
704 error_report("PCI: single function device can't be populated "
705 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
711 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
714 /* function 0 indicates single function, so function > 0 must be NULL */
715 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
716 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
717 error_report("PCI: %x.0 indicates single function, "
718 "but %x.%x is already populated.",
726 static void pci_config_alloc(PCIDevice
*pci_dev
)
728 int config_size
= pci_config_size(pci_dev
);
730 pci_dev
->config
= g_malloc0(config_size
);
731 pci_dev
->cmask
= g_malloc0(config_size
);
732 pci_dev
->wmask
= g_malloc0(config_size
);
733 pci_dev
->w1cmask
= g_malloc0(config_size
);
734 pci_dev
->used
= g_malloc0(config_size
);
737 static void pci_config_free(PCIDevice
*pci_dev
)
739 g_free(pci_dev
->config
);
740 g_free(pci_dev
->cmask
);
741 g_free(pci_dev
->wmask
);
742 g_free(pci_dev
->w1cmask
);
743 g_free(pci_dev
->used
);
746 /* -1 for devfn means auto assign */
747 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
748 const char *name
, int devfn
)
750 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
751 PCIConfigReadFunc
*config_read
= pc
->config_read
;
752 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
755 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
756 devfn
+= PCI_FUNC_MAX
) {
757 if (!bus
->devices
[devfn
])
760 error_report("PCI: no slot/function available for %s, all in use", name
);
763 } else if (bus
->devices
[devfn
]) {
764 error_report("PCI: slot %d function %d not available for %s, in use by %s",
765 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
769 pci_dev
->devfn
= devfn
;
770 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
771 pci_dev
->irq_state
= 0;
772 pci_config_alloc(pci_dev
);
774 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
775 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
776 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
777 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
779 if (!pc
->is_bridge
) {
780 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
781 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
782 pc
->subsystem_vendor_id
);
783 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
786 pci_set_default_subsystem_id(pci_dev
);
789 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
790 assert(!pc
->subsystem_vendor_id
);
791 assert(!pc
->subsystem_id
);
793 pci_init_cmask(pci_dev
);
794 pci_init_wmask(pci_dev
);
795 pci_init_w1cmask(pci_dev
);
797 pci_init_mask_bridge(pci_dev
);
799 if (pci_init_multifunction(bus
, pci_dev
)) {
800 pci_config_free(pci_dev
);
805 config_read
= pci_default_read_config
;
807 config_write
= pci_default_write_config
;
808 pci_dev
->config_read
= config_read
;
809 pci_dev
->config_write
= config_write
;
810 bus
->devices
[devfn
] = pci_dev
;
811 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
812 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
816 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
818 qemu_free_irqs(pci_dev
->irq
);
819 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
820 pci_config_free(pci_dev
);
823 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
828 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
829 r
= &pci_dev
->io_regions
[i
];
830 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
832 memory_region_del_subregion(r
->address_space
, r
->memory
);
836 static int pci_unregister_device(DeviceState
*dev
)
838 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
839 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
841 pci_unregister_io_regions(pci_dev
);
842 pci_del_option_rom(pci_dev
);
848 do_pci_unregister_device(pci_dev
);
852 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
853 uint8_t type
, MemoryRegion
*memory
)
858 pcibus_t size
= memory_region_size(memory
);
860 assert(region_num
>= 0);
861 assert(region_num
< PCI_NUM_REGIONS
);
862 if (size
& (size
-1)) {
863 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
864 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
868 r
= &pci_dev
->io_regions
[region_num
];
869 r
->addr
= PCI_BAR_UNMAPPED
;
875 addr
= pci_bar(pci_dev
, region_num
);
876 if (region_num
== PCI_ROM_SLOT
) {
877 /* ROM enable bit is writable */
878 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
880 pci_set_long(pci_dev
->config
+ addr
, type
);
881 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
882 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
883 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
884 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
886 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
887 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
889 pci_dev
->io_regions
[region_num
].memory
= memory
;
890 pci_dev
->io_regions
[region_num
].address_space
891 = type
& PCI_BASE_ADDRESS_SPACE_IO
892 ? pci_dev
->bus
->address_space_io
893 : pci_dev
->bus
->address_space_mem
;
896 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
898 return pci_dev
->io_regions
[region_num
].addr
;
901 static pcibus_t
pci_bar_address(PCIDevice
*d
,
902 int reg
, uint8_t type
, pcibus_t size
)
904 pcibus_t new_addr
, last_addr
;
905 int bar
= pci_bar(d
, reg
);
906 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
908 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
909 if (!(cmd
& PCI_COMMAND_IO
)) {
910 return PCI_BAR_UNMAPPED
;
912 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
913 last_addr
= new_addr
+ size
- 1;
914 /* NOTE: we have only 64K ioports on PC */
915 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
916 return PCI_BAR_UNMAPPED
;
921 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
922 return PCI_BAR_UNMAPPED
;
924 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
925 new_addr
= pci_get_quad(d
->config
+ bar
);
927 new_addr
= pci_get_long(d
->config
+ bar
);
929 /* the ROM slot has a specific enable bit */
930 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
931 return PCI_BAR_UNMAPPED
;
933 new_addr
&= ~(size
- 1);
934 last_addr
= new_addr
+ size
- 1;
935 /* NOTE: we do not support wrapping */
936 /* XXX: as we cannot support really dynamic
937 mappings, we handle specific values as invalid
939 if (last_addr
<= new_addr
|| new_addr
== 0 ||
940 last_addr
== PCI_BAR_UNMAPPED
) {
941 return PCI_BAR_UNMAPPED
;
944 /* Now pcibus_t is 64bit.
945 * Check if 32 bit BAR wraps around explicitly.
946 * Without this, PC ide doesn't work well.
947 * TODO: remove this work around.
949 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
950 return PCI_BAR_UNMAPPED
;
954 * OS is allowed to set BAR beyond its addressable
955 * bits. For example, 32 bit OS can set 64bit bar
956 * to >4G. Check it. TODO: we might need to support
957 * it in the future for e.g. PAE.
959 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
960 return PCI_BAR_UNMAPPED
;
966 static void pci_update_mappings(PCIDevice
*d
)
972 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
973 r
= &d
->io_regions
[i
];
975 /* this region isn't registered */
979 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
981 /* This bar isn't changed */
982 if (new_addr
== r
->addr
)
985 /* now do the real mapping */
986 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
987 memory_region_del_subregion(r
->address_space
, r
->memory
);
990 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
991 memory_region_add_subregion_overlap(r
->address_space
,
992 r
->addr
, r
->memory
, 1);
997 static inline int pci_irq_disabled(PCIDevice
*d
)
999 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1002 /* Called after interrupt disabled field update in config space,
1003 * assert/deassert interrupts if necessary.
1004 * Gets original interrupt disable bit value (before update). */
1005 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1007 int i
, disabled
= pci_irq_disabled(d
);
1008 if (disabled
== was_irq_disabled
)
1010 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1011 int state
= pci_irq_state(d
, i
);
1012 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1016 uint32_t pci_default_read_config(PCIDevice
*d
,
1017 uint32_t address
, int len
)
1021 memcpy(&val
, d
->config
+ address
, len
);
1022 return le32_to_cpu(val
);
1025 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1027 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1029 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1030 uint8_t wmask
= d
->wmask
[addr
+ i
];
1031 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1032 assert(!(wmask
& w1cmask
));
1033 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1034 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1036 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1037 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1038 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1039 range_covers_byte(addr
, l
, PCI_COMMAND
))
1040 pci_update_mappings(d
);
1042 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1043 pci_update_irq_disabled(d
, was_irq_disabled
);
1045 msi_write_config(d
, addr
, val
, l
);
1046 msix_write_config(d
, addr
, val
, l
);
1049 /***********************************************************/
1050 /* generic PCI irq support */
1052 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1053 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1055 PCIDevice
*pci_dev
= opaque
;
1058 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1062 pci_set_irq_state(pci_dev
, irq_num
, level
);
1063 pci_update_irq_status(pci_dev
);
1064 if (pci_irq_disabled(pci_dev
))
1066 pci_change_irq_level(pci_dev
, irq_num
, change
);
1069 /* Special hooks used by device assignment */
1070 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1072 assert(!bus
->parent_dev
);
1073 bus
->route_intx_to_irq
= route_intx_to_irq
;
1076 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1082 pin
= bus
->map_irq(dev
, pin
);
1083 dev
= bus
->parent_dev
;
1085 assert(bus
->route_intx_to_irq
);
1086 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1089 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1095 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1096 dev
= bus
->devices
[i
];
1097 if (dev
&& dev
->intx_routing_notifier
) {
1098 dev
->intx_routing_notifier(dev
);
1100 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1101 pci_bus_fire_intx_routing_notifier(sec
);
1106 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1107 PCIINTxRoutingNotifier notifier
)
1109 dev
->intx_routing_notifier
= notifier
;
1112 /***********************************************************/
1113 /* monitor info on PCI */
1118 const char *fw_name
;
1119 uint16_t fw_ign_bits
;
1122 static const pci_class_desc pci_class_descriptions
[] =
1124 { 0x0001, "VGA controller", "display"},
1125 { 0x0100, "SCSI controller", "scsi"},
1126 { 0x0101, "IDE controller", "ide"},
1127 { 0x0102, "Floppy controller", "fdc"},
1128 { 0x0103, "IPI controller", "ipi"},
1129 { 0x0104, "RAID controller", "raid"},
1130 { 0x0106, "SATA controller"},
1131 { 0x0107, "SAS controller"},
1132 { 0x0180, "Storage controller"},
1133 { 0x0200, "Ethernet controller", "ethernet"},
1134 { 0x0201, "Token Ring controller", "token-ring"},
1135 { 0x0202, "FDDI controller", "fddi"},
1136 { 0x0203, "ATM controller", "atm"},
1137 { 0x0280, "Network controller"},
1138 { 0x0300, "VGA controller", "display", 0x00ff},
1139 { 0x0301, "XGA controller"},
1140 { 0x0302, "3D controller"},
1141 { 0x0380, "Display controller"},
1142 { 0x0400, "Video controller", "video"},
1143 { 0x0401, "Audio controller", "sound"},
1145 { 0x0403, "Audio controller", "sound"},
1146 { 0x0480, "Multimedia controller"},
1147 { 0x0500, "RAM controller", "memory"},
1148 { 0x0501, "Flash controller", "flash"},
1149 { 0x0580, "Memory controller"},
1150 { 0x0600, "Host bridge", "host"},
1151 { 0x0601, "ISA bridge", "isa"},
1152 { 0x0602, "EISA bridge", "eisa"},
1153 { 0x0603, "MC bridge", "mca"},
1154 { 0x0604, "PCI bridge", "pci"},
1155 { 0x0605, "PCMCIA bridge", "pcmcia"},
1156 { 0x0606, "NUBUS bridge", "nubus"},
1157 { 0x0607, "CARDBUS bridge", "cardbus"},
1158 { 0x0608, "RACEWAY bridge"},
1159 { 0x0680, "Bridge"},
1160 { 0x0700, "Serial port", "serial"},
1161 { 0x0701, "Parallel port", "parallel"},
1162 { 0x0800, "Interrupt controller", "interrupt-controller"},
1163 { 0x0801, "DMA controller", "dma-controller"},
1164 { 0x0802, "Timer", "timer"},
1165 { 0x0803, "RTC", "rtc"},
1166 { 0x0900, "Keyboard", "keyboard"},
1167 { 0x0901, "Pen", "pen"},
1168 { 0x0902, "Mouse", "mouse"},
1169 { 0x0A00, "Dock station", "dock", 0x00ff},
1170 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1171 { 0x0c00, "Fireware contorller", "fireware"},
1172 { 0x0c01, "Access bus controller", "access-bus"},
1173 { 0x0c02, "SSA controller", "ssa"},
1174 { 0x0c03, "USB controller", "usb"},
1175 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1179 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1180 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1185 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1186 d
= bus
->devices
[devfn
];
1193 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1194 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1196 bus
= pci_find_bus_nr(bus
, bus_num
);
1199 pci_for_each_device_under_bus(bus
, fn
);
1203 static const pci_class_desc
*get_class_desc(int class)
1205 const pci_class_desc
*desc
;
1207 desc
= pci_class_descriptions
;
1208 while (desc
->desc
&& class != desc
->class) {
1215 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1217 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1219 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1222 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1223 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1224 PciMemoryRegionList
*region
;
1230 region
= g_malloc0(sizeof(*region
));
1231 region
->value
= g_malloc0(sizeof(*region
->value
));
1233 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1234 region
->value
->type
= g_strdup("io");
1236 region
->value
->type
= g_strdup("memory");
1237 region
->value
->has_prefetch
= true;
1238 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1239 region
->value
->has_mem_type_64
= true;
1240 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1243 region
->value
->bar
= i
;
1244 region
->value
->address
= r
->addr
;
1245 region
->value
->size
= r
->size
;
1247 /* XXX: waiting for the qapi to support GSList */
1249 head
= cur_item
= region
;
1251 cur_item
->next
= region
;
1259 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1262 PciBridgeInfo
*info
;
1264 info
= g_malloc0(sizeof(*info
));
1266 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1267 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1268 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1270 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1271 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1272 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1274 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1275 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1276 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1278 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1279 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1280 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1282 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1283 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1285 info
->has_devices
= true;
1286 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1293 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1296 const pci_class_desc
*desc
;
1297 PciDeviceInfo
*info
;
1301 info
= g_malloc0(sizeof(*info
));
1302 info
->bus
= bus_num
;
1303 info
->slot
= PCI_SLOT(dev
->devfn
);
1304 info
->function
= PCI_FUNC(dev
->devfn
);
1306 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1307 info
->class_info
.class = class;
1308 desc
= get_class_desc(class);
1310 info
->class_info
.has_desc
= true;
1311 info
->class_info
.desc
= g_strdup(desc
->desc
);
1314 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1315 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1316 info
->regions
= qmp_query_pci_regions(dev
);
1317 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1319 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1320 info
->has_irq
= true;
1321 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1324 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1325 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1326 info
->has_pci_bridge
= true;
1327 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1333 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1335 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1339 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1340 dev
= bus
->devices
[devfn
];
1342 info
= g_malloc0(sizeof(*info
));
1343 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1345 /* XXX: waiting for the qapi to support GSList */
1347 head
= cur_item
= info
;
1349 cur_item
->next
= info
;
1358 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1360 PciInfo
*info
= NULL
;
1362 bus
= pci_find_bus_nr(bus
, bus_num
);
1364 info
= g_malloc0(sizeof(*info
));
1365 info
->bus
= bus_num
;
1366 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1372 PciInfoList
*qmp_query_pci(Error
**errp
)
1374 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1375 struct PCIHostBus
*host
;
1377 QLIST_FOREACH(host
, &host_buses
, next
) {
1378 info
= g_malloc0(sizeof(*info
));
1379 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1381 /* XXX: waiting for the qapi to support GSList */
1383 head
= cur_item
= info
;
1385 cur_item
->next
= info
;
1393 static const char * const pci_nic_models
[] = {
1405 static const char * const pci_nic_names
[] = {
1417 /* Initialize a PCI NIC. */
1418 /* FIXME callers should check for failure, but don't */
1419 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1420 const char *default_devaddr
)
1422 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1429 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1433 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1435 error_report("Invalid PCI device address %s for device %s",
1436 devaddr
, pci_nic_names
[i
]);
1440 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1441 dev
= &pci_dev
->qdev
;
1442 qdev_set_nic_properties(dev
, nd
);
1443 if (qdev_init(dev
) < 0)
1448 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1449 const char *default_devaddr
)
1453 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1456 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1462 /* Whether a given bus number is in range of the secondary
1463 * bus of the given bridge device. */
1464 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1466 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1467 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1468 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1469 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1472 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1480 if (pci_bus_num(bus
) == bus_num
) {
1484 /* Consider all bus numbers in range for the host pci bridge. */
1485 if (bus
->parent_dev
&&
1486 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1491 for (; bus
; bus
= sec
) {
1492 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1493 assert(sec
->parent_dev
);
1494 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1497 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1506 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1508 bus
= pci_find_bus_nr(bus
, bus_num
);
1513 return bus
->devices
[devfn
];
1516 static int pci_qdev_init(DeviceState
*qdev
)
1518 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1519 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1522 bool is_default_rom
;
1524 /* initialize cap_present for pci_is_express() and pci_config_size() */
1525 if (pc
->is_express
) {
1526 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1529 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1530 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1531 object_get_typename(OBJECT(qdev
)),
1533 if (pci_dev
== NULL
)
1535 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1536 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1537 do_pci_unregister_device(pci_dev
);
1541 rc
= pc
->init(pci_dev
);
1543 do_pci_unregister_device(pci_dev
);
1549 is_default_rom
= false;
1550 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1551 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1552 is_default_rom
= true;
1554 pci_add_option_rom(pci_dev
, is_default_rom
);
1557 /* Let buses differentiate between hotplug and when device is
1558 * enabled during qemu machine creation. */
1559 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1560 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1561 PCI_COLDPLUG_ENABLED
);
1563 int r
= pci_unregister_device(&pci_dev
->qdev
);
1571 static int pci_unplug_device(DeviceState
*qdev
)
1573 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1574 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1576 if (pc
->no_hotplug
) {
1577 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1580 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1581 PCI_HOTPLUG_DISABLED
);
1584 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1589 dev
= qdev_create(&bus
->qbus
, name
);
1590 qdev_prop_set_uint32(dev
, "addr", devfn
);
1591 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1592 return PCI_DEVICE(dev
);
1595 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1599 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1600 qdev_init_nofail(&dev
->qdev
);
1604 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1606 return pci_create_multifunction(bus
, devfn
, false, name
);
1609 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1611 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1614 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1616 int config_size
= pci_config_size(pdev
);
1617 int offset
= PCI_CONFIG_HEADER_SIZE
;
1619 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1622 else if (i
- offset
+ 1 == size
)
1627 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1632 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1635 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1636 prev
= next
+ PCI_CAP_LIST_NEXT
)
1637 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1645 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1647 uint8_t next
, prev
, found
= 0;
1649 if (!(pdev
->used
[offset
])) {
1653 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1655 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1656 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1657 if (next
<= offset
&& next
> found
) {
1664 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1665 This is needed for an option rom which is used for more than one device. */
1666 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1670 uint16_t rom_vendor_id
;
1671 uint16_t rom_device_id
;
1673 uint16_t pcir_offset
;
1676 /* Words in rom data are little endian (like in PCI configuration),
1677 so they can be read / written with pci_get_word / pci_set_word. */
1679 /* Only a valid rom will be patched. */
1680 rom_magic
= pci_get_word(ptr
);
1681 if (rom_magic
!= 0xaa55) {
1682 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1685 pcir_offset
= pci_get_word(ptr
+ 0x18);
1686 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1687 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1691 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1692 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1693 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1694 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1696 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1697 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1701 if (vendor_id
!= rom_vendor_id
) {
1702 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1703 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1704 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1705 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1707 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1710 if (device_id
!= rom_device_id
) {
1711 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1712 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1713 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1714 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1716 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1720 /* Add an option rom for the device */
1721 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1727 const VMStateDescription
*vmsd
;
1731 if (strlen(pdev
->romfile
) == 0)
1734 if (!pdev
->rom_bar
) {
1736 * Load rom via fw_cfg instead of creating a rom bar,
1737 * for 0.11 compatibility.
1739 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1740 if (class == 0x0300) {
1741 rom_add_vga(pdev
->romfile
);
1743 rom_add_option(pdev
->romfile
, -1);
1748 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1750 path
= g_strdup(pdev
->romfile
);
1753 size
= get_image_size(path
);
1755 error_report("%s: failed to find romfile \"%s\"",
1756 __FUNCTION__
, pdev
->romfile
);
1760 if (size
& (size
- 1)) {
1761 size
= 1 << qemu_fls(size
);
1764 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
1767 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
1769 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1771 pdev
->has_rom
= true;
1772 memory_region_init_ram(&pdev
->rom
, name
, size
);
1773 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1774 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1775 load_image(path
, ptr
);
1778 if (is_default_rom
) {
1779 /* Only the default rom images will be patched (if needed). */
1780 pci_patch_ids(pdev
, ptr
, size
);
1783 qemu_put_ram_ptr(ptr
);
1785 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1790 static void pci_del_option_rom(PCIDevice
*pdev
)
1795 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1796 memory_region_destroy(&pdev
->rom
);
1797 pdev
->has_rom
= false;
1802 * Reserve space and add capability to the linked list in pci config space
1805 * Find and reserve space and add capability to the linked list
1806 * in pci config space */
1807 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1808 uint8_t offset
, uint8_t size
)
1811 int i
, overlapping_cap
;
1814 offset
= pci_find_space(pdev
, size
);
1819 /* Verify that capabilities don't overlap. Note: device assignment
1820 * depends on this check to verify that the device is not broken.
1821 * Should never trigger for emulated devices, but it's helpful
1822 * for debugging these. */
1823 for (i
= offset
; i
< offset
+ size
; i
++) {
1824 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1825 if (overlapping_cap
) {
1826 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1827 "Attempt to add PCI capability %x at offset "
1828 "%x overlaps existing capability %x at offset %x\n",
1829 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1830 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1831 cap_id
, offset
, overlapping_cap
, i
);
1837 config
= pdev
->config
+ offset
;
1838 config
[PCI_CAP_LIST_ID
] = cap_id
;
1839 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1840 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1841 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1842 memset(pdev
->used
+ offset
, 0xFF, size
);
1843 /* Make capability read-only by default */
1844 memset(pdev
->wmask
+ offset
, 0, size
);
1845 /* Check capability by default */
1846 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1850 /* Unlink capability from the pci config space. */
1851 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1853 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1856 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1857 /* Make capability writable again */
1858 memset(pdev
->wmask
+ offset
, 0xff, size
);
1859 memset(pdev
->w1cmask
+ offset
, 0, size
);
1860 /* Clear cmask as device-specific registers can't be checked */
1861 memset(pdev
->cmask
+ offset
, 0, size
);
1862 memset(pdev
->used
+ offset
, 0, size
);
1864 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1865 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1868 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1870 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1873 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1875 PCIDevice
*d
= (PCIDevice
*)dev
;
1876 const pci_class_desc
*desc
;
1881 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1882 desc
= pci_class_descriptions
;
1883 while (desc
->desc
&& class != desc
->class)
1886 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1888 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1891 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1892 "pci id %04x:%04x (sub %04x:%04x)\n",
1893 indent
, "", ctxt
, pci_bus_num(d
->bus
),
1894 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1895 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1896 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1897 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1898 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1899 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1900 r
= &d
->io_regions
[i
];
1903 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1904 " [0x%"FMT_PCIBUS
"]\n",
1906 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1907 r
->addr
, r
->addr
+ r
->size
- 1);
1911 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
1913 PCIDevice
*d
= (PCIDevice
*)dev
;
1914 const char *name
= NULL
;
1915 const pci_class_desc
*desc
= pci_class_descriptions
;
1916 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1918 while (desc
->desc
&&
1919 (class & ~desc
->fw_ign_bits
) !=
1920 (desc
->class & ~desc
->fw_ign_bits
)) {
1925 name
= desc
->fw_name
;
1929 pstrcpy(buf
, len
, name
);
1931 snprintf(buf
, len
, "pci%04x,%04x",
1932 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1933 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1939 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
1941 PCIDevice
*d
= (PCIDevice
*)dev
;
1942 char path
[50], name
[33];
1945 off
= snprintf(path
, sizeof(path
), "%s@%x",
1946 pci_dev_fw_name(dev
, name
, sizeof name
),
1947 PCI_SLOT(d
->devfn
));
1948 if (PCI_FUNC(d
->devfn
))
1949 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
1950 return strdup(path
);
1953 static char *pcibus_get_dev_path(DeviceState
*dev
)
1955 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
1958 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1959 * 00 is added here to make this format compatible with
1960 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1961 * Slot.Function list specifies the slot and function numbers for all
1962 * devices on the path from root to the specific device. */
1963 char domain
[] = "DDDD:00";
1964 char slot
[] = ":SS.F";
1965 int domain_len
= sizeof domain
- 1 /* For '\0' */;
1966 int slot_len
= sizeof slot
- 1 /* For '\0' */;
1971 /* Calculate # of slots on path between device and root. */;
1973 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1977 path_len
= domain_len
+ slot_len
* slot_depth
;
1979 /* Allocate memory, fill in the terminating null byte. */
1980 path
= g_malloc(path_len
+ 1 /* For '\0' */);
1981 path
[path_len
] = '\0';
1983 /* First field is the domain. */
1984 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
1985 assert(s
== domain_len
);
1986 memcpy(path
, domain
, domain_len
);
1988 /* Fill in slot numbers. We walk up from device to root, so need to print
1989 * them in the reverse order, last to first. */
1990 p
= path
+ path_len
;
1991 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1993 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
1994 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
1995 assert(s
== slot_len
);
1996 memcpy(p
, slot
, slot_len
);
2002 static int pci_qdev_find_recursive(PCIBus
*bus
,
2003 const char *id
, PCIDevice
**pdev
)
2005 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2010 /* roughly check if given qdev is pci device */
2011 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2012 *pdev
= PCI_DEVICE(qdev
);
2018 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2020 struct PCIHostBus
*host
;
2023 QLIST_FOREACH(host
, &host_buses
, next
) {
2024 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2029 if (tmp
!= -ENODEV
) {
2037 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2039 return dev
->bus
->address_space_mem
;
2042 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2044 return dev
->bus
->address_space_io
;
2047 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2049 DeviceClass
*k
= DEVICE_CLASS(klass
);
2050 k
->init
= pci_qdev_init
;
2051 k
->unplug
= pci_unplug_device
;
2052 k
->exit
= pci_unregister_device
;
2053 k
->bus_info
= &pci_bus_info
;
2056 static TypeInfo pci_device_type_info
= {
2057 .name
= TYPE_PCI_DEVICE
,
2058 .parent
= TYPE_DEVICE
,
2059 .instance_size
= sizeof(PCIDevice
),
2061 .class_size
= sizeof(PCIDeviceClass
),
2062 .class_init
= pci_device_class_init
,
2065 static void pci_register_types(void)
2067 type_register_static(&pci_device_type_info
);
2070 type_init(pci_register_types
)