1 //-----------------------------------------------------------------------------
2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
3 // and the ARM. In the low-frequency modes it passes the data straight
4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
5 // frequency modes, the FPGA might perform some demodulation first, to
6 // reduce the amount of data that we must send to the ARM.
8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
11 // Jonathan Westhues, March 2006
12 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
13 //-----------------------------------------------------------------------------
16 `include "lo_passthru.v"
17 `include "lo_simulate.v"
18 `include "hi_read_tx.v"
19 `include "hi_read_rx_xcorr.v"
20 `include "hi_simulate.v"
21 `include "hi_iso14443a.v"
25 spcki
, miso
, mosi
, ncs
,
26 pck0i
, ck_1356meg
, ck_1356megb
,
27 pwr_lo
, pwr_hi
, pwr_oe1
, pwr_oe2
, pwr_oe3
, pwr_oe4
,
28 adc_d
, adc_clk
, adc_noe
,
29 ssp_frame
, ssp_din
, ssp_dout
, ssp_clk
,
33 input spcki
, mosi
, ncs
;
35 input pck0i
, ck_1356meg
, ck_1356megb
;
36 output pwr_lo
, pwr_hi
, pwr_oe1
, pwr_oe2
, pwr_oe3
, pwr_oe4
;
38 output adc_clk
, adc_noe
;
40 output ssp_frame
, ssp_din
, ssp_clk
;
41 input cross_hi
, cross_lo
;
44 //assign pck0 = pck0i;
45 IBUFG #
(.
IOSTANDARD("DEFAULT") ) pck0b(
49 //assign spck = spcki;
50 IBUFG #
(.
IOSTANDARD("DEFAULT") ) spckb(
54 //-----------------------------------------------------------------------------
55 // The SPI receiver. This sets up the configuration word, which the rest of
56 // the logic looks at to determine how to connect the A/D and the coil
57 // drivers (i.e., which section gets it). Also assign some symbolic names
58 // to the configuration bits, for use below.
59 //-----------------------------------------------------------------------------
65 // We switch modes between transmitting to the 13.56 MHz tag and receiving
66 // from it, which means that we must make sure that we can do so without
67 // glitching, or else we will glitch the transmitted carrier.
70 case(shift_reg
[15:12])
71 4'b0001: conf_word
<= shift_reg
[7:0];
72 4'b0010: divisor
<= shift_reg
[7:0];
76 always @(posedge spck
)
80 shift_reg
[15:1] <= shift_reg
[14:0];
85 wire [2:0] major_mode
;
86 assign major_mode
= conf_word
[7:5];
88 // For the low-frequency configuration:
90 assign lo_is_125khz
= conf_word
[3];
92 // For the high-frequency transmit configuration: modulation depth, either
93 // 100% (just quite driving antenna, steady LOW), or shallower (tri-state
94 // some fraction of the buffers)
95 wire hi_read_tx_shallow_modulation
;
96 assign hi_read_tx_shallow_modulation
= conf_word
[0];
98 // For the high-frequency receive correlator: frequency against which to
100 wire hi_read_rx_xcorr_848
;
101 assign hi_read_rx_xcorr_848
= conf_word
[0];
102 // and whether to drive the coil (reader) or just short it (snooper)
103 wire hi_read_rx_xcorr_snoop
;
104 assign hi_read_rx_xcorr_snoop
= conf_word
[1];
106 // Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
107 wire hi_read_rx_xcorr_quarter
;
108 assign hi_read_rx_xcorr_quarter
= conf_word
[2];
110 // For the high-frequency simulated tag: what kind of modulation to use.
111 wire [2:0] hi_simulate_mod_type
;
112 assign hi_simulate_mod_type
= conf_word
[2:0];
114 //-----------------------------------------------------------------------------
115 // And then we instantiate the modules corresponding to each of the FPGA's
116 // major modes, and use muxes to connect the outputs of the active mode to
118 //-----------------------------------------------------------------------------
121 pck0
, ck_1356meg
, ck_1356megb
,
122 lr_pwr_lo
, lr_pwr_hi
, lr_pwr_oe1
, lr_pwr_oe2
, lr_pwr_oe3
, lr_pwr_oe4
,
124 lr_ssp_frame
, lr_ssp_din
, ssp_dout
, lr_ssp_clk
,
127 lo_is_125khz
, divisor
131 pck0
, ck_1356meg
, ck_1356megb
,
132 lp_pwr_lo
, lp_pwr_hi
, lp_pwr_oe1
, lp_pwr_oe2
, lp_pwr_oe3
, lp_pwr_oe4
,
134 lp_ssp_frame
, lp_ssp_din
, ssp_dout
, lp_ssp_clk
,
140 pck0
, ck_1356meg
, ck_1356megb
,
141 ls_pwr_lo
, ls_pwr_hi
, ls_pwr_oe1
, ls_pwr_oe2
, ls_pwr_oe3
, ls_pwr_oe4
,
143 ls_ssp_frame
, ls_ssp_din
, ssp_dout
, ls_ssp_clk
,
149 pck0
, ck_1356meg
, ck_1356megb
,
150 ht_pwr_lo
, ht_pwr_hi
, ht_pwr_oe1
, ht_pwr_oe2
, ht_pwr_oe3
, ht_pwr_oe4
,
152 ht_ssp_frame
, ht_ssp_din
, ssp_dout
, ht_ssp_clk
,
155 hi_read_tx_shallow_modulation
158 hi_read_rx_xcorr
hrxc(
159 pck0
, ck_1356meg
, ck_1356megb
,
160 hrxc_pwr_lo
, hrxc_pwr_hi
, hrxc_pwr_oe1
, hrxc_pwr_oe2
, hrxc_pwr_oe3
, hrxc_pwr_oe4
,
162 hrxc_ssp_frame
, hrxc_ssp_din
, ssp_dout
, hrxc_ssp_clk
,
165 hi_read_rx_xcorr_848
, hi_read_rx_xcorr_snoop
, hi_read_rx_xcorr_quarter
169 pck0
, ck_1356meg
, ck_1356megb
,
170 hs_pwr_lo
, hs_pwr_hi
, hs_pwr_oe1
, hs_pwr_oe2
, hs_pwr_oe3
, hs_pwr_oe4
,
172 hs_ssp_frame
, hs_ssp_din
, ssp_dout
, hs_ssp_clk
,
179 pck0
, ck_1356meg
, ck_1356megb
,
180 hisn_pwr_lo
, hisn_pwr_hi
, hisn_pwr_oe1
, hisn_pwr_oe2
, hisn_pwr_oe3
, hisn_pwr_oe4
,
182 hisn_ssp_frame
, hisn_ssp_din
, ssp_dout
, hisn_ssp_clk
,
189 // 000 -- LF reader (generic)
190 // 001 -- LF simulated tag (generic)
191 // 010 -- HF reader, transmitting to tag; modulation depth selectable
192 // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
193 // 100 -- HF simulated tag
194 // 101 -- HF ISO14443-A
195 // 110 -- LF passthrough
196 // 111 -- everything off
198 mux8
mux_ssp_clk (major_mode
, ssp_clk
, lr_ssp_clk
, ls_ssp_clk
, ht_ssp_clk
, hrxc_ssp_clk
, hs_ssp_clk
, hisn_ssp_clk
, lp_ssp_clk
, 1'b0);
199 mux8
mux_ssp_din (major_mode
, ssp_din
, lr_ssp_din
, ls_ssp_din
, ht_ssp_din
, hrxc_ssp_din
, hs_ssp_din
, hisn_ssp_din
, lp_ssp_din
, 1'b0);
200 mux8
mux_ssp_frame (major_mode
, ssp_frame
, lr_ssp_frame
, ls_ssp_frame
, ht_ssp_frame
, hrxc_ssp_frame
, hs_ssp_frame
, hisn_ssp_frame
, lp_ssp_frame
, 1'b0);
201 mux8
mux_pwr_oe1 (major_mode
, pwr_oe1
, lr_pwr_oe1
, ls_pwr_oe1
, ht_pwr_oe1
, hrxc_pwr_oe1
, hs_pwr_oe1
, hisn_pwr_oe1
, lp_pwr_oe1
, 1'b0);
202 mux8
mux_pwr_oe2 (major_mode
, pwr_oe2
, lr_pwr_oe2
, ls_pwr_oe2
, ht_pwr_oe2
, hrxc_pwr_oe2
, hs_pwr_oe2
, hisn_pwr_oe2
, lp_pwr_oe2
, 1'b0);
203 mux8
mux_pwr_oe3 (major_mode
, pwr_oe3
, lr_pwr_oe3
, ls_pwr_oe3
, ht_pwr_oe3
, hrxc_pwr_oe3
, hs_pwr_oe3
, hisn_pwr_oe3
, lp_pwr_oe3
, 1'b0);
204 mux8
mux_pwr_oe4 (major_mode
, pwr_oe4
, lr_pwr_oe4
, ls_pwr_oe4
, ht_pwr_oe4
, hrxc_pwr_oe4
, hs_pwr_oe4
, hisn_pwr_oe4
, lp_pwr_oe4
, 1'b0);
205 mux8
mux_pwr_lo (major_mode
, pwr_lo
, lr_pwr_lo
, ls_pwr_lo
, ht_pwr_lo
, hrxc_pwr_lo
, hs_pwr_lo
, hisn_pwr_lo
, lp_pwr_lo
, 1'b0);
206 mux8
mux_pwr_hi (major_mode
, pwr_hi
, lr_pwr_hi
, ls_pwr_hi
, ht_pwr_hi
, hrxc_pwr_hi
, hs_pwr_hi
, hisn_pwr_hi
, lp_pwr_hi
, 1'b0);
207 mux8
mux_adc_clk (major_mode
, adc_clk
, lr_adc_clk
, ls_adc_clk
, ht_adc_clk
, hrxc_adc_clk
, hs_adc_clk
, hisn_adc_clk
, lp_adc_clk
, 1'b0);
208 mux8
mux_dbg (major_mode
, dbg
, lr_dbg
, ls_dbg
, ht_dbg
, hrxc_dbg
, hs_dbg
, hisn_dbg
, lp_dbg
, 1'b0);
210 // In all modes, let the ADC's outputs be enabled.
211 assign adc_noe
= 1'b0;