3 #include "gpu_array_tile.h"
8 /* Print the name of the local copy of a given group of array references.
10 __isl_give isl_printer
*gpu_array_ref_group_print_name(
11 struct gpu_array_ref_group
*group
, __isl_take isl_printer
*p
)
15 if (group
->private_tile
)
16 p
= isl_printer_print_str(p
, "private_");
17 else if (group
->shared_tile
)
18 p
= isl_printer_print_str(p
, "shared_");
21 p
= isl_printer_print_str(p
, group
->array
->name
);
22 if (!global
&& group
->local_array
->n_group
> 1) {
23 p
= isl_printer_print_str(p
, "_");
24 p
= isl_printer_print_int(p
, group
->nr
);
30 /* Return the union of all read (read = 1) and/or write (write = 1)
31 * access relations in the group.
33 __isl_give isl_union_map
*gpu_array_ref_group_access_relation(
34 struct gpu_array_ref_group
*group
, int read
, int write
)
37 isl_union_map
*access
;
39 access
= isl_union_map_empty(isl_map_get_space(group
->access
));
40 for (i
= 0; i
< group
->n_ref
; ++i
) {
43 if (!((read
&& group
->refs
[i
]->read
) ||
44 (write
&& group
->refs
[i
]->write
)))
46 map_i
= isl_map_copy(group
->refs
[i
]->access
);
47 access
= isl_union_map_union(access
,
48 isl_union_map_from_map(map_i
));
54 /* Return the effective gpu_array_tile associated to "group" or
55 * NULL if there is no such gpu_array_tile.
56 * If we have computed both a private and a shared tile, then
57 * the private tile is used.
59 struct gpu_array_tile
*gpu_array_ref_group_tile(
60 struct gpu_array_ref_group
*group
)
62 if (group
->private_tile
)
63 return group
->private_tile
;
64 if (group
->shared_tile
)
65 return group
->shared_tile
;
69 /* Does the tile associated to "group" require unrolling of the schedule
70 * dimensions mapped to threads?
71 * Note that this can only happen for private tiles.
73 int gpu_array_ref_group_requires_unroll(struct gpu_array_ref_group
*group
)
75 struct gpu_array_tile
*tile
;
77 tile
= gpu_array_ref_group_tile(group
);
80 return tile
->requires_unroll
;
87 * or -a(p,i) - j = g f(e) if sign < 0,
88 * store a(p,i) in bound->shift and g (stride) in bound->stride.
89 * a(p,i) is assumed to be an expression in only the parameters
90 * and the input dimensions.
92 static void extract_stride(__isl_keep isl_constraint
*c
,
93 struct gpu_array_bound
*bound
, __isl_keep isl_val
*stride
, int sign
)
102 isl_val_free(bound
->stride
);
103 bound
->stride
= isl_val_copy(stride
);
105 space
= isl_constraint_get_space(c
);
106 space
= isl_space_domain(space
);
108 nparam
= isl_space_dim(space
, isl_dim_param
);
109 nvar
= isl_space_dim(space
, isl_dim_set
);
111 v
= isl_constraint_get_constant_val(c
);
114 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
115 aff
= isl_aff_set_constant_val(aff
, v
);
117 for (i
= 0; i
< nparam
; ++i
) {
118 if (!isl_constraint_involves_dims(c
, isl_dim_param
, i
, 1))
120 v
= isl_constraint_get_coefficient_val(c
, isl_dim_param
, i
);
123 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_param
, i
, v
);
126 for (i
= 0; i
< nvar
; ++i
) {
127 if (!isl_constraint_involves_dims(c
, isl_dim_in
, i
, 1))
129 v
= isl_constraint_get_coefficient_val(c
, isl_dim_in
, i
);
132 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_in
, i
, v
);
138 /* Given an equality constraint of a map with a single output dimension j,
139 * check if the constraint is of the form
141 * a(p,i) + j = g f(e)
143 * with a(p,i) an expression in the parameters and input dimensions
144 * and f(e) an expression in the existentially quantified variables.
145 * If so, and if g is larger than any such g from a previously considered
146 * constraint, then call extract_stride to record the stride information
149 static int check_stride_constraint(__isl_take isl_constraint
*c
, void *user
)
155 struct gpu_array_bound
*bound
= user
;
157 ctx
= isl_constraint_get_ctx(c
);
158 n_div
= isl_constraint_dim(c
, isl_dim_div
);
159 v
= isl_constraint_get_coefficient_val(c
, isl_dim_out
, 0);
161 if (n_div
&& (isl_val_is_one(v
) || isl_val_is_negone(v
))) {
162 int s
= isl_val_sgn(v
);
163 isl_val
*stride
= isl_val_zero(ctx
);
166 for (i
= 0; i
< n_div
; ++i
) {
167 v
= isl_constraint_get_coefficient_val(c
,
169 stride
= isl_val_gcd(stride
, v
);
171 if (!isl_val_is_zero(stride
) &&
172 isl_val_gt(stride
, bound
->stride
))
173 extract_stride(c
, bound
, stride
, s
);
175 isl_val_free(stride
);
179 isl_constraint_free(c
);
183 /* Given contraints on an array index i, check if we can find
184 * a shift a(p) and a stride g such that
188 * If so, record the information in bound and apply the mapping
189 * i -> (i + a(p))/g to the array index in bounds and return
190 * the new constraints.
191 * If not, simply return the original constraints.
193 * If bounds is a subset of the space
197 * then the bound recorded in bound->shift is of the form
201 * with s(D) equal to a(p) above.
202 * Next, we construct a mapping of the form
204 * [D -> i] -> [D -> (i + S(D))/g]
206 * This mapping is computed as follows.
207 * We first introduce "i" in the domain through precomposition
208 * with [D -> i] -> D obtaining
212 * Adding [D -> i] -> i produces
214 * [D -> i] -> i + s(D)
216 * and the domain product with [D -> i] -> D yields
218 * [D -> i] -> [D -> i + s(D)]
220 * Composition with [D -> i] -> [D -> i/g] gives the desired result.
222 static __isl_give isl_basic_map
*check_stride(struct gpu_array_bound
*bound
,
223 __isl_take isl_basic_map
*bounds
)
227 isl_basic_map
*shift
, *id
, *bmap
, *scale
;
231 bound
->stride
= NULL
;
233 hull
= isl_basic_map_affine_hull(isl_basic_map_copy(bounds
));
235 isl_basic_map_foreach_constraint(hull
, &check_stride_constraint
, bound
);
237 isl_basic_map_free(hull
);
242 shift
= isl_basic_map_from_aff(isl_aff_copy(bound
->shift
));
243 space
= isl_basic_map_get_space(bounds
);
244 bmap
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
245 shift
= isl_basic_map_apply_range(bmap
, shift
);
246 space
= isl_basic_map_get_space(bounds
);
247 id
= isl_basic_map_range_map(isl_basic_map_universe(space
));
248 shift
= isl_basic_map_sum(id
, shift
);
249 space
= isl_basic_map_get_space(bounds
);
250 id
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
251 shift
= isl_basic_map_range_product(id
, shift
);
253 space
= isl_space_domain(isl_basic_map_get_space(bounds
));
254 id
= isl_basic_map_identity(isl_space_map_from_set(space
));
255 space
= isl_space_range(isl_basic_map_get_space(bounds
));
256 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
257 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, 0, 1);
258 aff
= isl_aff_scale_down_val(aff
, isl_val_copy(bound
->stride
));
259 scale
= isl_basic_map_from_aff(aff
);
260 scale
= isl_basic_map_product(id
, scale
);
262 bmap
= isl_basic_map_apply_range(shift
, scale
);
263 bset
= isl_basic_set_apply(isl_basic_map_wrap(bounds
), bmap
);
264 bounds
= isl_basic_set_unwrap(bset
);
269 /* Data used in compute_array_dim_size and compute_size_in_direction.
271 * pos is the position of the variable representing the array index,
272 * i.e., the variable for which want to compute the size. This variable
273 * is also the last variable in the set.
275 struct gpu_size_info
{
277 struct gpu_array_bound
*bound
;
281 /* Given a constraint from the basic set describing the bounds on
282 * an array index, check if it is a lower bound, say m i >= b(x), and,
283 * if so, check whether the expression "i - ceil(b(x)/m) + 1" has a constant
284 * upper bound. If so, and if this bound is smaller than any bound
285 * derived from earlier constraints, set the size to this bound on
286 * the expression and the lower bound to ceil(b(x)/m).
288 static int compute_size_in_direction(__isl_take isl_constraint
*c
, void *user
)
290 struct gpu_size_info
*size
= user
;
297 nparam
= isl_basic_set_dim(size
->bset
, isl_dim_param
);
298 n_div
= isl_constraint_dim(c
, isl_dim_div
);
300 if (isl_constraint_involves_dims(c
, isl_dim_div
, 0, n_div
) ||
301 !isl_constraint_is_lower_bound(c
, isl_dim_set
, size
->pos
)) {
302 isl_constraint_free(c
);
306 aff
= isl_constraint_get_bound(c
, isl_dim_set
, size
->pos
);
307 aff
= isl_aff_ceil(aff
);
309 lb
= isl_aff_copy(aff
);
311 aff
= isl_aff_neg(aff
);
312 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, size
->pos
, 1);
314 v
= isl_basic_set_max_val(size
->bset
, aff
);
317 if (isl_val_is_int(v
)) {
318 v
= isl_val_add_ui(v
, 1);
319 if (!size
->bound
->size
|| isl_val_lt(v
, size
->bound
->size
)) {
320 isl_val_free(size
->bound
->size
);
321 size
->bound
->size
= isl_val_copy(v
);
322 lb
= isl_aff_drop_dims(lb
, isl_dim_in
, size
->pos
, 1);
323 isl_aff_free(size
->bound
->lb
);
324 size
->bound
->lb
= isl_aff_copy(lb
);
330 isl_constraint_free(c
);
335 /* Given a basic map "bounds" that maps parameters and input dimensions
336 * to a single output dimension, look for an expression in the parameters
337 * and input dimensions such that the range of the output dimension shifted
338 * by this expression is a constant.
340 * In particular, we currently only consider lower bounds on the output
341 * dimension as candidate expressions.
343 static int compute_array_dim_size(struct gpu_array_bound
*bound
,
344 __isl_take isl_basic_map
*bounds
)
346 struct gpu_size_info size
;
348 bounds
= isl_basic_map_detect_equalities(bounds
);
349 bounds
= check_stride(bound
, bounds
);
355 size
.pos
= isl_basic_map_dim(bounds
, isl_dim_in
);
356 size
.bset
= isl_basic_map_wrap(bounds
);
357 size
.bset
= isl_basic_set_flatten(size
.bset
);
358 size
.bset
= isl_set_simple_hull(isl_basic_set_compute_divs(size
.bset
));
359 isl_basic_set_foreach_constraint(size
.bset
, &compute_size_in_direction
,
361 isl_basic_set_free(size
.bset
);
363 return bound
->size
? 0 : -1;
366 /* Check if we can find a memory tile for the given array
367 * based on the given accesses, and if so, put the results in "tile".
369 * We project the accesses on each index in turn and look for a parametric
370 * offset such that the size is constant.
372 static int can_tile(__isl_keep isl_map
*access
, struct gpu_array_tile
*tile
)
376 for (i
= 0; i
< tile
->n
; ++i
) {
380 access_i
= isl_map_copy(access
);
381 access_i
= isl_map_project_out(access_i
, isl_dim_out
, 0, i
);
382 access_i
= isl_map_project_out(access_i
, isl_dim_out
,
383 1, tile
->n
- (i
+ 1));
384 access_i
= isl_map_compute_divs(access_i
);
385 hull
= isl_map_simple_hull(access_i
);
386 if (compute_array_dim_size(&tile
->bound
[i
], hull
) < 0)
393 /* Internal data structure for gpu_group_references.
395 * scop represents the input scop.
396 * kernel_depth is the schedule depth where the kernel launch will
397 * be introduced, i.e., it is the depth of the band that is mapped
399 * thread_depth is the schedule depth where the thread mark is located,
400 * i.e., it is the depth of the band that is mapped to threads and also
401 * the schedule depth at which the copying to/from shared/private memory
402 * is computed. The copy operation may then later be hoisted to
404 * n_thread is the number of schedule dimensions in the band that
405 * is mapped to threads.
406 * privatization lives in the range of thread_sched (i.e., it is
407 * of dimension thread_depth + n_thread) and encodes the mapping
408 * to thread identifiers (as parameters).
409 * shared_sched contains the first thread_depth dimensions of the
411 * thread_sched contains the first (thread_depth + n_thread) dimensions
412 * of the kernel schedule.
413 * full_sched is a union_map representation of the entire kernel schedule.
415 struct gpu_group_data
{
416 struct ppcg_scop
*scop
;
420 isl_set
*privatization
;
421 isl_union_map
*shared_sched
;
422 isl_union_map
*thread_sched
;
423 isl_union_map
*full_sched
;
426 /* Construct a map from domain_dim to domain_dim that increments
427 * the dimension at position "pos" and leaves all other dimensions
430 static __isl_give isl_map
*next(__isl_take isl_space
*domain_dim
, int pos
)
433 int len
= isl_space_dim(domain_dim
, isl_dim_set
);
438 dim
= isl_space_map_from_set(domain_dim
);
439 next
= isl_basic_map_universe(isl_space_copy(dim
));
440 ls
= isl_local_space_from_space(dim
);
442 for (i
= 0; i
< len
; ++i
) {
445 c
= isl_equality_alloc(isl_local_space_copy(ls
));
446 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, 1);
447 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
449 c
= isl_constraint_set_constant_si(c
, 1);
450 next
= isl_basic_map_add_constraint(next
, c
);
453 isl_local_space_free(ls
);
455 return isl_map_from_basic_map(next
);
458 /* Check if the given access is coalesced (or if there is no point
459 * in trying to coalesce the access by mapping the array to shared memory).
460 * That is, check whether incrementing the dimension that will get
461 * wrapped over the last thread index results in incrementing
462 * the last array index.
464 * If no two consecutive array elements are ever accessed by "access",
465 * then mapping the corresponding array to shared memory will not
466 * improve coalescing. In fact, the copying will likely be performed
467 * by a single thread. Consider the access as coalesced such that
468 * the caller will not try and map the array to shared memory just
469 * to improve coalescing.
471 * This function is only called for access relations without reuse and
472 * kernels with at least one thread identifier.
474 static int access_is_coalesced(struct gpu_group_data
*data
,
475 __isl_keep isl_union_map
*access
)
480 isl_map
*next_thread_x
;
481 isl_map
*next_element
;
483 int coalesced
, empty
;
485 access
= isl_union_map_copy(access
);
486 access
= isl_union_map_apply_domain(access
,
487 isl_union_map_copy(data
->full_sched
));
488 access_map
= isl_map_from_union_map(access
);
490 space
= isl_map_get_space(access_map
);
491 space
= isl_space_range(space
);
492 next_element
= next(space
, isl_space_dim(space
, isl_dim_set
) - 1);
494 accessed
= isl_map_range(isl_map_copy(access_map
));
495 map
= isl_map_copy(next_element
);
496 map
= isl_map_intersect_domain(map
, isl_set_copy(accessed
));
497 map
= isl_map_intersect_range(map
, accessed
);
498 empty
= isl_map_is_empty(map
);
501 if (empty
< 0 || empty
) {
502 isl_map_free(next_element
);
503 isl_map_free(access_map
);
507 space
= isl_map_get_space(access_map
);
508 space
= isl_space_domain(space
);
509 next_thread_x
= next(space
, data
->thread_depth
+ data
->n_thread
- 1);
511 map
= isl_map_apply_domain(next_thread_x
, isl_map_copy(access_map
));
512 map
= isl_map_apply_range(map
, access_map
);
514 coalesced
= isl_map_is_subset(map
, next_element
);
516 isl_map_free(next_element
);
522 /* Given an access relation in terms of at least data->thread_depth initial
523 * dimensions of the computed schedule, check if it is bijective for
524 * fixed values of the first data->thread_depth dimensions.
525 * We perform this check by equating these dimensions to parameters.
527 static int access_is_bijective(struct gpu_group_data
*data
,
528 __isl_keep isl_map
*access
)
536 access
= isl_map_copy(access
);
537 space
= isl_space_params(isl_map_get_space(access
));
538 ids
= ppcg_scop_generate_names(data
->scop
, data
->thread_depth
, "s");
539 dim
= isl_map_dim(access
, isl_dim_in
);
540 par
= parametrization(space
, dim
, 0, ids
);
541 isl_id_list_free(ids
);
542 access
= isl_map_intersect_domain(access
, par
);
543 res
= isl_map_is_bijective(access
);
544 isl_map_free(access
);
549 /* Compute the number of outer schedule tile dimensions that affect
550 * the offset of "tile".
551 * If there is no such dimension, then return the index
552 * of the first kernel dimension, i.e., data->kernel_depth.
554 static int compute_tile_depth(struct gpu_group_data
*data
,
555 struct gpu_array_tile
*tile
)
559 for (j
= data
->thread_depth
- 1; j
>= data
->kernel_depth
; --j
) {
560 for (i
= 0; i
< tile
->n
; ++i
) {
564 lb
= tile
->bound
[i
].lb
;
565 if (isl_aff_involves_dims(lb
, isl_dim_in
, j
, 1))
568 shift
= tile
->bound
[i
].shift
;
571 if (isl_aff_involves_dims(shift
, isl_dim_in
, j
, 1))
581 /* Adjust the fields of "tile" to reflect the new input dimension "new_dim",
582 * where "old_dim" is the old dimension.
583 * The dimension beyond "new_dim" are assumed not to affect the tile,
584 * so they can simply be dropped.
586 static int tile_adjust_depth(struct gpu_array_tile
*tile
,
587 int old_dim
, int new_dim
)
591 if (old_dim
== new_dim
)
594 for (i
= 0; i
< tile
->n
; ++i
) {
595 tile
->bound
[i
].lb
= isl_aff_drop_dims(tile
->bound
[i
].lb
,
596 isl_dim_in
, new_dim
, old_dim
- new_dim
);
597 if (!tile
->bound
[i
].lb
)
599 if (!tile
->bound
[i
].shift
)
601 tile
->bound
[i
].shift
= isl_aff_drop_dims(tile
->bound
[i
].shift
,
602 isl_dim_in
, new_dim
, old_dim
- new_dim
);
603 if (!tile
->bound
[i
].shift
)
610 /* Determine the number of schedule dimensions that affect the offset of the
611 * shared or private tile and store the result in group->depth, with
612 * a lower bound of data->kernel_depth.
613 * If there is no tile defined on the array reference group,
614 * then set group->depth to data->thread_depth.
615 * Also adjust the fields of the tile to only refer to the group->depth
616 * outer schedule dimensions.
618 static int set_depth(struct gpu_group_data
*data
,
619 struct gpu_array_ref_group
*group
)
621 struct gpu_array_tile
*tile
;
623 group
->depth
= data
->thread_depth
;
625 tile
= gpu_array_ref_group_tile(group
);
629 group
->depth
= compute_tile_depth(data
, tile
);
630 if (tile_adjust_depth(tile
, data
->thread_depth
, group
->depth
) < 0)
636 /* Fill up the groups array with singleton groups, i.e., one group
637 * per reference, initializing the array, access, write, n_ref and refs fields.
638 * In particular the access field is initialized to the scheduled
639 * access relation of the array reference.
641 * Return the number of elements initialized, i.e., the number of
642 * active references in the current kernel.
644 static int populate_array_references(struct gpu_local_array_info
*local
,
645 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
649 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->shared_sched
);
652 for (i
= 0; i
< local
->array
->n_ref
; ++i
) {
655 struct gpu_array_ref_group
*group
;
656 struct gpu_stmt_access
*access
= local
->array
->refs
[i
];
658 map
= isl_map_copy(access
->access
);
659 umap
= isl_union_map_from_map(map
);
660 umap
= isl_union_map_apply_domain(umap
,
661 isl_union_map_copy(data
->shared_sched
));
663 if (isl_union_map_is_empty(umap
)) {
664 isl_union_map_free(umap
);
668 map
= isl_map_from_union_map(umap
);
669 map
= isl_map_detect_equalities(map
);
671 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
674 group
->local_array
= local
;
675 group
->array
= local
->array
;
677 group
->write
= access
->write
;
678 group
->exact_write
= access
->exact_write
;
679 group
->slice
= access
->n_index
< local
->array
->n_index
;
680 group
->refs
= &local
->array
->refs
[i
];
689 /* If group->n_ref == 1, then group->refs was set by
690 * populate_array_references to point directly into
691 * group->array->refs and should not be freed.
692 * If group->n_ref > 1, then group->refs was set by join_groups
693 * to point to a newly allocated array.
695 struct gpu_array_ref_group
*gpu_array_ref_group_free(
696 struct gpu_array_ref_group
*group
)
700 gpu_array_tile_free(group
->shared_tile
);
701 gpu_array_tile_free(group
->private_tile
);
702 isl_map_free(group
->access
);
703 if (group
->n_ref
> 1)
709 /* Check if the access relations of group1 and group2 overlap within
712 static int accesses_overlap(struct gpu_array_ref_group
*group1
,
713 struct gpu_array_ref_group
*group2
)
717 disjoint
= isl_map_is_disjoint(group1
->access
, group2
->access
);
724 /* Combine the given two groups into a single group, containing
725 * the references of both groups.
727 static struct gpu_array_ref_group
*join_groups(
728 struct gpu_array_ref_group
*group1
,
729 struct gpu_array_ref_group
*group2
)
733 struct gpu_array_ref_group
*group
;
735 ctx
= isl_map_get_ctx(group1
->access
);
736 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
739 group
->local_array
= group1
->local_array
;
740 group
->array
= group1
->array
;
741 group
->access
= isl_map_union(isl_map_copy(group1
->access
),
742 isl_map_copy(group2
->access
));
743 group
->write
= group1
->write
|| group2
->write
;
744 group
->exact_write
= group1
->exact_write
&& group2
->exact_write
;
745 group
->slice
= group1
->slice
|| group2
->slice
;
746 group
->n_ref
= group1
->n_ref
+ group2
->n_ref
;
747 group
->refs
= isl_alloc_array(ctx
, struct gpu_stmt_access
*,
750 return gpu_array_ref_group_free(group
);
751 for (i
= 0; i
< group1
->n_ref
; ++i
)
752 group
->refs
[i
] = group1
->refs
[i
];
753 for (i
= 0; i
< group2
->n_ref
; ++i
)
754 group
->refs
[group1
->n_ref
+ i
] = group2
->refs
[i
];
759 /* Combine the given two groups into a single group and free
760 * the original two groups.
762 static struct gpu_array_ref_group
*join_groups_and_free(
763 struct gpu_array_ref_group
*group1
,
764 struct gpu_array_ref_group
*group2
)
766 struct gpu_array_ref_group
*group
;
768 group
= join_groups(group1
, group2
);
769 gpu_array_ref_group_free(group1
);
770 gpu_array_ref_group_free(group2
);
774 /* Report that the array reference group with the given access relation
775 * is not mapped to shared memory in the given kernel because
776 * it does not exhibit any reuse and is considered to be coalesced.
778 static void report_no_reuse_and_coalesced(struct ppcg_kernel
*kernel
,
779 __isl_keep isl_union_map
*access
)
784 ctx
= isl_union_map_get_ctx(access
);
785 p
= isl_printer_to_file(ctx
, stdout
);
786 p
= isl_printer_print_str(p
, "Array reference group ");
787 p
= isl_printer_print_union_map(p
, access
);
788 p
= isl_printer_print_str(p
,
789 " not considered for mapping to shared memory in kernel");
790 p
= isl_printer_print_int(p
, kernel
->id
);
791 p
= isl_printer_print_str(p
,
792 " because it exhibits no reuse and is considered to be coalesced");
793 p
= isl_printer_end_line(p
);
797 /* Given an access relation in terms of the data->thread_depth initial
798 * dimensions of the computed schedule and the thread identifiers
799 * (as parameters), check if the use of the corresponding private tile
800 * requires unrolling.
802 * If we are creating a private tile because we are forced to,
803 * then no unrolling is required.
804 * Otherwise we check if "access" is bijective and unrolling
805 * is required if it is not. Note that the access relation
806 * has already been determined to be bijective before the introduction
807 * of the thread identifiers and the removal of the schedule dimensions
808 * that are mapped to these threads. If the access relation is no longer
809 * bijective, then this means that more than one value of one of those
810 * schedule dimensions is mapped to the same thread and therefore
811 * unrolling is required.
813 static int check_requires_unroll(struct gpu_group_data
*data
,
814 __isl_keep isl_map
*access
, int force_private
)
820 bijective
= access_is_bijective(data
, access
);
826 /* Compute the private and/or shared memory tiles for the array
827 * reference group "group" of array "array".
828 * Return 0 on success and -1 on error.
830 * If the array is a read-only scalar or if the user requested
831 * not to use shared or private memory, then we do not need to do anything.
833 * If any reference in the reference group accesses more than one element,
834 * then we would have to make sure that the layout in shared memory
835 * is the same as that in global memory. Since we do not handle this yet
836 * (and it may not even be possible), we refuse to map to private or
837 * shared memory in such cases.
839 * If the array group involves any may writes (that are not must writes),
840 * then we would have to make sure that we load the data into shared/private
841 * memory first in case the data is not written by the kernel
842 * (but still written back out to global memory).
843 * Since we don't have any such mechanism at the moment, we don't
844 * compute shared/private tiles for groups involving may writes.
846 * We only try to compute a shared memory tile if there is any reuse
847 * or if the access is not coalesced.
849 * For computing a private memory tile, we also require that there is
850 * some reuse. Moreover, we require that the access is private
851 * to the thread. That is, we check that any given array element
852 * is only accessed by a single thread.
853 * We compute an access relation that maps the outer
854 * data->thread_depth + data->n_thread schedule dimensions.
855 * The latter data->n_thread will be mapped to thread identifiers.
856 * We actually check that those iterators that will be wrapped
857 * partition the array space. This check is stricter than necessary
858 * since several iterations may be mapped onto the same thread
859 * and then they could be allowed to access the same memory elements,
860 * but our check does not allow this situation.
862 * We also check that the index expression only depends on parallel
863 * loops. That way, we can move those loops innermost and unroll them.
864 * Again, we use a test that is stricter than necessary.
865 * We actually check whether the index expression only depends
866 * on the iterators that are wrapped over the threads.
867 * These are necessarily parallel, but there may be more parallel loops.
869 * Combining the injectivity of the first test with the single-valuedness
870 * of the second test, we simply test for bijectivity.
872 * If the use of the private tile requires unrolling, but some
873 * of the other arrays are forcibly mapped to private memory,
874 * then we do not allow the use of this private tile since
875 * we cannot move the schedule dimensions that need to be unrolled down
876 * without performing some kind of expansion on those arrays
877 * that are forcibly mapped to private memory.
879 * If the array is marked force_private, then we bypass all checks
880 * and assume we can (and should) use registers.
882 * If it turns out we can (or have to) use registers, we compute
883 * the private memory tile size using can_tile, after introducing a dependence
884 * on the thread indices.
886 static int compute_group_bounds_core(struct ppcg_kernel
*kernel
,
887 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
889 isl_ctx
*ctx
= isl_space_get_ctx(group
->array
->space
);
890 isl_union_map
*access
;
891 int n_index
= group
->array
->n_index
;
892 int no_reuse
, coalesced
;
894 int force_private
= group
->local_array
->force_private
;
895 int use_shared
= kernel
->options
->use_shared_memory
&&
897 int use_private
= force_private
|| kernel
->options
->use_private_memory
;
901 if (!use_shared
&& !use_private
)
903 if (gpu_array_is_read_only_scalar(group
->array
))
905 if (!force_private
&& !group
->exact_write
)
910 access
= gpu_array_ref_group_access_relation(group
, 1, 1);
911 no_reuse
= isl_union_map_is_injective(access
);
914 if (use_shared
&& no_reuse
)
915 coalesced
= access_is_coalesced(data
, access
);
917 if (r
>= 0 && kernel
->options
->debug
->verbose
&&
918 use_shared
&& no_reuse
&& coalesced
)
919 report_no_reuse_and_coalesced(kernel
, access
);
921 if (use_shared
&& (!no_reuse
|| !coalesced
)) {
922 group
->shared_tile
= gpu_array_tile_create(ctx
,
923 group
->array
->n_index
);
924 if (!group
->shared_tile
)
926 else if (!can_tile(group
->access
, group
->shared_tile
))
928 gpu_array_tile_free(group
->shared_tile
);
931 if (r
< 0 || (!force_private
&& (!use_private
|| no_reuse
))) {
932 isl_union_map_free(access
);
936 access
= isl_union_map_apply_domain(access
,
937 isl_union_map_copy(data
->thread_sched
));
939 acc
= isl_map_from_union_map(access
);
941 if (!force_private
&& !access_is_bijective(data
, acc
)) {
946 acc
= isl_map_intersect_domain(acc
, isl_set_copy(data
->privatization
));
947 acc
= isl_map_project_out(acc
, isl_dim_in
, data
->thread_depth
,
949 requires_unroll
= check_requires_unroll(data
, acc
, force_private
);
950 if (requires_unroll
< 0 ||
951 (requires_unroll
&& kernel
->any_force_private
)) {
953 return requires_unroll
< 0 ? -1 : 0;
956 group
->private_tile
= gpu_array_tile_create(ctx
, n_index
);
957 if (!group
->private_tile
) {
961 group
->private_tile
->requires_unroll
= requires_unroll
;
962 if (!can_tile(acc
, group
->private_tile
))
963 group
->private_tile
= gpu_array_tile_free(group
->private_tile
);
967 if (force_private
&& !group
->private_tile
)
968 isl_die(ctx
, isl_error_internal
,
969 "unable to map array reference group to registers",
975 /* Compute the private and/or shared memory tiles for the array
976 * reference group "group" of array "array" and set the tile depth.
977 * Return 0 on success and -1 on error.
979 static int compute_group_bounds(struct ppcg_kernel
*kernel
,
980 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
984 if (compute_group_bounds_core(kernel
, group
, data
) < 0)
986 if (set_depth(data
, group
) < 0)
992 /* If two groups have overlapping access relations (as determined by
993 * the "overlap" function) and if one of them involves a write,
994 * then merge the two groups into one.
995 * If "compute_bounds" is set, then call compute_group_bounds
996 * on the merged groups.
998 * Return the updated number of groups.
999 * Return -1 on error.
1001 static int group_writes(struct ppcg_kernel
*kernel
,
1002 int n
, struct gpu_array_ref_group
**groups
,
1003 int (*overlap
)(struct gpu_array_ref_group
*group1
,
1004 struct gpu_array_ref_group
*group2
), int compute_bounds
,
1005 struct gpu_group_data
*data
)
1009 for (i
= 0; i
< n
; ++i
) {
1010 for (j
= n
- 1; j
> i
; --j
) {
1011 if (!groups
[i
]->write
&& !groups
[j
]->write
)
1014 if (!overlap(groups
[i
], groups
[j
]))
1017 groups
[i
] = join_groups_and_free(groups
[i
], groups
[j
]);
1019 groups
[j
] = groups
[n
- 1];
1020 groups
[n
- 1] = NULL
;
1025 if (compute_bounds
&&
1026 compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1034 /* If two groups have overlapping access relations (within the innermost
1035 * loop) and if one of them involves a write, then merge the two groups
1038 * Return the updated number of groups.
1040 static int group_overlapping_writes(struct ppcg_kernel
*kernel
,
1041 int n
, struct gpu_array_ref_group
**groups
,
1042 struct gpu_group_data
*data
)
1044 return group_writes(kernel
, n
, groups
, &accesses_overlap
, 0, data
);
1047 /* Check if the access relations of group1 and group2 overlap within
1048 * the outermost min(group1->depth, group2->depth) loops.
1050 static int depth_accesses_overlap(struct gpu_array_ref_group
*group1
,
1051 struct gpu_array_ref_group
*group2
)
1056 isl_map
*map_i
, *map_j
, *map
;
1058 depth
= group1
->depth
;
1059 if (group2
->depth
< depth
)
1060 depth
= group2
->depth
;
1061 map_i
= isl_map_copy(group1
->access
);
1062 dim
= isl_map_dim(map_i
, isl_dim_in
);
1063 map_i
= isl_map_eliminate(map_i
, isl_dim_in
, depth
, dim
- depth
);
1064 map_j
= isl_map_copy(group2
->access
);
1065 map_j
= isl_map_eliminate(map_j
, isl_dim_in
, depth
, dim
- depth
);
1066 map
= isl_map_intersect(map_i
, map_j
);
1067 empty
= isl_map_is_empty(map
);
1073 /* If two groups have overlapping access relations (within the outer
1074 * depth loops) and if one of them involves a write,
1075 * then merge the two groups into one.
1077 * Return the updated number of groups.
1079 static int group_depth_overlapping_writes(struct ppcg_kernel
*kernel
,
1080 int n
, struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1082 return group_writes(kernel
, n
, groups
, &depth_accesses_overlap
, 1,
1086 /* Is the size of the tile specified by "tile" smaller than the sum of
1087 * the sizes of the tiles specified by "tile1" and "tile2"?
1089 static int smaller_tile(struct gpu_array_tile
*tile
,
1090 struct gpu_array_tile
*tile1
, struct gpu_array_tile
*tile2
)
1093 isl_val
*size
, *size1
, *size2
;
1095 size
= gpu_array_tile_size(tile
);
1096 size1
= gpu_array_tile_size(tile1
);
1097 size2
= gpu_array_tile_size(tile2
);
1099 size
= isl_val_sub(size
, size1
);
1100 size
= isl_val_sub(size
, size2
);
1101 smaller
= isl_val_is_neg(size
);
1108 /* Given an initial grouping of array references and shared memory tiles
1109 * for each group that allows for a shared memory tile, merge two groups
1110 * if both have a shared memory tile, the merged group also has
1111 * a shared memory tile and the size of the tile for the merge group
1112 * is smaller than the sum of the tile sizes of the individual groups.
1114 * If merging two groups decreases the depth of the tile of
1115 * one or both of the two groups, then we need to check for overlapping
1118 * Return the number of groups after merging.
1119 * Return -1 on error.
1121 static int group_common_shared_memory_tile(struct ppcg_kernel
*kernel
,
1122 struct gpu_array_info
*array
, int n
,
1123 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1126 int recompute_overlap
= 0;
1127 isl_ctx
*ctx
= isl_space_get_ctx(array
->space
);
1129 for (i
= 0; i
< n
; ++i
) {
1130 if (!groups
[i
]->shared_tile
)
1132 for (j
= n
- 1; j
> i
; --j
) {
1135 struct gpu_array_ref_group
*group
;
1137 if (!groups
[j
]->shared_tile
)
1140 map
= isl_map_intersect(isl_map_copy(groups
[i
]->access
),
1141 isl_map_copy(groups
[j
]->access
));
1142 empty
= isl_map_is_empty(map
);
1148 group
= join_groups(groups
[i
], groups
[j
]);
1149 if (compute_group_bounds(kernel
, group
, data
) < 0) {
1150 gpu_array_ref_group_free(group
);
1153 if (!group
->shared_tile
||
1154 !smaller_tile(group
->shared_tile
,
1155 groups
[i
]->shared_tile
,
1156 groups
[j
]->shared_tile
)) {
1157 gpu_array_ref_group_free(group
);
1161 if (group
->depth
< groups
[i
]->depth
||
1162 group
->depth
< groups
[j
]->depth
)
1163 recompute_overlap
= 1;
1164 gpu_array_ref_group_free(groups
[i
]);
1165 gpu_array_ref_group_free(groups
[j
]);
1168 groups
[j
] = groups
[n
- 1];
1173 if (recompute_overlap
)
1174 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1178 /* Set array->n_group and array->groups to n and groups.
1180 * Additionally, set the "nr" field of each group.
1182 static void set_array_groups(struct gpu_local_array_info
*array
,
1183 int n
, struct gpu_array_ref_group
**groups
)
1188 array
->groups
= groups
;
1190 for (i
= 0; i
< n
; ++i
)
1194 /* Group array references that should be considered together when
1195 * deciding whether to access them from private, shared or global memory.
1196 * Return -1 on error.
1198 * In particular, if two array references overlap and if one of them
1199 * is a write, then the two references are grouped together.
1200 * We first perform an initial grouping based only on the access relation.
1201 * After computing shared and private memory tiles, we check for
1202 * overlapping writes again, but this time taking into account
1203 * the depth of the effective tile.
1205 * Furthermore, if two groups admit a shared memory tile and if the
1206 * combination of the two also admits a shared memory tile, we merge
1209 * If the array contains structures, then there is no need to compute
1210 * reference groups since we do not map such arrays to private or shared
1213 static int group_array_references(struct ppcg_kernel
*kernel
,
1214 struct gpu_local_array_info
*local
, struct gpu_group_data
*data
)
1218 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1219 struct gpu_array_ref_group
**groups
;
1221 if (local
->array
->has_compound_element
)
1224 groups
= isl_calloc_array(ctx
, struct gpu_array_ref_group
*,
1225 local
->array
->n_ref
);
1229 n
= populate_array_references(local
, groups
, data
);
1231 n
= group_overlapping_writes(kernel
, n
, groups
, data
);
1233 for (i
= 0; i
< n
; ++i
)
1234 if (compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1237 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1239 n
= group_common_shared_memory_tile(kernel
, local
->array
,
1242 set_array_groups(local
, n
, groups
);
1247 for (i
= 0; i
< local
->array
->n_ref
; ++i
)
1248 gpu_array_ref_group_free(groups
[i
]);
1252 /* For each scalar in the input program, check if there are any
1253 * order dependences active inside the current kernel, within
1254 * the same iteration of "host_schedule".
1255 * If so, mark the scalar as force_private so that it will be
1256 * mapped to a register.
1258 static void check_scalar_live_ranges_in_host(struct ppcg_kernel
*kernel
,
1259 __isl_take isl_union_map
*host_schedule
)
1262 isl_union_map
*sched
;
1263 isl_union_set
*domain
;
1264 isl_union_map
*same_host_iteration
;
1266 kernel
->any_force_private
= 0;
1268 sched
= isl_union_map_universe(isl_union_map_copy(host_schedule
));
1269 domain
= isl_union_map_domain(sched
);
1271 same_host_iteration
= isl_union_map_apply_range(host_schedule
,
1272 isl_union_map_reverse(isl_union_map_copy(host_schedule
)));
1274 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1275 struct gpu_local_array_info
*local
= &kernel
->array
[i
];
1276 isl_union_map
*order
;
1278 local
->force_private
= 0;
1279 if (local
->array
->n_index
!= 0)
1281 order
= isl_union_map_copy(local
->array
->dep_order
);
1282 order
= isl_union_map_intersect_domain(order
,
1283 isl_union_set_copy(domain
));
1284 order
= isl_union_map_intersect_range(order
,
1285 isl_union_set_copy(domain
));
1286 order
= isl_union_map_intersect(order
,
1287 isl_union_map_copy(same_host_iteration
));
1288 if (!isl_union_map_is_empty(order
)) {
1289 local
->force_private
= 1;
1290 kernel
->any_force_private
= 1;
1292 isl_union_map_free(order
);
1295 isl_union_map_free(same_host_iteration
);
1296 isl_union_set_free(domain
);
1299 /* For each scalar in the input program, check if there are any
1300 * order dependences active inside the current kernel, within
1301 * the same iteration of the host schedule, i.e., the prefix
1302 * schedule at "node".
1303 * If so, mark the scalar as force_private so that it will be
1304 * mapped to a register.
1306 static void check_scalar_live_ranges(struct ppcg_kernel
*kernel
,
1307 __isl_keep isl_schedule_node
*node
)
1309 isl_union_map
*sched
;
1311 if (!kernel
->options
->live_range_reordering
)
1314 sched
= isl_schedule_node_get_prefix_schedule_union_map(node
);
1316 check_scalar_live_ranges_in_host(kernel
, sched
);
1319 /* Create a set of dimension data->thread_depth + data->n_thread
1320 * that equates the residue of the final data->n_thread dimensions
1321 * modulo the "sizes" to the thread identifiers.
1322 * "space" is a parameter space containing the thread identifiers.
1323 * Store the computed set in data->privatization.
1325 static void compute_privatization(struct gpu_group_data
*data
,
1326 __isl_take isl_space
*space
, int *sizes
)
1330 isl_local_space
*ls
;
1333 ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1334 space
= isl_space_set_from_params(space
);
1335 space
= isl_space_add_dims(space
, isl_dim_set
,
1336 data
->thread_depth
+ data
->n_thread
);
1337 set
= isl_set_universe(space
);
1338 space
= isl_set_get_space(set
);
1339 ls
= isl_local_space_from_space(space
);
1341 for (i
= 0; i
< data
->n_thread
; ++i
) {
1342 isl_aff
*aff
, *aff2
;
1348 aff
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1349 isl_dim_set
, data
->thread_depth
+ i
);
1350 v
= isl_val_int_from_si(ctx
, sizes
[i
]);
1351 aff
= isl_aff_mod_val(aff
, v
);
1352 snprintf(name
, sizeof(name
), "t%d", i
);
1353 pos
= isl_set_find_dim_by_name(set
, isl_dim_param
, name
);
1354 aff2
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1355 isl_dim_param
, pos
);
1356 aff
= isl_aff_sub(aff
, aff2
);
1357 c
= isl_equality_from_aff(aff
);
1358 set
= isl_set_add_constraint(set
, c
);
1361 isl_local_space_free(ls
);
1362 data
->privatization
= set
;
1365 /* Group references of all arrays in "kernel".
1366 * "node" points to the kernel mark.
1368 * We first extract all required schedule information into
1369 * a gpu_group_data structure and then consider each array
1372 int gpu_group_references(struct ppcg_kernel
*kernel
,
1373 __isl_keep isl_schedule_node
*node
)
1378 struct gpu_group_data data
;
1380 check_scalar_live_ranges(kernel
, node
);
1382 data
.scop
= kernel
->prog
->scop
;
1384 data
.kernel_depth
= isl_schedule_node_get_schedule_depth(node
);
1386 node
= isl_schedule_node_copy(node
);
1387 node
= gpu_tree_move_down_to_thread(node
, kernel
->core
);
1389 isl_schedule_node_get_prefix_schedule_relation(node
);
1390 data
.shared_sched
= isl_union_map_detect_equalities(data
.shared_sched
);
1392 node
= isl_schedule_node_child(node
, 0);
1393 data
.thread_depth
= isl_schedule_node_get_schedule_depth(node
);
1394 data
.n_thread
= isl_schedule_node_band_n_member(node
);
1395 data
.thread_sched
= isl_union_map_copy(data
.shared_sched
);
1396 data
.thread_sched
= isl_union_map_flat_range_product(data
.thread_sched
,
1397 isl_schedule_node_band_get_partial_schedule_union_map(node
));
1398 data
.thread_sched
= isl_union_map_detect_equalities(data
.thread_sched
);
1399 node
= isl_schedule_node_child(node
, 0);
1400 data
.full_sched
= isl_union_map_copy(data
.thread_sched
);
1401 data
.full_sched
= isl_union_map_flat_range_product(data
.full_sched
,
1402 isl_schedule_node_get_subtree_schedule_union_map(node
));
1403 isl_schedule_node_free(node
);
1405 space
= isl_union_set_get_space(kernel
->thread_filter
);
1406 compute_privatization(&data
, space
, kernel
->block_dim
);
1408 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1409 r
= group_array_references(kernel
, &kernel
->array
[i
], &data
);
1414 isl_union_map_free(data
.shared_sched
);
1415 isl_union_map_free(data
.thread_sched
);
1416 isl_union_map_free(data
.full_sched
);
1417 isl_set_free(data
.privatization
);
1422 /* Given a description of an array tile "tile" and the "space"
1426 * where D represents the first group->depth schedule dimensions
1427 * and A represents the array, construct an isl_multi_aff
1429 * { [D[i] -> A[a]] -> A'[a'] }
1431 * with A' a scaled down copy of A according to the shifts and strides
1432 * in "tile". In particular,
1434 * a' = (a + shift(i))/stride
1436 * "insert_array" represents
1440 * and is used to insert A into the domain of functions that only
1443 static __isl_give isl_multi_aff
*strided_tile(
1444 struct gpu_array_tile
*tile
, __isl_keep isl_space
*space
,
1445 __isl_keep isl_multi_aff
*insert_array
)
1449 isl_multi_aff
*shift
;
1450 isl_multi_val
*stride
;
1452 isl_local_space
*ls
;
1453 isl_multi_aff
*tiling
;
1455 ctx
= isl_space_get_ctx(space
);
1456 space2
= isl_space_domain(isl_space_copy(space
));
1457 ls
= isl_local_space_from_space(space2
);
1458 space2
= isl_space_range(isl_space_copy(space
));
1459 stride
= isl_multi_val_zero(space2
);
1460 shift
= isl_multi_aff_zero(isl_space_copy(space
));
1462 for (i
= 0; i
< tile
->n
; ++i
) {
1463 struct gpu_array_bound
*bound
= &tile
->bound
[i
];
1467 if (tile
->bound
[i
].shift
) {
1468 stride_i
= isl_val_copy(bound
->stride
);
1469 shift_i
= isl_aff_copy(bound
->shift
);
1471 stride_i
= isl_val_one(ctx
);
1472 shift_i
= isl_aff_zero_on_domain(
1473 isl_local_space_copy(ls
));
1476 stride
= isl_multi_val_set_val(stride
, i
, stride_i
);
1477 shift
= isl_multi_aff_set_aff(shift
, i
, shift_i
);
1479 isl_local_space_free(ls
);
1481 shift
= isl_multi_aff_pullback_multi_aff(shift
,
1482 isl_multi_aff_copy(insert_array
));
1484 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1485 tiling
= isl_multi_aff_add(tiling
, shift
);
1486 tiling
= isl_multi_aff_scale_down_multi_val(tiling
, stride
);
1491 /* Compute a tiling for the array reference group "group".
1493 * The tiling is of the form
1495 * { [D[i] -> A[a]] -> T[t] }
1497 * where D represents the first group->depth schedule dimensions,
1498 * A represents the global array and T represents the shared or
1499 * private memory tile. The name of T is the name of the local
1502 * If there is any stride in the accesses, then the mapping is
1504 * t = (a + shift(i))/stride - lb(i)
1506 * otherwise, it is simply
1510 void gpu_array_ref_group_compute_tiling(struct gpu_array_ref_group
*group
)
1514 struct gpu_array_tile
*tile
;
1515 struct gpu_array_info
*array
= group
->array
;
1517 isl_multi_aff
*tiling
, *lb
, *insert_array
;
1521 tile
= group
->private_tile
;
1523 tile
= group
->shared_tile
;
1527 space
= isl_map_get_space(group
->access
);
1528 dim
= isl_space_dim(space
, isl_dim_in
);
1529 space
= isl_space_drop_dims(space
, isl_dim_in
, group
->depth
,
1530 dim
- group
->depth
);
1531 insert_array
= isl_multi_aff_domain_map(isl_space_copy(space
));
1533 for (i
= 0; i
< tile
->n
; ++i
)
1534 if (tile
->bound
[i
].shift
)
1538 tiling
= strided_tile(tile
, space
, insert_array
);
1540 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1542 lb
= isl_multi_aff_zero(space
);
1543 for (i
= 0; i
< tile
->n
; ++i
) {
1544 isl_aff
*lb_i
= isl_aff_copy(tile
->bound
[i
].lb
);
1545 lb
= isl_multi_aff_set_aff(lb
, i
, lb_i
);
1547 lb
= isl_multi_aff_pullback_multi_aff(lb
, insert_array
);
1549 tiling
= isl_multi_aff_sub(tiling
, lb
);
1551 p
= isl_printer_to_str(isl_multi_aff_get_ctx(tiling
));
1552 p
= gpu_array_ref_group_print_name(group
, p
);
1553 local_name
= isl_printer_get_str(p
);
1554 isl_printer_free(p
);
1555 tiling
= isl_multi_aff_set_tuple_name(tiling
, isl_dim_out
, local_name
);
1558 tile
->tiling
= tiling
;