6 /* A group of array references in a kernel that should be handled together.
7 * If private_tile is not NULL, then it is mapped to registers.
8 * Otherwise, if shared_tile is not NULL, it is mapped to shared memory.
9 * Otherwise, it is accessed from global memory.
11 struct gpu_array_ref_group
{
12 /* The references in this group access this array. */
13 struct gpu_array_info
*array
;
14 /* Position of this group in the list of reference groups of array. */
17 /* The following fields are use during the construction of the groups.
18 * access is the combined access relation relative to the shared
19 * memory tiling. In particular, the domain of the map corresponds
20 * to the first shared_len dimensions of the computed schedule.
21 * write is set if any access in the group is a write.
22 * exact_write is set if all writes are definite writes.
23 * slice is set if there is at least one access in the group
24 * that refers to more than one element
31 /* The shared memory tile, NULL if none. */
32 struct gpu_array_tile
*shared_tile
;
34 /* The private memory tile, NULL if none. */
35 struct gpu_array_tile
*private_tile
;
37 /* References in this group; point to elements of a linked list. */
39 struct gpu_stmt_access
**refs
;
41 /* Last shared memory tile dimension that affects tile of this group. */
45 int gpu_group_references(struct gpu_gen
*gen
);
47 __isl_give isl_printer
*gpu_array_ref_group_print_name(
48 struct gpu_array_ref_group
*group
, __isl_take isl_printer
*p
);
49 void gpu_array_ref_group_compute_tiling(struct gpu_array_ref_group
*group
);
50 __isl_give isl_union_map
*gpu_array_ref_group_access_relation(
51 struct gpu_array_ref_group
*group
, int read
, int write
);
52 struct gpu_array_ref_group
*gpu_array_ref_group_free(
53 struct gpu_array_ref_group
*group
);