1 #include <isl/constraint.h>
4 #include "gpu_array_tile.h"
9 /* Print the name of the local copy of a given group of array references.
11 __isl_give isl_printer
*gpu_array_ref_group_print_name(
12 struct gpu_array_ref_group
*group
, __isl_take isl_printer
*p
)
16 if (group
->private_tile
)
17 p
= isl_printer_print_str(p
, "private_");
18 else if (group
->shared_tile
)
19 p
= isl_printer_print_str(p
, "shared_");
22 p
= isl_printer_print_str(p
, group
->array
->name
);
23 if (!global
&& group
->local_array
->n_group
> 1) {
24 p
= isl_printer_print_str(p
, "_");
25 p
= isl_printer_print_int(p
, group
->nr
);
31 /* Return the union of all read (read = 1) and/or write (write = 1)
32 * access relations in the group.
34 __isl_give isl_union_map
*gpu_array_ref_group_access_relation(
35 struct gpu_array_ref_group
*group
, int read
, int write
)
38 isl_union_map
*access
;
40 access
= isl_union_map_empty(isl_map_get_space(group
->access
));
41 for (i
= 0; i
< group
->n_ref
; ++i
) {
44 if (!((read
&& group
->refs
[i
]->read
) ||
45 (write
&& group
->refs
[i
]->write
)))
47 map_i
= isl_map_copy(group
->refs
[i
]->access
);
48 access
= isl_union_map_union(access
,
49 isl_union_map_from_map(map_i
));
55 /* Return the effective gpu_array_tile associated to "group" or
56 * NULL if there is no such gpu_array_tile.
57 * If we have computed both a private and a shared tile, then
58 * the private tile is used.
60 struct gpu_array_tile
*gpu_array_ref_group_tile(
61 struct gpu_array_ref_group
*group
)
63 if (group
->private_tile
)
64 return group
->private_tile
;
65 if (group
->shared_tile
)
66 return group
->shared_tile
;
70 /* Does the tile associated to "group" require unrolling of the schedule
71 * dimensions mapped to threads?
72 * Note that this can only happen for private tiles.
74 int gpu_array_ref_group_requires_unroll(struct gpu_array_ref_group
*group
)
76 struct gpu_array_tile
*tile
;
78 tile
= gpu_array_ref_group_tile(group
);
81 return tile
->requires_unroll
;
88 * or -a(p,i) - j = g f(e) if sign < 0,
89 * store a(p,i) in bound->shift and g (stride) in bound->stride.
90 * a(p,i) is assumed to be an expression in only the parameters
91 * and the input dimensions.
93 static void extract_stride(__isl_keep isl_constraint
*c
,
94 struct gpu_array_bound
*bound
, __isl_keep isl_val
*stride
, int sign
)
103 isl_val_free(bound
->stride
);
104 bound
->stride
= isl_val_copy(stride
);
106 space
= isl_constraint_get_space(c
);
107 space
= isl_space_domain(space
);
109 nparam
= isl_space_dim(space
, isl_dim_param
);
110 nvar
= isl_space_dim(space
, isl_dim_set
);
112 v
= isl_constraint_get_constant_val(c
);
115 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
116 aff
= isl_aff_set_constant_val(aff
, v
);
118 for (i
= 0; i
< nparam
; ++i
) {
119 if (!isl_constraint_involves_dims(c
, isl_dim_param
, i
, 1))
121 v
= isl_constraint_get_coefficient_val(c
, isl_dim_param
, i
);
124 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_param
, i
, v
);
127 for (i
= 0; i
< nvar
; ++i
) {
128 if (!isl_constraint_involves_dims(c
, isl_dim_in
, i
, 1))
130 v
= isl_constraint_get_coefficient_val(c
, isl_dim_in
, i
);
133 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_in
, i
, v
);
139 /* Given an equality constraint of a map with a single output dimension j,
140 * check if the constraint is of the form
142 * a(p,i) + j = g f(e)
144 * with a(p,i) an expression in the parameters and input dimensions
145 * and f(e) an expression in the existentially quantified variables.
146 * If so, and if g is larger than any such g from a previously considered
147 * constraint, then call extract_stride to record the stride information
150 static int check_stride_constraint(__isl_take isl_constraint
*c
, void *user
)
156 struct gpu_array_bound
*bound
= user
;
158 ctx
= isl_constraint_get_ctx(c
);
159 n_div
= isl_constraint_dim(c
, isl_dim_div
);
160 v
= isl_constraint_get_coefficient_val(c
, isl_dim_out
, 0);
162 if (n_div
&& (isl_val_is_one(v
) || isl_val_is_negone(v
))) {
163 int s
= isl_val_sgn(v
);
164 isl_val
*stride
= isl_val_zero(ctx
);
167 for (i
= 0; i
< n_div
; ++i
) {
168 v
= isl_constraint_get_coefficient_val(c
,
170 stride
= isl_val_gcd(stride
, v
);
172 if (!isl_val_is_zero(stride
) &&
173 isl_val_gt(stride
, bound
->stride
))
174 extract_stride(c
, bound
, stride
, s
);
176 isl_val_free(stride
);
180 isl_constraint_free(c
);
184 /* Given contraints on an array index i, check if we can find
185 * a shift a(p) and a stride g such that
189 * If so, record the information in bound and apply the mapping
190 * i -> (i + a(p))/g to the array index in bounds and return
191 * the new constraints.
192 * If not, simply return the original constraints.
194 * If bounds is a subset of the space
198 * then the bound recorded in bound->shift is of the form
202 * with s(D) equal to a(p) above.
203 * Next, we construct a mapping of the form
205 * [D -> i] -> [D -> (i + S(D))/g]
207 * This mapping is computed as follows.
208 * We first introduce "i" in the domain through precomposition
209 * with [D -> i] -> D obtaining
213 * Adding [D -> i] -> i produces
215 * [D -> i] -> i + s(D)
217 * and the domain product with [D -> i] -> D yields
219 * [D -> i] -> [D -> i + s(D)]
221 * Composition with [D -> i] -> [D -> i/g] gives the desired result.
223 static __isl_give isl_basic_map
*check_stride(struct gpu_array_bound
*bound
,
224 __isl_take isl_basic_map
*bounds
)
228 isl_basic_map
*shift
, *id
, *bmap
, *scale
;
232 bound
->stride
= NULL
;
234 hull
= isl_basic_map_affine_hull(isl_basic_map_copy(bounds
));
236 isl_basic_map_foreach_constraint(hull
, &check_stride_constraint
, bound
);
238 isl_basic_map_free(hull
);
243 shift
= isl_basic_map_from_aff(isl_aff_copy(bound
->shift
));
244 space
= isl_basic_map_get_space(bounds
);
245 bmap
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
246 shift
= isl_basic_map_apply_range(bmap
, shift
);
247 space
= isl_basic_map_get_space(bounds
);
248 id
= isl_basic_map_range_map(isl_basic_map_universe(space
));
249 shift
= isl_basic_map_sum(id
, shift
);
250 space
= isl_basic_map_get_space(bounds
);
251 id
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
252 shift
= isl_basic_map_range_product(id
, shift
);
254 space
= isl_space_domain(isl_basic_map_get_space(bounds
));
255 id
= isl_basic_map_identity(isl_space_map_from_set(space
));
256 space
= isl_space_range(isl_basic_map_get_space(bounds
));
257 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
258 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, 0, 1);
259 aff
= isl_aff_scale_down_val(aff
, isl_val_copy(bound
->stride
));
260 scale
= isl_basic_map_from_aff(aff
);
261 scale
= isl_basic_map_product(id
, scale
);
263 bmap
= isl_basic_map_apply_range(shift
, scale
);
264 bset
= isl_basic_set_apply(isl_basic_map_wrap(bounds
), bmap
);
265 bounds
= isl_basic_set_unwrap(bset
);
270 /* Data used in compute_array_dim_size and compute_size_in_direction.
272 * pos is the position of the variable representing the array index,
273 * i.e., the variable for which want to compute the size. This variable
274 * is also the last variable in the set.
276 struct gpu_size_info
{
278 struct gpu_array_bound
*bound
;
282 /* Given a constraint from the basic set describing the bounds on
283 * an array index, check if it is a lower bound, say m i >= b(x), and,
284 * if so, check whether the expression "i - ceil(b(x)/m) + 1" has a constant
285 * upper bound. If so, and if this bound is smaller than any bound
286 * derived from earlier constraints, set the size to this bound on
287 * the expression and the lower bound to ceil(b(x)/m).
289 static int compute_size_in_direction(__isl_take isl_constraint
*c
, void *user
)
291 struct gpu_size_info
*size
= user
;
298 nparam
= isl_basic_set_dim(size
->bset
, isl_dim_param
);
299 n_div
= isl_constraint_dim(c
, isl_dim_div
);
301 if (isl_constraint_involves_dims(c
, isl_dim_div
, 0, n_div
) ||
302 !isl_constraint_is_lower_bound(c
, isl_dim_set
, size
->pos
)) {
303 isl_constraint_free(c
);
307 aff
= isl_constraint_get_bound(c
, isl_dim_set
, size
->pos
);
308 aff
= isl_aff_ceil(aff
);
310 lb
= isl_aff_copy(aff
);
312 aff
= isl_aff_neg(aff
);
313 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, size
->pos
, 1);
315 v
= isl_basic_set_max_val(size
->bset
, aff
);
318 if (isl_val_is_int(v
)) {
319 v
= isl_val_add_ui(v
, 1);
320 if (!size
->bound
->size
|| isl_val_lt(v
, size
->bound
->size
)) {
321 isl_val_free(size
->bound
->size
);
322 size
->bound
->size
= isl_val_copy(v
);
323 lb
= isl_aff_drop_dims(lb
, isl_dim_in
, size
->pos
, 1);
324 isl_aff_free(size
->bound
->lb
);
325 size
->bound
->lb
= isl_aff_copy(lb
);
331 isl_constraint_free(c
);
336 /* Given a basic map "bounds" that maps parameters and input dimensions
337 * to a single output dimension, look for an expression in the parameters
338 * and input dimensions such that the range of the output dimension shifted
339 * by this expression is a constant.
341 * In particular, we currently only consider lower bounds on the output
342 * dimension as candidate expressions.
344 static int compute_array_dim_size(struct gpu_array_bound
*bound
,
345 __isl_take isl_basic_map
*bounds
)
347 struct gpu_size_info size
;
349 bounds
= isl_basic_map_detect_equalities(bounds
);
350 bounds
= check_stride(bound
, bounds
);
356 size
.pos
= isl_basic_map_dim(bounds
, isl_dim_in
);
357 size
.bset
= isl_basic_map_wrap(bounds
);
358 size
.bset
= isl_basic_set_flatten(size
.bset
);
359 size
.bset
= isl_set_simple_hull(isl_basic_set_compute_divs(size
.bset
));
360 isl_basic_set_foreach_constraint(size
.bset
, &compute_size_in_direction
,
362 isl_basic_set_free(size
.bset
);
364 return bound
->size
? 0 : -1;
367 /* Check if we can find a memory tile for the given array
368 * based on the given accesses, and if so, put the results in "tile".
370 * We project the accesses on each index in turn and look for a parametric
371 * offset such that the size is constant.
373 static int can_tile(__isl_keep isl_map
*access
, struct gpu_array_tile
*tile
)
377 for (i
= 0; i
< tile
->n
; ++i
) {
381 access_i
= isl_map_copy(access
);
382 access_i
= isl_map_project_out(access_i
, isl_dim_out
, 0, i
);
383 access_i
= isl_map_project_out(access_i
, isl_dim_out
,
384 1, tile
->n
- (i
+ 1));
385 access_i
= isl_map_compute_divs(access_i
);
386 hull
= isl_map_simple_hull(access_i
);
387 if (compute_array_dim_size(&tile
->bound
[i
], hull
) < 0)
394 /* Internal data structure for gpu_group_references.
396 * scop represents the input scop.
397 * kernel_depth is the schedule depth where the kernel launch will
398 * be introduced, i.e., it is the depth of the band that is mapped
400 * thread_depth is the schedule depth where the thread mark is located,
401 * i.e., it is the depth of the band that is mapped to threads and also
402 * the schedule depth at which the copying to/from shared/private memory
403 * is computed. The copy operation may then later be hoisted to
405 * n_thread is the number of schedule dimensions in the band that
406 * is mapped to threads.
407 * privatization lives in the range of thread_sched (i.e., it is
408 * of dimension thread_depth + n_thread) and encodes the mapping
409 * to thread identifiers (as parameters).
410 * host_sched contains the kernel_depth dimensions of the host schedule.
411 * shared_sched contains the first thread_depth dimensions of the
413 * thread_sched contains the first (thread_depth + n_thread) dimensions
414 * of the kernel schedule.
415 * full_sched is a union_map representation of the entire kernel schedule.
417 struct gpu_group_data
{
418 struct ppcg_scop
*scop
;
422 isl_set
*privatization
;
423 isl_union_map
*host_sched
;
424 isl_union_map
*shared_sched
;
425 isl_union_map
*thread_sched
;
426 isl_union_map
*full_sched
;
429 /* Construct a map from domain_dim to domain_dim that increments
430 * the dimension at position "pos" and leaves all other dimensions
433 static __isl_give isl_map
*next(__isl_take isl_space
*domain_dim
, int pos
)
436 int len
= isl_space_dim(domain_dim
, isl_dim_set
);
441 dim
= isl_space_map_from_set(domain_dim
);
442 next
= isl_basic_map_universe(isl_space_copy(dim
));
443 ls
= isl_local_space_from_space(dim
);
445 for (i
= 0; i
< len
; ++i
) {
448 c
= isl_equality_alloc(isl_local_space_copy(ls
));
449 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, 1);
450 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
452 c
= isl_constraint_set_constant_si(c
, 1);
453 next
= isl_basic_map_add_constraint(next
, c
);
456 isl_local_space_free(ls
);
458 return isl_map_from_basic_map(next
);
461 /* Check if the given access is coalesced (or if there is no point
462 * in trying to coalesce the access by mapping the array to shared memory).
463 * That is, check whether incrementing the dimension that will get
464 * wrapped over the last thread index results in incrementing
465 * the last array index.
467 * If no two consecutive array elements are ever accessed by "access",
468 * then mapping the corresponding array to shared memory will not
469 * improve coalescing. In fact, the copying will likely be performed
470 * by a single thread. Consider the access as coalesced such that
471 * the caller will not try and map the array to shared memory just
472 * to improve coalescing.
474 * This function is only called for access relations without reuse and
475 * kernels with at least one thread identifier.
477 static int access_is_coalesced(struct gpu_group_data
*data
,
478 __isl_keep isl_union_map
*access
)
483 isl_map
*next_thread_x
;
484 isl_map
*next_element
;
486 int coalesced
, empty
;
488 access
= isl_union_map_copy(access
);
489 access
= isl_union_map_apply_domain(access
,
490 isl_union_map_copy(data
->full_sched
));
491 access_map
= isl_map_from_union_map(access
);
493 space
= isl_map_get_space(access_map
);
494 space
= isl_space_range(space
);
495 next_element
= next(space
, isl_space_dim(space
, isl_dim_set
) - 1);
497 accessed
= isl_map_range(isl_map_copy(access_map
));
498 map
= isl_map_copy(next_element
);
499 map
= isl_map_intersect_domain(map
, isl_set_copy(accessed
));
500 map
= isl_map_intersect_range(map
, accessed
);
501 empty
= isl_map_is_empty(map
);
504 if (empty
< 0 || empty
) {
505 isl_map_free(next_element
);
506 isl_map_free(access_map
);
510 space
= isl_map_get_space(access_map
);
511 space
= isl_space_domain(space
);
512 next_thread_x
= next(space
, data
->thread_depth
+ data
->n_thread
- 1);
514 map
= isl_map_apply_domain(next_thread_x
, isl_map_copy(access_map
));
515 map
= isl_map_apply_range(map
, access_map
);
517 coalesced
= isl_map_is_subset(map
, next_element
);
519 isl_map_free(next_element
);
525 /* Replace the host schedule dimensions in the access relation "access"
526 * by parameters, so that they are treated as fixed when checking for reuse
527 * (within a kernel) or whether two consecutive elements are accessed
530 static __isl_give isl_union_map
*localize_access(struct gpu_group_data
*data
,
531 __isl_take isl_union_map
*access
)
539 umap
= isl_union_map_copy(data
->host_sched
);
540 space
= isl_union_map_get_space(umap
);
541 n
= data
->kernel_depth
;
542 ids
= ppcg_scop_generate_names(data
->scop
, n
, "__ppcg_host_");
543 param
= parametrization(space
, n
, 0, ids
);
544 isl_id_list_free(ids
);
545 umap
= isl_union_map_intersect_range(umap
,
546 isl_union_set_from_set(param
));
547 access
= isl_union_map_intersect_domain(access
,
548 isl_union_map_domain(umap
));
553 /* Given an access relation in terms of at least data->thread_depth initial
554 * dimensions of the computed schedule, check if it is bijective for
555 * fixed values of the first data->thread_depth dimensions.
556 * We perform this check by equating these dimensions to parameters.
558 static int access_is_bijective(struct gpu_group_data
*data
,
559 __isl_keep isl_map
*access
)
567 access
= isl_map_copy(access
);
568 space
= isl_space_params(isl_map_get_space(access
));
569 ids
= ppcg_scop_generate_names(data
->scop
, data
->thread_depth
, "s");
570 dim
= isl_map_dim(access
, isl_dim_in
);
571 par
= parametrization(space
, dim
, 0, ids
);
572 isl_id_list_free(ids
);
573 access
= isl_map_intersect_domain(access
, par
);
574 res
= isl_map_is_bijective(access
);
575 isl_map_free(access
);
580 /* Compute the number of outer schedule tile dimensions that affect
581 * the offset of "tile".
582 * If there is no such dimension, then return the index
583 * of the first kernel dimension, i.e., data->kernel_depth.
585 static int compute_tile_depth(struct gpu_group_data
*data
,
586 struct gpu_array_tile
*tile
)
590 for (j
= data
->thread_depth
- 1; j
>= data
->kernel_depth
; --j
) {
591 for (i
= 0; i
< tile
->n
; ++i
) {
595 lb
= tile
->bound
[i
].lb
;
596 if (isl_aff_involves_dims(lb
, isl_dim_in
, j
, 1))
599 shift
= tile
->bound
[i
].shift
;
602 if (isl_aff_involves_dims(shift
, isl_dim_in
, j
, 1))
612 /* Adjust the fields of "tile" to reflect the new input dimension "new_dim",
613 * where "old_dim" is the old dimension.
614 * The dimension beyond "new_dim" are assumed not to affect the tile,
615 * so they can simply be dropped.
617 static int tile_adjust_depth(struct gpu_array_tile
*tile
,
618 int old_dim
, int new_dim
)
622 if (old_dim
== new_dim
)
625 for (i
= 0; i
< tile
->n
; ++i
) {
626 tile
->bound
[i
].lb
= isl_aff_drop_dims(tile
->bound
[i
].lb
,
627 isl_dim_in
, new_dim
, old_dim
- new_dim
);
628 if (!tile
->bound
[i
].lb
)
630 if (!tile
->bound
[i
].shift
)
632 tile
->bound
[i
].shift
= isl_aff_drop_dims(tile
->bound
[i
].shift
,
633 isl_dim_in
, new_dim
, old_dim
- new_dim
);
634 if (!tile
->bound
[i
].shift
)
641 /* Determine the number of schedule dimensions that affect the offset of the
642 * shared or private tile and store the result in group->depth, with
643 * a lower bound of data->kernel_depth.
644 * If there is no tile defined on the array reference group,
645 * then set group->depth to data->thread_depth.
646 * Also adjust the fields of the tile to only refer to the group->depth
647 * outer schedule dimensions.
649 static int set_depth(struct gpu_group_data
*data
,
650 struct gpu_array_ref_group
*group
)
652 struct gpu_array_tile
*tile
;
654 group
->depth
= data
->thread_depth
;
656 tile
= gpu_array_ref_group_tile(group
);
660 group
->depth
= compute_tile_depth(data
, tile
);
661 if (tile_adjust_depth(tile
, data
->thread_depth
, group
->depth
) < 0)
667 /* Fill up the groups array with singleton groups, i.e., one group
668 * per reference, initializing the array, access, write, n_ref and refs fields.
669 * In particular the access field is initialized to the scheduled
670 * access relation of the array reference.
672 * Return the number of elements initialized, i.e., the number of
673 * active references in the current kernel.
675 static int populate_array_references(struct gpu_local_array_info
*local
,
676 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
680 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->shared_sched
);
683 for (i
= 0; i
< local
->array
->n_ref
; ++i
) {
686 struct gpu_array_ref_group
*group
;
687 struct gpu_stmt_access
*access
= local
->array
->refs
[i
];
689 map
= isl_map_copy(access
->access
);
690 umap
= isl_union_map_from_map(map
);
691 umap
= isl_union_map_apply_domain(umap
,
692 isl_union_map_copy(data
->shared_sched
));
694 if (isl_union_map_is_empty(umap
)) {
695 isl_union_map_free(umap
);
699 map
= isl_map_from_union_map(umap
);
700 map
= isl_map_detect_equalities(map
);
702 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
705 group
->local_array
= local
;
706 group
->array
= local
->array
;
708 group
->write
= access
->write
;
709 group
->exact_write
= access
->exact_write
;
710 group
->slice
= access
->n_index
< local
->array
->n_index
;
711 group
->refs
= &local
->array
->refs
[i
];
720 /* If group->n_ref == 1, then group->refs was set by
721 * populate_array_references to point directly into
722 * group->array->refs and should not be freed.
723 * If group->n_ref > 1, then group->refs was set by join_groups
724 * to point to a newly allocated array.
726 struct gpu_array_ref_group
*gpu_array_ref_group_free(
727 struct gpu_array_ref_group
*group
)
731 gpu_array_tile_free(group
->shared_tile
);
732 gpu_array_tile_free(group
->private_tile
);
733 isl_map_free(group
->access
);
734 if (group
->n_ref
> 1)
740 /* Check if the access relations of group1 and group2 overlap within
743 static int accesses_overlap(struct gpu_array_ref_group
*group1
,
744 struct gpu_array_ref_group
*group2
)
748 disjoint
= isl_map_is_disjoint(group1
->access
, group2
->access
);
755 /* Combine the given two groups into a single group, containing
756 * the references of both groups.
758 static struct gpu_array_ref_group
*join_groups(
759 struct gpu_array_ref_group
*group1
,
760 struct gpu_array_ref_group
*group2
)
764 struct gpu_array_ref_group
*group
;
766 if (!group1
|| !group2
)
769 ctx
= isl_map_get_ctx(group1
->access
);
770 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
773 group
->local_array
= group1
->local_array
;
774 group
->array
= group1
->array
;
775 group
->access
= isl_map_union(isl_map_copy(group1
->access
),
776 isl_map_copy(group2
->access
));
777 group
->write
= group1
->write
|| group2
->write
;
778 group
->exact_write
= group1
->exact_write
&& group2
->exact_write
;
779 group
->slice
= group1
->slice
|| group2
->slice
;
780 group
->n_ref
= group1
->n_ref
+ group2
->n_ref
;
781 group
->refs
= isl_alloc_array(ctx
, struct gpu_stmt_access
*,
784 return gpu_array_ref_group_free(group
);
785 for (i
= 0; i
< group1
->n_ref
; ++i
)
786 group
->refs
[i
] = group1
->refs
[i
];
787 for (i
= 0; i
< group2
->n_ref
; ++i
)
788 group
->refs
[group1
->n_ref
+ i
] = group2
->refs
[i
];
793 /* Combine the given two groups into a single group and free
794 * the original two groups.
796 static struct gpu_array_ref_group
*join_groups_and_free(
797 struct gpu_array_ref_group
*group1
,
798 struct gpu_array_ref_group
*group2
)
800 struct gpu_array_ref_group
*group
;
802 group
= join_groups(group1
, group2
);
803 gpu_array_ref_group_free(group1
);
804 gpu_array_ref_group_free(group2
);
808 /* Report that the array reference group with the given access relation
809 * is not mapped to shared memory in the given kernel because
810 * it does not exhibit any reuse and is considered to be coalesced.
812 static void report_no_reuse_and_coalesced(struct ppcg_kernel
*kernel
,
813 __isl_keep isl_union_map
*access
)
818 ctx
= isl_union_map_get_ctx(access
);
819 p
= isl_printer_to_file(ctx
, stdout
);
820 p
= isl_printer_print_str(p
, "Array reference group ");
821 p
= isl_printer_print_union_map(p
, access
);
822 p
= isl_printer_print_str(p
,
823 " not considered for mapping to shared memory in kernel");
824 p
= isl_printer_print_int(p
, kernel
->id
);
825 p
= isl_printer_print_str(p
,
826 " because it exhibits no reuse and is considered to be coalesced");
827 p
= isl_printer_end_line(p
);
831 /* Given an access relation in terms of the data->thread_depth initial
832 * dimensions of the computed schedule and the thread identifiers
833 * (as parameters), check if the use of the corresponding private tile
834 * requires unrolling.
836 * If we are creating a private tile because we are forced to,
837 * then no unrolling is required.
838 * Otherwise we check if "access" is bijective and unrolling
839 * is required if it is not. Note that the access relation
840 * has already been determined to be bijective before the introduction
841 * of the thread identifiers and the removal of the schedule dimensions
842 * that are mapped to these threads. If the access relation is no longer
843 * bijective, then this means that more than one value of one of those
844 * schedule dimensions is mapped to the same thread and therefore
845 * unrolling is required.
847 static int check_requires_unroll(struct gpu_group_data
*data
,
848 __isl_keep isl_map
*access
, int force_private
)
854 bijective
= access_is_bijective(data
, access
);
860 /* Compute the private and/or shared memory tiles for the array
861 * reference group "group" of array "array".
862 * Return 0 on success and -1 on error.
864 * If the array is a read-only scalar or if the user requested
865 * not to use shared or private memory, then we do not need to do anything.
867 * If any reference in the reference group accesses more than one element,
868 * then we would have to make sure that the layout in shared memory
869 * is the same as that in global memory. Since we do not handle this yet
870 * (and it may not even be possible), we refuse to map to private or
871 * shared memory in such cases.
873 * If the array group involves any may writes (that are not must writes),
874 * then we would have to make sure that we load the data into shared/private
875 * memory first in case the data is not written by the kernel
876 * (but still written back out to global memory).
877 * Since we don't have any such mechanism at the moment, we don't
878 * compute shared/private tiles for groups involving may writes.
880 * We only try to compute a shared memory tile if there is any reuse
881 * or if the access is not coalesced.
882 * Reuse and coalescing are checked within the given kernel.
884 * For computing a private memory tile, we also require that there is
885 * some reuse. Moreover, we require that the access is private
886 * to the thread. That is, we check that any given array element
887 * is only accessed by a single thread.
888 * We compute an access relation that maps the outer
889 * data->thread_depth + data->n_thread schedule dimensions.
890 * The latter data->n_thread will be mapped to thread identifiers.
891 * We actually check that those iterators that will be wrapped
892 * partition the array space. This check is stricter than necessary
893 * since several iterations may be mapped onto the same thread
894 * and then they could be allowed to access the same memory elements,
895 * but our check does not allow this situation.
897 * We also check that the index expression only depends on parallel
898 * loops. That way, we can move those loops innermost and unroll them.
899 * Again, we use a test that is stricter than necessary.
900 * We actually check whether the index expression only depends
901 * on the iterators that are wrapped over the threads.
902 * These are necessarily parallel, but there may be more parallel loops.
904 * Combining the injectivity of the first test with the single-valuedness
905 * of the second test, we simply test for bijectivity.
907 * If the use of the private tile requires unrolling, but some
908 * of the other arrays are forcibly mapped to private memory,
909 * then we do not allow the use of this private tile since
910 * we cannot move the schedule dimensions that need to be unrolled down
911 * without performing some kind of expansion on those arrays
912 * that are forcibly mapped to private memory.
914 * If the array is marked force_private, then we bypass all checks
915 * and assume we can (and should) use registers.
917 * If it turns out we can (or have to) use registers, we compute
918 * the private memory tile size using can_tile, after introducing a dependence
919 * on the thread indices.
921 static int compute_group_bounds_core(struct ppcg_kernel
*kernel
,
922 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
924 isl_ctx
*ctx
= isl_space_get_ctx(group
->array
->space
);
925 isl_union_map
*access
, *local
;
926 int n_index
= group
->array
->n_index
;
927 int no_reuse
, coalesced
;
929 int force_private
= group
->local_array
->force_private
;
930 int use_shared
= kernel
->options
->use_shared_memory
&&
932 int use_private
= force_private
|| kernel
->options
->use_private_memory
;
936 if (!use_shared
&& !use_private
)
938 if (gpu_array_is_read_only_scalar(group
->array
))
940 if (!force_private
&& !group
->exact_write
)
945 access
= gpu_array_ref_group_access_relation(group
, 1, 1);
946 local
= localize_access(data
, isl_union_map_copy(access
));
947 no_reuse
= isl_union_map_is_injective(local
);
950 if (use_shared
&& no_reuse
)
951 coalesced
= access_is_coalesced(data
, local
);
952 isl_union_map_free(local
);
954 if (r
>= 0 && kernel
->options
->debug
->verbose
&&
955 use_shared
&& no_reuse
&& coalesced
)
956 report_no_reuse_and_coalesced(kernel
, access
);
958 if (use_shared
&& (!no_reuse
|| !coalesced
)) {
959 group
->shared_tile
= gpu_array_tile_create(ctx
,
960 group
->array
->n_index
);
961 if (!group
->shared_tile
)
963 else if (!can_tile(group
->access
, group
->shared_tile
))
965 gpu_array_tile_free(group
->shared_tile
);
968 if (r
< 0 || (!force_private
&& (!use_private
|| no_reuse
))) {
969 isl_union_map_free(access
);
973 access
= isl_union_map_apply_domain(access
,
974 isl_union_map_copy(data
->thread_sched
));
976 acc
= isl_map_from_union_map(access
);
978 if (!force_private
&& !access_is_bijective(data
, acc
)) {
983 acc
= isl_map_intersect_domain(acc
, isl_set_copy(data
->privatization
));
984 acc
= isl_map_project_out(acc
, isl_dim_in
, data
->thread_depth
,
986 requires_unroll
= check_requires_unroll(data
, acc
, force_private
);
987 if (requires_unroll
< 0 ||
988 (requires_unroll
&& kernel
->any_force_private
)) {
990 return requires_unroll
< 0 ? -1 : 0;
993 group
->private_tile
= gpu_array_tile_create(ctx
, n_index
);
994 if (!group
->private_tile
) {
998 group
->private_tile
->requires_unroll
= requires_unroll
;
999 if (!can_tile(acc
, group
->private_tile
))
1000 group
->private_tile
= gpu_array_tile_free(group
->private_tile
);
1004 if (force_private
&& !group
->private_tile
)
1005 isl_die(ctx
, isl_error_internal
,
1006 "unable to map array reference group to registers",
1012 /* Compute the private and/or shared memory tiles for the array
1013 * reference group "group" of array "array" and set the tile depth.
1014 * Return 0 on success and -1 on error.
1016 static int compute_group_bounds(struct ppcg_kernel
*kernel
,
1017 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
1021 if (compute_group_bounds_core(kernel
, group
, data
) < 0)
1023 if (set_depth(data
, group
) < 0)
1029 /* If two groups have overlapping access relations (as determined by
1030 * the "overlap" function) and if one of them involves a write,
1031 * then merge the two groups into one.
1032 * If "compute_bounds" is set, then call compute_group_bounds
1033 * on the merged groups.
1035 * Return the updated number of groups.
1036 * Return -1 on error.
1038 static int group_writes(struct ppcg_kernel
*kernel
,
1039 int n
, struct gpu_array_ref_group
**groups
,
1040 int (*overlap
)(struct gpu_array_ref_group
*group1
,
1041 struct gpu_array_ref_group
*group2
), int compute_bounds
,
1042 struct gpu_group_data
*data
)
1046 for (i
= 0; i
< n
; ++i
) {
1047 for (j
= n
- 1; j
> i
; --j
) {
1048 if (!groups
[i
]->write
&& !groups
[j
]->write
)
1051 if (!overlap(groups
[i
], groups
[j
]))
1054 groups
[i
] = join_groups_and_free(groups
[i
], groups
[j
]);
1056 groups
[j
] = groups
[n
- 1];
1057 groups
[n
- 1] = NULL
;
1062 if (compute_bounds
&&
1063 compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1071 /* If two groups have overlapping access relations (within the innermost
1072 * loop) and if one of them involves a write, then merge the two groups
1075 * Return the updated number of groups.
1077 static int group_overlapping_writes(struct ppcg_kernel
*kernel
,
1078 int n
, struct gpu_array_ref_group
**groups
,
1079 struct gpu_group_data
*data
)
1081 return group_writes(kernel
, n
, groups
, &accesses_overlap
, 0, data
);
1084 /* Check if the access relations of group1 and group2 overlap within
1085 * the outermost min(group1->depth, group2->depth) loops.
1087 static int depth_accesses_overlap(struct gpu_array_ref_group
*group1
,
1088 struct gpu_array_ref_group
*group2
)
1093 isl_map
*map_i
, *map_j
, *map
;
1095 depth
= group1
->depth
;
1096 if (group2
->depth
< depth
)
1097 depth
= group2
->depth
;
1098 map_i
= isl_map_copy(group1
->access
);
1099 dim
= isl_map_dim(map_i
, isl_dim_in
);
1100 map_i
= isl_map_eliminate(map_i
, isl_dim_in
, depth
, dim
- depth
);
1101 map_j
= isl_map_copy(group2
->access
);
1102 map_j
= isl_map_eliminate(map_j
, isl_dim_in
, depth
, dim
- depth
);
1103 map
= isl_map_intersect(map_i
, map_j
);
1104 empty
= isl_map_is_empty(map
);
1110 /* If two groups have overlapping access relations (within the outer
1111 * depth loops) and if one of them involves a write,
1112 * then merge the two groups into one.
1114 * Return the updated number of groups.
1116 static int group_depth_overlapping_writes(struct ppcg_kernel
*kernel
,
1117 int n
, struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1119 return group_writes(kernel
, n
, groups
, &depth_accesses_overlap
, 1,
1123 /* Is the size of the tile specified by "tile" smaller than the sum of
1124 * the sizes of the tiles specified by "tile1" and "tile2"?
1126 static int smaller_tile(struct gpu_array_tile
*tile
,
1127 struct gpu_array_tile
*tile1
, struct gpu_array_tile
*tile2
)
1130 isl_val
*size
, *size1
, *size2
;
1132 size
= gpu_array_tile_size(tile
);
1133 size1
= gpu_array_tile_size(tile1
);
1134 size2
= gpu_array_tile_size(tile2
);
1136 size
= isl_val_sub(size
, size1
);
1137 size
= isl_val_sub(size
, size2
);
1138 smaller
= isl_val_is_neg(size
);
1145 /* Given an initial grouping of array references and shared memory tiles
1146 * for each group that allows for a shared memory tile, merge two groups
1147 * if both have a shared memory tile, the merged group also has
1148 * a shared memory tile and the size of the tile for the merge group
1149 * is smaller than the sum of the tile sizes of the individual groups.
1151 * If merging two groups decreases the depth of the tile of
1152 * one or both of the two groups, then we need to check for overlapping
1155 * Return the number of groups after merging.
1156 * Return -1 on error.
1158 static int group_common_shared_memory_tile(struct ppcg_kernel
*kernel
,
1159 struct gpu_array_info
*array
, int n
,
1160 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1163 int recompute_overlap
= 0;
1164 isl_ctx
*ctx
= isl_space_get_ctx(array
->space
);
1166 for (i
= 0; i
< n
; ++i
) {
1167 if (!groups
[i
]->shared_tile
)
1169 for (j
= n
- 1; j
> i
; --j
) {
1172 struct gpu_array_ref_group
*group
;
1174 if (!groups
[j
]->shared_tile
)
1177 map
= isl_map_intersect(isl_map_copy(groups
[i
]->access
),
1178 isl_map_copy(groups
[j
]->access
));
1179 empty
= isl_map_is_empty(map
);
1185 group
= join_groups(groups
[i
], groups
[j
]);
1186 if (compute_group_bounds(kernel
, group
, data
) < 0) {
1187 gpu_array_ref_group_free(group
);
1190 if (!group
->shared_tile
||
1191 !smaller_tile(group
->shared_tile
,
1192 groups
[i
]->shared_tile
,
1193 groups
[j
]->shared_tile
)) {
1194 gpu_array_ref_group_free(group
);
1198 if (group
->depth
< groups
[i
]->depth
||
1199 group
->depth
< groups
[j
]->depth
)
1200 recompute_overlap
= 1;
1201 gpu_array_ref_group_free(groups
[i
]);
1202 gpu_array_ref_group_free(groups
[j
]);
1205 groups
[j
] = groups
[n
- 1];
1210 if (recompute_overlap
)
1211 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1215 /* Set array->n_group and array->groups to n and groups.
1217 * Additionally, set the "nr" field of each group.
1219 static void set_array_groups(struct gpu_local_array_info
*array
,
1220 int n
, struct gpu_array_ref_group
**groups
)
1225 array
->groups
= groups
;
1227 for (i
= 0; i
< n
; ++i
)
1231 /* Combine all groups in "groups" into a single group and return
1232 * the new number of groups (1 or 0 if there were no groups to start with).
1234 static int join_all_groups(int n
, struct gpu_array_ref_group
**groups
)
1238 for (i
= n
- 1; i
> 0; --i
) {
1239 groups
[0] = join_groups_and_free(groups
[0], groups
[i
]);
1247 /* Group array references that should be considered together when
1248 * deciding whether to access them from private, shared or global memory.
1249 * Return -1 on error.
1251 * In particular, if two array references overlap and if one of them
1252 * is a write, then the two references are grouped together.
1253 * We first perform an initial grouping based only on the access relation.
1254 * After computing shared and private memory tiles, we check for
1255 * overlapping writes again, but this time taking into account
1256 * the depth of the effective tile.
1258 * Furthermore, if two groups admit a shared memory tile and if the
1259 * combination of the two also admits a shared memory tile, we merge
1262 * If the array contains structures, then we compute a single
1263 * reference group without trying to find any tiles
1264 * since we do not map such arrays to private or shared
1267 static int group_array_references(struct ppcg_kernel
*kernel
,
1268 struct gpu_local_array_info
*local
, struct gpu_group_data
*data
)
1272 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1273 struct gpu_array_ref_group
**groups
;
1275 groups
= isl_calloc_array(ctx
, struct gpu_array_ref_group
*,
1276 local
->array
->n_ref
);
1280 n
= populate_array_references(local
, groups
, data
);
1282 if (local
->array
->has_compound_element
) {
1283 n
= join_all_groups(n
, groups
);
1284 set_array_groups(local
, n
, groups
);
1288 n
= group_overlapping_writes(kernel
, n
, groups
, data
);
1290 for (i
= 0; i
< n
; ++i
)
1291 if (compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1294 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1296 n
= group_common_shared_memory_tile(kernel
, local
->array
,
1299 set_array_groups(local
, n
, groups
);
1304 for (i
= 0; i
< local
->array
->n_ref
; ++i
)
1305 gpu_array_ref_group_free(groups
[i
]);
1309 /* For each scalar in the input program, check if there are any
1310 * order dependences active inside the current kernel, within
1311 * the same iteration of "host_schedule".
1312 * If so, mark the scalar as force_private so that it will be
1313 * mapped to a register.
1315 static void check_scalar_live_ranges_in_host(struct ppcg_kernel
*kernel
,
1316 __isl_take isl_union_map
*host_schedule
)
1319 isl_union_map
*sched
;
1320 isl_union_set
*domain
;
1321 isl_union_map
*same_host_iteration
;
1323 kernel
->any_force_private
= 0;
1325 sched
= isl_union_map_universe(isl_union_map_copy(host_schedule
));
1326 domain
= isl_union_map_domain(sched
);
1328 same_host_iteration
= isl_union_map_apply_range(host_schedule
,
1329 isl_union_map_reverse(isl_union_map_copy(host_schedule
)));
1331 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1332 struct gpu_local_array_info
*local
= &kernel
->array
[i
];
1333 isl_union_map
*order
;
1335 local
->force_private
= 0;
1336 if (local
->array
->n_index
!= 0)
1338 order
= isl_union_map_copy(local
->array
->dep_order
);
1339 order
= isl_union_map_intersect_domain(order
,
1340 isl_union_set_copy(domain
));
1341 order
= isl_union_map_intersect_range(order
,
1342 isl_union_set_copy(domain
));
1343 order
= isl_union_map_intersect(order
,
1344 isl_union_map_copy(same_host_iteration
));
1345 if (!isl_union_map_is_empty(order
)) {
1346 local
->force_private
= 1;
1347 kernel
->any_force_private
= 1;
1349 isl_union_map_free(order
);
1352 isl_union_map_free(same_host_iteration
);
1353 isl_union_set_free(domain
);
1356 /* For each scalar in the input program, check if there are any
1357 * order dependences active inside the current kernel, within
1358 * the same iteration of the host schedule, i.e., the prefix
1359 * schedule at "node".
1360 * If so, mark the scalar as force_private so that it will be
1361 * mapped to a register.
1363 static void check_scalar_live_ranges(struct ppcg_kernel
*kernel
,
1364 __isl_keep isl_schedule_node
*node
)
1366 isl_union_map
*sched
;
1368 if (!kernel
->options
->live_range_reordering
)
1371 sched
= isl_schedule_node_get_prefix_schedule_union_map(node
);
1373 check_scalar_live_ranges_in_host(kernel
, sched
);
1376 /* Create a set of dimension data->thread_depth + data->n_thread
1377 * that equates the residue of the final data->n_thread dimensions
1378 * modulo the "sizes" to the thread identifiers.
1379 * "space" is a parameter space containing the thread identifiers.
1380 * Store the computed set in data->privatization.
1382 static void compute_privatization(struct gpu_group_data
*data
,
1383 __isl_take isl_space
*space
, int *sizes
)
1387 isl_local_space
*ls
;
1390 ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1391 space
= isl_space_set_from_params(space
);
1392 space
= isl_space_add_dims(space
, isl_dim_set
,
1393 data
->thread_depth
+ data
->n_thread
);
1394 set
= isl_set_universe(space
);
1395 space
= isl_set_get_space(set
);
1396 ls
= isl_local_space_from_space(space
);
1398 for (i
= 0; i
< data
->n_thread
; ++i
) {
1399 isl_aff
*aff
, *aff2
;
1405 aff
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1406 isl_dim_set
, data
->thread_depth
+ i
);
1407 v
= isl_val_int_from_si(ctx
, sizes
[i
]);
1408 aff
= isl_aff_mod_val(aff
, v
);
1409 snprintf(name
, sizeof(name
), "t%d", i
);
1410 pos
= isl_set_find_dim_by_name(set
, isl_dim_param
, name
);
1411 aff2
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1412 isl_dim_param
, pos
);
1413 aff
= isl_aff_sub(aff
, aff2
);
1414 c
= isl_equality_from_aff(aff
);
1415 set
= isl_set_add_constraint(set
, c
);
1418 isl_local_space_free(ls
);
1419 data
->privatization
= set
;
1422 /* Group references of all arrays in "kernel".
1423 * "node" points to the kernel mark.
1425 * We first extract all required schedule information into
1426 * a gpu_group_data structure and then consider each array
1429 int gpu_group_references(struct ppcg_kernel
*kernel
,
1430 __isl_keep isl_schedule_node
*node
)
1435 struct gpu_group_data data
;
1437 check_scalar_live_ranges(kernel
, node
);
1439 data
.scop
= kernel
->prog
->scop
;
1441 data
.kernel_depth
= isl_schedule_node_get_schedule_depth(node
);
1442 data
.host_sched
= isl_schedule_node_get_prefix_schedule_relation(node
);
1444 node
= isl_schedule_node_copy(node
);
1445 node
= gpu_tree_move_down_to_thread(node
, kernel
->core
);
1447 isl_schedule_node_get_prefix_schedule_relation(node
);
1448 data
.shared_sched
= isl_union_map_detect_equalities(data
.shared_sched
);
1450 node
= isl_schedule_node_child(node
, 0);
1451 data
.thread_depth
= isl_schedule_node_get_schedule_depth(node
);
1452 data
.n_thread
= isl_schedule_node_band_n_member(node
);
1453 data
.thread_sched
= isl_union_map_copy(data
.shared_sched
);
1454 data
.thread_sched
= isl_union_map_flat_range_product(data
.thread_sched
,
1455 isl_schedule_node_band_get_partial_schedule_union_map(node
));
1456 data
.thread_sched
= isl_union_map_detect_equalities(data
.thread_sched
);
1457 node
= isl_schedule_node_child(node
, 0);
1458 data
.full_sched
= isl_union_map_copy(data
.thread_sched
);
1459 data
.full_sched
= isl_union_map_flat_range_product(data
.full_sched
,
1460 isl_schedule_node_get_subtree_schedule_union_map(node
));
1461 isl_schedule_node_free(node
);
1463 space
= isl_union_set_get_space(kernel
->thread_filter
);
1464 compute_privatization(&data
, space
, kernel
->block_dim
);
1466 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1467 r
= group_array_references(kernel
, &kernel
->array
[i
], &data
);
1472 isl_union_map_free(data
.host_sched
);
1473 isl_union_map_free(data
.shared_sched
);
1474 isl_union_map_free(data
.thread_sched
);
1475 isl_union_map_free(data
.full_sched
);
1476 isl_set_free(data
.privatization
);
1481 /* Given a description of an array tile "tile" and the "space"
1485 * where D represents the first group->depth schedule dimensions
1486 * and A represents the array, construct an isl_multi_aff
1488 * { [D[i] -> A[a]] -> A'[a'] }
1490 * with A' a scaled down copy of A according to the shifts and strides
1491 * in "tile". In particular,
1493 * a' = (a + shift(i))/stride
1495 * "insert_array" represents
1499 * and is used to insert A into the domain of functions that only
1502 static __isl_give isl_multi_aff
*strided_tile(
1503 struct gpu_array_tile
*tile
, __isl_keep isl_space
*space
,
1504 __isl_keep isl_multi_aff
*insert_array
)
1508 isl_multi_aff
*shift
;
1509 isl_multi_val
*stride
;
1511 isl_local_space
*ls
;
1512 isl_multi_aff
*tiling
;
1514 ctx
= isl_space_get_ctx(space
);
1515 space2
= isl_space_domain(isl_space_copy(space
));
1516 ls
= isl_local_space_from_space(space2
);
1517 space2
= isl_space_range(isl_space_copy(space
));
1518 stride
= isl_multi_val_zero(space2
);
1519 shift
= isl_multi_aff_zero(isl_space_copy(space
));
1521 for (i
= 0; i
< tile
->n
; ++i
) {
1522 struct gpu_array_bound
*bound
= &tile
->bound
[i
];
1526 if (tile
->bound
[i
].shift
) {
1527 stride_i
= isl_val_copy(bound
->stride
);
1528 shift_i
= isl_aff_copy(bound
->shift
);
1530 stride_i
= isl_val_one(ctx
);
1531 shift_i
= isl_aff_zero_on_domain(
1532 isl_local_space_copy(ls
));
1535 stride
= isl_multi_val_set_val(stride
, i
, stride_i
);
1536 shift
= isl_multi_aff_set_aff(shift
, i
, shift_i
);
1538 isl_local_space_free(ls
);
1540 shift
= isl_multi_aff_pullback_multi_aff(shift
,
1541 isl_multi_aff_copy(insert_array
));
1543 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1544 tiling
= isl_multi_aff_add(tiling
, shift
);
1545 tiling
= isl_multi_aff_scale_down_multi_val(tiling
, stride
);
1550 /* Compute a tiling for the array reference group "group".
1552 * The tiling is of the form
1554 * { [D[i] -> A[a]] -> T[t] }
1556 * where D represents the first group->depth schedule dimensions,
1557 * A represents the global array and T represents the shared or
1558 * private memory tile. The name of T is the name of the local
1561 * If there is any stride in the accesses, then the mapping is
1563 * t = (a + shift(i))/stride - lb(i)
1565 * otherwise, it is simply
1569 void gpu_array_ref_group_compute_tiling(struct gpu_array_ref_group
*group
)
1573 struct gpu_array_tile
*tile
;
1574 struct gpu_array_info
*array
= group
->array
;
1576 isl_multi_aff
*tiling
, *lb
, *insert_array
;
1580 tile
= group
->private_tile
;
1582 tile
= group
->shared_tile
;
1586 space
= isl_map_get_space(group
->access
);
1587 dim
= isl_space_dim(space
, isl_dim_in
);
1588 space
= isl_space_drop_dims(space
, isl_dim_in
, group
->depth
,
1589 dim
- group
->depth
);
1590 insert_array
= isl_multi_aff_domain_map(isl_space_copy(space
));
1592 for (i
= 0; i
< tile
->n
; ++i
)
1593 if (tile
->bound
[i
].shift
)
1597 tiling
= strided_tile(tile
, space
, insert_array
);
1599 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1601 lb
= isl_multi_aff_zero(space
);
1602 for (i
= 0; i
< tile
->n
; ++i
) {
1603 isl_aff
*lb_i
= isl_aff_copy(tile
->bound
[i
].lb
);
1604 lb
= isl_multi_aff_set_aff(lb
, i
, lb_i
);
1606 lb
= isl_multi_aff_pullback_multi_aff(lb
, insert_array
);
1608 tiling
= isl_multi_aff_sub(tiling
, lb
);
1610 p
= isl_printer_to_str(isl_multi_aff_get_ctx(tiling
));
1611 p
= gpu_array_ref_group_print_name(group
, p
);
1612 local_name
= isl_printer_get_str(p
);
1613 isl_printer_free(p
);
1614 tiling
= isl_multi_aff_set_tuple_name(tiling
, isl_dim_out
, local_name
);
1617 tile
->tiling
= tiling
;