2 * Copyright 2010-2011 INRIA Saclay
3 * Copyright 2012-2014 Ecole Normale Superieure
4 * Copyright 2015 Sven Verdoolaege
6 * Use of this software is governed by the MIT license
8 * Written by Sven Verdoolaege, INRIA Saclay - Ile-de-France,
9 * Parc Club Orsay Universite, ZAC des vignes, 4 rue Jacques Monod,
11 * and Ecole Normale Superieure, 45 rue d'Ulm, 75230 Paris, France
14 #include <isl/constraint.h>
17 #include "gpu_array_tile.h"
18 #include "gpu_group.h"
22 /* Print the name of the local copy of a given group of array references.
24 __isl_give isl_printer
*gpu_array_ref_group_print_name(
25 struct gpu_array_ref_group
*group
, __isl_take isl_printer
*p
)
28 enum ppcg_group_access_type type
;
30 type
= gpu_array_ref_group_type(group
);
31 if (type
== ppcg_access_private
)
32 p
= isl_printer_print_str(p
, "private_");
33 else if (type
== ppcg_access_shared
)
34 p
= isl_printer_print_str(p
, "shared_");
37 p
= isl_printer_print_str(p
, group
->array
->name
);
38 if (!global
&& group
->local_array
->n_group
> 1) {
39 p
= isl_printer_print_str(p
, "_");
40 p
= isl_printer_print_int(p
, group
->nr
);
46 /* Return the union of all read (read = 1) and/or write (write = 1)
47 * access relations in the group.
49 __isl_give isl_union_map
*gpu_array_ref_group_access_relation(
50 struct gpu_array_ref_group
*group
, int read
, int write
)
53 isl_union_map
*access
;
55 access
= isl_union_map_empty(isl_map_get_space(group
->access
));
56 for (i
= 0; i
< group
->n_ref
; ++i
) {
59 if (!((read
&& group
->refs
[i
]->read
) ||
60 (write
&& group
->refs
[i
]->write
)))
62 map_i
= isl_map_copy(group
->refs
[i
]->access
);
63 access
= isl_union_map_union(access
,
64 isl_union_map_from_map(map_i
));
70 /* Should this array reference group be mapped to private, shared or global
72 * If we have computed both a private and a shared tile, then
73 * the tile with the smallest depth is used. If both have the same depth,
74 * then the private tile is used.
76 enum ppcg_group_access_type
gpu_array_ref_group_type(
77 struct gpu_array_ref_group
*group
)
79 if (group
->private_tile
&& group
->shared_tile
&&
80 group
->shared_tile
->depth
< group
->private_tile
->depth
)
81 return ppcg_access_shared
;
82 if (group
->private_tile
)
83 return ppcg_access_private
;
84 if (group
->shared_tile
)
85 return ppcg_access_shared
;
86 return ppcg_access_global
;
90 /* Return the effective gpu_array_tile associated to "group" or
91 * NULL if there is no such gpu_array_tile.
93 struct gpu_array_tile
*gpu_array_ref_group_tile(
94 struct gpu_array_ref_group
*group
)
96 switch (gpu_array_ref_group_type(group
)) {
97 case ppcg_access_global
:
99 case ppcg_access_shared
:
100 return group
->shared_tile
;
101 case ppcg_access_private
:
102 return group
->private_tile
;
106 /* Does the tile associated to "group" require unrolling of the schedule
107 * dimensions mapped to threads?
108 * Note that this can only happen for private tiles.
110 int gpu_array_ref_group_requires_unroll(struct gpu_array_ref_group
*group
)
112 struct gpu_array_tile
*tile
;
114 tile
= gpu_array_ref_group_tile(group
);
117 return tile
->requires_unroll
;
120 /* Given a constraint
122 * a(p,i) + j = g f(e)
124 * or -a(p,i) - j = g f(e) if sign < 0,
125 * store a(p,i) in bound->shift and g (stride) in bound->stride.
126 * a(p,i) is assumed to be an expression in only the parameters
127 * and the input dimensions.
129 static void extract_stride(__isl_keep isl_constraint
*c
,
130 struct gpu_array_bound
*bound
, __isl_keep isl_val
*stride
, int sign
)
139 isl_val_free(bound
->stride
);
140 bound
->stride
= isl_val_copy(stride
);
142 space
= isl_constraint_get_space(c
);
143 space
= isl_space_domain(space
);
145 nparam
= isl_space_dim(space
, isl_dim_param
);
146 nvar
= isl_space_dim(space
, isl_dim_set
);
148 v
= isl_constraint_get_constant_val(c
);
151 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
152 aff
= isl_aff_set_constant_val(aff
, v
);
154 for (i
= 0; i
< nparam
; ++i
) {
155 if (!isl_constraint_involves_dims(c
, isl_dim_param
, i
, 1))
157 v
= isl_constraint_get_coefficient_val(c
, isl_dim_param
, i
);
160 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_param
, i
, v
);
163 for (i
= 0; i
< nvar
; ++i
) {
164 if (!isl_constraint_involves_dims(c
, isl_dim_in
, i
, 1))
166 v
= isl_constraint_get_coefficient_val(c
, isl_dim_in
, i
);
169 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_in
, i
, v
);
175 /* Given an equality constraint of a map with a single output dimension j,
176 * check if the constraint is of the form
178 * a(p,i) + j = g f(e)
180 * with a(p,i) an expression in the parameters and input dimensions
181 * and f(e) an expression in the existentially quantified variables.
182 * If so, and if g is larger than any such g from a previously considered
183 * constraint, then call extract_stride to record the stride information
186 static isl_stat
check_stride_constraint(__isl_take isl_constraint
*c
,
193 struct gpu_array_bound
*bound
= user
;
195 ctx
= isl_constraint_get_ctx(c
);
196 n_div
= isl_constraint_dim(c
, isl_dim_div
);
197 v
= isl_constraint_get_coefficient_val(c
, isl_dim_out
, 0);
199 if (n_div
&& (isl_val_is_one(v
) || isl_val_is_negone(v
))) {
200 int s
= isl_val_sgn(v
);
201 isl_val
*stride
= isl_val_zero(ctx
);
204 for (i
= 0; i
< n_div
; ++i
) {
205 v
= isl_constraint_get_coefficient_val(c
,
207 stride
= isl_val_gcd(stride
, v
);
209 if (!isl_val_is_zero(stride
) &&
210 isl_val_gt(stride
, bound
->stride
))
211 extract_stride(c
, bound
, stride
, s
);
213 isl_val_free(stride
);
217 isl_constraint_free(c
);
221 /* Given contraints on an array index i, check if we can find
222 * a shift a(p) and a stride g such that
226 * If so, record the information in bound and apply the mapping
227 * i -> (i + a(p))/g to the array index in bounds and return
228 * the new constraints.
229 * If not, simply return the original constraints.
231 * If bounds is a subset of the space
235 * then the bound recorded in bound->shift is of the form
239 * with s(D) equal to a(p) above.
240 * Next, we construct a mapping of the form
242 * [D -> i] -> [D -> (i + S(D))/g]
244 * This mapping is computed as follows.
245 * We first introduce "i" in the domain through precomposition
246 * with [D -> i] -> D obtaining
250 * Adding [D -> i] -> i produces
252 * [D -> i] -> i + s(D)
254 * and the domain product with [D -> i] -> D yields
256 * [D -> i] -> [D -> i + s(D)]
258 * Composition with [D -> i] -> [D -> i/g] gives the desired result.
260 static __isl_give isl_basic_map
*check_stride(struct gpu_array_bound
*bound
,
261 __isl_take isl_basic_map
*bounds
)
265 isl_basic_map
*shift
, *id
, *bmap
, *scale
;
269 bound
->stride
= NULL
;
271 hull
= isl_basic_map_affine_hull(isl_basic_map_copy(bounds
));
273 isl_basic_map_foreach_constraint(hull
, &check_stride_constraint
, bound
);
275 isl_basic_map_free(hull
);
280 shift
= isl_basic_map_from_aff(isl_aff_copy(bound
->shift
));
281 space
= isl_basic_map_get_space(bounds
);
282 bmap
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
283 shift
= isl_basic_map_apply_range(bmap
, shift
);
284 space
= isl_basic_map_get_space(bounds
);
285 id
= isl_basic_map_range_map(isl_basic_map_universe(space
));
286 shift
= isl_basic_map_sum(id
, shift
);
287 space
= isl_basic_map_get_space(bounds
);
288 id
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
289 shift
= isl_basic_map_range_product(id
, shift
);
291 space
= isl_space_domain(isl_basic_map_get_space(bounds
));
292 id
= isl_basic_map_identity(isl_space_map_from_set(space
));
293 space
= isl_space_range(isl_basic_map_get_space(bounds
));
294 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
295 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, 0, 1);
296 aff
= isl_aff_scale_down_val(aff
, isl_val_copy(bound
->stride
));
297 scale
= isl_basic_map_from_aff(aff
);
298 scale
= isl_basic_map_product(id
, scale
);
300 bmap
= isl_basic_map_apply_range(shift
, scale
);
301 bset
= isl_basic_set_apply(isl_basic_map_wrap(bounds
), bmap
);
302 bounds
= isl_basic_set_unwrap(bset
);
307 /* Data used in compute_array_dim_size and compute_size_in_direction.
309 * pos is the position of the variable representing the array index,
310 * i.e., the variable for which want to compute the size. This variable
311 * is also the last variable in the set.
313 struct gpu_size_info
{
315 struct gpu_array_bound
*bound
;
319 /* Given a constraint from the basic set describing the bounds on
320 * an array index, check if it is a lower bound, say m i >= b(x), and,
321 * if so, check whether the expression "i - ceil(b(x)/m) + 1" has a constant
322 * upper bound. If so, and if this bound is smaller than any bound
323 * derived from earlier constraints, set the size to this bound on
324 * the expression and the lower bound to ceil(b(x)/m).
326 static isl_stat
compute_size_in_direction(__isl_take isl_constraint
*c
,
329 struct gpu_size_info
*size
= user
;
336 nparam
= isl_basic_set_dim(size
->bset
, isl_dim_param
);
337 n_div
= isl_constraint_dim(c
, isl_dim_div
);
339 if (isl_constraint_involves_dims(c
, isl_dim_div
, 0, n_div
) ||
340 !isl_constraint_is_lower_bound(c
, isl_dim_set
, size
->pos
)) {
341 isl_constraint_free(c
);
345 aff
= isl_constraint_get_bound(c
, isl_dim_set
, size
->pos
);
346 aff
= isl_aff_ceil(aff
);
348 lb
= isl_aff_copy(aff
);
350 aff
= isl_aff_neg(aff
);
351 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, size
->pos
, 1);
353 v
= isl_basic_set_max_val(size
->bset
, aff
);
356 if (isl_val_is_int(v
)) {
357 v
= isl_val_add_ui(v
, 1);
358 if (!size
->bound
->size
|| isl_val_lt(v
, size
->bound
->size
)) {
359 isl_val_free(size
->bound
->size
);
360 size
->bound
->size
= isl_val_copy(v
);
361 lb
= isl_aff_drop_dims(lb
, isl_dim_in
, size
->pos
, 1);
362 isl_aff_free(size
->bound
->lb
);
363 size
->bound
->lb
= isl_aff_copy(lb
);
369 isl_constraint_free(c
);
374 /* Given a basic map "bounds" that maps parameters and input dimensions
375 * to a single output dimension, look for an expression in the parameters
376 * and input dimensions such that the range of the output dimension shifted
377 * by this expression is a constant.
379 * In particular, we currently only consider lower bounds on the output
380 * dimension as candidate expressions.
382 static int compute_array_dim_size(struct gpu_array_bound
*bound
,
383 __isl_take isl_basic_map
*bounds
)
385 struct gpu_size_info size
;
387 bounds
= isl_basic_map_detect_equalities(bounds
);
388 bounds
= check_stride(bound
, bounds
);
394 size
.pos
= isl_basic_map_dim(bounds
, isl_dim_in
);
395 size
.bset
= isl_basic_map_wrap(bounds
);
396 size
.bset
= isl_basic_set_flatten(size
.bset
);
397 size
.bset
= isl_set_simple_hull(isl_basic_set_compute_divs(size
.bset
));
398 isl_basic_set_foreach_constraint(size
.bset
, &compute_size_in_direction
,
400 isl_basic_set_free(size
.bset
);
402 return bound
->size
? 0 : -1;
405 /* Check if we can find a memory tile for the given array
406 * based on the given accesses, and if so, put the results in "tile".
408 * We project the accesses on each index in turn and look for a parametric
409 * offset such that the size is constant.
411 * tile->depth is initialized to the input dimension of the computed bounds.
413 static int can_tile(__isl_keep isl_map
*access
, struct gpu_array_tile
*tile
)
417 tile
->depth
= isl_map_dim(access
, isl_dim_in
);
419 for (i
= 0; i
< tile
->n
; ++i
) {
423 access_i
= isl_map_copy(access
);
424 access_i
= isl_map_project_out(access_i
, isl_dim_out
, 0, i
);
425 access_i
= isl_map_project_out(access_i
, isl_dim_out
,
426 1, tile
->n
- (i
+ 1));
427 access_i
= isl_map_compute_divs(access_i
);
428 hull
= isl_map_simple_hull(access_i
);
429 if (compute_array_dim_size(&tile
->bound
[i
], hull
) < 0)
436 /* Internal data structure for gpu_group_references.
438 * scop represents the input scop.
439 * kernel_depth is the schedule depth where the kernel launch will
440 * be introduced, i.e., it is the depth of the band that is mapped
442 * shared_depth is the schedule depth at which the copying to/from
443 * shared memory is computed. The copy operation may then
444 * later be hoisted to a higher level.
445 * thread_depth is the schedule depth where the thread mark is located,
446 * i.e., it is the depth of the band that is mapped to threads and also
447 * the schedule depth at which the copying to/from private memory
448 * is computed. The copy operation may then later be hoisted to
450 * Currently, shared_depth is equal to thread_depth.
451 * n_thread is the number of schedule dimensions in the band that
452 * is mapped to threads.
453 * privatization lives in the range of thread_sched (i.e., it is
454 * of dimension thread_depth + n_thread) and encodes the mapping
455 * to thread identifiers (as parameters).
456 * host_sched contains the kernel_depth dimensions of the host schedule.
457 * shared_sched contains the first shared_depth dimensions of the
459 * copy_sched contains the first thread_depth dimensions of the
461 * thread_sched contains the first (thread_depth + n_thread) dimensions
462 * of the kernel schedule.
463 * full_sched is a union_map representation of the entire kernel schedule.
464 * The schedules are all formulated in terms of the original statement
465 * instances, i.e., those that appear in the domains of the access
468 struct gpu_group_data
{
469 struct ppcg_scop
*scop
;
474 isl_set
*privatization
;
475 isl_union_map
*host_sched
;
476 isl_union_map
*shared_sched
;
477 isl_union_map
*copy_sched
;
478 isl_union_map
*thread_sched
;
479 isl_union_map
*full_sched
;
482 /* Construct a map from domain_space to domain_space that increments
483 * the dimension at position "pos" and leaves all other dimensions
486 static __isl_give isl_map
*next(__isl_take isl_space
*domain_space
, int pos
)
492 space
= isl_space_map_from_set(domain_space
);
493 next
= isl_multi_aff_identity(space
);
494 aff
= isl_multi_aff_get_aff(next
, pos
);
495 aff
= isl_aff_add_constant_si(aff
, 1);
496 next
= isl_multi_aff_set_aff(next
, pos
, aff
);
498 return isl_map_from_multi_aff(next
);
501 /* Check if the given access is coalesced (or if there is no point
502 * in trying to coalesce the access by mapping the array to shared memory).
503 * That is, check whether incrementing the dimension that will get
504 * wrapped over the last thread index results in incrementing
505 * the last array index.
507 * If no two consecutive array elements are ever accessed by "access",
508 * then mapping the corresponding array to shared memory will not
509 * improve coalescing. In fact, the copying will likely be performed
510 * by a single thread. Consider the access as coalesced such that
511 * the caller will not try and map the array to shared memory just
512 * to improve coalescing.
514 * This function is only called for access relations without reuse and
515 * kernels with at least one thread identifier.
517 static int access_is_coalesced(struct gpu_group_data
*data
,
518 __isl_keep isl_union_map
*access
)
524 isl_map
*next_thread_x
;
525 isl_map
*next_element
;
527 int coalesced
, empty
;
529 access
= isl_union_map_copy(access
);
530 access
= isl_union_map_apply_domain(access
,
531 isl_union_map_copy(data
->full_sched
));
532 access_map
= isl_map_from_union_map(access
);
534 space
= isl_map_get_space(access_map
);
535 space
= isl_space_range(space
);
536 dim
= isl_space_dim(space
, isl_dim_set
);
538 next_element
= isl_map_empty(isl_space_map_from_set(space
));
540 next_element
= next(space
, dim
- 1);
542 accessed
= isl_map_range(isl_map_copy(access_map
));
543 map
= isl_map_copy(next_element
);
544 map
= isl_map_intersect_domain(map
, isl_set_copy(accessed
));
545 map
= isl_map_intersect_range(map
, accessed
);
546 empty
= isl_map_is_empty(map
);
549 if (empty
< 0 || empty
) {
550 isl_map_free(next_element
);
551 isl_map_free(access_map
);
555 space
= isl_map_get_space(access_map
);
556 space
= isl_space_domain(space
);
557 next_thread_x
= next(space
, data
->thread_depth
+ data
->n_thread
- 1);
559 map
= isl_map_apply_domain(next_thread_x
, isl_map_copy(access_map
));
560 map
= isl_map_apply_range(map
, access_map
);
562 coalesced
= isl_map_is_subset(map
, next_element
);
564 isl_map_free(next_element
);
570 /* Replace the host schedule dimensions in the access relation "access"
571 * by parameters, so that they are treated as fixed when checking for reuse
572 * (within a kernel) or whether two consecutive elements are accessed
575 static __isl_give isl_union_map
*localize_access(struct gpu_group_data
*data
,
576 __isl_take isl_union_map
*access
)
584 umap
= isl_union_map_copy(data
->host_sched
);
585 space
= isl_union_map_get_space(umap
);
586 n
= data
->kernel_depth
;
587 ids
= ppcg_scop_generate_names(data
->scop
, n
, "__ppcg_host_");
588 param
= parametrization(space
, n
, 0, ids
);
589 isl_id_list_free(ids
);
590 umap
= isl_union_map_intersect_range(umap
,
591 isl_union_set_from_set(param
));
592 access
= isl_union_map_intersect_domain(access
,
593 isl_union_map_domain(umap
));
598 /* Given an access relation in terms of at least data->thread_depth initial
599 * dimensions of the computed schedule, check if it is bijective for
600 * fixed values of the first data->thread_depth dimensions.
601 * We perform this check by equating these dimensions to parameters.
603 static int access_is_bijective(struct gpu_group_data
*data
,
604 __isl_keep isl_map
*access
)
612 access
= isl_map_copy(access
);
613 space
= isl_space_params(isl_map_get_space(access
));
614 ids
= ppcg_scop_generate_names(data
->scop
, data
->thread_depth
, "s");
615 dim
= isl_map_dim(access
, isl_dim_in
);
616 par
= parametrization(space
, dim
, 0, ids
);
617 isl_id_list_free(ids
);
618 access
= isl_map_intersect_domain(access
, par
);
619 res
= isl_map_is_bijective(access
);
620 isl_map_free(access
);
625 /* Compute the number of outer schedule tile dimensions that affect
626 * the offset of "tile".
627 * If there is no such dimension, then return the index
628 * of the first kernel dimension, i.e., data->kernel_depth.
630 static int compute_tile_depth(struct gpu_group_data
*data
,
631 struct gpu_array_tile
*tile
)
635 for (j
= tile
->depth
- 1; j
>= data
->kernel_depth
; --j
) {
636 for (i
= 0; i
< tile
->n
; ++i
) {
640 lb
= tile
->bound
[i
].lb
;
641 if (isl_aff_involves_dims(lb
, isl_dim_in
, j
, 1))
644 shift
= tile
->bound
[i
].shift
;
647 if (isl_aff_involves_dims(shift
, isl_dim_in
, j
, 1))
657 /* Return the lowest depth between data->kernel_depth and data->thread_depth
658 * at which every array element accessed through "acc" is accessed
659 * by a single thread. The input dimension of "acc" is
660 * data->thread_depth + data->n_thread, where the final data->n_thread
661 * dimensions are those that will be mapped to threads.
662 * If the values for these dimensions are uniquely determined
663 * by the array index and a given number of outer dimensions, then
664 * there is only one thread accessing that array element within those
667 * The input space of "acc" is first split up, such that it has the form
671 * with O the outer dimensions, T the dimensions that will be mapped to threads
672 * and A the array index.
674 * Then the positions of T and A are interchanged to simplify the test
675 * whether T uniquely depends on O and A.
676 * In particular, the above access relation is first combined with
682 * [O -> T] -> [A -> T]
688 * is extracted, which is then uncurried to
692 * Finally, the final dimensions of O are projected out one by one
693 * until T is no longer uniquely determined by A and the remaining
694 * dimensions in O. The value returned is that of the last dimension
695 * that was successfully projected out.
696 * Note that there is no need to test whether [O -> A] -> T itself
697 * is single-valued as that was already tested in access_is_bijective.
699 static int compute_accessed_by_single_thread_depth(struct gpu_group_data
*data
,
700 __isl_keep isl_map
*acc
)
707 if (data
->thread_depth
== data
->kernel_depth
)
708 return data
->thread_depth
;
710 acc
= isl_map_copy(acc
);
712 space
= isl_map_get_space(acc
);
713 space
= isl_space_params(space
);
714 space
= isl_space_set_from_params(space
);
715 space
= isl_space_add_dims(space
, isl_dim_set
, data
->thread_depth
);
716 space
= isl_space_from_domain(space
);
717 space
= isl_space_add_dims(space
, isl_dim_out
, data
->n_thread
);
718 space
= isl_space_wrap(space
);
719 map
= isl_set_flatten_map(isl_set_universe(space
));
720 acc
= isl_map_apply_range(map
, acc
);
722 space
= isl_space_domain(isl_map_get_space(acc
));
723 map
= isl_map_range_map(isl_map_universe(isl_space_unwrap(space
)));
724 acc
= isl_map_range_product(acc
, map
);
725 acc
= isl_map_domain_factor_domain(acc
);
726 acc
= isl_map_uncurry(acc
);
728 for (i
= data
->thread_depth
- 1; i
>= data
->kernel_depth
; --i
) {
729 acc
= isl_map_project_out(acc
, isl_dim_in
, i
, 1);
730 sv
= isl_map_is_single_valued(acc
);
742 /* Adjust the fields of "tile" to reflect the new input dimension "depth".
743 * The dimension beyond "depth" are assumed not to affect the tile,
744 * so they can simply be dropped.
746 static int tile_adjust_depth(struct gpu_array_tile
*tile
, int depth
)
750 if (tile
->depth
== depth
)
753 for (i
= 0; i
< tile
->n
; ++i
) {
754 tile
->bound
[i
].lb
= isl_aff_drop_dims(tile
->bound
[i
].lb
,
755 isl_dim_in
, depth
, tile
->depth
- depth
);
756 if (!tile
->bound
[i
].lb
)
758 if (!tile
->bound
[i
].shift
)
760 tile
->bound
[i
].shift
= isl_aff_drop_dims(tile
->bound
[i
].shift
,
761 isl_dim_in
, depth
, tile
->depth
- depth
);
762 if (!tile
->bound
[i
].shift
)
771 /* Determine the number of schedule dimensions that affect the offset of the
772 * shared or private tile "tile" and store the result in tile->depth, with
773 * a lower bound of data->kernel_depth.
774 * Also adjust the fields of the tile to only refer to the tile->depth
775 * outer schedule dimensions.
777 static isl_stat
tile_set_depth(struct gpu_group_data
*data
,
778 struct gpu_array_tile
*tile
)
780 if (tile_adjust_depth(tile
, compute_tile_depth(data
, tile
)) < 0)
781 return isl_stat_error
;
786 /* Determine the number of schedule dimensions that affect the offset of the
787 * shared tile and store the minimum of the private and shared tile depth
788 * in group->min_depth, with a lower bound of data->kernel_depth.
789 * If there is no tile defined on the array reference group,
790 * then set group->min_depth to data->thread_depth.
792 static int set_depth(struct gpu_group_data
*data
,
793 struct gpu_array_ref_group
*group
)
795 group
->min_depth
= data
->thread_depth
;
797 if (group
->private_tile
) {
798 if (group
->private_tile
->depth
< group
->min_depth
)
799 group
->min_depth
= group
->private_tile
->depth
;
801 if (group
->shared_tile
) {
802 if (tile_set_depth(data
, group
->shared_tile
) < 0)
804 if (group
->shared_tile
->depth
< group
->min_depth
)
805 group
->min_depth
= group
->shared_tile
->depth
;
811 /* Fill up the groups array with singleton groups, i.e., one group
812 * per reference, initializing the array, access, write, n_ref and refs fields.
813 * In particular the access field is initialized to the scheduled
814 * access relation of the array reference.
816 * Return the number of elements initialized, i.e., the number of
817 * active references in the current kernel.
819 static int populate_array_references(struct gpu_local_array_info
*local
,
820 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
824 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->copy_sched
);
827 for (i
= 0; i
< local
->array
->n_ref
; ++i
) {
830 struct gpu_array_ref_group
*group
;
831 struct gpu_stmt_access
*access
= local
->array
->refs
[i
];
833 map
= isl_map_copy(access
->access
);
834 umap
= isl_union_map_from_map(map
);
835 umap
= isl_union_map_apply_domain(umap
,
836 isl_union_map_copy(data
->copy_sched
));
838 if (isl_union_map_is_empty(umap
)) {
839 isl_union_map_free(umap
);
843 map
= isl_map_from_union_map(umap
);
844 map
= isl_map_detect_equalities(map
);
846 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
849 group
->local_array
= local
;
850 group
->array
= local
->array
;
852 group
->write
= access
->write
;
853 group
->exact_write
= access
->exact_write
;
854 group
->slice
= access
->n_index
< local
->array
->n_index
;
855 group
->refs
= &local
->array
->refs
[i
];
864 /* If group->n_ref == 1, then group->refs was set by
865 * populate_array_references to point directly into
866 * group->array->refs and should not be freed.
867 * If group->n_ref > 1, then group->refs was set by join_groups
868 * to point to a newly allocated array.
870 struct gpu_array_ref_group
*gpu_array_ref_group_free(
871 struct gpu_array_ref_group
*group
)
875 gpu_array_tile_free(group
->shared_tile
);
876 gpu_array_tile_free(group
->private_tile
);
877 isl_map_free(group
->access
);
878 if (group
->n_ref
> 1)
884 /* Check if the access relations of group1 and group2 overlap within
887 static int accesses_overlap(struct gpu_array_ref_group
*group1
,
888 struct gpu_array_ref_group
*group2
)
892 disjoint
= isl_map_is_disjoint(group1
->access
, group2
->access
);
899 /* Combine the given two groups into a single group, containing
900 * the references of both groups.
902 static struct gpu_array_ref_group
*join_groups(
903 struct gpu_array_ref_group
*group1
,
904 struct gpu_array_ref_group
*group2
)
908 struct gpu_array_ref_group
*group
;
910 if (!group1
|| !group2
)
913 ctx
= isl_map_get_ctx(group1
->access
);
914 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
917 group
->local_array
= group1
->local_array
;
918 group
->array
= group1
->array
;
919 group
->access
= isl_map_union(isl_map_copy(group1
->access
),
920 isl_map_copy(group2
->access
));
921 group
->write
= group1
->write
|| group2
->write
;
922 group
->exact_write
= group1
->exact_write
&& group2
->exact_write
;
923 group
->slice
= group1
->slice
|| group2
->slice
;
924 group
->n_ref
= group1
->n_ref
+ group2
->n_ref
;
925 group
->refs
= isl_alloc_array(ctx
, struct gpu_stmt_access
*,
928 return gpu_array_ref_group_free(group
);
929 for (i
= 0; i
< group1
->n_ref
; ++i
)
930 group
->refs
[i
] = group1
->refs
[i
];
931 for (i
= 0; i
< group2
->n_ref
; ++i
)
932 group
->refs
[group1
->n_ref
+ i
] = group2
->refs
[i
];
937 /* Combine the given two groups into a single group and free
938 * the original two groups.
940 static struct gpu_array_ref_group
*join_groups_and_free(
941 struct gpu_array_ref_group
*group1
,
942 struct gpu_array_ref_group
*group2
)
944 struct gpu_array_ref_group
*group
;
946 group
= join_groups(group1
, group2
);
947 gpu_array_ref_group_free(group1
);
948 gpu_array_ref_group_free(group2
);
952 /* Report that the array reference group with the given access relation
953 * is not mapped to shared memory in the given kernel because
954 * it does not exhibit any reuse and is considered to be coalesced.
956 static void report_no_reuse_and_coalesced(struct ppcg_kernel
*kernel
,
957 __isl_keep isl_union_map
*access
)
962 ctx
= isl_union_map_get_ctx(access
);
963 p
= isl_printer_to_file(ctx
, stdout
);
964 p
= isl_printer_print_str(p
, "Array reference group ");
965 p
= isl_printer_print_union_map(p
, access
);
966 p
= isl_printer_print_str(p
,
967 " not considered for mapping to shared memory in kernel");
968 p
= isl_printer_print_int(p
, kernel
->id
);
969 p
= isl_printer_print_str(p
,
970 " because it exhibits no reuse and is considered to be coalesced");
971 p
= isl_printer_end_line(p
);
975 /* Given an access relation in terms of the data->thread_depth initial
976 * dimensions of the computed schedule and the thread identifiers
977 * (as parameters), check if the use of the corresponding private tile
978 * requires unrolling.
980 * If we are creating a private tile because we are forced to,
981 * then no unrolling is required.
982 * Otherwise we check if "access" is bijective and unrolling
983 * is required if it is not. Note that the access relation
984 * has already been determined to be bijective before the introduction
985 * of the thread identifiers and the removal of the schedule dimensions
986 * that are mapped to these threads. If the access relation is no longer
987 * bijective, then this means that more than one value of one of those
988 * schedule dimensions is mapped to the same thread and therefore
989 * unrolling is required.
991 static int check_requires_unroll(struct gpu_group_data
*data
,
992 __isl_keep isl_map
*access
, int force_private
)
998 bijective
= access_is_bijective(data
, access
);
1004 /* Map the domain of "access" to the outer data->shared_depth
1005 * schedule dimensions. When data->shared_depth is equal to
1006 * data->thread_depth, this result is already available in group->access.
1008 static __isl_give isl_map
*shared_access(struct gpu_array_ref_group
*group
,
1009 __isl_keep isl_union_map
*access
, struct gpu_group_data
*data
)
1011 isl_union_map
*shared
;
1013 if (data
->shared_depth
== data
->thread_depth
)
1014 return isl_map_copy(group
->access
);
1016 shared
= isl_union_map_copy(access
);
1017 shared
= isl_union_map_apply_domain(shared
,
1018 isl_union_map_copy(data
->shared_sched
));
1019 return isl_map_from_union_map(shared
);
1022 /* Compute the private and/or shared memory tiles for the array
1023 * reference group "group" of array "array".
1024 * Return 0 on success and -1 on error.
1026 * If the array is a read-only scalar or if the user requested
1027 * not to use shared or private memory, then we do not need to do anything.
1029 * If any reference in the reference group accesses more than one element,
1030 * then we would have to make sure that the layout in shared memory
1031 * is the same as that in global memory. Since we do not handle this yet
1032 * (and it may not even be possible), we refuse to map to private or
1033 * shared memory in such cases.
1035 * If the array group involves any may writes (that are not must writes),
1036 * then we would have to make sure that we load the data into shared/private
1037 * memory first in case the data is not written by the kernel
1038 * (but still written back out to global memory).
1039 * Since we don't have any such mechanism at the moment, we don't
1040 * compute shared/private tiles for groups involving may writes.
1042 * We only try to compute a shared memory tile if there is any reuse
1043 * or if the access is not coalesced.
1044 * Reuse and coalescing are checked within the given kernel.
1046 * For computing a private memory tile, we also require that there is
1047 * some reuse. Moreover, we require that the access is private
1048 * to the thread. That is, we check that any given array element
1049 * is only accessed by a single thread.
1050 * We compute an access relation that maps the outer
1051 * data->thread_depth + data->n_thread schedule dimensions.
1052 * The latter data->n_thread will be mapped to thread identifiers.
1053 * We actually check that those iterators that will be wrapped
1054 * partition the array space. This check is stricter than necessary
1055 * since several iterations may be mapped onto the same thread
1056 * and then they could be allowed to access the same memory elements,
1057 * but our check does not allow this situation.
1059 * For private memory tiles, the number of schedule dimensions that
1060 * affect the offset is computed and stored in tile->depth, with
1061 * a lower bound of data->kernel_depth. If this depth is smaller
1062 * than the minimal depth that still ensures that every element
1063 * is accessed by a single thread, then the depth is raised
1064 * to this minimal depth.
1065 * The fields of the tile are then adjusted to only refer to the tile->depth
1066 * outer schedule dimensions.
1068 * We also check that the index expression only depends on parallel
1069 * loops. That way, we can move those loops innermost and unroll them.
1070 * Again, we use a test that is stricter than necessary.
1071 * We actually check whether the index expression only depends
1072 * on the iterators that are wrapped over the threads.
1073 * These are necessarily parallel, but there may be more parallel loops.
1075 * Combining the injectivity of the first test with the single-valuedness
1076 * of the second test, we simply test for bijectivity.
1078 * If the use of the private tile requires unrolling, but some
1079 * of the other arrays are forcibly mapped to private memory,
1080 * then we do not allow the use of this private tile since
1081 * we cannot move the schedule dimensions that need to be unrolled down
1082 * without performing some kind of expansion on those arrays
1083 * that are forcibly mapped to private memory.
1085 * If the array is marked force_private, then we bypass all checks
1086 * and assume we can (and should) use registers.
1088 * If it turns out we can (or have to) use registers, we compute
1089 * the private memory tile size using can_tile, after introducing a dependence
1090 * on the thread indices.
1092 static int compute_group_bounds_core(struct ppcg_kernel
*kernel
,
1093 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
1095 isl_ctx
*ctx
= isl_space_get_ctx(group
->array
->space
);
1096 isl_union_map
*access
, *local
;
1097 int n_index
= group
->array
->n_index
;
1098 int no_reuse
, coalesced
;
1100 int force_private
= group
->local_array
->force_private
;
1101 int use_shared
= kernel
->options
->use_shared_memory
&&
1103 int use_private
= force_private
|| kernel
->options
->use_private_memory
;
1105 int requires_unroll
;
1108 if (!use_shared
&& !use_private
)
1110 if (gpu_array_is_read_only_scalar(group
->array
))
1112 if (!force_private
&& !group
->exact_write
)
1117 access
= gpu_array_ref_group_access_relation(group
, 1, 1);
1118 local
= localize_access(data
, isl_union_map_copy(access
));
1119 no_reuse
= isl_union_map_is_injective(local
);
1122 if (use_shared
&& no_reuse
)
1123 coalesced
= access_is_coalesced(data
, local
);
1124 isl_union_map_free(local
);
1126 if (r
>= 0 && kernel
->options
->debug
->verbose
&&
1127 use_shared
&& no_reuse
&& coalesced
)
1128 report_no_reuse_and_coalesced(kernel
, access
);
1130 if (use_shared
&& (!no_reuse
|| !coalesced
)) {
1131 group
->shared_tile
= gpu_array_tile_create(ctx
,
1132 group
->array
->n_index
);
1133 acc
= shared_access(group
, access
, data
);
1134 if (!group
->shared_tile
)
1136 else if (!can_tile(acc
, group
->shared_tile
))
1137 group
->shared_tile
=
1138 gpu_array_tile_free(group
->shared_tile
);
1142 if (r
< 0 || (!force_private
&& (!use_private
|| no_reuse
))) {
1143 isl_union_map_free(access
);
1147 access
= isl_union_map_apply_domain(access
,
1148 isl_union_map_copy(data
->thread_sched
));
1150 acc
= isl_map_from_union_map(access
);
1152 if (!force_private
&& !access_is_bijective(data
, acc
)) {
1157 unique_depth
= compute_accessed_by_single_thread_depth(data
, acc
);
1159 acc
= isl_map_intersect_domain(acc
, isl_set_copy(data
->privatization
));
1160 acc
= isl_map_project_out(acc
, isl_dim_in
, data
->thread_depth
,
1162 requires_unroll
= check_requires_unroll(data
, acc
, force_private
);
1163 if (unique_depth
< 0 || requires_unroll
< 0 ||
1164 (requires_unroll
&& kernel
->any_force_private
)) {
1166 return requires_unroll
< 0 ? -1 : 0;
1169 group
->private_tile
= gpu_array_tile_create(ctx
, n_index
);
1170 if (!group
->private_tile
) {
1174 group
->private_tile
->requires_unroll
= requires_unroll
;
1175 if (!can_tile(acc
, group
->private_tile
))
1176 group
->private_tile
= gpu_array_tile_free(group
->private_tile
);
1180 if (group
->private_tile
) {
1181 struct gpu_array_tile
*tile
= group
->private_tile
;
1182 int tile_depth
= compute_tile_depth(data
, tile
);
1183 if (tile_depth
< unique_depth
)
1184 tile_depth
= unique_depth
;
1185 if (tile_adjust_depth(tile
, tile_depth
) < 0)
1189 if (force_private
&& !group
->private_tile
)
1190 isl_die(ctx
, isl_error_internal
,
1191 "unable to map array reference group to registers",
1197 /* Compute the private and/or shared memory tiles for the array
1198 * reference group "group" of array "array" and set the tile depth.
1199 * Return 0 on success and -1 on error.
1201 static int compute_group_bounds(struct ppcg_kernel
*kernel
,
1202 struct gpu_array_ref_group
*group
, struct gpu_group_data
*data
)
1206 if (compute_group_bounds_core(kernel
, group
, data
) < 0)
1208 if (set_depth(data
, group
) < 0)
1214 /* If two groups have overlapping access relations (as determined by
1215 * the "overlap" function) and if one of them involves a write,
1216 * then merge the two groups into one.
1217 * If "compute_bounds" is set, then call compute_group_bounds
1218 * on the merged groups.
1220 * Return the updated number of groups.
1221 * Return -1 on error.
1223 static int group_writes(struct ppcg_kernel
*kernel
,
1224 int n
, struct gpu_array_ref_group
**groups
,
1225 int (*overlap
)(struct gpu_array_ref_group
*group1
,
1226 struct gpu_array_ref_group
*group2
), int compute_bounds
,
1227 struct gpu_group_data
*data
)
1231 for (i
= 0; i
< n
; ++i
) {
1232 for (j
= n
- 1; j
> i
; --j
) {
1233 if (!groups
[i
]->write
&& !groups
[j
]->write
)
1236 if (!overlap(groups
[i
], groups
[j
]))
1239 groups
[i
] = join_groups_and_free(groups
[i
], groups
[j
]);
1241 groups
[j
] = groups
[n
- 1];
1242 groups
[n
- 1] = NULL
;
1247 if (compute_bounds
&&
1248 compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1256 /* If two groups have overlapping access relations (within the innermost
1257 * loop) and if one of them involves a write, then merge the two groups
1260 * Return the updated number of groups.
1262 static int group_overlapping_writes(struct ppcg_kernel
*kernel
,
1263 int n
, struct gpu_array_ref_group
**groups
,
1264 struct gpu_group_data
*data
)
1266 return group_writes(kernel
, n
, groups
, &accesses_overlap
, 0, data
);
1269 /* Check if the access relations of group1 and group2 overlap within
1270 * the outermost min(group1->min_depth, group2->min_depth) loops.
1272 static int depth_accesses_overlap(struct gpu_array_ref_group
*group1
,
1273 struct gpu_array_ref_group
*group2
)
1278 isl_map
*map_i
, *map_j
, *map
;
1280 depth
= group1
->min_depth
;
1281 if (group2
->min_depth
< depth
)
1282 depth
= group2
->min_depth
;
1283 map_i
= isl_map_copy(group1
->access
);
1284 dim
= isl_map_dim(map_i
, isl_dim_in
);
1285 map_i
= isl_map_eliminate(map_i
, isl_dim_in
, depth
, dim
- depth
);
1286 map_j
= isl_map_copy(group2
->access
);
1287 map_j
= isl_map_eliminate(map_j
, isl_dim_in
, depth
, dim
- depth
);
1288 map
= isl_map_intersect(map_i
, map_j
);
1289 empty
= isl_map_is_empty(map
);
1295 /* If two groups have overlapping access relations (within the outer
1296 * depth loops) and if one of them involves a write,
1297 * then merge the two groups into one.
1299 * Return the updated number of groups.
1301 static int group_depth_overlapping_writes(struct ppcg_kernel
*kernel
,
1302 int n
, struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1304 return group_writes(kernel
, n
, groups
, &depth_accesses_overlap
, 1,
1308 /* Is the size of the tile specified by "tile" smaller than the sum of
1309 * the sizes of the tiles specified by "tile1" and "tile2"?
1311 static int smaller_tile(struct gpu_array_tile
*tile
,
1312 struct gpu_array_tile
*tile1
, struct gpu_array_tile
*tile2
)
1315 isl_val
*size
, *size1
, *size2
;
1317 size
= gpu_array_tile_size(tile
);
1318 size1
= gpu_array_tile_size(tile1
);
1319 size2
= gpu_array_tile_size(tile2
);
1321 size
= isl_val_sub(size
, size1
);
1322 size
= isl_val_sub(size
, size2
);
1323 smaller
= isl_val_is_neg(size
);
1330 /* Given an initial grouping of array references and shared memory tiles
1331 * for each group that allows for a shared memory tile, merge two groups
1332 * if both have a shared memory tile, the merged group also has
1333 * a shared memory tile and the size of the tile for the merge group
1334 * is smaller than the sum of the tile sizes of the individual groups.
1336 * If merging two groups decreases the depth of the tile of
1337 * one or both of the two groups, then we need to check for overlapping
1340 * Return the number of groups after merging.
1341 * Return -1 on error.
1343 static int group_common_shared_memory_tile(struct ppcg_kernel
*kernel
,
1344 struct gpu_array_info
*array
, int n
,
1345 struct gpu_array_ref_group
**groups
, struct gpu_group_data
*data
)
1348 int recompute_overlap
= 0;
1350 for (i
= 0; i
< n
; ++i
) {
1351 if (!groups
[i
]->shared_tile
)
1353 for (j
= n
- 1; j
> i
; --j
) {
1354 struct gpu_array_ref_group
*group
;
1356 if (!groups
[j
]->shared_tile
)
1359 if (!depth_accesses_overlap(groups
[i
], groups
[j
]))
1362 group
= join_groups(groups
[i
], groups
[j
]);
1363 if (compute_group_bounds(kernel
, group
, data
) < 0) {
1364 gpu_array_ref_group_free(group
);
1367 if (!group
->shared_tile
||
1368 !smaller_tile(group
->shared_tile
,
1369 groups
[i
]->shared_tile
,
1370 groups
[j
]->shared_tile
)) {
1371 gpu_array_ref_group_free(group
);
1375 if (group
->min_depth
< groups
[i
]->min_depth
||
1376 group
->min_depth
< groups
[j
]->min_depth
)
1377 recompute_overlap
= 1;
1378 gpu_array_ref_group_free(groups
[i
]);
1379 gpu_array_ref_group_free(groups
[j
]);
1382 groups
[j
] = groups
[n
- 1];
1387 if (recompute_overlap
)
1388 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1392 /* Set array->n_group and array->groups to n and groups.
1394 * Additionally, set the "nr" field of each group.
1396 static void set_array_groups(struct gpu_local_array_info
*array
,
1397 int n
, struct gpu_array_ref_group
**groups
)
1402 array
->groups
= groups
;
1404 for (i
= 0; i
< n
; ++i
)
1408 /* Combine all groups in "groups" into a single group and return
1409 * the new number of groups (1 or 0 if there were no groups to start with).
1411 static int join_all_groups(int n
, struct gpu_array_ref_group
**groups
)
1415 for (i
= n
- 1; i
> 0; --i
) {
1416 groups
[0] = join_groups_and_free(groups
[0], groups
[i
]);
1424 /* Group array references that should be considered together when
1425 * deciding whether to access them from private, shared or global memory.
1426 * Return -1 on error.
1428 * In particular, if two array references overlap and if one of them
1429 * is a write, then the two references are grouped together.
1430 * We first perform an initial grouping based only on the access relation.
1431 * After computing shared and private memory tiles, we check for
1432 * overlapping writes again, but this time taking into account
1433 * the depth of the effective tile.
1435 * Furthermore, if two groups admit a shared memory tile and if the
1436 * combination of the two also admits a shared memory tile, we merge
1439 * If the array contains structures, then we compute a single
1440 * reference group without trying to find any tiles
1441 * since we do not map such arrays to private or shared
1442 * memory. The only exception is when those arrays of structures
1443 * are required to be mapped to private memory.
1445 static int group_array_references(struct ppcg_kernel
*kernel
,
1446 struct gpu_local_array_info
*local
, struct gpu_group_data
*data
)
1450 isl_ctx
*ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1451 struct gpu_array_ref_group
**groups
;
1453 groups
= isl_calloc_array(ctx
, struct gpu_array_ref_group
*,
1454 local
->array
->n_ref
);
1458 n
= populate_array_references(local
, groups
, data
);
1460 if (local
->array
->has_compound_element
&& !local
->force_private
) {
1461 n
= join_all_groups(n
, groups
);
1462 set_array_groups(local
, n
, groups
);
1466 n
= group_overlapping_writes(kernel
, n
, groups
, data
);
1468 for (i
= 0; i
< n
; ++i
)
1469 if (compute_group_bounds(kernel
, groups
[i
], data
) < 0)
1472 n
= group_depth_overlapping_writes(kernel
, n
, groups
, data
);
1474 n
= group_common_shared_memory_tile(kernel
, local
->array
,
1477 set_array_groups(local
, n
, groups
);
1482 for (i
= 0; i
< local
->array
->n_ref
; ++i
)
1483 gpu_array_ref_group_free(groups
[i
]);
1487 /* For each array in the input program that can be mapped to private memory,
1488 * check if there are any order dependences active inside the current kernel,
1489 * within the same iteration of the host schedule, i.e., the prefix
1490 * schedule at "node".
1491 * If so, mark the array as force_private so that its reference groups will be
1492 * mapped to a registers.
1494 * Note that the arrays that cannot be mapped to private memory have
1495 * had their order dependences added to prog->array_order and
1496 * subsequently to the coincidence constraints.
1498 static void check_can_be_private_live_ranges(struct ppcg_kernel
*kernel
,
1499 __isl_keep isl_schedule_node
*node
)
1502 isl_union_map
*sched
;
1503 isl_union_set
*domain
;
1504 isl_multi_union_pw_aff
*prefix
;
1505 isl_union_pw_multi_aff
*contraction
;
1507 if (!kernel
->options
->live_range_reordering
)
1510 kernel
->any_force_private
= 0;
1512 prefix
= isl_schedule_node_get_prefix_schedule_multi_union_pw_aff(node
);
1513 contraction
= isl_union_pw_multi_aff_copy(kernel
->contraction
);
1514 prefix
= isl_multi_union_pw_aff_pullback_union_pw_multi_aff(prefix
,
1516 domain
= isl_union_set_copy(kernel
->expanded_domain
);
1517 domain
= isl_union_set_universe(domain
);
1519 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1520 struct gpu_local_array_info
*local
= &kernel
->array
[i
];
1521 isl_union_map
*order
;
1523 local
->force_private
= 0;
1524 if (!gpu_array_can_be_private(local
->array
))
1526 order
= isl_union_map_copy(local
->array
->dep_order
);
1527 order
= isl_union_map_intersect_domain(order
,
1528 isl_union_set_copy(domain
));
1529 order
= isl_union_map_intersect_range(order
,
1530 isl_union_set_copy(domain
));
1531 order
= isl_union_map_eq_at_multi_union_pw_aff(order
,
1532 isl_multi_union_pw_aff_copy(prefix
));
1533 if (!isl_union_map_is_empty(order
)) {
1534 local
->force_private
= 1;
1535 kernel
->any_force_private
= 1;
1537 isl_union_map_free(order
);
1540 isl_multi_union_pw_aff_free(prefix
);
1541 isl_union_set_free(domain
);
1544 /* Expand the domain of the schedule "s" by plugging in
1545 * the contraction "contraction" and return the result.
1547 static __isl_give isl_union_map
*expand(__isl_take isl_union_map
*s
,
1548 __isl_keep isl_union_pw_multi_aff
*contraction
)
1550 contraction
= isl_union_pw_multi_aff_copy(contraction
);
1551 s
= isl_union_map_preimage_domain_union_pw_multi_aff(s
, contraction
);
1555 /* Create a set of dimension data->thread_depth + data->n_thread
1556 * that equates the residue of the final data->n_thread dimensions
1557 * modulo the kernel->block_dim sizes to the thread identifiers.
1558 * Store the computed set in data->privatization.
1560 * The construction starts with the space of kernel->thread_filter,
1561 * which is known to reference all thread identifiers.
1563 static void compute_privatization(struct gpu_group_data
*data
,
1564 struct ppcg_kernel
*kernel
)
1569 isl_local_space
*ls
;
1572 ctx
= isl_union_map_get_ctx(data
->shared_sched
);
1573 space
= isl_union_set_get_space(kernel
->thread_filter
);
1574 space
= isl_space_set_from_params(space
);
1575 space
= isl_space_add_dims(space
, isl_dim_set
,
1576 data
->thread_depth
+ data
->n_thread
);
1577 set
= isl_set_universe(space
);
1578 space
= isl_set_get_space(set
);
1579 ls
= isl_local_space_from_space(space
);
1581 for (i
= 0; i
< data
->n_thread
; ++i
) {
1582 isl_aff
*aff
, *aff2
;
1588 aff
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1589 isl_dim_set
, data
->thread_depth
+ i
);
1590 v
= isl_val_int_from_si(ctx
, kernel
->block_dim
[i
]);
1591 aff
= isl_aff_mod_val(aff
, v
);
1592 id
= isl_id_list_get_id(kernel
->thread_ids
, i
);
1593 pos
= isl_set_find_dim_by_id(set
, isl_dim_param
, id
);
1595 aff2
= isl_aff_var_on_domain(isl_local_space_copy(ls
),
1596 isl_dim_param
, pos
);
1597 aff
= isl_aff_sub(aff
, aff2
);
1598 c
= isl_equality_from_aff(aff
);
1599 set
= isl_set_add_constraint(set
, c
);
1602 isl_local_space_free(ls
);
1603 data
->privatization
= set
;
1606 /* Return the prefix schedule at "node" as a relation
1607 * between domain elements and schedule dimensions after detecting
1608 * equalities in this relation.
1610 static __isl_give isl_union_map
*prefix_with_equalities(
1611 __isl_keep isl_schedule_node
*node
)
1613 isl_union_map
*schedule
;
1615 schedule
= isl_schedule_node_get_prefix_schedule_relation(node
);
1616 schedule
= isl_union_map_detect_equalities(schedule
);
1621 /* Group references of all arrays in "kernel".
1622 * "node" points to the kernel mark.
1624 * We first extract all required schedule information into
1625 * a gpu_group_data structure and then consider each array
1628 int gpu_group_references(struct ppcg_kernel
*kernel
,
1629 __isl_keep isl_schedule_node
*node
)
1633 isl_union_pw_multi_aff
*contraction
;
1634 struct gpu_group_data data
;
1636 check_can_be_private_live_ranges(kernel
, node
);
1638 data
.scop
= kernel
->prog
->scop
;
1640 data
.kernel_depth
= isl_schedule_node_get_schedule_depth(node
);
1641 data
.host_sched
= isl_schedule_node_get_prefix_schedule_relation(node
);
1643 node
= isl_schedule_node_copy(node
);
1644 node
= gpu_tree_move_down_to_thread(node
, kernel
->core
);
1645 data
.shared_depth
= isl_schedule_node_get_schedule_depth(node
);
1646 data
.shared_sched
= prefix_with_equalities(node
);
1648 node
= isl_schedule_node_child(node
, 0);
1649 data
.thread_depth
= isl_schedule_node_get_schedule_depth(node
);
1650 data
.n_thread
= isl_schedule_node_band_n_member(node
);
1651 data
.copy_sched
= isl_union_map_copy(data
.shared_sched
);
1652 data
.thread_sched
= isl_union_map_copy(data
.copy_sched
);
1653 data
.thread_sched
= isl_union_map_flat_range_product(data
.thread_sched
,
1654 isl_schedule_node_band_get_partial_schedule_union_map(node
));
1655 data
.thread_sched
= isl_union_map_detect_equalities(data
.thread_sched
);
1657 contraction
= isl_union_pw_multi_aff_copy(kernel
->contraction
);
1658 data
.host_sched
= expand(data
.host_sched
, contraction
);
1659 data
.shared_sched
= expand(data
.shared_sched
, contraction
);
1660 isl_union_map_free(data
.copy_sched
);
1661 data
.copy_sched
= isl_union_map_copy(data
.shared_sched
);
1662 data
.thread_sched
= expand(data
.thread_sched
, contraction
);
1663 isl_union_pw_multi_aff_free(contraction
);
1665 node
= isl_schedule_node_child(node
, 0);
1666 data
.full_sched
= isl_union_map_copy(data
.thread_sched
);
1667 data
.full_sched
= isl_union_map_flat_range_product(data
.full_sched
,
1668 isl_schedule_node_get_subtree_schedule_union_map(node
));
1669 isl_schedule_node_free(node
);
1671 compute_privatization(&data
, kernel
);
1673 for (i
= 0; i
< kernel
->n_array
; ++i
) {
1674 r
= group_array_references(kernel
, &kernel
->array
[i
], &data
);
1679 isl_union_map_free(data
.host_sched
);
1680 isl_union_map_free(data
.shared_sched
);
1681 isl_union_map_free(data
.copy_sched
);
1682 isl_union_map_free(data
.thread_sched
);
1683 isl_union_map_free(data
.full_sched
);
1684 isl_set_free(data
.privatization
);
1689 /* Given a description of an array tile "tile" and the "space"
1693 * where D represents the first tile->depth schedule dimensions
1694 * and A represents the array, construct an isl_multi_aff
1696 * { [D[i] -> A[a]] -> A'[a'] }
1698 * with A' a scaled down copy of A according to the shifts and strides
1699 * in "tile". In particular,
1701 * a' = (a + shift(i))/stride
1703 * "insert_array" represents
1707 * and is used to insert A into the domain of functions that only
1710 static __isl_give isl_multi_aff
*strided_tile(
1711 struct gpu_array_tile
*tile
, __isl_keep isl_space
*space
,
1712 __isl_keep isl_multi_aff
*insert_array
)
1716 isl_multi_aff
*shift
;
1717 isl_multi_val
*stride
;
1719 isl_local_space
*ls
;
1720 isl_multi_aff
*tiling
;
1722 ctx
= isl_space_get_ctx(space
);
1723 space2
= isl_space_domain(isl_space_copy(space
));
1724 ls
= isl_local_space_from_space(space2
);
1725 space2
= isl_space_range(isl_space_copy(space
));
1726 stride
= isl_multi_val_zero(space2
);
1727 shift
= isl_multi_aff_zero(isl_space_copy(space
));
1729 for (i
= 0; i
< tile
->n
; ++i
) {
1730 struct gpu_array_bound
*bound
= &tile
->bound
[i
];
1734 if (tile
->bound
[i
].shift
) {
1735 stride_i
= isl_val_copy(bound
->stride
);
1736 shift_i
= isl_aff_copy(bound
->shift
);
1738 stride_i
= isl_val_one(ctx
);
1739 shift_i
= isl_aff_zero_on_domain(
1740 isl_local_space_copy(ls
));
1743 stride
= isl_multi_val_set_val(stride
, i
, stride_i
);
1744 shift
= isl_multi_aff_set_aff(shift
, i
, shift_i
);
1746 isl_local_space_free(ls
);
1748 shift
= isl_multi_aff_pullback_multi_aff(shift
,
1749 isl_multi_aff_copy(insert_array
));
1751 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1752 tiling
= isl_multi_aff_add(tiling
, shift
);
1753 tiling
= isl_multi_aff_scale_down_multi_val(tiling
, stride
);
1758 /* Compute a tiling for the array reference group "group".
1760 * The tiling is of the form
1762 * { [D[i] -> A[a]] -> T[t] }
1764 * where D represents the first tile->depth schedule dimensions,
1765 * A represents the global array and T represents the shared or
1766 * private memory tile. The name of T is the name of the local
1769 * If there is any stride in the accesses, then the mapping is
1771 * t = (a + shift(i))/stride - lb(i)
1773 * otherwise, it is simply
1777 void gpu_array_ref_group_compute_tiling(struct gpu_array_ref_group
*group
)
1780 struct gpu_array_tile
*tile
;
1782 isl_multi_aff
*tiling
, *lb
, *insert_array
;
1786 tile
= gpu_array_ref_group_tile(group
);
1790 space
= isl_map_get_space(group
->access
);
1791 space
= isl_space_from_range(isl_space_range(space
));
1792 space
= isl_space_add_dims(space
, isl_dim_in
, tile
->depth
);
1793 insert_array
= isl_multi_aff_domain_map(isl_space_copy(space
));
1795 for (i
= 0; i
< tile
->n
; ++i
)
1796 if (tile
->bound
[i
].shift
)
1800 tiling
= strided_tile(tile
, space
, insert_array
);
1802 tiling
= isl_multi_aff_range_map(isl_space_copy(space
));
1804 lb
= isl_multi_aff_zero(space
);
1805 for (i
= 0; i
< tile
->n
; ++i
) {
1806 isl_aff
*lb_i
= isl_aff_copy(tile
->bound
[i
].lb
);
1807 lb
= isl_multi_aff_set_aff(lb
, i
, lb_i
);
1809 lb
= isl_multi_aff_pullback_multi_aff(lb
, insert_array
);
1811 tiling
= isl_multi_aff_sub(tiling
, lb
);
1813 p
= isl_printer_to_str(isl_multi_aff_get_ctx(tiling
));
1814 p
= gpu_array_ref_group_print_name(group
, p
);
1815 local_name
= isl_printer_get_str(p
);
1816 isl_printer_free(p
);
1817 tiling
= isl_multi_aff_set_tuple_name(tiling
, isl_dim_out
, local_name
);
1820 tile
->tiling
= tiling
;