2 * Copyright 2010-2011 INRIA Saclay
3 * Copyright 2012 Ecole Normale Superieure
5 * Use of this software is governed by the GNU LGPLv2.1 license
7 * Written by Sven Verdoolaege, INRIA Saclay - Ile-de-France,
8 * Parc Club Orsay Universite, ZAC des vignes, 4 rue Jacques Monod,
10 * and Ecole Normale Superieure, 45 rue d’Ulm, 75230 Paris, France
16 #include <isl/polynomial.h>
17 #include <isl/union_set.h>
22 #include <isl/schedule.h>
23 #include <isl/options.h>
24 #include <isl/ast_build.h>
28 #include "ppcg_options.h"
30 /* The fields stride, shift and shift_map only contain valid information
32 * If so, they express that current index is such that if you add shift,
33 * then the result is always a multiple of stride.
34 * shift_map contains the mapping
36 * i -> (i + shift)/stride
38 * Let D represent the initial shared_len dimensions of the computed schedule.
39 * The spaces of "lb" and "shift" are of the form
43 * "shift_map" is of the form
45 * [D -> i] -> [D -> (i + shift(D))/stride]
47 struct gpu_array_bound
{
53 isl_basic_map
*shift_map
;
56 /* A tile of an array.
58 * n is the dimension of the array.
59 * bound is an array of size "n" representing the lower bound
60 * and size for each index.
62 struct gpu_array_tile
{
64 struct gpu_array_bound
*bound
;
67 struct gpu_array_info
;
69 /* A group of array references in a kernel that should be handled together.
70 * If private_tile is not NULL, then it is mapped to registers.
71 * Otherwise, if shared_tile is not NULL, it is mapped to shared memory.
72 * Otherwise, it is accessed from global memory.
74 struct gpu_array_ref_group
{
75 /* The references in this group access this array. */
76 struct gpu_array_info
*array
;
77 /* Position of this group in the list of reference groups of array. */
80 /* The following fields are use during the construction of the groups.
81 * access is the combined access relation relative to the shared
82 * memory tiling. In particular, the domain of the map corresponds
83 * to the first shared_len dimensions of the computed schedule.
84 * write is set if any access in the group is a write.
89 /* The shared memory tile, NULL if none. */
90 struct gpu_array_tile
*shared_tile
;
92 /* The private memory tile, NULL if none. */
93 struct gpu_array_tile
*private_tile
;
95 /* References in this group; point to elements of a linked list. */
97 struct gpu_stmt_access
**refs
;
99 /* Last shared memory tile dimension that affects tile of this group. */
105 struct ppcg_options
*options
;
107 struct gpu_prog
*prog
;
109 /* tile, grid and block sizes for each kernel */
110 isl_union_map
*sizes
;
112 /* Identifier of current kernel. */
114 /* Pointer to the current kernel. */
115 struct ppcg_kernel
*kernel
;
117 /* First tile dimension. */
119 /* Number of tile dimensions. */
121 /* Number of initial parallel loops among tile dimensions. */
124 /* Number of dimensions determining shared memory. */
127 /* Number of rows in the untiled schedule. */
129 /* Number of rows in the tiled schedule. */
131 /* Number of rows in schedule after tiling/wrapping over threads. */
132 int thread_tiled_len
;
134 /* Global untiled schedule. */
135 isl_union_map
*sched
;
136 /* Local (per kernel launch) tiled schedule. */
137 isl_union_map
*tiled_sched
;
138 /* Local schedule per shared memory tile loop iteration. */
139 isl_union_map
*local_sched
;
141 /* Local tiled schedule projected onto the shared tile loops and
142 * the loops that will be wrapped over the threads,
143 * with all shared tile loops parametrized.
145 isl_union_map
*shared_sched
;
146 /* Projects out the loops that will be wrapped over the threads
149 isl_union_map
*shared_proj
;
151 /* A map that takes the range of shared_sched as input,
152 * wraps the appropriate loops over the threads and then projects
155 isl_map
*privatization
;
157 /* A map from the shared memory tile loops and the thread indices
158 * (as parameters) to the set of accessed memory elements that
159 * will be accessed through private copies.
161 isl_union_map
*private_access
;
163 /* The schedule for the current private/shared access
164 * (within print_private_access or print_shared_access).
167 /* The array reference group corresponding to copy_sched. */
168 struct gpu_array_ref_group
*copy_group
;
170 /* First loop to unroll (or -1 if none) in the current part of the
177 /* Note: in the input file, the sizes of the grid and the blocks
178 * are specified in the order x, y, z, but internally, the sizes
179 * are stored in reverse order, so that the last element always
180 * refers to the x dimension.
187 /* Print the name of the local copy of a given group of array references.
189 static __isl_give isl_printer
*print_array_name(__isl_take isl_printer
*p
,
190 struct gpu_array_ref_group
*group
)
194 if (group
->private_tile
)
195 p
= isl_printer_print_str(p
, "private_");
196 else if (group
->shared_tile
)
197 p
= isl_printer_print_str(p
, "shared_");
200 p
= isl_printer_print_str(p
, group
->array
->name
);
201 if (!global
&& group
->array
->n_group
> 1) {
202 p
= isl_printer_print_str(p
, "_");
203 p
= isl_printer_print_int(p
, group
->nr
);
209 /* Collect all references to the given array and store pointers to them
212 static void collect_references(struct gpu_prog
*prog
,
213 struct gpu_array_info
*array
)
219 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
220 struct gpu_stmt
*stmt
= &prog
->stmts
[i
];
221 struct gpu_stmt_access
*access
;
223 for (access
= stmt
->accesses
; access
; access
= access
->next
) {
225 name
= isl_map_get_tuple_name(access
->access
,
227 if (name
&& !strcmp(array
->name
, name
))
233 array
->refs
= isl_alloc_array(prog
->ctx
, struct gpu_stmt_access
*, n
);
237 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
238 struct gpu_stmt
*stmt
= &prog
->stmts
[i
];
239 struct gpu_stmt_access
*access
;
241 for (access
= stmt
->accesses
; access
; access
= access
->next
) {
243 name
= isl_map_get_tuple_name(access
->access
,
245 if (!name
|| strcmp(array
->name
, name
))
248 array
->refs
[n
++] = access
;
253 /* Create a gpu_array_tile for an array of dimension "n_index".
255 static struct gpu_array_tile
*create_tile(isl_ctx
*ctx
, int n_index
)
258 struct gpu_array_tile
*tile
;
260 tile
= isl_calloc_type(ctx
, struct gpu_array_tile
);
265 tile
->bound
= isl_alloc_array(ctx
, struct gpu_array_bound
, n_index
);
268 for (i
= 0; i
< n_index
; ++i
) {
269 tile
->bound
[i
].size
= NULL
;
270 tile
->bound
[i
].lb
= NULL
;
271 tile
->bound
[i
].stride
= NULL
;
272 tile
->bound
[i
].shift
= NULL
;
273 tile
->bound
[i
].shift_map
= NULL
;
279 static void *free_tile(struct gpu_array_tile
*tile
)
286 for (j
= 0; j
< tile
->n
; ++j
) {
287 isl_val_free(tile
->bound
[j
].size
);
288 isl_val_free(tile
->bound
[j
].stride
);
289 isl_aff_free(tile
->bound
[j
].lb
);
290 isl_aff_free(tile
->bound
[j
].shift
);
291 isl_basic_map_free(tile
->bound
[j
].shift_map
);
299 static struct pet_array
*find_array(struct ppcg_scop
*scop
,
300 __isl_keep isl_set
*accessed
)
305 id
= isl_set_get_tuple_id(accessed
);
307 for (i
= 0; i
< scop
->n_array
; ++i
) {
310 id_i
= isl_set_get_tuple_id(scop
->arrays
[i
]->extent
);
317 return i
< scop
->n_array
? scop
->arrays
[i
] : NULL
;
320 /* Compute and return the extent of "array", taking into account the set of
323 * In particular, the extent in the outer dimension is taken
324 * from "accessed", while then extent in the remaing dimensions
325 * are taken from array->extent.
327 * The extent in the outer dimension cannot be taken from array->extent
328 * because that may be unbounded. Furthermore, even if it is bounded,
329 * it may be larger than the piece of the array that is being accessed.
331 static __isl_give isl_set
*compute_extent(struct pet_array
*array
,
332 __isl_keep isl_set
*accessed
)
339 extent
= isl_set_copy(array
->extent
);
341 n_index
= isl_set_dim(accessed
, isl_dim_set
);
345 extent
= isl_set_project_out(extent
, isl_dim_set
, 0, 1);
346 outer
= isl_set_copy(accessed
);
347 outer
= isl_set_project_out(outer
, isl_dim_set
, 1, n_index
- 1);
348 extent
= isl_set_flat_product(outer
, extent
);
349 id
= isl_set_get_tuple_id(accessed
);
350 extent
= isl_set_set_tuple_id(extent
, id
);
355 /* Compute bounds on the host arrays based on the accessed elements
356 * and collect all references to the array.
358 * If the array is zero-dimensional, i.e., a scalar, we check
359 * whether it is read-only.
361 static int extract_array_info(__isl_take isl_set
*array
, void *user
)
364 struct gpu_prog
*prog
= (struct gpu_prog
*)user
;
368 struct pet_array
*pa
;
371 n_index
= isl_set_dim(array
, isl_dim_set
);
372 name
= isl_set_get_tuple_name(array
);
373 bounds
= isl_alloc_array(isl_set_get_ctx(array
),
374 isl_pw_aff
*, n_index
);
376 prog
->array
[prog
->n_array
].dim
= isl_set_get_space(array
);
377 prog
->array
[prog
->n_array
].name
= strdup(name
);
378 prog
->array
[prog
->n_array
].n_index
= n_index
;
379 prog
->array
[prog
->n_array
].bound
= bounds
;
381 pa
= find_array(prog
->scop
, array
);
384 prog
->array
[prog
->n_array
].type
= strdup(pa
->element_type
);
385 prog
->array
[prog
->n_array
].size
= pa
->element_size
;
386 prog
->array
[prog
->n_array
].local
= pa
->declared
&& !pa
->exposed
;
390 isl_union_map
*write
;
393 write
= isl_union_map_copy(prog
->write
);
394 space
= isl_set_universe(isl_set_get_space(array
));
395 write
= isl_union_map_intersect_range(write
,
396 isl_union_set_from_set(space
));
397 empty
= isl_union_map_is_empty(write
);
398 isl_union_map_free(write
);
400 prog
->array
[prog
->n_array
].read_only
= empty
;
403 extent
= compute_extent(pa
, array
);
404 for (i
= 0; i
< n_index
; ++i
) {
410 bound
= isl_set_dim_max(isl_set_copy(extent
), i
);
412 dom
= isl_pw_aff_domain(isl_pw_aff_copy(bound
));
413 ls
= isl_local_space_from_space(isl_set_get_space(dom
));
414 one
= isl_aff_zero_on_domain(ls
);
415 one
= isl_aff_add_constant_si(one
, 1);
416 bound
= isl_pw_aff_add(bound
, isl_pw_aff_alloc(dom
, one
));
417 bound
= isl_pw_aff_gist(bound
, isl_set_copy(prog
->context
));
421 prog
->array
[prog
->n_array
].extent
= extent
;
423 collect_references(prog
, &prog
->array
[prog
->n_array
]);
431 void collect_array_info(struct gpu_prog
*prog
)
433 isl_union_set
*arrays
;
435 arrays
= isl_union_map_range(isl_union_map_copy(prog
->read
));
436 arrays
= isl_union_set_union(arrays
,
437 isl_union_map_range(isl_union_map_copy(prog
->write
)));
438 arrays
= isl_union_set_coalesce(arrays
);
440 prog
->n_array
= isl_union_set_n_set(arrays
);
441 prog
->array
= isl_alloc_array(prog
->ctx
,
442 struct gpu_array_info
, prog
->n_array
);
445 isl_union_set_foreach_set(arrays
, &extract_array_info
, prog
);
446 isl_union_set_free(arrays
);
449 static void free_array_info(struct gpu_prog
*prog
)
453 for (i
= 0; i
< prog
->n_array
; ++i
) {
454 int n_index
= prog
->array
[i
].n_index
;
455 free(prog
->array
[i
].type
);
456 free(prog
->array
[i
].name
);
457 for (j
= 0; j
< n_index
; ++j
)
458 isl_pw_aff_free(prog
->array
[i
].bound
[j
]);
459 isl_space_free(prog
->array
[i
].dim
);
460 isl_set_free(prog
->array
[i
].extent
);
461 free(prog
->array
[i
].bound
);
462 free(prog
->array
[i
].refs
);
467 /* Check if a gpu array is a scalar. A scalar is a value that is not stored
468 * as an array or through a pointer reference, but as single data element. At
469 * the moment, scalars are represented as zero dimensional arrays.
471 int gpu_array_is_scalar(struct gpu_array_info
*array
)
473 return (array
->n_index
== 0);
476 /* Is "array" a read-only scalar?
478 int gpu_array_is_read_only_scalar(struct gpu_array_info
*array
)
480 return gpu_array_is_scalar(array
) && array
->read_only
;
483 /* Internal data structure for extract_size_of_type.
484 * "type" specifies the name of the space that we want to extract.
485 * "res" is used to store the subset of that space.
487 struct ppcg_extract_size_data
{
492 /* This function is called for each set in a union_set.
493 * If the name of the set matches data->type, we store the
496 static int extract_size_of_type(__isl_take isl_set
*size
, void *user
)
498 struct ppcg_extract_size_data
*data
= user
;
501 name
= isl_set_get_tuple_name(size
);
502 if (name
&& !strcmp(name
, data
->type
)) {
511 /* Given a union map { kernel[i] -> *[...] },
512 * return the range in the space called "type" for the kernel with
513 * sequence number "id".
515 static __isl_give isl_set
*extract_sizes(__isl_keep isl_union_map
*sizes
,
516 const char *type
, int id
)
520 isl_union_set
*local_sizes
;
521 struct ppcg_extract_size_data data
= { type
, NULL
};
526 space
= isl_union_map_get_space(sizes
);
527 space
= isl_space_set_from_params(space
);
528 space
= isl_space_add_dims(space
, isl_dim_set
, 1);
529 space
= isl_space_set_tuple_name(space
, isl_dim_set
, "kernel");
530 dom
= isl_set_universe(space
);
531 dom
= isl_set_fix_si(dom
, isl_dim_set
, 0, id
);
533 local_sizes
= isl_union_set_apply(isl_union_set_from_set(dom
),
534 isl_union_map_copy(sizes
));
535 isl_union_set_foreach_set(local_sizes
, &extract_size_of_type
, &data
);
536 isl_union_set_free(local_sizes
);
540 /* Given a singleton set, extract the first (at most *len) elements
541 * of the single integer tuple into *sizes and update *len if needed.
543 static void read_sizes_from_set(__isl_take isl_set
*set
, int *sizes
, int *len
)
551 dim
= isl_set_dim(set
, isl_dim_set
);
555 for (i
= 0; i
< *len
; ++i
) {
558 v
= isl_set_plain_get_val_if_fixed(set
, isl_dim_set
, i
);
561 sizes
[i
] = isl_val_get_num_si(v
);
568 /* Extract user specified "tile" sizes from the "sizes" command line option,
569 * defaulting to option->tile_size in each dimension.
571 static void read_tile_sizes(struct gpu_gen
*gen
)
576 gen
->tile_size
= isl_alloc_array(gen
->ctx
, int, gen
->tile_len
);
577 assert(gen
->tile_size
);
578 for (n
= 0; n
< gen
->tile_len
; ++n
)
579 gen
->tile_size
[n
] = gen
->options
->tile_size
;
581 size
= extract_sizes(gen
->sizes
, "tile", gen
->kernel_id
);
582 read_sizes_from_set(size
, gen
->tile_size
, &gen
->tile_len
);
584 if (gen
->n_parallel
> gen
->tile_len
)
585 gen
->n_parallel
= gen
->tile_len
;
588 /* Extract user specified "block" sizes from the "sizes" command line option,
589 * after filling in some potentially useful defaults.
591 static void read_block_sizes(struct gpu_gen
*gen
)
597 gen
->n_block
= (n
<= 3) ? n
: 3;
598 switch (gen
->n_block
) {
600 gen
->block_dim
[0] = 512;
603 gen
->block_dim
[0] = 32;
604 gen
->block_dim
[1] = 16;
607 gen
->block_dim
[0] = 32;
608 gen
->block_dim
[1] = 4;
609 gen
->block_dim
[2] = 4;
613 size
= extract_sizes(gen
->sizes
, "block", gen
->kernel_id
);
614 read_sizes_from_set(size
, gen
->block_dim
, &gen
->n_block
);
617 /* Extract user specified "grid" sizes from the "sizes" command line option,
618 * after filling in some potentially useful defaults.
620 static void read_grid_sizes(struct gpu_gen
*gen
)
622 int n
= gen
->n_parallel
;
625 gen
->n_grid
= (n
<= 2) ? n
: 2;
626 switch (gen
->n_grid
) {
628 gen
->grid_dim
[0] = 32768;
631 gen
->grid_dim
[0] = 256;
632 gen
->grid_dim
[1] = 256;
636 size
= extract_sizes(gen
->sizes
, "grid", gen
->kernel_id
);
637 read_sizes_from_set(size
, gen
->grid_dim
, &gen
->n_grid
);
640 /* Extract user specified sizes from the "sizes" command line option
641 * after filling in some potentially useful defaults.
643 static void read_sizes(struct gpu_gen
*gen
)
645 read_tile_sizes(gen
);
646 read_block_sizes(gen
);
647 read_grid_sizes(gen
);
650 static void free_stmts(struct gpu_stmt
*stmts
, int n
)
654 for (i
= 0; i
< n
; ++i
) {
655 struct gpu_stmt_access
*access
, *next
;
657 for (access
= stmts
[i
].accesses
; access
; access
= next
) {
659 isl_map_free(access
->access
);
663 isl_id_free(stmts
[i
].id
);
668 void clear_gpu_gen(struct gpu_gen
*gen
)
670 isl_union_map_free(gen
->sizes
);
671 isl_union_map_free(gen
->sched
);
674 /* Construct a map from a domain of dimensionality "len"
675 * to a domain of dimensionality "len" + "tile_len" that tiles
676 * the "tile_len" coordinates starting at "first".
677 * In particular, [s_i] -> [s_i / tile_size[i], s_i % tile_size[i]].
678 * "dim" prescribes the parameters.
680 static __isl_give isl_map
*tile(__isl_take isl_space
*dim
, int len
,
681 int first
, int tile_len
, int *tile_size
)
688 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
689 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
+ tile_len
);
690 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
691 ls
= isl_local_space_from_space(dim
);
693 for (i
= 0; i
< len
- tile_len
; ++i
) {
694 int j
= i
< first
? i
: i
+ tile_len
;
695 int k
= i
< first
? i
: i
+ 2 * tile_len
;
697 c
= isl_equality_alloc(isl_local_space_copy(ls
));
698 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, j
, -1);
699 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, k
, 1);
700 bmap
= isl_basic_map_add_constraint(bmap
, c
);
703 for (i
= 0; i
< tile_len
; ++i
) {
704 c
= isl_equality_alloc(isl_local_space_copy(ls
));
705 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
,
707 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
708 first
+ i
, tile_size
[i
]);
709 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
710 first
+ i
+ tile_len
, 1);
711 bmap
= isl_basic_map_add_constraint(bmap
, c
);
713 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
714 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
715 first
+ i
+ tile_len
, 1);
716 bmap
= isl_basic_map_add_constraint(bmap
, c
);
718 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
719 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
720 first
+ i
+ tile_len
, -1);
721 c
= isl_constraint_set_constant_si(c
, tile_size
[i
] - 1);
722 bmap
= isl_basic_map_add_constraint(bmap
, c
);
725 isl_local_space_free(ls
);
727 return isl_map_from_basic_map(bmap
);
730 /* Construct a map from a domain of dimensionality "len"
731 * to a domain of dimensionality "len" + "wrap_len" that "wraps"
732 * the "wrap_len" coordinates starting at "first" according to "wrap_size".
733 * In particular, [s_i] -> [s_i, s_i % wrap_size[i]].
734 * To do so, we need extra variables corresponding to [s_i / wrap_size[i]],
735 * that are projected out at the end.
736 * "dim" prescribes the parameters.
738 static __isl_give isl_map
*wrap(__isl_take isl_space
*dim
, int len
,
739 int first
, int wrap_len
, int *wrap_size
)
746 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
747 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
+ 2 * wrap_len
);
748 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
749 ls
= isl_local_space_from_space(dim
);
751 for (i
= 0; i
< len
; ++i
) {
752 int k
= i
< first
+ wrap_len
? i
: i
+ 2 * wrap_len
;
754 c
= isl_equality_alloc(isl_local_space_copy(ls
));
755 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, -1);
756 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, k
, 1);
757 bmap
= isl_basic_map_add_constraint(bmap
, c
);
760 for (i
= 0; i
< wrap_len
; ++i
) {
761 c
= isl_equality_alloc(isl_local_space_copy(ls
));
762 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
764 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
765 first
+ wrap_len
+ i
, 1);
766 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
767 first
+ 2 * wrap_len
+ i
, wrap_size
[i
]);
768 bmap
= isl_basic_map_add_constraint(bmap
, c
);
770 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
771 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
772 first
+ wrap_len
+ i
, 1);
773 bmap
= isl_basic_map_add_constraint(bmap
, c
);
775 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
776 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
777 first
+ wrap_len
+ i
, -1);
778 c
= isl_constraint_set_constant_si(c
, wrap_size
[i
] - 1);
779 bmap
= isl_basic_map_add_constraint(bmap
, c
);
782 isl_local_space_free(ls
);
784 bmap
= isl_basic_map_project_out(bmap
, isl_dim_out
,
785 first
+ 2 * wrap_len
, wrap_len
);
787 return isl_map_from_basic_map(bmap
);
790 /* Add "n" parameters named prefix%d.
792 static __isl_give isl_set
*add_params( __isl_take isl_set
*set
,
793 int n
, const char *prefix
)
799 nparam
= isl_set_dim(set
, isl_dim_param
);
800 set
= isl_set_add_dims(set
, isl_dim_param
, n
);
802 for (i
= 0; i
< n
; ++i
) {
803 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
804 set
= isl_set_set_dim_name(set
, isl_dim_param
,
811 /* Equate the "n" dimensions of "set" starting at "first" to
812 * freshly created parameters named prefix%d.
814 static __isl_give isl_set
*parametrize(__isl_take isl_set
*set
,
815 int first
, int n
, const char *prefix
)
820 nparam
= isl_set_dim(set
, isl_dim_param
);
822 set
= add_params(set
, n
, prefix
);
824 for (i
= 0; i
< n
; ++i
)
825 set
= isl_set_equate(set
, isl_dim_param
, nparam
+ i
,
826 isl_dim_set
, first
+ i
);
831 /* Given a parameter space "space", create a set of dimension "len"
832 * of which the "n" dimensions starting at "first" are equated to
833 * freshly created parameters named prefix%d.
835 static __isl_give isl_set
*parametrization(__isl_take isl_space
*space
,
836 int len
, int first
, int n
, const char *prefix
)
840 space
= isl_space_set_from_params(space
);
841 space
= isl_space_add_dims(space
, isl_dim_set
, len
);
842 set
= isl_set_universe(space
);
844 return parametrize(set
, first
, n
, prefix
);
847 /* Tile the B loops over the tile sizes and then tile/wrap
848 * the T1 loops over the blocks.
850 static __isl_give isl_union_map
*tile_schedule(struct gpu_gen
*gen
,
851 __isl_take isl_union_map
*sched
)
854 isl_map
*tiling
, *block_tiling
;
856 dim
= isl_union_map_get_space(sched
);
857 tiling
= tile(isl_space_copy(dim
), gen
->untiled_len
,
858 gen
->tile_first
, gen
->tile_len
, gen
->tile_size
);
860 if (gen
->options
->wrap
)
861 block_tiling
= wrap(dim
, gen
->untiled_len
+ gen
->tile_len
,
862 gen
->tile_first
, gen
->n_grid
, gen
->grid_dim
);
864 block_tiling
= tile(dim
, gen
->untiled_len
+ gen
->tile_len
,
865 gen
->tile_first
, gen
->n_grid
, gen
->grid_dim
);
867 gen
->tiled_len
= gen
->untiled_len
+ gen
->tile_len
+ gen
->n_grid
;
869 tiling
= isl_map_apply_range(tiling
, block_tiling
);
871 sched
= isl_union_map_apply_range(sched
,
872 isl_union_map_from_map(tiling
));
874 gen
->shared_len
= gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
;
879 /* Equate the "T1P" iterators in the tiled schedule "sched"
880 * to the block dimensions.
882 static __isl_give isl_union_map
*parametrize_tiled_schedule(
883 struct gpu_gen
*gen
, __isl_take isl_union_map
*sched
)
888 dim
= isl_union_map_get_space(sched
);
889 par
= parametrization(dim
, gen
->tiled_len
,
890 gen
->tile_first
+ gen
->n_grid
, gen
->n_grid
, "b");
891 sched
= isl_union_map_intersect_range(sched
,
892 isl_union_set_from_set(par
));
897 /* Tile/wrap the P1 loops over the threads.
899 static __isl_give isl_union_map
*thread_tile_schedule(struct gpu_gen
*gen
,
900 __isl_take isl_union_map
*sched
)
906 dim
= isl_union_map_get_space(sched
);
908 if (gen
->options
->wrap
)
909 tiling
= wrap(isl_space_copy(dim
), gen
->tiled_len
,
910 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
912 tiling
= tile(isl_space_copy(dim
), gen
->tiled_len
,
913 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
914 gen
->thread_tiled_len
= gen
->tiled_len
+ gen
->n_block
;
916 sched
= isl_union_map_apply_range(sched
,
917 isl_union_map_from_map(tiling
));
919 par
= parametrization(dim
, gen
->thread_tiled_len
,
920 gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
+ gen
->n_block
,
922 sched
= isl_union_map_intersect_range(sched
,
923 isl_union_set_from_set(par
));
925 gen
->shared_len
= gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
;
930 /* If the user asked for it, scale the shared memory tile loops
931 * (T1T and T2) of "sched" by gen->tile_size[i].
932 * If we are not performing "wrapping", then additionally scale the T1P
933 * loops by gen->grid_dim[i].
935 static __isl_give isl_union_map
*scale_tile_loops(struct gpu_gen
*gen
,
936 __isl_take isl_union_map
*sched
)
940 isl_basic_map
*scale
;
944 if (!gen
->options
->scale_tile_loops
)
947 dim
= isl_union_map_get_space(sched
);
948 dim
= isl_space_add_dims(dim
, isl_dim_in
, gen
->tiled_len
);
949 dim
= isl_space_add_dims(dim
, isl_dim_out
, gen
->tiled_len
);
950 scale
= isl_basic_map_universe(isl_space_copy(dim
));
951 ls
= isl_local_space_from_space(dim
);
953 for (i
= 0; i
< gen
->tiled_len
; ++i
) {
956 if (i
>= gen
->tile_first
&& i
< gen
->tile_first
+ gen
->n_grid
) {
957 f
= gen
->tile_size
[i
- gen
->tile_first
];
958 if (!gen
->options
->wrap
)
959 f
*= gen
->grid_dim
[i
- gen
->tile_first
];
960 } else if (i
>= gen
->tile_first
+ gen
->n_grid
&&
961 i
< gen
->tile_first
+ gen
->n_grid
+ gen
->tile_len
) {
962 f
= gen
->tile_size
[i
- (gen
->tile_first
+ gen
->n_grid
)];
965 c
= isl_equality_alloc(isl_local_space_copy(ls
));
966 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
967 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
968 scale
= isl_basic_map_add_constraint(scale
, c
);
971 isl_local_space_free(ls
);
973 sched
= isl_union_map_apply_range(sched
,
974 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
979 /* If we are not performing "wrapping" and if the user asked for it,
980 * scale the thread tile loops (P1T) of "sched" by gen->block_dim[i].
982 static __isl_give isl_union_map
*scale_thread_tile_loops(struct gpu_gen
*gen
,
983 __isl_take isl_union_map
*sched
)
987 isl_basic_map
*scale
;
991 if (gen
->options
->wrap
)
993 if (!gen
->options
->scale_tile_loops
)
996 dim
= isl_union_map_get_space(sched
);
997 dim
= isl_space_add_dims(dim
, isl_dim_in
, gen
->thread_tiled_len
);
998 dim
= isl_space_add_dims(dim
, isl_dim_out
, gen
->thread_tiled_len
);
999 scale
= isl_basic_map_universe(isl_space_copy(dim
));
1000 ls
= isl_local_space_from_space(dim
);
1002 for (i
= 0; i
< gen
->thread_tiled_len
; ++i
) {
1005 if (i
>= gen
->shared_len
&&
1006 i
< gen
->shared_len
+ gen
->n_block
)
1007 f
= gen
->block_dim
[i
- gen
->shared_len
];
1009 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1010 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
1011 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
1012 scale
= isl_basic_map_add_constraint(scale
, c
);
1015 isl_local_space_free(ls
);
1017 sched
= isl_union_map_apply_range(sched
,
1018 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
1023 /* If we are not performing "wrapping" and if the user asked for it,
1024 * scale the "n_tile" loops starting at "first" of "sched" by gen->block_dim[i].
1026 static __isl_give isl_union_map
*scale_access_tile_loops(struct gpu_gen
*gen
,
1027 __isl_take isl_union_map
*sched
, int len
, int first
, int n_tile
)
1031 isl_basic_map
*scale
;
1033 isl_local_space
*ls
;
1035 if (gen
->options
->wrap
)
1037 if (!gen
->options
->scale_tile_loops
)
1040 dim
= isl_union_map_get_space(sched
);
1041 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
1042 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
);
1043 scale
= isl_basic_map_universe(isl_space_copy(dim
));
1044 ls
= isl_local_space_from_space(dim
);
1046 for (i
= 0; i
< len
; ++i
) {
1049 if (i
>= first
&& i
< first
+ n_tile
)
1050 f
= gen
->kernel
->block_dim
[i
- first
];
1052 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1053 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
1054 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
1055 scale
= isl_basic_map_add_constraint(scale
, c
);
1058 isl_local_space_free(ls
);
1060 sched
= isl_union_map_apply_range(sched
,
1061 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
1066 /* Add "len" parameters p[i] called prefix%d,
1067 * with bounds to 0 <= p[i] < size[i].
1069 __isl_give isl_set
*add_bounded_parameters(__isl_take isl_set
*set
,
1070 int len
, int *size
, const char *prefix
)
1075 isl_basic_set
*bset
;
1077 isl_local_space
*ls
;
1080 nparam
= isl_set_dim(set
, isl_dim_param
);
1081 set
= isl_set_add_dims(set
, isl_dim_param
, len
);
1083 for (i
= 0; i
< len
; ++i
) {
1084 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
1085 set
= isl_set_set_dim_name(set
, isl_dim_param
,
1089 dim
= isl_set_get_space(set
);
1090 bset
= isl_basic_set_universe(isl_space_copy(dim
));
1091 ls
= isl_local_space_from_space(dim
);
1093 for (i
= 0; i
< len
; ++i
) {
1094 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
1095 c
= isl_constraint_set_coefficient_si(c
, isl_dim_param
,
1097 bset
= isl_basic_set_add_constraint(bset
, c
);
1099 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
1100 c
= isl_constraint_set_coefficient_si(c
, isl_dim_param
,
1102 c
= isl_constraint_set_constant_si(c
, size
[i
] - 1);
1103 bset
= isl_basic_set_add_constraint(bset
, c
);
1106 isl_local_space_free(ls
);
1108 return isl_set_intersect(set
, isl_set_from_basic_set(bset
));
1111 /* Add "len" parameters p[i] called prefix%d,
1112 * with bounds to 0 <= p[i] < size[i].
1114 static __isl_give isl_set
*add_bounded_parameters_dynamic(
1115 __isl_take isl_set
*set
, __isl_keep isl_multi_pw_aff
*size
,
1121 isl_local_space
*ls
;
1124 len
= isl_multi_pw_aff_dim(size
, isl_dim_out
);
1125 nparam
= isl_set_dim(set
, isl_dim_param
);
1126 set
= isl_set_add_dims(set
, isl_dim_param
, len
);
1128 for (i
= 0; i
< len
; ++i
) {
1129 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
1130 set
= isl_set_set_dim_name(set
, isl_dim_param
,
1134 space
= isl_space_params(isl_set_get_space(set
));
1135 ls
= isl_local_space_from_space(space
);
1136 for (i
= 0; i
< len
; ++i
) {
1137 isl_pw_aff
*param
, *size_i
, *zero
;
1140 param
= isl_pw_aff_var_on_domain(isl_local_space_copy(ls
),
1141 isl_dim_param
, nparam
+ i
);
1143 size_i
= isl_multi_pw_aff_get_pw_aff(size
, i
);
1144 bound
= isl_pw_aff_lt_set(isl_pw_aff_copy(param
), size_i
);
1145 set
= isl_set_intersect_params(set
, bound
);
1147 zero
= isl_pw_aff_zero_on_domain(isl_local_space_copy(ls
));
1148 bound
= isl_pw_aff_ge_set(param
, zero
);
1149 set
= isl_set_intersect_params(set
, bound
);
1151 isl_local_space_free(ls
);
1156 /* Given a mapping "sched" of the form
1158 * [D -> A] -> [D -> T(A)]
1160 * apply the mapping encoded in tile->bound[i].shift_map
1161 * to the range of "sched".
1162 * The mappings in tile->bound[i].shift_map are of the form
1164 * [D -> a] -> [D -> s(D,a)]
1166 * We first compose them with a mapping
1170 * (If tile->bound[i].shift_map is not set, then it is assumed to be
1171 * an identity mapping and then we use this second mapping instead.)
1174 * [D -> a] -> s(D,a)
1176 * We precompose them with a projection on the i th dimension to obtain
1178 * [D -> T] -> s(D,T)
1180 * and collect these into
1182 * [D -> T] -> S(D,T)
1184 * Introducing D in the range yields
1186 * [D -> T] -> [D -> S(D,T)]
1188 * and application to "sched" yields
1190 * [D -> A] -> [D -> S(D,T(A))]
1192 static __isl_give isl_map
*pre_shift(__isl_take isl_map
*sched
,
1193 struct gpu_array_tile
*tile
)
1196 isl_ctx
*ctx
= isl_map_get_ctx(sched
);
1197 isl_space
*space
, *space2
;
1199 isl_map
*map
, *id
, *pre_shift
;
1201 space
= isl_space_range(isl_map_get_space(sched
));
1202 space2
= isl_space_from_domain(isl_space_copy(space
));
1203 pre_shift
= isl_map_universe(space2
);
1204 space
= isl_space_domain(isl_space_unwrap(space
));
1205 id
= isl_map_identity(isl_space_map_from_set(isl_space_copy(space
)));
1206 space
= isl_space_from_domain(space
);
1207 space
= isl_space_add_dims(space
, isl_dim_out
, 1);
1208 def
= isl_basic_map_range_map(isl_basic_map_universe(space
));
1210 for (i
= 0; i
< tile
->n
; ++i
) {
1211 isl_basic_map
*bmap
, *drop
;
1214 space
= isl_space_alloc(ctx
, 0, tile
->n
, tile
->n
);
1215 proj
= isl_map_identity(space
);
1216 proj
= isl_map_project_out(proj
, isl_dim_out
,
1217 i
+ 1, tile
->n
- (i
+ 1));
1218 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, i
);
1219 proj
= isl_map_product(isl_map_copy(id
), proj
);
1221 if (!tile
->bound
[i
].shift_map
)
1222 bmap
= isl_basic_map_copy(def
);
1224 bmap
= isl_basic_map_copy(tile
->bound
[i
].shift_map
);
1225 bmap
= isl_basic_map_apply_range(bmap
,
1226 isl_basic_map_copy(def
));
1229 map
= isl_map_from_basic_map(bmap
);
1230 map
= isl_map_apply_range(proj
, map
);
1231 pre_shift
= isl_map_flat_range_product(pre_shift
, map
);
1235 isl_basic_map_free(def
);
1237 space
= isl_space_domain(isl_map_get_space(pre_shift
));
1238 map
= isl_map_domain_map(isl_map_universe(isl_space_unwrap(space
)));
1239 pre_shift
= isl_map_range_product(map
, pre_shift
);
1241 sched
= isl_map_apply_range(sched
, pre_shift
);
1246 /* Given an access relation to a tile of an array, construct a map that
1247 * maps each element in the space of the access relation
1248 * to a copy of the tile shifted to the origin
1249 * (based on the lower bounds in group->private_tile or group->shared_tile).
1250 * If any of the indices is strided, then
1251 * {private,shared}_tile->bound[i].shift_map is applied to the index first.
1252 * The domain space of the resulting map is that of access "access",
1253 * while the range space is anonymous.
1254 * The resulting map only encodes the mapping to the shift tile and
1255 * not the constraints of "access".
1257 * Let the space of the access relation be
1261 * We first construct an identity relation on a wrapped copy of this space,
1262 * except that it strips off the name of array
1264 * [D -> A] -> [D -> T(A)] (1)
1266 * The bounds in tile->bound[i].lb are of the form
1270 * We collect them into
1274 * and then transform them into
1276 * [D -> T] -> T - B(D) (2)
1278 * Combining those two mappings (1) and (2) yields
1280 * [D -> A] -> T(A) - B(D)
1282 * If there are any strides, then (1) is first transformed into (1')
1284 * [D -> A] -> [D -> T'(A)] (1')
1286 * by a call to pre_shift.
1288 static __isl_give isl_map
*shift_access(__isl_take isl_map
*access
,
1289 struct gpu_array_ref_group
*group
)
1297 struct gpu_array_tile
*tile
;
1298 int n_index
= group
->array
->n_index
;
1300 tile
= group
->private_tile
;
1302 tile
= group
->shared_tile
;
1304 space
= isl_space_domain(isl_map_get_space(access
));
1305 space
= isl_space_map_from_set(space
);
1306 id1
= isl_map_identity(space
);
1307 space
= isl_space_range(isl_map_get_space(access
));
1308 space
= isl_space_map_from_set(space
);
1309 space
= isl_space_set_tuple_name(space
, isl_dim_out
, NULL
);
1310 id2
= isl_map_identity(space
);
1311 sched
= isl_map_product(id1
, id2
);
1313 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(sched
)));
1314 space
= isl_space_from_domain(isl_space_domain(space
));
1315 shift
= isl_map_universe(space
);
1316 for (i
= 0; i
< n_index
; ++i
) {
1317 map
= isl_map_from_aff(isl_aff_copy(tile
->bound
[i
].lb
));
1318 shift
= isl_map_flat_range_product(shift
, map
);
1321 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(sched
)));
1322 map
= isl_map_universe(space
);
1323 id1
= isl_map_range_map(isl_map_copy(map
));
1324 map
= isl_map_domain_map(map
);
1325 shift
= isl_map_neg(shift
);
1326 shift
= isl_map_apply_range(map
, shift
);
1327 shift
= isl_map_sum(id1
, shift
);
1329 for (i
= 0; i
< n_index
; ++i
)
1330 if (tile
->bound
[i
].shift_map
)
1334 sched
= pre_shift(sched
, tile
);
1336 sched
= isl_map_apply_range(sched
, shift
);
1338 isl_map_free(access
);
1343 /* Given a schedule that iterates over all elements in a piece of an array,
1344 * perform tiling/wrapping over the threads.
1346 * In particular, we tile the final iterators so that the final thread
1347 * dimension runs over the final array dimension.
1348 * However, if those final iterators have only a single iteration,
1349 * we try to tile earlier iterators instead.
1351 static __isl_give isl_map
*tile_access_schedule(struct gpu_gen
*gen
,
1352 __isl_take isl_map
*sched
)
1355 isl_union_map
*usched
;
1358 unsigned nvar
= isl_map_dim(sched
, isl_dim_out
);
1362 n_tile
= gen
->kernel
->n_block
;
1363 if (n_tile
> nvar
) {
1365 sched
= isl_map_insert_dims(sched
,
1366 isl_dim_out
, 0, n_tile
- nvar
);
1367 for (i
= 0; i
< n_tile
- nvar
; ++i
)
1368 sched
= isl_map_fix_si(sched
, isl_dim_out
, i
, 0);
1372 first
= nvar
- n_tile
;
1374 for (; first
> 0; first
--)
1375 if (!isl_map_plain_is_fixed(sched
, isl_dim_out
,
1376 first
+ n_tile
- 1, NULL
))
1379 dim
= isl_map_get_space(sched
);
1380 dim
= isl_space_params(dim
);
1381 if (gen
->options
->wrap
)
1382 tiling
= wrap(isl_space_copy(dim
), nvar
, first
,
1383 n_tile
, gen
->kernel
->block_dim
);
1385 tiling
= tile(isl_space_copy(dim
), nvar
, first
,
1386 n_tile
, gen
->kernel
->block_dim
);
1387 sched
= isl_map_apply_range(sched
, tiling
);
1389 par
= parametrization(dim
, nvar
+ n_tile
, first
+ n_tile
, n_tile
, "t");
1390 sched
= isl_map_intersect_range(sched
, par
);
1392 usched
= isl_union_map_from_map(sched
);
1393 usched
= scale_access_tile_loops(gen
, usched
, nvar
+ n_tile
,
1395 sched
= isl_map_from_union_map(usched
);
1400 /* Given an index expression "pa" into a tile of an array, adjust the expression
1401 * to a shift of the tile to the origin
1402 * (based on the lower bounds in "bound".
1403 * If the index is strided, then we first add
1404 * bound->shift and divide by bound->stride.
1405 * In the end, we compute the gist with respect to "domain".
1407 * All of the input expression "pa", the set "domain" and
1408 * the output are expressed in terms of the AST schedule domain.
1409 * The expressions in "bound" are expressed
1410 * in terms of the first shared_len dimensions of the schedule computed by PPCG.
1411 * The mapping "sched2shared" maps the former domain to the latter domain.
1413 static __isl_give isl_pw_aff
*shift_index(__isl_take isl_pw_aff
*pa
,
1414 struct gpu_array_info
*array
,
1415 struct gpu_array_bound
*bound
, __isl_take isl_set
*domain
,
1416 __isl_take isl_map
*sched2shared
)
1420 isl_pw_multi_aff
*pma
;
1423 map
= isl_map_from_aff(isl_aff_copy(bound
->shift
));
1424 map
= isl_map_apply_range(isl_map_copy(sched2shared
), map
);
1425 pma
= isl_pw_multi_aff_from_map(map
);
1426 tmp
= isl_pw_multi_aff_get_pw_aff(pma
, 0);
1427 isl_pw_multi_aff_free(pma
);
1428 pa
= isl_pw_aff_add(pa
, tmp
);
1429 pa
= isl_pw_aff_scale_down_val(pa
, isl_val_copy(bound
->stride
));
1433 map
= isl_map_from_aff(isl_aff_copy(bound
->lb
));
1434 map
= isl_map_apply_range(sched2shared
, map
);
1435 pma
= isl_pw_multi_aff_from_map(map
);
1436 tmp
= isl_pw_multi_aff_get_pw_aff(pma
, 0);
1437 isl_pw_multi_aff_free(pma
);
1438 pa
= isl_pw_aff_sub(pa
, tmp
);
1439 pa
= isl_pw_aff_coalesce(pa
);
1440 pa
= isl_pw_aff_gist(pa
, domain
);
1445 /* Return the union of all read (read = 1) and/or write (write = 1)
1446 * access relations in the group.
1448 static __isl_give isl_union_map
*group_access_relation(
1449 struct gpu_array_ref_group
*group
, int read
, int write
)
1452 isl_union_map
*access
;
1454 access
= isl_union_map_empty(isl_map_get_space(group
->access
));
1455 for (i
= 0; i
< group
->n_ref
; ++i
) {
1458 if (!((read
&& group
->refs
[i
]->read
) ||
1459 (write
&& group
->refs
[i
]->write
)))
1461 map_i
= isl_map_copy(group
->refs
[i
]->access
);
1462 access
= isl_union_map_union(access
,
1463 isl_union_map_from_map(map_i
));
1469 /* Return a map from the first shared_len dimensions of the computed
1470 * schedule to the values of the given index "i"
1471 * of the elements in the array tile in global memory that corresponds
1472 * to the shared memory copy.
1473 * In particular, if a is the index, then the range of the map
1477 * is constrained as follows
1479 * tile_offset(D) <= a <= tile_offset(D) + tile_size - 1 (1)
1483 * 0 <= a <= array_size - 1 (2)
1486 * Note that if some stride has been detected (i.e., when
1487 * group->shared_tile->bound[i].shift is set), then offset and size (i.e.,
1488 * constraints (1)) apply to the shifted and scaled down copy of the tile.
1489 * These constraints therefore have to be mapped back to the original
1490 * array space using the inverse of the shift_map.
1492 static __isl_give isl_map
*group_tile_dim(struct gpu_array_ref_group
*group
,
1497 isl_map
*map
, *tile
, *gt
;
1500 map
= isl_map_from_aff(isl_aff_copy(group
->shared_tile
->bound
[i
].lb
));
1501 space
= isl_space_range(isl_map_get_space(map
));
1502 map
= isl_map_apply_range(map
, isl_map_lex_le(isl_space_copy(space
)));
1505 aff
= isl_aff_copy(group
->shared_tile
->bound
[i
].lb
);
1506 aff
= isl_aff_add_constant_val(aff
,
1507 isl_val_copy(group
->shared_tile
->bound
[i
].size
));
1508 map
= isl_map_from_aff(aff
);
1509 gt
= isl_map_lex_gt(space
);
1510 map
= isl_map_apply_range(map
, isl_map_copy(gt
));
1511 tile
= isl_map_intersect(tile
, map
);
1513 if (group
->shared_tile
->bound
[i
].shift
) {
1514 isl_basic_map
*shift
;
1515 shift
= isl_basic_map_copy(group
->shared_tile
->bound
[i
].shift_map
);
1516 shift
= isl_basic_map_reverse(shift
);
1517 tile
= isl_set_unwrap(isl_set_apply(isl_map_wrap(tile
),
1518 isl_map_from_basic_map(shift
)));
1521 tile
= isl_map_lower_bound_si(tile
, isl_dim_out
, 0, 0);
1523 bound
= isl_set_from_pw_aff(isl_pw_aff_copy(group
->array
->bound
[i
]));
1524 bound
= isl_set_apply(bound
, gt
);
1525 tile
= isl_map_intersect_range(tile
, bound
);
1530 /* Return a map from the first shared_len dimensions of the computed
1531 * schedule to the array tile in
1532 * global memory that corresponds to the shared memory copy.
1534 static __isl_give isl_map
*group_tile(struct gpu_array_ref_group
*group
)
1537 int n_index
= group
->array
->n_index
;
1540 tile
= group_tile_dim(group
, 0);
1541 for (i
= 1; i
< n_index
; ++i
) {
1544 tile_i
= group_tile_dim(group
, i
);
1545 tile
= isl_map_flat_range_product(tile
, tile_i
);
1548 tile
= isl_map_set_tuple_name(tile
, isl_dim_out
, group
->array
->name
);
1553 /* Given a mapping "sched" from the AST schedule to a domain,
1554 * return the corresponding mapping from the AST schedule to
1555 * to the first shared_len dimensions of the schedule computed by PPCG.
1557 static __isl_give isl_map
*compute_sched_to_shared(struct gpu_gen
*gen
,
1558 __isl_take isl_map
*sched
)
1560 isl_union_map
*umap
;
1564 space
= isl_space_range(isl_map_get_space(sched
));
1565 space
= isl_space_from_domain(space
);
1566 space
= isl_space_add_dims(space
, isl_dim_out
, gen
->shared_len
);
1568 umap
= isl_union_map_copy(gen
->shared_sched
);
1569 umap
= isl_union_map_apply_range(umap
,
1570 isl_union_map_copy(gen
->shared_proj
));
1571 map
= isl_union_map_extract_map(umap
, space
);
1572 isl_union_map_free(umap
);
1574 sched
= isl_map_apply_range(sched
, map
);
1575 sched
= isl_map_detect_equalities(sched
);
1580 /* Set unroll[j] if the input dimension j is involved in
1581 * the index expression represented by ma.
1583 static int check_unroll(__isl_take isl_set
*set
, __isl_take isl_multi_aff
*ma
,
1587 int n_in
= isl_multi_aff_dim(ma
, isl_dim_in
);
1588 int n_out
= isl_multi_aff_dim(ma
, isl_dim_out
);
1591 for (i
= 0; i
< n_out
; ++i
) {
1594 aff
= isl_multi_aff_get_aff(ma
, i
);
1595 for (j
= 0; j
< n_in
; ++j
)
1596 if (isl_aff_involves_dims(aff
, isl_dim_in
, j
, 1))
1602 isl_multi_aff_free(ma
);
1606 /* Given an array pos mapping input dimensions to the corresponding
1607 * output dimension, construct the corresponding map.
1609 static __isl_give isl_map
*permutation(__isl_take isl_space
*dim
,
1614 isl_basic_map
*bmap
;
1615 isl_local_space
*ls
;
1617 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
1618 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
);
1619 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
1620 ls
= isl_local_space_from_space(dim
);
1622 for (i
= 0; i
< len
; ++i
) {
1623 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1624 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
,
1626 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, pos
[i
],
1628 bmap
= isl_basic_map_add_constraint(bmap
, c
);
1630 isl_local_space_free(ls
);
1632 return isl_map_from_basic_map(bmap
);
1635 /* Find all loops involved in any of the index expressions for any of
1636 * the private accesses, move them innermost and then mark them as
1637 * requiring unrolling by setting gen->first_unroll.
1638 * The loops involved should all be parallel because of the checks
1639 * we performed in check_private_group_access. Moving them innermost
1640 * is therefore a valid transformation.
1642 * Loops up to gen->shared_len are generated before the mapping to
1643 * threads is applied. They should therefore be ignored.
1645 * We compute the hidden equalities of the schedule first
1646 * since we will need them in our calls to isl_pw_multi_aff_from_map
1647 * and because we want to make sure that the same equalities
1648 * are also available to the code generator.
1650 static __isl_give isl_union_map
*interchange_for_unroll(struct gpu_gen
*gen
,
1651 __isl_take isl_union_map
*sched
)
1654 int unroll
[gen
->thread_tiled_len
];
1655 int perm
[gen
->thread_tiled_len
];
1658 int len
= gen
->shared_len
+ gen
->n_parallel
+ gen
->n_block
;
1660 gen
->first_unroll
= -1;
1662 sched
= isl_union_map_detect_equalities(sched
);
1663 for (i
= 0; i
< gen
->thread_tiled_len
; ++i
)
1665 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
1666 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
1668 for (j
= 0; j
< array
->n_group
; ++j
) {
1669 isl_union_map
*access
;
1671 isl_pw_multi_aff
*pma
;
1673 if (!array
->groups
[j
]->private_tile
)
1676 access
= group_access_relation(array
->groups
[j
], 1, 1);
1677 access
= isl_union_map_apply_domain(access
,
1678 isl_union_map_copy(sched
));
1680 acc
= isl_map_from_union_map(access
);
1681 pma
= isl_pw_multi_aff_from_map(acc
);
1682 isl_pw_multi_aff_foreach_piece(pma
,
1683 &check_unroll
, unroll
);
1685 isl_pw_multi_aff_free(pma
);
1689 for (i
= gen
->shared_len
; i
< len
; ++i
)
1696 for (i
= len
; i
< gen
->thread_tiled_len
; ++i
)
1701 for (i
= 0; i
< gen
->shared_len
; ++i
)
1703 for (i
= gen
->shared_len
; i
< gen
->thread_tiled_len
; ++i
)
1706 gen
->first_unroll
= j
- gen
->shared_len
;
1707 for (i
= gen
->shared_len
; i
< len
; ++i
)
1711 dim
= isl_union_map_get_space(sched
);
1712 permute
= permutation(dim
, perm
, gen
->thread_tiled_len
);
1713 sched
= isl_union_map_apply_range(sched
,
1714 isl_union_map_from_map(permute
));
1719 /* Given a constraint
1721 * a(p,i) + j = g f(e)
1723 * or -a(p,i) - j = g f(e) if sign < 0,
1724 * store a(p,i) in bound->shift and g (stride) in bound->stride.
1725 * a(p,i) is assumed to be an expression in only the parameters
1726 * and the input dimensions.
1728 static void extract_stride(__isl_keep isl_constraint
*c
,
1729 struct gpu_array_bound
*bound
, __isl_keep isl_val
*stride
, int sign
)
1738 isl_val_free(bound
->stride
);
1739 bound
->stride
= isl_val_copy(stride
);
1741 space
= isl_constraint_get_space(c
);
1742 space
= isl_space_domain(space
);
1744 nparam
= isl_space_dim(space
, isl_dim_param
);
1745 nvar
= isl_space_dim(space
, isl_dim_set
);
1747 v
= isl_constraint_get_constant_val(c
);
1750 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
1751 aff
= isl_aff_set_constant_val(aff
, v
);
1753 for (i
= 0; i
< nparam
; ++i
) {
1754 if (!isl_constraint_involves_dims(c
, isl_dim_param
, i
, 1))
1756 v
= isl_constraint_get_coefficient_val(c
, isl_dim_param
, i
);
1759 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_param
, i
, v
);
1762 for (i
= 0; i
< nvar
; ++i
) {
1763 if (!isl_constraint_involves_dims(c
, isl_dim_in
, i
, 1))
1765 v
= isl_constraint_get_coefficient_val(c
, isl_dim_in
, i
);
1768 aff
= isl_aff_add_coefficient_val(aff
, isl_dim_in
, i
, v
);
1774 /* Given an equality constraint of a map with a single output dimension j,
1775 * check if the constraint is of the form
1777 * a(p,i) + j = g f(e)
1779 * with a(p,i) an expression in the parameters and input dimensions
1780 * and f(e) an expression in the existentially quantified variables.
1781 * If so, and if g is larger than any such g from a previously considered
1782 * constraint, then call extract_stride to record the stride information
1785 static int check_stride_constraint(__isl_take isl_constraint
*c
, void *user
)
1791 struct gpu_array_bound
*bound
= user
;
1793 ctx
= isl_constraint_get_ctx(c
);
1794 n_div
= isl_constraint_dim(c
, isl_dim_div
);
1795 v
= isl_constraint_get_coefficient_val(c
, isl_dim_out
, 0);
1797 if (n_div
&& (isl_val_is_one(v
) || isl_val_is_negone(v
))) {
1798 int s
= isl_val_sgn(v
);
1799 isl_val
*stride
= isl_val_zero(ctx
);
1802 for (i
= 0; i
< n_div
; ++i
) {
1803 v
= isl_constraint_get_coefficient_val(c
,
1805 stride
= isl_val_gcd(stride
, v
);
1807 if (!isl_val_is_zero(stride
) &&
1808 isl_val_gt(stride
, bound
->stride
))
1809 extract_stride(c
, bound
, stride
, s
);
1811 isl_val_free(stride
);
1815 isl_constraint_free(c
);
1819 /* Given contraints on an array index i, check if we can find
1820 * a shift a(p) and a stride g such that
1822 * a(p) + i = 0 mod g
1824 * If so, record the information in bound and apply the mapping
1825 * i -> (i + a(p))/g to the array index in bounds and return
1826 * the new constraints.
1827 * If not, simply return the original constraints.
1829 * If bounds is a subset of the space
1833 * then the bound recorded in bound->shift is of the form
1837 * with s(D) equal to a(p) above.
1838 * The mapping recorded in bound->shift_map is of the form
1840 * [D -> i] -> [D -> (i + S(D))/g]
1842 * This mapping is computed as follows.
1843 * We first introduce "i" in the domain through precomposition
1844 * with [D -> i] -> D obtaining
1848 * Adding [D -> i] -> i produces
1850 * [D -> i] -> i + s(D)
1852 * and the domain product with [D -> i] -> D yields
1854 * [D -> i] -> [D -> i + s(D)]
1856 * Composition with [D -> i] -> [D -> i/g] gives the desired result.
1858 static __isl_give isl_basic_map
*check_stride(struct gpu_array_bound
*bound
,
1859 __isl_take isl_basic_map
*bounds
)
1862 isl_basic_map
*hull
;
1863 isl_basic_map
*shift
, *id
, *bmap
, *scale
;
1864 isl_basic_set
*bset
;
1867 bound
->stride
= NULL
;
1869 hull
= isl_basic_map_affine_hull(isl_basic_map_copy(bounds
));
1871 isl_basic_map_foreach_constraint(hull
, &check_stride_constraint
, bound
);
1873 isl_basic_map_free(hull
);
1878 shift
= isl_basic_map_from_aff(isl_aff_copy(bound
->shift
));
1879 space
= isl_basic_map_get_space(bounds
);
1880 bmap
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
1881 shift
= isl_basic_map_apply_range(bmap
, shift
);
1882 space
= isl_basic_map_get_space(bounds
);
1883 id
= isl_basic_map_range_map(isl_basic_map_universe(space
));
1884 shift
= isl_basic_map_sum(id
, shift
);
1885 space
= isl_basic_map_get_space(bounds
);
1886 id
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
1887 shift
= isl_basic_map_range_product(id
, shift
);
1889 space
= isl_space_domain(isl_basic_map_get_space(bounds
));
1890 id
= isl_basic_map_identity(isl_space_map_from_set(space
));
1891 space
= isl_space_range(isl_basic_map_get_space(bounds
));
1892 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
1893 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, 0, 1);
1894 aff
= isl_aff_scale_down_val(aff
, isl_val_copy(bound
->stride
));
1895 scale
= isl_basic_map_from_aff(aff
);
1896 scale
= isl_basic_map_product(id
, scale
);
1898 bound
->shift_map
= isl_basic_map_apply_range(shift
, scale
);
1899 bmap
= isl_basic_map_copy(bound
->shift_map
);
1900 bset
= isl_basic_set_apply(isl_basic_map_wrap(bounds
), bmap
);
1901 bounds
= isl_basic_set_unwrap(bset
);
1906 /* Data used in compute_array_dim_size and compute_size_in_direction.
1908 * pos is the position of the variable representing the array index,
1909 * i.e., the variable for which want to compute the size. This variable
1910 * is also the last variable in the set.
1912 struct gpu_size_info
{
1913 isl_basic_set
*bset
;
1914 struct gpu_array_bound
*bound
;
1918 /* Given a constraint from the basic set describing the bounds on
1919 * an array index, check if it is a lower bound, say m i >= b(x), and,
1920 * if so, check whether the expression "i - ceil(b(x)/m) + 1" has a constant
1921 * upper bound. If so, and if this bound is smaller than any bound
1922 * derived from earlier constraints, set the size to this bound on
1923 * the expression and the lower bound to ceil(b(x)/m).
1925 static int compute_size_in_direction(__isl_take isl_constraint
*c
, void *user
)
1927 struct gpu_size_info
*size
= user
;
1934 nparam
= isl_basic_set_dim(size
->bset
, isl_dim_param
);
1935 n_div
= isl_constraint_dim(c
, isl_dim_div
);
1937 if (isl_constraint_involves_dims(c
, isl_dim_div
, 0, n_div
) ||
1938 !isl_constraint_is_lower_bound(c
, isl_dim_set
, size
->pos
)) {
1939 isl_constraint_free(c
);
1943 aff
= isl_constraint_get_bound(c
, isl_dim_set
, size
->pos
);
1944 aff
= isl_aff_ceil(aff
);
1946 lb
= isl_aff_copy(aff
);
1948 aff
= isl_aff_neg(aff
);
1949 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, size
->pos
, 1);
1951 v
= isl_basic_set_max_val(size
->bset
, aff
);
1954 if (isl_val_is_int(v
)) {
1955 v
= isl_val_add_ui(v
, 1);
1956 if (!size
->bound
->size
|| isl_val_lt(v
, size
->bound
->size
)) {
1957 isl_val_free(size
->bound
->size
);
1958 size
->bound
->size
= isl_val_copy(v
);
1959 lb
= isl_aff_drop_dims(lb
, isl_dim_in
, size
->pos
, 1);
1960 isl_aff_free(size
->bound
->lb
);
1961 size
->bound
->lb
= isl_aff_copy(lb
);
1967 isl_constraint_free(c
);
1972 /* Given a basic map "bounds" that maps parameters and input dimensions
1973 * to a single output dimension, look for an expression in the parameters
1974 * and input dimensions such that the range of the output dimension shifted
1975 * by this expression is a constant.
1977 * In particular, we currently only consider lower bounds on the output
1978 * dimension as candidate expressions.
1980 static int compute_array_dim_size(struct gpu_array_bound
*bound
,
1981 __isl_take isl_basic_map
*bounds
)
1983 struct gpu_size_info size
;
1985 bounds
= isl_basic_map_detect_equalities(bounds
);
1986 bounds
= check_stride(bound
, bounds
);
1992 size
.pos
= isl_basic_map_dim(bounds
, isl_dim_in
);
1993 size
.bset
= isl_basic_map_wrap(bounds
);
1994 size
.bset
= isl_basic_set_flatten(size
.bset
);
1995 size
.bset
= isl_set_simple_hull(isl_basic_set_compute_divs(size
.bset
));
1996 isl_basic_set_foreach_constraint(size
.bset
, &compute_size_in_direction
,
1998 isl_basic_set_free(size
.bset
);
2000 return bound
->size
? 0 : -1;
2003 /* Check if we can find a memory tile for the given array
2004 * based on the given accesses, and if so, put the results in "tile".
2006 * We project the accesses on each index in turn and look for a parametric
2007 * offset such that the size is constant.
2009 static int can_tile(__isl_keep isl_map
*access
, struct gpu_array_tile
*tile
)
2013 for (i
= 0; i
< tile
->n
; ++i
) {
2015 isl_basic_map
*hull
;
2017 access_i
= isl_map_copy(access
);
2018 access_i
= isl_map_project_out(access_i
, isl_dim_out
, 0, i
);
2019 access_i
= isl_map_project_out(access_i
, isl_dim_out
,
2020 1, tile
->n
- (i
+ 1));
2021 access_i
= isl_map_compute_divs(access_i
);
2022 hull
= isl_map_simple_hull(access_i
);
2023 if (compute_array_dim_size(&tile
->bound
[i
], hull
) < 0)
2030 /* Construct a map with input the shared tile loops and the loops that
2031 * will be wrapped around the threads that relates these later loops
2032 * to the thread indices and then projects them out.
2034 static __isl_give isl_map
*compute_privatization(struct gpu_gen
*gen
)
2042 dim
= isl_union_map_get_space(gen
->shared_sched
);
2044 if (gen
->options
->wrap
)
2045 tiling
= wrap(isl_space_copy(dim
), gen
->shared_len
+ gen
->n_block
,
2046 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
2048 tiling
= tile(isl_space_copy(dim
), gen
->shared_len
+ gen
->n_block
,
2049 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
2053 par
= parametrization(dim
, gen
->shared_len
+ 2 * gen
->n_block
,
2054 gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
+ gen
->n_block
,
2057 priv
= isl_map_align_params(priv
, isl_set_get_space(par
));
2058 priv
= isl_map_intersect_range(priv
, par
);
2060 dim
= isl_map_get_space(priv
);
2061 dim
= isl_space_drop_dims(dim
, isl_dim_in
, 0, isl_space_dim(dim
, isl_dim_in
));
2062 dim
= isl_space_drop_dims(dim
, isl_dim_out
, 0, isl_space_dim(dim
, isl_dim_out
));
2063 proj
= projection(dim
, gen
->shared_len
+ 2 * gen
->n_block
,
2066 priv
= isl_map_apply_range(priv
, proj
);
2071 /* Construct a map from domain_dim to domain_dim that increments
2072 * the dimension at position "pos" and leaves all other dimensions
2075 static __isl_give isl_map
*next(__isl_take isl_space
*domain_dim
, int pos
)
2078 int len
= isl_space_dim(domain_dim
, isl_dim_set
);
2080 isl_basic_map
*next
;
2081 isl_local_space
*ls
;
2083 dim
= isl_space_map_from_set(domain_dim
);
2084 next
= isl_basic_map_universe(isl_space_copy(dim
));
2085 ls
= isl_local_space_from_space(dim
);
2087 for (i
= 0; i
< len
; ++i
) {
2090 c
= isl_equality_alloc(isl_local_space_copy(ls
));
2091 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, 1);
2092 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
2094 c
= isl_constraint_set_constant_si(c
, 1);
2095 next
= isl_basic_map_add_constraint(next
, c
);
2098 isl_local_space_free(ls
);
2100 return isl_map_from_basic_map(next
);
2103 /* Check if the given access is coalesced.
2104 * That is, check whether incrementing the dimension that will get
2105 * wrapped over the last thread index results in incrementing
2106 * the last array index.
2108 * This function is only called for access relations without reuse.
2110 static int access_is_coalesced(struct gpu_gen
*gen
,
2111 __isl_keep isl_union_map
*access
)
2114 isl_map
*access_map
;
2115 isl_map
*next_thread_x
;
2116 isl_map
*next_element
;
2120 access
= isl_union_map_copy(access
);
2121 access
= isl_union_map_apply_domain(access
,
2122 isl_union_map_copy(gen
->tiled_sched
));
2123 access_map
= isl_map_from_union_map(access
);
2125 dim
= isl_map_get_space(access_map
);
2126 dim
= isl_space_domain(dim
);
2127 next_thread_x
= next(dim
, gen
->shared_len
+ gen
->n_block
- 1);
2129 dim
= isl_map_get_space(access_map
);
2130 dim
= isl_space_range(dim
);
2131 next_element
= next(dim
, isl_space_dim(dim
, isl_dim_set
) - 1);
2133 map
= isl_map_apply_domain(next_thread_x
, isl_map_copy(access_map
));
2134 map
= isl_map_apply_range(map
, access_map
);
2136 coalesced
= isl_map_is_subset(map
, next_element
);
2138 isl_map_free(next_element
);
2144 /* Given an access relation in terms of the first gen->shared_len + gen->n_block
2145 * dimensions of the computed schedule, check if it is bijective for
2146 * fixed values of the first gen->shared_len dimensions.
2147 * We perform this check by equating these dimensions to parameters.
2149 static int access_is_bijective(struct gpu_gen
*gen
, __isl_keep isl_map
*access
)
2155 access
= isl_map_copy(access
);
2156 space
= isl_space_params(isl_map_get_space(access
));
2157 par
= parametrization(space
, gen
->shared_len
+ gen
->n_block
,
2158 0, gen
->shared_len
, "s");
2159 access
= isl_map_intersect_domain(access
, par
);
2160 res
= isl_map_is_bijective(access
);
2161 isl_map_free(access
);
2166 /* Look for the last shared tile loop that affects the offset of "tile"
2167 * and return the result.
2168 * If there is no such loop, then return the index of the loop
2169 * before the first shared tile loop, in particular gen->tile_first - 1.
2171 static int compute_tile_last_shared(struct gpu_gen
*gen
,
2172 struct gpu_array_tile
*tile
)
2176 for (j
= gen
->shared_len
- 1; j
>= gen
->tile_first
; --j
) {
2177 for (i
= 0; i
< tile
->n
; ++i
) {
2181 lb
= tile
->bound
[i
].lb
;
2182 if (isl_aff_involves_dims(lb
, isl_dim_in
, j
, 1))
2185 shift
= tile
->bound
[i
].shift
;
2188 if (isl_aff_involves_dims(shift
, isl_dim_in
, j
, 1))
2198 /* Look for the last shared tile loop that affects the offset of the
2199 * shared or private tile and store the result in group->last_shared.
2200 * If there is no such loop, then group->last_shared is set to a value
2201 * before the first shared tile loop, in particular gen->tile_first - 1.
2202 * If there is no tile defined on the array reference group,
2203 * then set group->last_shared to gen->shared_len - 1.
2205 static void set_last_shared(struct gpu_gen
*gen
,
2206 struct gpu_array_ref_group
*group
)
2208 struct gpu_array_tile
*tile
;
2210 group
->last_shared
= gen
->shared_len
- 1;
2212 tile
= group
->private_tile
;
2214 tile
= group
->shared_tile
;
2218 group
->last_shared
= compute_tile_last_shared(gen
, tile
);
2221 /* Compute a privatized copy of all access relations from reference groups that
2222 * are mapped to private memory and store the result in gen->privatization.
2224 static void compute_private_access(struct gpu_gen
*gen
)
2227 isl_union_map
*private;
2229 if (!gen
->options
->use_private_memory
)
2232 private = isl_union_map_empty(isl_union_map_get_space(gen
->shared_sched
));
2234 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2235 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2237 if (gpu_array_is_read_only_scalar(array
))
2240 for (j
= 0; j
< array
->n_group
; ++j
) {
2241 if (!array
->groups
[j
]->private_tile
)
2244 private = isl_union_map_union(private,
2245 group_access_relation(array
->groups
[j
], 1, 1));
2249 if (isl_union_map_is_empty(private))
2250 isl_union_map_free(private);
2252 isl_union_map
*priv
;
2254 private = isl_union_map_apply_domain(private,
2255 isl_union_map_copy(gen
->shared_sched
));
2256 priv
= isl_union_map_from_map(isl_map_copy(gen
->privatization
));
2257 private = isl_union_map_apply_domain(private, priv
);
2258 gen
->private_access
= private;
2262 /* Compute the size of the tile specified by "tile"
2263 * in number of elements and return the result.
2265 static __isl_give isl_val
*tile_size(isl_ctx
*ctx
, struct gpu_array_tile
*tile
)
2270 size
= isl_val_one(ctx
);
2272 for (i
= 0; i
< tile
->n
; ++i
)
2273 size
= isl_val_mul(size
, isl_val_copy(tile
->bound
[i
].size
));
2278 /* If max_shared_memory is not set to infinity (-1), then make
2279 * sure that the total amount of shared memory required by the
2280 * array reference groups mapped to shared memory is no larger
2281 * than this maximum.
2283 * We apply a greedy approach and discard (keep in global memory)
2284 * those groups that would result in a total memory size that
2285 * is larger than the maximum.
2287 static void check_shared_memory_bound(struct gpu_gen
*gen
)
2290 isl_val
*left
, *size
;
2292 if (gen
->options
->max_shared_memory
< 0)
2295 left
= isl_val_int_from_si(gen
->ctx
, gen
->options
->max_shared_memory
);
2297 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2298 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2300 for (j
= 0; j
< array
->n_group
; ++j
) {
2301 struct gpu_array_ref_group
*group
;
2303 group
= array
->groups
[j
];
2304 if (!group
->shared_tile
)
2307 size
= tile_size(gen
->ctx
, group
->shared_tile
);
2308 size
= isl_val_mul_ui(size
, array
->size
);
2310 if (isl_val_le(size
, left
)) {
2311 left
= isl_val_sub(left
, size
);
2316 group
->shared_tile
= free_tile(group
->shared_tile
);
2323 /* Fill up the groups array with singleton groups, i.e., one group
2324 * per reference, initializing the array, access, write, n_ref and refs fields.
2325 * In particular the access field is initialized to the scheduled
2326 * access relation of the array reference.
2328 * Return the number of elements initialized, i.e., the number of
2329 * active references in the current kernel.
2331 static int populate_array_references(struct gpu_array_info
*array
,
2332 __isl_keep isl_union_map
*sched
, struct gpu_array_ref_group
**groups
)
2336 isl_ctx
*ctx
= isl_union_map_get_ctx(sched
);
2339 for (i
= 0; i
< array
->n_ref
; ++i
) {
2340 isl_union_map
*umap
;
2342 struct gpu_array_ref_group
*group
;
2343 struct gpu_stmt_access
*access
= array
->refs
[i
];
2345 map
= isl_map_copy(access
->access
);
2346 umap
= isl_union_map_from_map(map
);
2347 umap
= isl_union_map_apply_domain(umap
,
2348 isl_union_map_copy(sched
));
2350 if (isl_union_map_is_empty(umap
)) {
2351 isl_union_map_free(umap
);
2355 map
= isl_map_from_union_map(umap
);
2356 map
= isl_map_detect_equalities(map
);
2358 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
2360 group
->array
= array
;
2361 group
->access
= map
;
2362 group
->write
= access
->write
;
2363 group
->refs
= &array
->refs
[i
];
2366 groups
[n
++] = group
;
2372 /* If group->n_ref == 1, then group->refs was set by
2373 * populate_array_references to point directly into
2374 * group->array->refs and should not be freed.
2375 * If group->n_ref > 1, then group->refs was set by join_groups
2376 * to point to a newly allocated array.
2378 static void free_array_ref_group(struct gpu_array_ref_group
*group
)
2382 free_tile(group
->shared_tile
);
2383 free_tile(group
->private_tile
);
2384 isl_map_free(group
->access
);
2385 if (group
->n_ref
> 1)
2390 /* Given a map where the input dimensions represent the tile loops,
2391 * eliminate the innermost of those that have a fixed value
2392 * until we reach one that does not (obviously) have a fixed value.
2394 static __isl_give isl_map
*eliminate_fixed_inner_loops(
2395 __isl_take isl_map
*access
)
2399 n
= isl_map_dim(access
, isl_dim_in
);
2401 for (i
= n
- 1; i
>= 0; --i
) {
2402 if (!isl_map_plain_is_fixed(access
, isl_dim_in
, i
, NULL
))
2404 access
= isl_map_eliminate(access
, isl_dim_in
, i
, 1);
2409 /* Check if the access relations of group1 and group2 overlap within
2410 * the innermost loop. In particular, ignore any inner dimension
2411 * with a fixed value.
2412 * The copying to and from shared memory will be performed within
2413 * the innermost actual loop so we are only allowed to consider
2414 * the dimensions up to that innermost loop while checking whether
2415 * two access relations overlap.
2417 static int accesses_overlap(struct gpu_array_ref_group
*group1
,
2418 struct gpu_array_ref_group
*group2
)
2421 isl_map
*access1
, *access2
;
2423 access1
= isl_map_copy(group1
->access
);
2424 access1
= eliminate_fixed_inner_loops(access1
);
2425 access2
= isl_map_copy(group2
->access
);
2426 access2
= eliminate_fixed_inner_loops(access2
);
2427 access1
= isl_map_intersect(access1
, access2
);
2428 empty
= isl_map_is_empty(access1
);
2429 isl_map_free(access1
);
2434 /* Combine the given two groups into a single group, containing
2435 * the references of both groups.
2437 static struct gpu_array_ref_group
*join_groups(
2438 struct gpu_array_ref_group
*group1
,
2439 struct gpu_array_ref_group
*group2
)
2443 struct gpu_array_ref_group
*group
;
2445 ctx
= isl_map_get_ctx(group1
->access
);
2446 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
2448 group
->array
= group1
->array
;
2449 group
->access
= isl_map_union(isl_map_copy(group1
->access
),
2450 isl_map_copy(group2
->access
));
2451 group
->write
= group1
->write
|| group2
->write
;
2452 group
->n_ref
= group1
->n_ref
+ group2
->n_ref
;
2453 group
->refs
= isl_alloc_array(ctx
, struct gpu_stmt_access
*,
2455 assert(group
->refs
);
2456 for (i
= 0; i
< group1
->n_ref
; ++i
)
2457 group
->refs
[i
] = group1
->refs
[i
];
2458 for (i
= 0; i
< group2
->n_ref
; ++i
)
2459 group
->refs
[group1
->n_ref
+ i
] = group2
->refs
[i
];
2464 /* Combine the given two groups into a single group and free
2465 * the original two groups.
2467 static struct gpu_array_ref_group
*join_groups_and_free(
2468 struct gpu_array_ref_group
*group1
,
2469 struct gpu_array_ref_group
*group2
)
2471 struct gpu_array_ref_group
*group
;
2473 group
= join_groups(group1
, group2
);
2474 free_array_ref_group(group1
);
2475 free_array_ref_group(group2
);
2479 /* Compute the private and/or shared memory tiles for the array
2480 * reference group "group" of array "array".
2482 * If the array is a read-only scalar or if the user requested
2483 * not to use shared or private memory, then we do not need to do anything.
2485 * We only try to compute a shared memory tile if there is any reuse
2486 * or if the access is not coalesced.
2488 * For computing a private memory tile, we also require that there is
2489 * some reuse. Moreover, we require that the access is private
2490 * to the thread. That is, we check that any given array element
2491 * is only accessed by a single thread.
2492 * We compute an access relation that maps the shared tile loop iterators
2493 * and the shared point loop iterators that will be wrapped over the
2494 * threads to the array elements.
2495 * We actually check that those iterators that will be wrapped
2496 * partition the array space. This check is stricter than necessary
2497 * since several iterations may be mapped onto the same thread
2498 * and then they could be allowed to access the same memory elements,
2499 * but our check does not allow this situation.
2501 * We also check that the index expression only depends on parallel
2502 * loops. That way, we can move those loops innermost and unroll them.
2503 * Again, we use a test that is stricter than necessary.
2504 * We actually check whether the index expression only depends
2505 * on the iterators that are wrapped over the threads.
2506 * These are necessarily parallel, but there may be more parallel loops.
2508 * Combining the injectivity of the first test with the single-valuedness
2509 * of the second test, we simply test for bijectivity.
2511 * If it turns out we can use registers, we compute the private memory
2512 * tile size using can_tile, after introducing a dependence
2513 * on the thread indices.
2515 static void compute_group_bounds_core(struct gpu_gen
*gen
,
2516 struct gpu_array_ref_group
*group
)
2518 isl_ctx
*ctx
= isl_space_get_ctx(group
->array
->dim
);
2519 isl_union_map
*access
;
2520 int n_index
= group
->array
->n_index
;
2523 int use_shared
= gen
->options
->use_shared_memory
;
2524 int use_private
= gen
->options
->use_private_memory
;
2526 if (!use_shared
&& !use_private
)
2528 if (gpu_array_is_read_only_scalar(group
->array
))
2531 access
= group_access_relation(group
, 1, 1);
2532 no_reuse
= isl_union_map_is_injective(access
);
2534 if (use_shared
&& (!no_reuse
|| !access_is_coalesced(gen
, access
))) {
2535 group
->shared_tile
= create_tile(ctx
, group
->array
->n_index
);
2536 if (!can_tile(group
->access
, group
->shared_tile
))
2537 group
->shared_tile
= free_tile(group
->shared_tile
);
2540 if (!use_private
|| no_reuse
) {
2541 isl_union_map_free(access
);
2545 access
= isl_union_map_apply_domain(access
,
2546 isl_union_map_copy(gen
->shared_sched
));
2548 acc
= isl_map_from_union_map(access
);
2550 if (!access_is_bijective(gen
, acc
)) {
2555 group
->private_tile
= create_tile(gen
->ctx
, n_index
);
2556 acc
= isl_map_apply_domain(acc
, isl_map_copy(gen
->privatization
));
2557 if (!can_tile(acc
, group
->private_tile
))
2558 group
->private_tile
= free_tile(group
->private_tile
);
2563 /* Compute the private and/or shared memory tiles for the array
2564 * reference group "group" of array "array" and set last_shared.
2566 static void compute_group_bounds(struct gpu_gen
*gen
,
2567 struct gpu_array_ref_group
*group
)
2569 compute_group_bounds_core(gen
, group
);
2570 set_last_shared(gen
, group
);
2573 /* If two groups have overlapping access relations (as determined by
2574 * the "overlap" function) and if one of them involves a write,
2575 * then merge the two groups into one.
2576 * If "compute_bounds" is set, then call compute_group_bounds
2577 * on the merged groups.
2579 * Return the updated number of groups.
2581 static int group_writes(struct gpu_gen
*gen
,
2582 int n
, struct gpu_array_ref_group
**groups
,
2583 int (*overlap
)(struct gpu_array_ref_group
*group1
,
2584 struct gpu_array_ref_group
*group2
), int compute_bounds
)
2588 for (i
= 0; i
< n
; ++i
) {
2589 for (j
= n
- 1; j
> i
; --j
) {
2590 if (!groups
[i
]->write
&& !groups
[j
]->write
)
2593 if (!overlap(groups
[i
], groups
[j
]))
2596 groups
[i
] = join_groups_and_free(groups
[i
], groups
[j
]);
2598 compute_group_bounds(gen
, groups
[i
]);
2600 groups
[j
] = groups
[n
- 1];
2608 /* If two groups have overlapping access relations (within the innermost
2609 * loop) and if one of them involves a write, then merge the two groups
2612 * Return the updated number of groups.
2614 static int group_overlapping_writes(struct gpu_gen
*gen
,
2615 int n
, struct gpu_array_ref_group
**groups
)
2617 return group_writes(gen
, n
, groups
, &accesses_overlap
, 0);
2620 /* Check if the access relations of group1 and group2 overlap within
2621 * the outermost min(group1->last_shared, group2->last_shared) loops.
2623 static int last_shared_accesses_overlap(struct gpu_array_ref_group
*group1
,
2624 struct gpu_array_ref_group
*group2
)
2629 isl_map
*map_i
, *map_j
, *map
;
2631 last_shared
= group1
->last_shared
;
2632 if (group2
->last_shared
< last_shared
)
2633 last_shared
= group2
->last_shared
;
2634 map_i
= isl_map_copy(group1
->access
);
2635 dim
= isl_map_dim(map_i
, isl_dim_in
);
2636 map_i
= isl_map_eliminate(map_i
, isl_dim_in
,
2637 last_shared
+ 1, dim
- (last_shared
+ 1));
2638 map_j
= isl_map_copy(group2
->access
);
2639 map_j
= isl_map_eliminate(map_j
, isl_dim_in
,
2640 last_shared
+ 1, dim
- (last_shared
+ 1));
2641 map
= isl_map_intersect(map_i
, map_j
);
2642 empty
= isl_map_is_empty(map
);
2648 /* If two groups have overlapping access relations (within the outer
2649 * last_shared loops) and if one of them involves a write,
2650 * then merge the two groups into one.
2652 * Return the updated number of groups.
2654 static int group_last_shared_overlapping_writes(struct gpu_gen
*gen
, int n
,
2655 struct gpu_array_ref_group
**groups
)
2657 return group_writes(gen
, n
, groups
, &last_shared_accesses_overlap
, 1);
2660 /* Is the size of the tile specified by "tile" smaller than the sum of
2661 * the sizes of the tiles specified by "tile1" and "tile2"?
2663 static int smaller_tile(isl_ctx
*ctx
, struct gpu_array_tile
*tile
,
2664 struct gpu_array_tile
*tile1
, struct gpu_array_tile
*tile2
)
2667 isl_val
*size
, *size1
, *size2
;
2669 size
= tile_size(ctx
, tile
);
2670 size1
= tile_size(ctx
, tile1
);
2671 size2
= tile_size(ctx
, tile2
);
2673 size
= isl_val_sub(size
, size1
);
2674 size
= isl_val_sub(size
, size2
);
2675 smaller
= isl_val_is_neg(size
);
2682 /* Given an initial grouping of array references and shared memory tiles
2683 * for each group that allows for a shared memory tile, merge two groups
2684 * if both have a shared memory tile, the merged group also has
2685 * a shared memory tile and the size of the tile for the merge group
2686 * is smaller than the sum of the tile sizes of the individual groups.
2688 * If merging two groups decreases the "last_shared" dimension of
2689 * one or both of the two groups, then we need to check for overlapping
2692 * Return the number of groups after merging.
2694 static int group_common_shared_memory_tile(struct gpu_gen
*gen
,
2695 struct gpu_array_info
*array
, int n
,
2696 struct gpu_array_ref_group
**groups
)
2699 int recompute_overlap
= 0;
2700 isl_ctx
*ctx
= isl_space_get_ctx(array
->dim
);
2702 for (i
= 0; i
< n
; ++i
) {
2703 if (!groups
[i
]->shared_tile
)
2705 for (j
= n
- 1; j
> i
; --j
) {
2708 struct gpu_array_ref_group
*group
;
2710 if (!groups
[j
]->shared_tile
)
2713 map
= isl_map_intersect(isl_map_copy(groups
[i
]->access
),
2714 isl_map_copy(groups
[j
]->access
));
2715 empty
= isl_map_is_empty(map
);
2721 group
= join_groups(groups
[i
], groups
[j
]);
2722 compute_group_bounds(gen
, group
);
2723 if (!group
->shared_tile
||
2724 !smaller_tile(ctx
, group
->shared_tile
,
2725 groups
[i
]->shared_tile
,
2726 groups
[j
]->shared_tile
)) {
2727 free_array_ref_group(group
);
2731 if (group
->last_shared
< groups
[i
]->last_shared
||
2732 group
->last_shared
< groups
[j
]->last_shared
)
2733 recompute_overlap
= 1;
2734 free_array_ref_group(groups
[i
]);
2735 free_array_ref_group(groups
[j
]);
2738 groups
[j
] = groups
[n
- 1];
2743 if (recompute_overlap
)
2744 n
= group_last_shared_overlapping_writes(gen
, n
, groups
);
2748 /* Set array->n_group and array->groups to n and groups.
2750 * Additionally, set the "nr" field of each group
2751 * and the "group" field of each reference in each group.
2753 static void set_array_groups(struct gpu_array_info
*array
,
2754 int n
, struct gpu_array_ref_group
**groups
)
2759 array
->groups
= groups
;
2761 for (i
= 0; i
< n
; ++i
) {
2764 for (j
= 0; j
< groups
[i
]->n_ref
; ++j
)
2765 groups
[i
]->refs
[j
]->group
= i
;
2769 /* Group array references that should be considered together when
2770 * deciding whether to access them from private, shared or global memory.
2772 * In particular, if two array references overlap and if one of them
2773 * is a write, then the two references are grouped together.
2774 * We first perform an initial grouping based only on the access relation.
2775 * After computing shared and private memory tiles, we check for
2776 * overlapping writes again, but this time taking into account
2777 * the "last_shared" property.
2779 * Furthermore, if two groups admit a shared memory tile and if the
2780 * combination of the two also admits a shared memory tile, we merge
2783 static void group_array_references(struct gpu_gen
*gen
,
2784 struct gpu_array_info
*array
, __isl_keep isl_union_map
*sched
)
2788 isl_ctx
*ctx
= isl_union_map_get_ctx(sched
);
2789 struct gpu_array_ref_group
**groups
;
2791 groups
= isl_calloc_array(ctx
, struct gpu_array_ref_group
*,
2795 n
= populate_array_references(array
, sched
, groups
);
2797 n
= group_overlapping_writes(gen
, n
, groups
);
2799 for (i
= 0; i
< n
; ++i
)
2800 compute_group_bounds(gen
, groups
[i
]);
2802 n
= group_last_shared_overlapping_writes(gen
, n
, groups
);
2804 n
= group_common_shared_memory_tile(gen
, array
, n
, groups
);
2806 set_array_groups(array
, n
, groups
);
2809 /* Take tiled_sched, project it onto the shared tile loops and
2810 * the loops that will be wrapped over the threads and
2811 * store the result in gen->shared_sched.
2812 * Also compute a projection that projects out the loops that will be
2813 * wrapped over the threads and store this projection in gen->shared_proj.
2815 static void compute_shared_sched(struct gpu_gen
*gen
)
2820 isl_union_map
*sched
;
2822 sched
= isl_union_map_copy(gen
->tiled_sched
);
2824 dim
= isl_union_map_get_space(sched
);
2825 proj
= projection(dim
, gen
->tiled_len
, gen
->shared_len
+ gen
->n_block
);
2826 sched
= isl_union_map_apply_range(sched
, isl_union_map_from_map(proj
));
2828 dim
= isl_union_map_get_space(sched
);
2829 proj
= projection(dim
, gen
->shared_len
+ gen
->n_block
, gen
->shared_len
);
2831 gen
->shared_sched
= sched
;
2832 gen
->shared_proj
= isl_union_map_from_map(proj
);
2835 /* Group references of all arrays in the program.
2837 static void group_references(struct gpu_gen
*gen
)
2840 isl_union_map
*sched
;
2842 sched
= isl_union_map_apply_range(isl_union_map_copy(gen
->shared_sched
),
2843 isl_union_map_copy(gen
->shared_proj
));
2845 for (i
= 0; i
< gen
->prog
->n_array
; ++i
)
2846 group_array_references(gen
, &gen
->prog
->array
[i
], sched
);
2848 isl_union_map_free(sched
);
2851 /* Free all array information that is local to the current kernel.
2853 static void free_local_array_info(struct gpu_gen
*gen
)
2857 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2858 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2860 for (j
= 0; j
< array
->n_group
; ++j
)
2861 free_array_ref_group(array
->groups
[j
]);
2862 free(array
->groups
);
2866 /* Compute the size of a bounding box around the origin and "set",
2867 * where "set" is assumed to contain only non-negative elements.
2868 * In particular, compute the maximal value of "set" in each direction
2871 static __isl_give isl_multi_pw_aff
*extract_size(__isl_take isl_set
*set
,
2872 __isl_keep isl_set
*context
)
2875 isl_multi_pw_aff
*mpa
;
2877 n
= isl_set_dim(set
, isl_dim_set
);
2878 mpa
= isl_multi_pw_aff_zero(isl_set_get_space(set
));
2879 for (i
= 0; i
< n
; ++i
) {
2884 bound
= isl_set_dim_max(isl_set_copy(set
), i
);
2885 bound
= isl_pw_aff_coalesce(bound
);
2886 bound
= isl_pw_aff_gist(bound
, isl_set_copy(context
));
2888 space
= isl_pw_aff_get_domain_space(bound
);
2889 one
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
2890 one
= isl_aff_add_constant_si(one
, 1);
2891 bound
= isl_pw_aff_add(bound
, isl_pw_aff_from_aff(one
));
2892 mpa
= isl_multi_pw_aff_set_pw_aff(mpa
, i
, bound
);
2899 /* Compute the effective grid size as a list of the sizes in each dimension.
2901 * The grid size specified by the user or set by default
2902 * in read_grid_sizes() and applied in tile_schedule(),
2903 * may be too large for the given code in the sense that
2904 * it may contain blocks that don't need to execute anything.
2905 * We therefore don't return this grid size, but instead the
2906 * smallest grid size that ensures that all blocks that actually
2907 * execute code are included in the grid.
2909 * We first extract a description of the grid, i.e., the possible values
2910 * of the block ids, from gen->tiled_sched.
2911 * The block ids are parameters in gen->tiled_sched.
2912 * We simply need to change them into set dimensions.
2914 * Then, for each block dimension, we compute the maximal value of the block id
2917 static __isl_give isl_multi_pw_aff
*extract_grid_size(struct gpu_gen
*gen
,
2918 struct ppcg_kernel
*kernel
)
2923 grid
= isl_union_map_params(isl_union_map_copy(gen
->tiled_sched
));
2924 grid
= isl_set_from_params(grid
);
2925 grid
= isl_set_add_dims(grid
, isl_dim_set
, gen
->n_grid
);
2926 for (i
= 0; i
< gen
->n_grid
; ++i
) {
2930 snprintf(name
, sizeof(name
), "b%d", i
);
2931 pos
= isl_set_find_dim_by_name(grid
, isl_dim_param
, name
);
2933 grid
= isl_set_equate(grid
, isl_dim_param
, pos
, isl_dim_set
, i
);
2934 grid
= isl_set_project_out(grid
, isl_dim_param
, pos
, 1);
2937 return extract_size(grid
, kernel
->context
);
2940 /* Compute the size of a fixed bounding box around the origin and "set",
2941 * where "set" is assumed to contain only non-negative elements,
2942 * and store the results in "size".
2943 * In particular, compute the maximal value of "set" in each direction
2946 static void extract_fixed_size(__isl_take isl_set
*set
, int *size
)
2949 isl_local_space
*ls
;
2952 n
= isl_set_dim(set
, isl_dim_set
);
2953 ls
= isl_local_space_from_space(isl_set_get_space(set
));
2954 obj
= isl_aff_zero_on_domain(ls
);
2955 for (i
= 0; i
< n
; ++i
) {
2958 obj
= isl_aff_set_coefficient_si(obj
, isl_dim_in
, i
, 1);
2959 max
= isl_set_max_val(set
, obj
);
2960 size
[i
] = isl_val_get_num_si(max
) + 1;
2962 obj
= isl_aff_set_coefficient_si(obj
, isl_dim_in
, i
, 0);
2968 /* Compute the effective block size as a list of the sizes in each dimension
2969 * and store the sizes in kernel->block_dim.
2971 * The block size specified by the user or set by default
2972 * in read_block_sizes() and applied in thread_tile_schedule(),
2973 * may be too large for the given code in the sense that
2974 * it may contain threads that don't need to execute anything.
2975 * We therefore don't store this block size in kernel->block_dim,
2976 * but instead the smallest block size that ensures that all threads
2977 * that actually execute code are included in the block.
2979 * The current implementation eliminates all parameters, ensuring
2980 * that the size is a fixed constant in each dimension.
2981 * In principle we could also compute parametric sizes.
2982 * We would have to make sure to project out all b%d and t%d parameters,
2985 static void extract_block_size(struct gpu_gen
*gen
, struct ppcg_kernel
*kernel
)
2990 isl_multi_pw_aff
*mpa
;
2992 block
= isl_union_map_params(isl_union_map_copy(gen
->local_sched
));
2993 block
= isl_set_from_params(block
);
2994 block
= isl_set_add_dims(block
, isl_dim_set
, gen
->n_block
);
2995 kernel
->n_block
= gen
->n_block
;
2996 for (i
= 0; i
< gen
->n_block
; ++i
) {
3000 snprintf(name
, sizeof(name
), "t%d", i
);
3001 pos
= isl_set_find_dim_by_name(block
, isl_dim_param
, name
);
3003 block
= isl_set_equate(block
, isl_dim_param
, pos
,
3006 nparam
= isl_set_dim(block
, isl_dim_param
);
3007 block
= isl_set_project_out(block
, isl_dim_param
, 0, nparam
);
3009 extract_fixed_size(block
, kernel
->block_dim
);
3012 void ppcg_kernel_free(void *user
)
3014 struct ppcg_kernel
*kernel
= user
;
3020 isl_multi_pw_aff_free(kernel
->grid_size
);
3021 isl_set_free(kernel
->context
);
3022 isl_union_set_free(kernel
->arrays
);
3023 isl_space_free(kernel
->space
);
3024 isl_ast_node_free(kernel
->tree
);
3026 for (i
= 0; i
< kernel
->n_array
; ++i
)
3027 isl_pw_aff_list_free(kernel
->array
[i
].bound
);
3028 free(kernel
->array
);
3030 for (i
= 0; i
< kernel
->n_var
; ++i
) {
3031 free(kernel
->var
[i
].name
);
3032 isl_vec_free(kernel
->var
[i
].size
);
3039 static void create_kernel_var(isl_ctx
*ctx
, struct gpu_array_ref_group
*group
,
3040 struct ppcg_kernel_var
*var
)
3043 struct gpu_array_tile
*tile
;
3047 var
->array
= group
->array
;
3049 tile
= group
->private_tile
;
3050 var
->type
= ppcg_access_private
;
3052 tile
= group
->shared_tile
;
3053 var
->type
= ppcg_access_shared
;
3056 p
= isl_printer_to_str(ctx
);
3057 p
= print_array_name(p
, group
);
3058 var
->name
= isl_printer_get_str(p
);
3059 isl_printer_free(p
);
3061 var
->size
= isl_vec_alloc(ctx
, group
->array
->n_index
);
3063 for (j
= 0; j
< group
->array
->n_index
; ++j
)
3064 var
->size
= isl_vec_set_element_val(var
->size
, j
,
3065 isl_val_copy(tile
->bound
[j
].size
));
3068 static void create_kernel_vars(struct gpu_gen
*gen
, struct ppcg_kernel
*kernel
)
3073 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3074 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3076 for (j
= 0; j
< array
->n_group
; ++j
) {
3077 struct gpu_array_ref_group
*group
= array
->groups
[j
];
3078 if (group
->private_tile
|| group
->shared_tile
)
3084 kernel
->var
= isl_calloc_array(gen
->ctx
, struct ppcg_kernel_var
, n
);
3085 assert(kernel
->var
);
3088 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3089 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3091 for (j
= 0; j
< array
->n_group
; ++j
) {
3092 struct gpu_array_ref_group
*group
= array
->groups
[j
];
3093 if (!group
->private_tile
&& !group
->shared_tile
)
3095 create_kernel_var(gen
->ctx
, group
, &kernel
->var
[n
]);
3101 /* The sizes of the arrays on the host that have been computed by
3102 * extract_array_info may depend on the parameters. Use the extra
3103 * constraints on the parameters that are valid at "host_domain"
3104 * to simplify these expressions and store the results in kernel->array.
3106 static void localize_bounds(struct gpu_gen
*gen
, struct ppcg_kernel
*kernel
,
3107 __isl_keep isl_set
*host_domain
)
3112 kernel
->array
= isl_calloc_array(gen
->ctx
,
3113 struct gpu_local_array_info
, gen
->prog
->n_array
);
3114 assert(kernel
->array
);
3115 kernel
->n_array
= gen
->prog
->n_array
;
3117 context
= isl_set_copy(host_domain
);
3118 context
= isl_set_params(context
);
3120 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3121 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3122 isl_pw_aff_list
*local
;
3124 if (array
->n_group
== 0)
3127 local
= isl_pw_aff_list_alloc(gen
->ctx
, array
->n_index
);
3129 for (j
= 0; j
< array
->n_index
; ++j
) {
3132 pwaff
= isl_pw_aff_copy(array
->bound
[j
]);
3133 pwaff
= isl_pw_aff_gist(pwaff
, isl_set_copy(context
));
3134 local
= isl_pw_aff_list_add(local
, pwaff
);
3137 kernel
->array
[i
].bound
= local
;
3139 isl_set_free(context
);
3142 /* Find the element in gen->stmt that has the given "id".
3143 * Return NULL if no such gpu_stmt can be found.
3145 static struct gpu_stmt
*find_stmt(struct gpu_prog
*prog
, __isl_keep isl_id
*id
)
3149 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
3150 if (id
== prog
->stmts
[i
].id
)
3154 return i
< prog
->n_stmts
? &prog
->stmts
[i
] : NULL
;
3157 /* Set gen->tile_len and gen->n_parallel to those of the statement
3158 * affected by the first map (part of the schedule)
3159 * on which this function is called.
3160 * Because of the way the schedule is constructed, the other statements
3161 * in the list, if any, should have the same values for these properties.
3163 static int extract_tile_len(__isl_take isl_map
*map
, void *user
)
3165 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3167 struct gpu_stmt
*stmt
;
3169 id
= isl_map_get_tuple_id(map
, isl_dim_in
);
3170 stmt
= find_stmt(gen
->prog
, id
);
3176 isl_die(gen
->ctx
, isl_error_unknown
,
3177 "statement not found", return -1);
3179 gen
->tile_len
= stmt
->tile_len
;
3180 gen
->n_parallel
= stmt
->n_parallel
;
3185 void ppcg_kernel_stmt_free(void *user
)
3188 struct ppcg_kernel_stmt
*stmt
= user
;
3193 switch (stmt
->type
) {
3194 case ppcg_kernel_copy
:
3195 isl_ast_expr_free(stmt
->u
.c
.index
);
3196 isl_ast_expr_free(stmt
->u
.c
.local_index
);
3198 case ppcg_kernel_domain
:
3199 for (i
= 0; i
< stmt
->u
.d
.n_access
; ++i
) {
3200 isl_ast_expr_list_free(stmt
->u
.d
.access
[i
].index
);
3201 free(stmt
->u
.d
.access
[i
].local_name
);
3203 free(stmt
->u
.d
.access
);
3205 case ppcg_kernel_sync
:
3212 /* Set the options of "context" to
3214 * { space -> [x] : x >= first }
3216 static __isl_give isl_ast_build
*set_unroll(
3217 __isl_take isl_ast_build
*build
, __isl_take isl_space
*space
,
3224 ctx
= isl_ast_build_get_ctx(build
);
3226 space
= isl_space_from_domain(space
);
3227 space
= isl_space_add_dims(space
, isl_dim_out
, 1);
3228 space
= isl_space_set_tuple_name(space
, isl_dim_out
, "unroll");
3229 unroll
= isl_map_universe(space
);
3230 unroll
= isl_map_lower_bound_si(unroll
, isl_dim_out
, 0, first
);
3231 opt
= isl_union_map_from_map(unroll
);
3233 build
= isl_ast_build_set_options(build
, opt
);
3238 /* Return a list of isl_ids of the form "prefix%d".
3240 static __isl_give isl_id_list
*generate_names(isl_ctx
*ctx
,
3241 int n
, const char *prefix
)
3247 names
= isl_id_list_alloc(ctx
, n
);
3248 for (i
= 0; i
< n
; ++i
) {
3251 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
3252 id
= isl_id_alloc(ctx
, name
, NULL
);
3253 names
= isl_id_list_add(names
, id
);
3259 /* Extend the schedule "schedule" with the part of "extension"
3260 * starting at "first" up to "len".
3262 static __isl_give isl_union_map
*extend_schedule(
3263 __isl_take isl_union_map
*schedule
,
3264 __isl_take isl_union_map
*extension
, int first
, int len
)
3268 isl_union_map
*umap
;
3271 space
= isl_union_map_get_space(schedule
);
3272 space
= isl_space_set_from_params(space
);
3273 space
= isl_space_add_dims(space
, isl_dim_set
, len
);
3274 proj
= isl_set_identity(isl_set_universe(space
));
3275 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, first
);
3276 extension
= isl_union_map_apply_range(extension
,
3277 isl_union_map_from_map(proj
));
3279 schedule
= isl_union_map_range_product(schedule
, extension
);
3284 /* This function is called for each access to an array in each instance
3285 * in the kernel of some statement in the original code.
3286 * Replace that access by an access to global, shared or private memory
3287 * and store the results in *kernel_access.
3289 * Since the array in shared or private memory is just
3290 * a shifted copy of part of the original array, we simply need
3291 * to subtract the lower bound, which was computed in can_tile.
3292 * If any of the indices is strided, then we first add
3293 * shared_tile->bound[i].shift and divide by shared_tile->bound[i].stride.
3295 * If the given array is accessed directly from global memory,
3296 * we don't need to perform any shifting and simply simplify
3297 * the expression in the context of the domain instead.
3299 * If the array space (range of access) has no name, then we are
3300 * accessing an iterator in the original program.
3302 * The input stmt_access->access relation maps the iteration domain
3303 * of the current statement to an array element.
3304 * The first step is to reformulate
3305 * this access relation in terms of the loop iterators of the generated
3306 * code through precomposition with gen->stmt_it.
3308 * The expressions in "tile" are formulated in terms of the first
3309 * gen->shared_len dimensions of the computed schedule using the mapping
3310 * sched2shared which maps the loop iterators to these dimensions.
3312 static void compute_index_expression(struct gpu_gen
*gen
,
3313 struct ppcg_kernel_access
*kernel_access
,
3314 struct gpu_stmt_access
*stmt_access
, __isl_keep isl_map
*stmt_it
,
3315 __isl_keep isl_map
*sched2shared
, __isl_keep isl_ast_build
*build
)
3318 isl_pw_multi_aff
*pma
;
3321 struct gpu_array_tile
*tile
= NULL
;
3323 if (isl_map_has_tuple_name(stmt_access
->access
, isl_dim_out
)) {
3326 struct gpu_array_ref_group
*group
;
3329 name
= isl_map_get_tuple_name(stmt_access
->access
, isl_dim_out
);
3331 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3332 if (strcmp(name
, gen
->prog
->array
[i
].name
))
3334 kernel_access
->array
= &gen
->prog
->array
[i
];
3335 kernel_access
->local_array
= &gen
->kernel
->array
[i
];
3337 assert(kernel_access
->array
);
3338 group
= kernel_access
->array
->groups
[stmt_access
->group
];
3339 p
= isl_printer_to_str(gen
->ctx
);
3340 p
= print_array_name(p
, group
);
3341 kernel_access
->local_name
= isl_printer_get_str(p
);
3342 isl_printer_free(p
);
3343 tile
= group
->private_tile
;
3344 kernel_access
->type
= ppcg_access_private
;
3346 tile
= group
->shared_tile
;
3347 kernel_access
->type
= ppcg_access_shared
;
3351 kernel_access
->type
= ppcg_access_global
;
3353 n_index
= isl_map_dim(stmt_access
->access
, isl_dim_out
);
3354 kernel_access
->index
= isl_ast_expr_list_alloc(gen
->ctx
, n_index
);
3359 access
= isl_map_copy(stmt_access
->access
);
3360 access
= isl_map_apply_range(isl_map_copy(stmt_it
), access
);
3361 pma
= isl_pw_multi_aff_from_map(access
);
3362 pma
= isl_pw_multi_aff_coalesce(pma
);
3364 for (i
= 0; i
< n_index
; ++i
) {
3369 index
= isl_pw_multi_aff_get_pw_aff(pma
, i
);
3371 if (!kernel_access
->array
) {
3373 domain
= isl_map_domain(isl_map_copy(stmt_it
));
3374 index
= isl_pw_aff_coalesce(index
);
3375 index
= isl_pw_aff_gist(index
, domain
);
3377 domain
= isl_map_domain(isl_map_copy(stmt_it
));
3378 index
= shift_index(index
, kernel_access
->array
,
3379 &tile
->bound
[i
], domain
,
3380 isl_map_copy(sched2shared
));
3383 expr
= isl_ast_build_expr_from_pw_aff(build
, index
);
3385 kernel_access
->index
= isl_ast_expr_list_add(
3386 kernel_access
->index
, expr
);
3389 isl_pw_multi_aff_free(pma
);
3392 /* This function is called for each instance of a user statement
3395 * We attach a struct ppcg_kernel_stmt to the "node", containing
3396 * local information about the accesses.
3397 * This information is computed from stmt_it, which expresses the domain
3398 * elements in terms of the generated loops, and sched2shared,
3399 * which expresses the first shared_len dimensions of the schedule
3400 * computed by PPCG in terms of the generated loops.
3402 static __isl_give isl_ast_node
*at_each_domain(__isl_take isl_ast_node
*node
,
3403 __isl_keep isl_ast_build
*build
, void *user
)
3405 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3406 struct ppcg_kernel_stmt
*stmt
;
3408 isl_map
*stmt_it
, *sched2shared
;
3409 isl_ast_expr
*expr
, *arg
;
3410 isl_union_map
*schedule
;
3412 struct gpu_stmt_access
*access
;
3414 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3416 return isl_ast_node_free(node
);
3418 expr
= isl_ast_node_user_get_expr(node
);
3419 arg
= isl_ast_expr_get_op_arg(expr
, 0);
3420 id
= isl_ast_expr_get_id(arg
);
3422 schedule
= isl_ast_build_get_schedule(build
);
3423 stmt_it
= isl_map_reverse(isl_map_from_union_map(schedule
));
3424 sched2shared
= compute_sched_to_shared(gen
, isl_map_copy(stmt_it
));
3426 stmt
->type
= ppcg_kernel_domain
;
3427 stmt
->u
.d
.stmt
= find_stmt(gen
->prog
, id
);
3428 if (!stmt
->u
.d
.stmt
)
3432 for (access
= stmt
->u
.d
.stmt
->accesses
; access
; access
= access
->next
)
3435 stmt
->u
.d
.access
= isl_calloc_array(gen
->ctx
,
3436 struct ppcg_kernel_access
, n
);
3437 if (!stmt
->u
.d
.access
)
3440 stmt
->u
.d
.n_access
= n
;
3442 access
= stmt
->u
.d
.stmt
->accesses
;
3443 for (i
= 0; i
< n
; ++i
, access
= access
->next
) {
3444 compute_index_expression(gen
, &stmt
->u
.d
.access
[i
], access
,
3445 stmt_it
, sched2shared
, build
);
3449 isl_map_free(stmt_it
);
3450 isl_map_free(sched2shared
);
3451 isl_ast_expr_free(arg
);
3452 isl_ast_expr_free(expr
);
3454 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3455 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3456 return isl_ast_node_set_annotation(node
, id
);
3459 isl_map_free(stmt_it
);
3460 ppcg_kernel_stmt_free(stmt
);
3461 isl_map_free(sched2shared
);
3462 return isl_ast_node_free(node
);
3465 /* This function is called when code has been generated for the shared
3466 * tile loops. The "schedule" refers only to the original statements.
3468 * We extend the schedule with that part of gen->local_sched that hasn't
3469 * been taken into account yet. This introduces parameters referring
3470 * to thread ids in the schedule, so we add them (with the appropriate
3471 * bounds to the context as well).
3472 * Finally, we set the appropriate unrolling options
3473 * if gen->first_unroll is set.
3475 static __isl_give isl_ast_node
*create_domain_leaf(
3476 __isl_take isl_union_map
*schedule
, __isl_take isl_ast_build
*build
,
3479 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3481 isl_union_map
*sched
;
3484 isl_id_list
*iterators
;
3487 schedule
= extend_schedule(schedule
,
3488 isl_union_map_copy(gen
->local_sched
),
3489 gen
->shared_len
, gen
->thread_tiled_len
);
3491 space
= isl_ast_build_get_schedule_space(build
);
3492 set
= isl_set_universe(space
);
3493 set
= add_bounded_parameters(set
, gen
->kernel
->n_block
,
3494 gen
->kernel
->block_dim
, "t");
3495 build
= isl_ast_build_restrict(build
, set
);
3497 n
= gen
->thread_tiled_len
- gen
->shared_len
;
3499 if (gen
->first_unroll
>= 0) {
3500 space
= isl_space_set_alloc(gen
->ctx
, 0, n
);
3501 build
= set_unroll(build
, space
, gen
->first_unroll
);
3503 iterators
= generate_names(gen
->ctx
, n
, "c");
3504 build
= isl_ast_build_set_iterators(build
, iterators
);
3505 build
= isl_ast_build_set_at_each_domain(build
, &at_each_domain
, gen
);
3506 tree
= isl_ast_build_ast_from_schedule(build
, schedule
);
3507 isl_ast_build_free(build
);
3512 /* This function is called for each statement node in the AST of the code
3513 * for copying to or from shared/private memory.
3514 * Attach a pointer to a ppcg_kernel_stmt representing the copy
3515 * statement to the node.
3516 * The statement name is {read,write}_{shared,private}_<array>.
3518 * The schedule is of the form
3522 * where A refers to a piece of an array and T to the corresponding
3523 * shifted tile. We split this schedule into mappings L -> A and L -> T
3524 * and store the corresponding expressions in stmt->index and stmt->local_index,
3525 * where stmt points to the ppcg_kernel_stmt that is attached to the node.
3527 static __isl_give isl_ast_node
*attach_copy_stmt(__isl_take isl_ast_node
*node
,
3528 __isl_keep isl_ast_build
*build
, void *user
)
3530 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3531 struct ppcg_kernel_stmt
*stmt
;
3535 isl_map
*access
, *local_access
, *map
;
3536 isl_pw_multi_aff
*pma
;
3540 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3542 return isl_ast_node_free(node
);
3544 access
= isl_map_from_union_map(isl_ast_build_get_schedule(build
));
3545 name
= isl_map_get_tuple_name(access
, isl_dim_in
);
3546 stmt
->u
.c
.read
= !strncmp(name
, "read", 4);
3547 access
= isl_map_reverse(access
);
3548 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(access
)));
3549 local_access
= isl_map_copy(access
);
3551 map
= isl_map_domain_map(isl_map_universe(isl_space_copy(space
)));
3552 id
= isl_map_get_tuple_id(access
, isl_dim_out
);
3553 map
= isl_map_set_tuple_id(map
, isl_dim_in
, id
);
3554 access
= isl_map_apply_range(access
, map
);
3555 pma
= isl_pw_multi_aff_from_map(access
);
3556 expr
= isl_ast_build_call_from_pw_multi_aff(build
, pma
);
3557 stmt
->u
.c
.index
= expr
;
3559 map
= isl_map_range_map(isl_map_universe(space
));
3560 id
= isl_map_get_tuple_id(local_access
, isl_dim_out
);
3561 map
= isl_map_set_tuple_id(map
, isl_dim_in
, id
);
3562 local_access
= isl_map_apply_range(local_access
, map
);
3563 pma
= isl_pw_multi_aff_from_map(local_access
);
3564 expr
= isl_ast_build_call_from_pw_multi_aff(build
, pma
);
3565 stmt
->u
.c
.local_index
= expr
;
3567 stmt
->u
.c
.array
= gen
->copy_group
->array
;
3568 array_index
= stmt
->u
.c
.array
- gen
->prog
->array
;
3569 stmt
->u
.c
.local_array
= &gen
->kernel
->array
[array_index
];
3570 stmt
->type
= ppcg_kernel_copy
;
3572 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3573 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3574 return isl_ast_node_set_annotation(node
, id
);
3577 /* Given a schedule of the form
3581 * (with S the first shared_len dimensions of the computed schedule,
3582 * A the array and L the schedule correponding to the generated loops),
3583 * indicating where the copying the array elements that need to be copied,
3584 * construct code for performing the copying.
3586 * "group" is the array reference group that is being copied
3587 * "type" is either "read" or "write"
3588 * private is set if copying needs to be performed to/from registers
3590 * We first construct a mapping to a shifted tile of the array,
3592 * [S -> A] -> T(S,A) (1)
3594 * If private is set, then we also use this mapping as a schedule
3595 * (which is already thread-specific and will be completely unrolled).
3596 * Otherwise, we wrap/tile the range over the threads.
3599 * [S -> A] -> T'(S,A)
3601 * Combined with the given schedule, we have
3603 * [S -> A] -> [L -> T'(S,A)] (2)
3605 * From the shifted tile mapping, we construct a mapping
3607 * [S -> A] -> [A -> T(S,A)]
3609 * and apply it to the schedule (2), obtaining
3611 * [A -> T(S(L),A)] -> [L -> T'(S(L),A)]
3613 * Note that we can project out S because it is uniquely defined by L.
3615 static __isl_give isl_ast_node
*copy_access(struct gpu_gen
*gen
,
3616 __isl_take isl_map
*sched
,
3617 const char *type
, struct gpu_array_ref_group
*group
,
3618 __isl_take isl_ast_build
*build
, int private)
3620 const char *array_name
;
3621 const char *mem
= private ? "private" : "shared";
3625 isl_map
*schedule
, *shift
, *map
;
3627 isl_id_list
*iterators
;
3630 shift
= isl_set_unwrap(isl_map_domain(isl_map_copy(sched
)));
3631 array_name
= isl_map_get_tuple_name(shift
, isl_dim_out
);
3632 shift
= shift_access(shift
, group
);
3634 schedule
= isl_map_copy(shift
);
3636 schedule
= tile_access_schedule(gen
, schedule
);
3638 n
= isl_map_dim(schedule
, isl_dim_out
);
3639 set
= isl_set_universe(isl_ast_build_get_schedule_space(build
));
3640 set
= add_bounded_parameters(set
, gen
->kernel
->n_block
,
3641 gen
->kernel
->block_dim
, "t");
3643 schedule
= isl_map_range_product(sched
, schedule
);
3646 name
= isl_alloc_array(gen
->ctx
, char,
3647 strlen(type
) + sizeof("_private_") + strlen(array_name
) + 20);
3648 if (group
->array
->n_group
> 1)
3649 sprintf(name
, "%s_%s_%s_%d", type
, mem
, array_name
, group
->nr
);
3651 sprintf(name
, "%s_%s_%s", type
, mem
, array_name
);
3652 shift
= isl_map_set_tuple_name(shift
,
3653 isl_dim_out
, name
+ strlen(type
) + 1);
3655 space
= isl_space_domain(isl_map_get_space(shift
));
3656 map
= isl_map_range_map(isl_map_universe(isl_space_unwrap(space
)));
3657 map
= isl_map_range_product(map
, shift
);
3659 schedule
= isl_map_apply_domain(schedule
, map
);
3661 schedule
= isl_map_set_tuple_name(schedule
, isl_dim_in
, name
);
3664 build
= isl_ast_build_restrict(build
, set
);
3666 gen
->copy_group
= group
;
3669 space
= isl_space_range(isl_map_get_space(schedule
));
3670 space
= isl_space_range(isl_space_unwrap(space
));
3671 build
= set_unroll(build
, space
, 0);
3673 iterators
= generate_names(gen
->ctx
, n
, "c");
3674 build
= isl_ast_build_set_iterators(build
, iterators
);
3675 build
= isl_ast_build_set_at_each_domain(build
, &attach_copy_stmt
, gen
);
3676 tree
= isl_ast_build_ast_from_schedule(build
,
3677 isl_union_map_from_map(schedule
));
3678 isl_ast_build_free(build
);
3683 /* Return code for reading into or writing from shared memory
3684 * the given array reference group.
3686 * If we are performing a read from global memory to shared memory and
3687 * if the array involved is not a scalar, then we copy
3688 * the entire tile to shared memory. This may result in some extra
3689 * elements getting copied, but it should lead to simpler code
3690 * (which means that fewer registers may be needed) and less divergence.
3692 * Otherwise, we only copy the elements that will be read or have been written
3696 * The input "sched" is of the form.
3700 * with S the first shared_len dimensions of the computed schedule,
3701 * A the array and L the schedule correponding to the generated loops.
3703 * We first drop "type",
3707 * If the above conditions are satisfied, we project out A,
3712 * and then introduce the group tile [S -> T], resulting in
3716 static __isl_give isl_ast_node
*copy_group_shared_accesses(
3717 struct gpu_gen
*gen
, struct gpu_array_ref_group
*group
,
3718 __isl_take isl_map
*sched
, __isl_take isl_ast_build
*build
)
3722 isl_union_map
*access
;
3724 type
= isl_map_get_tuple_name(sched
, isl_dim_in
);
3725 read
= !strcmp(type
, "read");
3727 sched
= isl_map_reset_tuple_id(sched
, isl_dim_in
);
3729 if (read
&& group
->array
->n_index
> 0) {
3733 space
= isl_space_domain(isl_map_get_space(sched
));
3734 space
= isl_space_unwrap(space
);
3735 map
= isl_map_domain_map(isl_map_universe(space
));
3736 sched
= isl_map_apply_domain(sched
, map
);
3738 map
= group_tile(group
);
3739 map
= isl_map_reverse(isl_map_domain_map(map
));
3740 sched
= isl_map_apply_domain(sched
, map
);
3743 return copy_access(gen
, sched
, type
, group
, build
, 0);
3746 /* Return code for reading into or writing from private memory
3747 * the given array reference group.
3749 * Let S be the first shared_len dimensions of the computed schedule,
3750 * D the iteration domains, A the array and L the schedule correponding
3751 * to the generated loops.
3752 * "sched" is of the form
3756 * where type is either "read" or "write".
3757 * We apply the privatization D -> S(t), with t the thread ids,
3758 * to the access relation D -> A to obtain the privatized access relation
3762 * We drop the type from "sched" and intersect with the privatized access
3763 * relation to obtain
3767 static __isl_give isl_ast_node
*copy_group_private_accesses(
3768 struct gpu_gen
*gen
, struct gpu_array_ref_group
*group
,
3769 __isl_take isl_map
*sched
, __isl_take isl_ast_build
*build
)
3773 isl_union_map
*priv
;
3774 isl_union_map
*access
;
3775 isl_map
*access_map
;
3777 type
= isl_map_get_tuple_name(sched
, isl_dim_in
);
3778 read
= !strcmp(type
, "read");
3780 priv
= isl_union_map_from_map(isl_map_copy(gen
->privatization
));
3781 priv
= isl_union_map_apply_range(isl_union_map_copy(gen
->shared_sched
),
3784 access
= group_access_relation(group
, read
, !read
);
3785 access
= isl_union_map_apply_domain(access
, priv
);
3786 access_map
= isl_map_from_union_map(access
);
3788 sched
= isl_map_reset_tuple_id(sched
, isl_dim_in
);
3789 sched
= isl_map_intersect_domain(sched
, isl_map_wrap(access_map
));
3791 return copy_access(gen
, sched
, type
, group
, build
, 1);
3794 /* Return code for reading into or writing from shared or private memory.
3796 * "schedule" is of the form
3800 * with S be the first shared_len dimensions of the computed schedule,
3801 * A the array and L the schedule correponding to the generated loops.
3802 * The array reference group is attached to "type".
3804 static __isl_give isl_ast_node
*create_access_leaf(
3805 struct gpu_gen
*gen
, __isl_take isl_map
*schedule
,
3806 __isl_take isl_ast_build
*build
)
3808 struct gpu_array_ref_group
*group
;
3811 id
= isl_map_get_tuple_id(schedule
, isl_dim_in
);
3812 group
= isl_id_get_user(id
);
3815 if (group
->private_tile
)
3816 return copy_group_private_accesses(gen
, group
, schedule
,
3819 return copy_group_shared_accesses(gen
, group
, schedule
,
3823 /* Create a domain node representing a synchronization.
3825 static __isl_give isl_ast_node
*create_sync_leaf(
3826 struct gpu_gen
*gen
, __isl_take isl_map
*schedule
,
3827 __isl_take isl_ast_build
*build
)
3829 struct ppcg_kernel_stmt
*stmt
;
3835 isl_map_free(schedule
);
3837 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3841 stmt
->type
= ppcg_kernel_sync
;
3843 space
= isl_ast_build_get_schedule_space(build
);
3844 space
= isl_space_from_domain(space
);
3845 space
= isl_space_set_tuple_name(space
, isl_dim_out
, "sync");
3846 expr
= isl_ast_build_call_from_pw_multi_aff(build
,
3847 isl_pw_multi_aff_from_multi_aff(isl_multi_aff_zero(space
)));
3848 node
= isl_ast_node_alloc_user(expr
);
3849 isl_ast_build_free(build
);
3851 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3852 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3853 return isl_ast_node_set_annotation(node
, id
);
3856 /* This function is called during the code generation at the point
3857 * where the schedule domain element is completely determined by
3858 * the generated code. The input schedule contains the original
3859 * statements as well as synchronization and copy "statements".
3860 * The latter are scheduled at different points than any of the original
3861 * statements, so they will only arrive here in isolation.
3863 * If the current schedule only refers to a single statement,
3864 * we check if it is a copy or synchronization statement and
3865 * call the appropriate functions.
3866 * Otherwise, we assume we are dealing with the original statements
3867 * and we call create_domain_leaf.
3869 static __isl_give isl_ast_node
*create_kernel_leaf(
3870 __isl_take isl_ast_build
*build
, void *user
)
3872 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3874 isl_union_map
*schedule
;
3877 schedule
= isl_ast_build_get_schedule(build
);
3879 if (isl_union_map_n_map(schedule
) != 1)
3880 return create_domain_leaf(schedule
, build
, user
);
3882 map
= isl_map_from_union_map(schedule
);
3883 name
= isl_map_get_tuple_name(map
, isl_dim_in
);
3884 if (!strcmp(name
, "read") || !strcmp(name
, "write"))
3885 return create_access_leaf(gen
, map
, build
);
3886 if (!strcmp(name
, "sync"))
3887 return create_sync_leaf(gen
, map
, build
);
3889 return create_domain_leaf(isl_union_map_from_map(map
), build
, user
);
3892 /* Mark all odd schedule dimensions as "atomic" (when the even dimensions
3893 * have value 0) and all even schedule dimensions as "unroll".
3895 * That is, the options look as follows
3897 * { [0, b, 0, d, ..., 0] -> atomic[i] : exists a : i = 2 a + 1;
3898 * [a, b, c, d, ..., z] -> unroll[i] : exists a : i = 2 a }
3900 * The even positions are used to be able to schedule copying blocks
3901 * and synchronization before or after each level of the shared memory
3902 * tile loops and we want to make sure that code for these is generated
3903 * separately (within each level).
3905 static __isl_give isl_ast_build
*set_atomic_and_unroll(
3906 __isl_take isl_ast_build
*build
,
3907 __isl_take isl_space
*space
, int sched_len
)
3913 isl_local_space
*ls
;
3916 ctx
= isl_ast_build_get_ctx(build
);
3918 space
= isl_space_params(space
);
3919 space
= isl_space_add_dims(space
, isl_dim_set
, sched_len
);
3920 space
= isl_space_from_domain(space
);
3921 space
= isl_space_add_dims(space
, isl_dim_out
, 2);
3922 map
= isl_map_universe(isl_space_copy(space
));
3923 for (i
= 0; i
< sched_len
; i
+= 2)
3924 map
= isl_map_fix_si(map
, isl_dim_in
, i
, 0);
3925 ls
= isl_local_space_from_space(isl_map_get_space(map
));
3926 c
= isl_equality_alloc(ls
);
3927 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 0, 1);
3928 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 1, 2);
3929 c
= isl_constraint_set_constant_si(c
, 1);
3930 map
= isl_map_add_constraint(map
, c
);
3931 map
= isl_map_project_out(map
, isl_dim_out
, 1, 1);
3932 map
= isl_map_set_tuple_name(map
, isl_dim_out
, "atomic");
3933 opt
= isl_union_map_from_map(map
);
3935 map
= isl_map_universe(space
);
3936 ls
= isl_local_space_from_space(isl_map_get_space(map
));
3937 c
= isl_equality_alloc(ls
);
3938 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 0, 1);
3939 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 1, 2);
3940 map
= isl_map_add_constraint(map
, c
);
3941 map
= isl_map_project_out(map
, isl_dim_out
, 1, 1);
3942 map
= isl_map_set_tuple_name(map
, isl_dim_out
, "unroll");
3943 opt
= isl_union_map_add_map(opt
, map
);
3945 build
= isl_ast_build_set_options(build
, opt
);
3950 /* Return a map that maps a space of dimension gen->shared_len
3951 * to its last dimensions starting at gen->tile_first.
3952 * The range is of dimension
3954 * 2 * (gen->shared_len - gen->tile_first) + 1
3956 * The input dimensions are mapped to the odd dimensions in the output,
3957 * while the even dimensions (except 2*pos) are fixed to 0.
3958 * Output dimension 2*pos (if pos >= 0) is fixed to "val".
3959 * If pos >= 0, then only the pos first dimensions starting at gen->tile_first
3960 * are mapped to the output. The remaining input dimensions are projected
3961 * out and the corresponding output dimensions are fixed to 0.
3963 static __isl_give isl_map
*insert_even(struct gpu_gen
*gen
,
3964 __isl_take isl_space
*space
, int pos
, int val
)
3969 space
= isl_space_set_from_params(space
);
3970 space
= isl_space_add_dims(space
, isl_dim_set
, gen
->shared_len
);
3971 space
= isl_space_map_from_set(space
);
3972 proj
= isl_map_identity(space
);
3973 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, gen
->tile_first
);
3974 n
= gen
->shared_len
- gen
->tile_first
;
3975 for (i
= 0; i
<= n
; ++i
) {
3976 proj
= isl_map_insert_dims(proj
, isl_dim_out
, 2 * i
, 1);
3978 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
, val
);
3980 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
, 0);
3986 proj
= isl_map_eliminate(proj
, isl_dim_in
, gen
->tile_first
+ pos
,
3987 gen
->shared_len
- (gen
->tile_first
+ pos
));
3988 for (i
= pos
; i
< n
; ++i
)
3989 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
+ 1, 0);
3994 /* Given the AST context schedule "schedule" and the mapping from
3995 * domains to the shared tile loops "shared_sched", add a schedule
3996 * for a synchronization operation at position "val" of loop level "pos".
3998 * schedule is of the form
4002 * (with D the iteration domains and L the already generated loops),
4003 * while shared_sched is of the form
4007 * We combine them into
4013 * [s_0,...] -> [0,s_{tile_first},0,..., val, 0, 0, ... 0]
4015 * and use the result as a schedule for "sync".
4017 static __isl_give isl_union_map
*add_sync_schedule(struct gpu_gen
*gen
,
4018 __isl_take isl_union_map
*res
, __isl_keep isl_union_map
*schedule
,
4019 __isl_keep isl_union_map
*shared_sched
, int pos
, int val
)
4022 isl_map
*proj
, *map
;
4024 shared_sched
= isl_union_map_copy(shared_sched
);
4025 schedule
= isl_union_map_copy(schedule
);
4027 space
= isl_union_map_get_space(shared_sched
);
4028 schedule
= isl_union_map_apply_domain(shared_sched
, schedule
);
4029 map
= isl_map_from_union_map(schedule
);
4031 proj
= insert_even(gen
, space
, pos
, val
);
4032 map
= isl_map_apply_range(map
, proj
);
4033 map
= isl_map_from_range(isl_map_wrap(map
));
4034 map
= isl_map_set_tuple_name(map
, isl_dim_in
, "sync");
4036 res
= isl_union_map_add_map(res
, map
);
4041 /* Given the AST context schedule "schedule" and the mapping from
4042 * domains to the shared tile loops "shared_sched", add a schedule
4043 * for copying an array reference group to/from shared/private memory.
4044 * "read" is set if data should be copied from global memory
4045 * to shared/private memory.
4046 * "k" represents the current group
4047 * "s" is the total number of groups
4049 * We schedule an operation before or after the innermost loop
4050 * of "shared_sched" that affects the tile of the array reference group.
4052 * schedule is of the form
4056 * (with D the iteration domains and L the already generated loops),
4057 * while shared_sched is of the form
4061 * We first compute the access relation for the reference group
4065 * and combine it with shared_sched into
4069 * If this results in an empty relation, no copying needs to be performed
4071 * Otherwise, we invert the relation and combine it with "schedule" into
4075 * The actual additional piece of the schedule is obtained from combining
4081 * [s_0,...] -> [0,s_{tile_first},0,..., val, 0, 0, ... 0]
4083 * The position of "val" corresponds to the innermost loop that affects
4084 * the tile and the value indicates where the copying is scheduled
4085 * with respect to the actual kernel code (at value 0).
4086 * Reads are schedule before the code, writes to global memory from
4087 * private memory are scheduled at values 1 to s, writes to global
4088 * memory from shared memory are scheduled at values s + 2 to 2 * s + 1.
4090 * If we are scheduling a read from global memory to shared memory,
4091 * we insert a synchronization before the kernel code (at the innermost
4093 * If we are scheduling a write to global memory, then we add
4094 * a synchronization after all writes (at value 2 *s + 2).
4095 * However, there is no need for a synchronization after the outermost loop.
4096 * A write to global memory from private memory at the innermost level
4097 * does not require a synchronization, because it is covered by
4098 * the synchronization after the kernel inserted by body_schedule.
4100 static __isl_give isl_union_map
*add_group_schedule(struct gpu_gen
*gen
,
4101 __isl_take isl_union_map
*res
, __isl_keep isl_union_map
*schedule
,
4102 __isl_keep isl_union_map
*shared_sched
,
4103 struct gpu_array_ref_group
*group
, int read
, int k
, int s
)
4108 isl_union_map
*access
;
4109 isl_map
*map
, *proj
, *access_map
;
4112 access
= group_access_relation(group
, read
, !read
);
4113 access
= isl_union_map_range_product(isl_union_map_copy(shared_sched
),
4116 if (isl_union_map_is_empty(access
)) {
4117 isl_union_map_free(access
);
4121 access
= isl_union_map_reverse(access
);
4122 access
= isl_union_map_apply_range(access
,
4123 isl_union_map_copy(schedule
));
4124 access_map
= isl_map_from_union_map(access
);
4126 space
= isl_space_copy(group
->array
->dim
);
4127 space
= isl_space_from_range(space
);
4128 space
= isl_space_add_dims(space
, isl_dim_in
, gen
->shared_len
);
4129 map
= isl_map_domain_map(isl_map_universe(space
));
4131 space
= isl_union_map_get_space(schedule
);
4132 pos
= group
->last_shared
+ 1 - gen
->tile_first
;
4136 else if (group
->private_tile
)
4139 val
= 1 + s
+ 1 + k
;
4140 proj
= insert_even(gen
, space
, pos
, val
);
4141 map
= isl_map_apply_range(map
, proj
);
4143 access_map
= isl_map_range_product(access_map
, map
);
4145 id
= isl_id_alloc(gen
->ctx
, read
? "read" : "write", group
);
4146 access_map
= isl_map_set_tuple_id(access_map
, isl_dim_in
, id
);
4148 res
= isl_union_map_add_map(res
, access_map
);
4150 n
= gen
->shared_len
- gen
->tile_first
;
4152 if (!group
->private_tile
)
4153 res
= add_sync_schedule(gen
, res
, schedule
,
4154 shared_sched
, n
, -1);
4158 if (pos
== n
&& group
->private_tile
)
4160 res
= add_sync_schedule(gen
, res
, schedule
, shared_sched
,
4167 /* Return a schedule for the shared tile loops based on the current
4168 * AST context schedule.
4170 * We create a "shared_sched" that maps the domains to the first
4171 * shared_len dimensions of the computed schedule, project out the
4172 * first tile_first dimensions (as these are already covered by
4173 * the host code) and insert "statement-level" dimensions at even
4174 * positions so that we can schedule copy blocks and synchronization
4175 * before/after each level.
4177 * In particular, copy blocks are inserted inside the innermost
4178 * level that affect the tile. For the copying to global memory,
4179 * those from private memory are scheduled before those from shared
4180 * memory such that synchronization can be inserted between the two
4181 * at the innermost level.
4182 * Synchronization is inserted at the innermost level before the
4183 * actual kernel code if there is any copying from global memory
4184 * to shared memory. It is inserted unconditionally at the innermost
4185 * level after the actual kernel code and the copying to global memory
4186 * from private memory (if any). Finally, it is inserted after
4187 * any copying to global memory, except at the outermost level
4188 * and at the innermost level if there is no copying from shared
4189 * memory. The copying from private memory is covered by the unconditional
4190 * synchronization at the innermost level.
4192 static __isl_give isl_union_map
*body_schedule(struct gpu_gen
*gen
,
4193 __isl_take isl_union_map
*schedule
)
4197 isl_union_map
*shared_sched
;
4198 isl_union_map
*sched
;
4199 isl_map
*proj
, *map
;
4202 shared_sched
= isl_union_map_copy(gen
->tiled_sched
);
4203 proj
= projection(isl_union_map_get_space(shared_sched
),
4204 gen
->tiled_len
, gen
->shared_len
);
4205 shared_sched
= isl_union_map_apply_range(shared_sched
,
4206 isl_union_map_from_map(proj
));
4207 space
= isl_union_map_get_space(shared_sched
);
4208 proj
= insert_even(gen
, space
, -1, 0);
4209 sched
= isl_union_map_apply_range(isl_union_map_copy(shared_sched
),
4210 isl_union_map_from_map(proj
));
4212 res
= isl_union_map_range_product(isl_union_map_copy(schedule
), sched
);
4215 for (i
= 0; i
< gen
->prog
->n_array
; ++i
)
4216 s
+= gen
->prog
->array
[i
].n_group
;
4219 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
4220 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
4222 for (j
= 0; j
< array
->n_group
; ++j
) {
4223 struct gpu_array_ref_group
*group
;
4225 group
= array
->groups
[j
];
4226 if (!group
->private_tile
&& !group
->shared_tile
)
4228 res
= add_group_schedule(gen
, res
, schedule
,
4229 shared_sched
, group
, 0, k
, s
);
4230 res
= add_group_schedule(gen
, res
, schedule
,
4231 shared_sched
, group
, 1, k
, s
);
4236 res
= add_sync_schedule(gen
, res
, schedule
, shared_sched
,
4237 gen
->shared_len
- gen
->tile_first
, 1 + s
);
4239 isl_union_map_free(shared_sched
);
4240 isl_union_map_free(schedule
);
4245 /* Generate code for "kernel" in the given "context".
4247 * We first generate code for the shared tile loops (T1T, T1P and T2)
4248 * in a context that includes the block ids.
4249 * Within each iteration of these loops an additional code generation
4250 * is performed (within create_kernel_leaf) for the rest of the schedule
4251 * in a context that includes the thread ids.
4253 static __isl_give isl_ast_node
*generate_kernel(struct gpu_gen
*gen
,
4254 __isl_keep isl_ast_build
*build
, __isl_keep isl_set
*host_domain
,
4255 __isl_keep isl_multi_pw_aff
*grid_size
)
4259 isl_id_list
*iterators
;
4260 isl_union_map
*schedule
;
4264 schedule
= isl_ast_build_get_schedule(build
);
4266 build
= isl_ast_build_copy(build
);
4267 build
= isl_ast_build_restrict(build
, isl_set_copy(host_domain
));
4268 space
= isl_ast_build_get_schedule_space(build
);
4269 set
= isl_set_universe(isl_space_copy(space
));
4270 set
= add_bounded_parameters_dynamic(set
, grid_size
, "b");
4271 build
= isl_ast_build_restrict(build
, set
);
4273 schedule
= body_schedule(gen
, schedule
);
4275 sched_len
= 2 * (gen
->shared_len
- gen
->tile_first
) + 1;
4277 build
= set_atomic_and_unroll(build
, space
, sched_len
);
4278 iterators
= generate_names(gen
->ctx
, sched_len
, "g");
4279 build
= isl_ast_build_set_iterators(build
, iterators
);
4280 build
= isl_ast_build_set_create_leaf(build
, &create_kernel_leaf
, gen
);
4281 tree
= isl_ast_build_ast_from_schedule(build
, schedule
);
4282 isl_ast_build_free(build
);
4287 /* Attach "id" to the given node.
4289 static __isl_give isl_ast_node
*attach_id(__isl_take isl_ast_node
*node
,
4290 __isl_keep isl_ast_build
*build
, void *user
)
4294 node
= isl_ast_node_set_annotation(node
, id
);
4299 /* Construct an AST node for performing a kernel launch and attach
4300 * the information about the kernel to that node.
4302 * The kernel AST has been constructed in the context of the range
4303 * of "schedule". In particular, the grid size has been computed
4304 * in the context. We therefore still need to make sure that these
4305 * constraints are expressed in the code. We do this by creating a schedule
4307 * kernel[] -> [S -> []]
4309 * where S is the schedule domain, i.e., the range of "schedule".
4310 * The AST generation will then create a single call surrounded by
4311 * all the condition in "S" that have not been expressed yet.
4313 * The kernel information is attached to this node in attach_id.
4315 static __isl_give isl_ast_node
*construct_launch(
4316 __isl_take isl_ast_build
*build
, __isl_take isl_union_map
*schedule
,
4317 __isl_take
struct ppcg_kernel
*kernel
)
4321 isl_union_set
*domain
;
4326 ctx
= isl_ast_build_get_ctx(build
);
4328 id
= isl_id_alloc(ctx
, NULL
, kernel
);
4329 id
= isl_id_set_free_user(id
, &ppcg_kernel_free
);
4331 domain
= isl_union_map_range(schedule
);
4332 set
= isl_set_from_union_set(domain
);
4333 map
= isl_map_from_domain(set
);
4334 map
= isl_map_from_range(isl_map_wrap(map
));
4335 map
= isl_map_set_tuple_name(map
, isl_dim_in
, "kernel");
4336 schedule
= isl_union_map_from_map(map
);
4338 build
= isl_ast_build_set_at_each_domain(build
, &attach_id
, id
);
4339 node
= isl_ast_build_ast_from_schedule(build
, schedule
);
4340 isl_ast_build_free(build
);
4345 /* This function is called for each leaf in the AST of the host code.
4346 * We first specialize the schedule to the site of the leaf, compute
4347 * the size of shared memory and then construct the body of host code
4348 * and the associated kernel.
4350 * The necessary information for printing the kernel launch is
4351 * stored in a struct ppcg_kernel and attached to the leaf node
4352 * created to represent the launch.
4354 static __isl_give isl_ast_node
*create_host_leaf(
4355 __isl_take isl_ast_build
*build
, void *user
)
4357 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
4360 struct ppcg_kernel
*kernel
;
4361 isl_set
*host_domain
;
4362 isl_union_map
*schedule
;
4363 isl_union_map
*local_sched
;
4364 isl_union_map
*access
;
4365 isl_union_set
*domain
;
4368 schedule
= isl_ast_build_get_schedule(build
);
4370 isl_union_map_foreach_map(schedule
, &extract_tile_len
, gen
);
4373 domain
= isl_union_map_domain(isl_union_map_copy(schedule
));
4375 local_sched
= isl_union_map_copy(gen
->sched
);
4376 local_sched
= isl_union_map_intersect_domain(local_sched
, domain
);
4377 access
= isl_union_map_union(isl_union_map_copy(gen
->prog
->read
),
4378 isl_union_map_copy(gen
->prog
->write
));
4379 access
= isl_union_map_apply_domain(access
,
4380 isl_union_map_copy(local_sched
));
4382 gen
->tiled_sched
= tile_schedule(gen
, local_sched
);
4383 gen
->tiled_sched
= parametrize_tiled_schedule(gen
, gen
->tiled_sched
);
4384 gen
->tiled_sched
= scale_tile_loops(gen
, gen
->tiled_sched
);
4386 gen
->local_sched
= isl_union_map_copy(gen
->tiled_sched
);
4387 gen
->local_sched
= thread_tile_schedule(gen
, gen
->local_sched
);
4388 gen
->local_sched
= scale_thread_tile_loops(gen
, gen
->local_sched
);
4390 kernel
= gen
->kernel
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel
);
4394 kernel
->id
= gen
->kernel_id
++;
4395 kernel
->context
= isl_union_map_params(isl_union_map_copy(schedule
));
4396 kernel
->grid_size
= extract_grid_size(gen
, kernel
);
4397 extract_block_size(gen
, kernel
);
4398 kernel
->arrays
= isl_union_map_range(access
);
4399 kernel
->space
= isl_ast_build_get_schedule_space(build
);
4401 gen
->private_access
= NULL
;
4402 compute_shared_sched(gen
);
4403 gen
->privatization
= compute_privatization(gen
);
4404 group_references(gen
);
4405 compute_private_access(gen
);
4406 check_shared_memory_bound(gen
);
4407 host_domain
= isl_set_from_union_set(isl_union_map_range(
4408 isl_union_map_copy(schedule
)));
4409 localize_bounds(gen
, kernel
, host_domain
);
4411 gen
->local_sched
= interchange_for_unroll(gen
, gen
->local_sched
);
4413 kernel
->tree
= generate_kernel(gen
, build
, host_domain
,
4415 create_kernel_vars(gen
, kernel
);
4417 free_local_array_info(gen
);
4418 isl_map_free(gen
->privatization
);
4419 isl_union_map_free(gen
->private_access
);
4420 isl_union_map_free(gen
->local_sched
);
4421 isl_union_map_free(gen
->tiled_sched
);
4422 isl_union_map_free(gen
->shared_sched
);
4423 isl_union_map_free(gen
->shared_proj
);
4424 isl_set_free(host_domain
);
4425 free(gen
->tile_size
);
4427 node
= construct_launch(build
, schedule
, kernel
);
4431 isl_union_map_free(schedule
);
4435 /* Use isl to generate code for the outer gen->tile_first loops
4436 * of the global schedule in gen->sched, resulting in the host code.
4437 * Within each iteration of this partial schedule, i.e., for each kernel
4438 * launch, create_host_leaf takes care of generating the kernel code.
4440 static __isl_give isl_ast_node
*generate_host_code(struct gpu_gen
*gen
)
4442 isl_ast_build
*build
;
4444 isl_union_map
*sched
;
4446 isl_id_list
*iterators
;
4448 sched
= isl_union_map_copy(gen
->sched
);
4449 proj
= projection(isl_union_map_get_space(sched
),
4450 gen
->untiled_len
, gen
->tile_first
);
4451 sched
= isl_union_map_apply_range(sched
, isl_union_map_from_map(proj
));
4453 isl_options_set_ast_build_group_coscheduled(gen
->ctx
, 1);
4454 build
= isl_ast_build_from_context(isl_set_copy(gen
->prog
->context
));
4455 iterators
= generate_names(gen
->ctx
, gen
->tile_first
, "h");
4456 build
= isl_ast_build_set_iterators(build
, iterators
);
4457 build
= isl_ast_build_set_create_leaf(build
, &create_host_leaf
, gen
);
4458 tree
= isl_ast_build_ast_from_schedule(build
, sched
);
4459 isl_ast_build_free(build
);
4464 __isl_give isl_union_map
*extract_sizes_from_str(isl_ctx
*ctx
, const char *str
)
4468 return isl_union_map_read_from_str(ctx
, str
);
4471 /* Information about the outermost tilable bands in the forest of bands.
4473 * tile_len and n_parallel are only sets on band_info structures
4474 * that correspond to outermost bands. For other bands (in particular,
4475 * ancestors of the outermost bands), n_parallal is set to 0.
4477 * prefix is the (padded) schedule leading up to the outermost tilable bands.
4479 * tile_first is the number of schedule dimensions in prefix.
4481 * suffix is the schedule of the outermost tilable bands and their descendants.
4484 struct gpu_gen
*gen
;
4488 isl_union_map
*prefix
;
4489 isl_union_map
*suffix
;
4492 /* Set tile_len and n_parallel of the statement to that of
4493 * their outermost band, recorded in the band_info.
4495 static int set_stmt_tile_len(__isl_take isl_map
*map
, void *user
)
4497 struct band_info
*info
= user
;
4498 struct gpu_stmt
*stmt
;
4501 id
= isl_map_get_tuple_id(map
, isl_dim_in
);
4502 stmt
= find_stmt(info
->gen
->prog
, id
);
4505 stmt
->tile_len
= info
->tile_len
;
4506 stmt
->n_parallel
= info
->n_parallel
;
4513 static void list_select_outer_band(struct gpu_gen
*gen
,
4514 __isl_take isl_band_list
*list
, int pos
, struct band_info
*list_info
);
4516 /* Check if this band has any parallel loops. If so, take it as
4517 * the outermost tilable band. If not, continue looking for the
4518 * outermost tilable band in the children of the current band.
4520 static void band_select_outer_band(struct gpu_gen
*gen
,
4521 __isl_take isl_band
*band
, int pos
, struct band_info
*info
)
4523 int n
= isl_band_n_member(band
);
4526 for (n_parallel
= 0; n_parallel
< n
; ++n_parallel
)
4527 if (!isl_band_member_is_zero_distance(band
, n_parallel
))
4530 info
->n_parallel
= n_parallel
;
4533 info
->tile_first
= pos
;
4535 info
->prefix
= isl_band_get_prefix_schedule(band
);
4536 info
->suffix
= isl_union_map_flat_range_product(
4537 isl_band_get_partial_schedule(band
),
4538 isl_band_get_suffix_schedule(band
));
4539 isl_union_map_foreach_map(info
->prefix
,
4540 &set_stmt_tile_len
, info
);
4541 } else if (isl_band_has_children(band
)) {
4542 isl_band_list
*children
;
4543 children
= isl_band_get_children(band
);
4544 list_select_outer_band(gen
, children
, pos
+ n
, info
);
4547 info
->tile_first
= pos
+ n
;
4549 info
->prefix
= isl_union_map_flat_range_product(
4550 isl_band_get_prefix_schedule(band
),
4551 isl_band_get_partial_schedule(band
));
4552 info
->suffix
= isl_band_get_suffix_schedule(band
);
4553 isl_union_map_foreach_map(info
->prefix
,
4554 &set_stmt_tile_len
, info
);
4557 isl_band_free(band
);
4560 /* Comparison function that returns a non-zero value for band_infos
4561 * with different tile_len fields or different n_parallel fields.
4563 static int cmp_band(const void *p1
, const void *p2
)
4565 const struct band_info
*info1
= p1
;
4566 const struct band_info
*info2
= p2
;
4568 if (info1
->tile_len
!= info2
->tile_len
)
4569 return info1
->tile_len
- info2
->tile_len
;
4571 return info1
->n_parallel
- info2
->n_parallel
;
4574 /* Extend "umap" with coordinates with fixed value "val"
4575 * to a total length of "dst_len", assuming the original dimension is "src_len".
4577 static __isl_give isl_union_map
*extend_range(
4578 __isl_take isl_union_map
*umap
, int src_len
, int dst_len
, int val
)
4584 dim
= isl_union_map_get_space(umap
);
4585 map
= isl_map_reverse(projection(dim
, dst_len
, src_len
));
4586 for (i
= src_len
; i
< dst_len
; ++i
)
4587 map
= isl_map_fix_si(map
, isl_dim_out
, i
, val
);
4589 umap
= isl_union_map_apply_range(umap
, isl_union_map_from_map(map
));
4594 /* Group bands with the same values for tile_len and n_parallel.
4595 * The prefix schedule is then extended with a fixed coordinate that
4596 * is different for each such group.
4597 * Note that the actual values for this coordinate are not important.
4598 * The bands have already been effectively separated at a higher level
4599 * or they are independent and may be executed in parallel.
4600 * The list of band_info has been sorted before this functions is called.
4602 static void separate_bands(struct band_info
*info
, int n
)
4607 for (i
= 0; i
< n
; ++i
) {
4608 int l
= info
[i
].tile_first
;
4611 (info
[i
].tile_len
!= info
[i
- 1].tile_len
||
4612 info
[i
].n_parallel
!= info
[i
- 1].n_parallel
))
4615 info
[i
].prefix
= extend_range(info
[i
].prefix
,
4617 info
[i
].tile_first
= l
+ 1;
4621 /* Select the outermost bands in the elements of the list, align
4622 * their prefix schedules, separate bands with different values
4623 * for tile_len and/or n_parallel and then combine the resulting
4624 * prefix and suffix schedules into a single pair of prefix and
4625 * suffix schedules for the entire list.
4627 static void list_select_outer_band(struct gpu_gen
*gen
,
4628 __isl_take isl_band_list
*list
, int pos
, struct band_info
*list_info
)
4632 int n
= isl_band_list_n_band(list
);
4633 isl_ctx
*ctx
= isl_band_list_get_ctx(list
);
4634 struct band_info
*info
;
4636 isl_union_map
*prefix
;
4637 isl_union_map
*suffix
;
4640 info
= isl_calloc_array(ctx
, struct band_info
, n
);
4644 for (i
= 0; i
< n
; ++i
) {
4645 band
= isl_band_list_get_band(list
, i
);
4646 band_select_outer_band(gen
, band
, pos
, &info
[i
]);
4647 if (info
[i
].tile_first
> max_tile_first
)
4648 max_tile_first
= info
[i
].tile_first
;
4651 for (i
= 0; i
< n
; ++i
) {
4652 if (info
[i
].tile_first
== max_tile_first
)
4654 info
[i
].prefix
= extend_range(info
[i
].prefix
,
4655 info
[i
].tile_first
, max_tile_first
, 0);
4656 info
[i
].tile_first
= max_tile_first
;
4659 qsort(info
, n
, sizeof(struct band_info
), &cmp_band
);
4661 for (i
= 0; i
< n
- 1; ++i
)
4662 if (info
[i
].tile_len
!= info
[i
+ 1].tile_len
||
4663 info
[i
].n_parallel
!= info
[i
+ 1].n_parallel
)
4667 separate_bands(info
, n
);
4669 prefix
= info
[0].prefix
;
4670 suffix
= info
[0].suffix
;
4672 for (i
= 1; i
< n
; ++i
) {
4673 prefix
= isl_union_map_union(prefix
, info
[i
].prefix
);
4674 suffix
= isl_union_map_union(suffix
, info
[i
].suffix
);
4677 list_info
->tile_first
= info
[0].tile_first
;
4678 list_info
->tile_len
= -1;
4679 list_info
->prefix
= prefix
;
4680 list_info
->suffix
= suffix
;
4682 isl_band_list_free(list
);
4686 /* Select the outermost tilable band that (by construction)
4687 * has at least one parallel loop.
4688 * The starting position of the aligned band is stored in the pair
4690 * The sizes and number of parallel loops may be different in different
4691 * parts of the band forest and are therefore stored in the gpu_stmts.
4693 * Return the complete schedule, with the tilable bands aligned
4694 * at gen->tile_first and padded with zero, if needed.
4696 static __isl_give isl_union_map
*select_outer_tilable_band(struct gpu_gen
*gen
,
4697 __isl_keep isl_schedule
*schedule
)
4699 isl_band_list
*list
;
4700 struct band_info info
;
4702 gen
->n_parallel
= 0;
4705 list
= isl_schedule_get_band_forest(schedule
);
4707 list_select_outer_band(gen
, list
, 0, &info
);
4709 gen
->tile_first
= info
.tile_first
;
4710 info
.suffix
= align_range(info
.suffix
);
4712 return isl_union_map_flat_range_product(info
.prefix
, info
.suffix
);
4715 /* Set gen->untiled_len to the number of scheduling dimensions
4716 * for the schedule of the first domain.
4717 * We assume here that this number is the same for all domains.
4719 static int set_untiled_len(__isl_take isl_map
*map
, void *user
)
4721 unsigned *untiled_len
= user
;
4723 *untiled_len
= isl_map_dim(map
, isl_dim_out
);
4729 /* Compute an appropriate schedule based on the accesses in
4730 * gen->read and gen->write.
4732 * We use the dependences in gen->prog->scop to compute
4733 * a schedule that has a parallel loop in each tilable band.
4734 * Finally, we select the outermost tilable band.
4736 static void compute_schedule(struct gpu_gen
*gen
)
4738 isl_union_set
*domain
;
4739 isl_union_map
*dep_raw
, *dep
;
4740 isl_union_map
*sched
;
4741 isl_schedule
*schedule
;
4743 dep_raw
= isl_union_map_copy(gen
->prog
->scop
->dep_flow
);
4745 dep
= isl_union_map_copy(gen
->prog
->scop
->dep_false
);
4746 dep
= isl_union_map_union(dep
, dep_raw
);
4747 dep
= isl_union_map_coalesce(dep
);
4749 domain
= isl_union_set_copy(gen
->prog
->scop
->domain
);
4750 domain
= isl_union_set_intersect_params(domain
,
4751 isl_set_copy(gen
->prog
->scop
->context
));
4752 schedule
= isl_union_set_compute_schedule(isl_union_set_copy(domain
),
4753 isl_union_map_copy(dep
), dep
);
4754 if (gen
->options
->debug
->dump_schedule
)
4755 isl_schedule_dump(schedule
);
4757 sched
= select_outer_tilable_band(gen
, schedule
);
4759 isl_union_map_foreach_map(sched
, &set_untiled_len
, &gen
->untiled_len
);
4760 sched
= isl_union_map_intersect_domain(sched
, domain
);
4763 isl_schedule_free(schedule
);
4766 /* Compute the sets of array elements that need to be copied in and out.
4768 * In particular, for each array that is written anywhere in gen->prog and
4769 * that is visible outside the corresponding scop, we copy out its entire
4772 * Any array elements that is read without first being written needs
4773 * to be copied in. Furthermore, if there are any array elements that
4774 * are copied out, but that are not written inside gen->prog, then
4775 * they also need to be copied in to ensure that the value after execution
4776 * is the same as the value before execution.
4777 * While computing the set of array elements that
4778 * are copied out but not written, we intersect both sets with the context.
4779 * This helps in those cases where the arrays are declared with a fixed size,
4780 * while the accesses are parametric and the context assigns a fixed value
4781 * to the parameters.
4783 static void compute_copy_in_and_out(struct gpu_gen
*gen
)
4786 isl_union_set
*write
;
4787 isl_union_set
*copy_in
, *copy_out
;
4788 isl_union_set
*not_written
;
4789 isl_union_map
*uninitialized
;
4791 write
= isl_union_map_range(isl_union_map_copy(gen
->prog
->write
));
4792 write
= isl_union_set_intersect_params(write
,
4793 isl_set_copy(gen
->prog
->context
));
4794 copy_out
= isl_union_set_empty(isl_union_set_get_space(write
));
4796 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
4801 if (gen
->prog
->array
[i
].local
)
4804 space
= isl_space_copy(gen
->prog
->array
[i
].dim
);
4805 write_i
= isl_union_set_extract_set(write
, space
);
4806 empty
= isl_set_fast_is_empty(write_i
);
4807 isl_set_free(write_i
);
4811 write_i
= isl_set_copy(gen
->prog
->array
[i
].extent
);
4812 copy_out
= isl_union_set_add_set(copy_out
, write_i
);
4815 copy_out
= isl_union_set_intersect_params(copy_out
,
4816 isl_set_copy(gen
->prog
->context
));
4818 gen
->prog
->copy_out
= isl_union_set_copy(copy_out
);
4820 uninitialized
= isl_union_map_copy(gen
->prog
->scop
->live_in
);
4821 copy_in
= isl_union_map_range(uninitialized
);
4823 not_written
= isl_union_set_subtract(copy_out
, write
);
4824 copy_in
= isl_union_set_union(copy_in
, not_written
);
4825 gen
->prog
->copy_in
= copy_in
;
4828 static struct gpu_stmt_access
**expr_extract_access(struct pet_expr
*expr
,
4829 struct gpu_stmt_access
**next_access
)
4831 struct gpu_stmt_access
*access
;
4832 isl_ctx
*ctx
= isl_map_get_ctx(expr
->acc
.access
);
4834 access
= isl_alloc_type(ctx
, struct gpu_stmt_access
);
4836 access
->next
= NULL
;
4837 access
->read
= expr
->acc
.read
;
4838 access
->write
= expr
->acc
.write
;
4839 access
->access
= isl_map_copy(expr
->acc
.access
);
4841 *next_access
= access
;
4842 next_access
= &(*next_access
)->next
;
4846 static struct gpu_stmt_access
**expr_extract_accesses(struct pet_expr
*expr
,
4847 struct gpu_stmt_access
**next_access
)
4851 for (i
= 0; i
< expr
->n_arg
; ++i
)
4852 next_access
= expr_extract_accesses(expr
->args
[i
],
4855 if (expr
->type
== pet_expr_access
)
4856 next_access
= expr_extract_access(expr
, next_access
);
4861 static void pet_stmt_extract_accesses(struct gpu_stmt
*stmt
)
4863 struct gpu_stmt_access
**next_access
= &stmt
->accesses
;
4865 stmt
->accesses
= NULL
;
4866 expr_extract_accesses(stmt
->body
, next_access
);
4869 /* Return an array of gpu_stmt representing the statements in "scop".
4871 static struct gpu_stmt
*extract_stmts(isl_ctx
*ctx
, struct ppcg_scop
*scop
,
4872 __isl_keep isl_set
*context
)
4875 struct gpu_stmt
*stmts
;
4877 stmts
= isl_calloc_array(ctx
, struct gpu_stmt
, scop
->n_stmt
);
4880 for (i
= 0; i
< scop
->n_stmt
; ++i
) {
4881 struct gpu_stmt
*s
= &stmts
[i
];
4883 s
->id
= isl_set_get_tuple_id(scop
->stmts
[i
]->domain
);
4884 s
->body
= scop
->stmts
[i
]->body
;
4885 pet_stmt_extract_accesses(s
);
4891 /* Replace the scop in the "input" file by equivalent code
4892 * that uses the GPU. "scop" is assumed to correspond to this scop.
4894 * We first compute a schedule that respects the dependences
4895 * of the original program and select the outermost band
4896 * of tilable dimensions that has at least one parallel loop.
4897 * We then have three blocks of dimensions
4901 * The tilable band "B" is first tiled according to "tile" sizes, resulting
4906 * For each iteration of the T loop and for each array, we compute
4907 * the array elements accessed by that iteration, construct a rectangular
4908 * box around it and shift it to the origin. The result is used
4909 * as shared memory for the array.
4911 * We then split off at most 2 parallel loops from the T loops and
4912 * at most 3 parallel loops from the P loops
4916 * The T1/P1 loops are then tiled or "wrapped" over the blocks/threads,
4917 * according to "grid"/"block" sizes.
4919 * H T1T T1P T2 P1T P1P P2 G
4921 * Finally, the T1P and P1P iterators are equated to the block and
4922 * thread dimensions respectively and so are effectively removed.
4923 * The H loops are run on the host. The T1T, T2, P1T, P2 and G loops
4924 * are run on the GPU.
4926 * Code is generated in three stages. We first generate code for the
4927 * host (the H loops), with iterators h%d. Then, for each leaf node
4928 * of the resulting AST, we generate code for the shared loops (up to
4929 * and including T2), with iterators g%d and after equating the H loops
4930 * to h%d parameters and the T1P loops to the block dimensions.
4931 * Finally, we generate code for the remaining loops in a similar fashion.
4933 __isl_give isl_ast_node
*generate_gpu(isl_ctx
*ctx
, struct gpu_prog
*prog
,
4934 struct ppcg_options
*options
)
4936 isl_union_map
*sched
;
4945 gen
.sizes
= extract_sizes_from_str(ctx
, options
->sizes
);
4946 gen
.options
= options
;
4948 compute_schedule(&gen
);
4949 compute_copy_in_and_out(&gen
);
4952 tree
= generate_host_code(&gen
);
4954 clear_gpu_gen(&gen
);
4959 struct gpu_prog
*gpu_prog_alloc(isl_ctx
*ctx
, struct ppcg_scop
*scop
)
4961 struct gpu_prog
*prog
;
4966 prog
= isl_calloc_type(ctx
, struct gpu_prog
);
4971 prog
->context
= isl_set_copy(scop
->context
);
4972 prog
->n_stmts
= scop
->n_stmt
;
4973 prog
->stmts
= extract_stmts(ctx
, scop
, prog
->context
);
4974 prog
->read
= isl_union_map_copy(scop
->reads
);
4975 prog
->write
= isl_union_map_copy(scop
->writes
);
4977 collect_array_info(prog
);
4982 void gpu_prog_free(struct gpu_prog
*prog
)
4986 free_array_info(prog
);
4987 free_stmts(prog
->stmts
, prog
->n_stmts
);
4988 isl_union_set_free(prog
->copy_in
);
4989 isl_union_set_free(prog
->copy_out
);
4990 isl_union_map_free(prog
->read
);
4991 isl_union_map_free(prog
->write
);
4992 isl_set_free(prog
->context
);