2 * include/asm-sh/spinlock.h
4 * Copyright (C) 2002, 2003 Paul Mundt
5 * Copyright (C) 2006, 2007 Akio Idehara
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #ifndef __ASM_SH_SPINLOCK_H
12 #define __ASM_SH_SPINLOCK_H
15 * The only locking implemented here uses SH-4A opcodes. For others,
16 * split this out as per atomic-*.h.
18 #ifndef CONFIG_CPU_SH4A
19 #error "Need movli.l/movco.l for spinlocks"
23 * Your basic SMP spinlocks, allowing only a single CPU anywhere
26 #define arch_spin_is_locked(x) ((x)->lock <= 0)
27 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
28 #define arch_spin_unlock_wait(x) \
29 do { while (arch_spin_is_locked(x)) cpu_relax(); } while (0)
32 * Simple spin lock operations. There are two variants, one clears IRQ's
33 * on the local processor, one does not.
35 * We make no fairness assumptions. They have a cost.
37 static inline void arch_spin_lock(arch_spinlock_t
*lock
)
42 __asm__
__volatile__ (
44 "movli.l @%2, %0 ! arch_spin_lock \n\t"
47 "movco.l %0, @%2 \n\t"
51 : "=&z" (tmp
), "=&r" (oldval
)
57 static inline void arch_spin_unlock(arch_spinlock_t
*lock
)
61 __asm__
__volatile__ (
62 "mov #1, %0 ! arch_spin_unlock \n\t"
70 static inline int arch_spin_trylock(arch_spinlock_t
*lock
)
72 unsigned long tmp
, oldval
;
74 __asm__
__volatile__ (
76 "movli.l @%2, %0 ! arch_spin_trylock \n\t"
79 "movco.l %0, @%2 \n\t"
82 : "=&z" (tmp
), "=&r" (oldval
)
91 * Read-write spinlocks, allowing multiple readers but only one writer.
93 * NOTE! it is quite common to have readers in interrupts but no interrupt
94 * writers. For those circumstances we can "mix" irq-safe locks - any writer
95 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
100 * read_can_lock - would read_trylock() succeed?
101 * @lock: the rwlock in question.
103 #define __raw_read_can_lock(x) ((x)->lock > 0)
106 * write_can_lock - would write_trylock() succeed?
107 * @lock: the rwlock in question.
109 #define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
111 static inline void __raw_read_lock(arch_rwlock_t
*rw
)
115 __asm__
__volatile__ (
117 "movli.l @%1, %0 ! __raw_read_lock \n\t"
121 "movco.l %0, @%1 \n\t"
129 static inline void __raw_read_unlock(arch_rwlock_t
*rw
)
133 __asm__
__volatile__ (
135 "movli.l @%1, %0 ! __raw_read_unlock \n\t"
137 "movco.l %0, @%1 \n\t"
145 static inline void __raw_write_lock(arch_rwlock_t
*rw
)
149 __asm__
__volatile__ (
151 "movli.l @%1, %0 ! __raw_write_lock \n\t"
155 "movco.l %0, @%1 \n\t"
158 : "r" (&rw
->lock
), "r" (RW_LOCK_BIAS
)
163 static inline void __raw_write_unlock(arch_rwlock_t
*rw
)
165 __asm__
__volatile__ (
166 "mov.l %1, @%0 ! __raw_write_unlock \n\t"
168 : "r" (&rw
->lock
), "r" (RW_LOCK_BIAS
)
173 static inline int __raw_read_trylock(arch_rwlock_t
*rw
)
175 unsigned long tmp
, oldval
;
177 __asm__
__volatile__ (
179 "movli.l @%2, %0 ! __raw_read_trylock \n\t"
184 "movco.l %0, @%2 \n\t"
188 : "=&z" (tmp
), "=&r" (oldval
)
196 static inline int __raw_write_trylock(arch_rwlock_t
*rw
)
198 unsigned long tmp
, oldval
;
200 __asm__
__volatile__ (
202 "movli.l @%2, %0 ! __raw_write_trylock \n\t"
208 "movco.l %0, @%2 \n\t"
211 : "=&z" (tmp
), "=&r" (oldval
)
212 : "r" (&rw
->lock
), "r" (RW_LOCK_BIAS
)
216 return (oldval
> (RW_LOCK_BIAS
- 1));
219 #define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
220 #define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
222 #define arch_spin_relax(lock) cpu_relax()
223 #define arch_read_relax(lock) cpu_relax()
224 #define arch_write_relax(lock) cpu_relax()
226 #endif /* __ASM_SH_SPINLOCK_H */