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mach-orion5x/common.c: remove unnecessary (void *) casts
[pohmelfs.git] / drivers / serial / 8250_pci.c
blobb28af13c45a179f08da023374a9f7b30cf347937
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71 }
72
73 static int
74 setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76 {
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap_nocache(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106 }
107
108 /*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_port *port, int idx)
114 {
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132 }
133
134 /*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138 static int
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_port *port, int idx)
141 {
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153 }
154
155 /*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162 static int pci_hp_diva_init(struct pci_dev *dev)
163 {
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186 }
187
188 /*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192 static int
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
196 {
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
217 return setup_port(priv, port, bar, offset, board->reg_shift);
218 }
219
220 /*
221 * Added for EKF Intel i960 serial boards
222 */
223 static int pci_inteli960ni_init(struct pci_dev *dev)
224 {
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237 }
238
239 /*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
245 static int pci_plx9050_init(struct pci_dev *dev)
246 {
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258 irq_config = 0x43;
259
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 /*
272 * enable/disable interrupts
273 */
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286 }
287
288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289 {
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308 }
309
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
312
313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314 {
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334 }
335
336
337 /* MITE registers */
338 #define MITE_IOWBSR1 0xc4
339 #define MITE_IOWCR1 0xf4
340 #define MITE_LCIMR1 0x08
341 #define MITE_LCIMR2 0x10
342
343 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346 {
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365 }
366
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368 static int
369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_port *port, int idx)
371 {
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386 }
387
388 /*
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
393 */
394
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
397
398 static int sbs_init(struct pci_dev *dev)
399 {
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416 }
417
418 /*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422 static void __devexit sbs_exit(struct pci_dev *dev)
423 {
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
429 writeb(0, p + OCT_REG_CR_OFF);
430 iounmap(p);
431 }
432
433 /*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
445 *
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
463 static int pci_siig10x_init(struct pci_dev *dev)
464 {
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488 }
489
490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
493 static int pci_siig20x_init(struct pci_dev *dev)
494 {
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508 }
509
510 static int pci_siig_init(struct pci_dev *dev)
511 {
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521 }
522
523 static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_port *port, int idx)
526 {
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535 }
536
537 /*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
542 static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544 };
545
546 static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552 };
553
554 static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559 };
560
561 static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564 };
565
566 static const struct timedia_struct {
567 int num;
568 const unsigned short *ids;
569 } timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
574 };
575
576 static int pci_timedia_init(struct pci_dev *dev)
577 {
578 const unsigned short *ids;
579 int i, j;
580
581 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
582 ids = timedia_data[i].ids;
583 for (j = 0; ids[j]; j++)
584 if (dev->subsystem_device == ids[j])
585 return timedia_data[i].num;
586 }
587 return 0;
588 }
589
590 /*
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
593 */
594 static int
595 pci_timedia_setup(struct serial_private *priv,
596 const struct pciserial_board *board,
597 struct uart_port *port, int idx)
598 {
599 unsigned int bar = 0, offset = board->first_offset;
600
601 switch (idx) {
602 case 0:
603 bar = 0;
604 break;
605 case 1:
606 offset = board->uart_offset;
607 bar = 0;
608 break;
609 case 2:
610 bar = 1;
611 break;
612 case 3:
613 offset = board->uart_offset;
614 /* FALLTHROUGH */
615 case 4: /* BAR 2 */
616 case 5: /* BAR 3 */
617 case 6: /* BAR 4 */
618 case 7: /* BAR 5 */
619 bar = idx - 2;
620 }
621
622 return setup_port(priv, port, bar, offset, board->reg_shift);
623 }
624
625 /*
626 * Some Titan cards are also a little weird
627 */
628 static int
629 titan_400l_800l_setup(struct serial_private *priv,
630 const struct pciserial_board *board,
631 struct uart_port *port, int idx)
632 {
633 unsigned int bar, offset = board->first_offset;
634
635 switch (idx) {
636 case 0:
637 bar = 1;
638 break;
639 case 1:
640 bar = 2;
641 break;
642 default:
643 bar = 4;
644 offset = (idx - 2) * board->uart_offset;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 static int pci_xircom_init(struct pci_dev *dev)
651 {
652 msleep(100);
653 return 0;
654 }
655
656 static int pci_ni8420_init(struct pci_dev *dev)
657 {
658 void __iomem *p;
659 unsigned long base, len;
660 unsigned int bar = 0;
661
662 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
663 moan_device("no memory in bar", dev);
664 return 0;
665 }
666
667 base = pci_resource_start(dev, bar);
668 len = pci_resource_len(dev, bar);
669 p = ioremap_nocache(base, len);
670 if (p == NULL)
671 return -ENOMEM;
672
673 /* Enable CPU Interrupt */
674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
675 p + NI8420_INT_ENABLE_REG);
676
677 iounmap(p);
678 return 0;
679 }
680
681 #define MITE_IOWBSR1_WSIZE 0xa
682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
683 #define MITE_IOWBSR1_WENAB (1 << 7)
684 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
687
688 static int pci_ni8430_init(struct pci_dev *dev)
689 {
690 void __iomem *p;
691 unsigned long base, len;
692 u32 device_window;
693 unsigned int bar = 0;
694
695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
696 moan_device("no memory in bar", dev);
697 return 0;
698 }
699
700 base = pci_resource_start(dev, bar);
701 len = pci_resource_len(dev, bar);
702 p = ioremap_nocache(base, len);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /* Set device window address and size in BAR0 */
707 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
709 writel(device_window, p + MITE_IOWBSR1);
710
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
713 p + MITE_IOWCR1);
714
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
717
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
720
721 iounmap(p);
722 return 0;
723 }
724
725 /* UART Port Control Register */
726 #define NI8430_PORTCON 0x0f
727 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
728
729 static int
730 pci_ni8430_setup(struct serial_private *priv,
731 const struct pciserial_board *board,
732 struct uart_port *port, int idx)
733 {
734 void __iomem *p;
735 unsigned long base, len;
736 unsigned int bar, offset = board->first_offset;
737
738 if (idx >= board->num_ports)
739 return 1;
740
741 bar = FL_GET_BASE(board->flags);
742 offset += idx * board->uart_offset;
743
744 base = pci_resource_start(priv->dev, bar);
745 len = pci_resource_len(priv->dev, bar);
746 p = ioremap_nocache(base, len);
747
748 /* enable the transciever */
749 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
750 p + offset + NI8430_PORTCON);
751
752 iounmap(p);
753
754 return setup_port(priv, port, bar, offset, board->reg_shift);
755 }
756
757
758 static int pci_netmos_init(struct pci_dev *dev)
759 {
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial = dev->subsystem_device & 0xf;
762
763 if (dev->device == PCI_DEVICE_ID_NETMOS_9901)
764 return 0;
765 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
766 dev->subsystem_device == 0x0299)
767 return 0;
768
769 if (num_serial == 0)
770 return -ENODEV;
771 return num_serial;
772 }
773
774 /*
775 * These chips are available with optionally one parallel port and up to
776 * two serial ports. Unfortunately they all have the same product id.
777 *
778 * Basic configuration is done over a region of 32 I/O ports. The base
779 * ioport is called INTA or INTC, depending on docs/other drivers.
780 *
781 * The region of the 32 I/O ports is configured in POSIO0R...
782 */
783
784 /* registers */
785 #define ITE_887x_MISCR 0x9c
786 #define ITE_887x_INTCBAR 0x78
787 #define ITE_887x_UARTBAR 0x7c
788 #define ITE_887x_PS0BAR 0x10
789 #define ITE_887x_POSIO0 0x60
790
791 /* I/O space size */
792 #define ITE_887x_IOSIZE 32
793 /* I/O space size (bits 26-24; 8 bytes = 011b) */
794 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
795 /* I/O space size (bits 26-24; 32 bytes = 101b) */
796 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
797 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
798 #define ITE_887x_POSIO_SPEED (3 << 29)
799 /* enable IO_Space bit */
800 #define ITE_887x_POSIO_ENABLE (1 << 31)
801
802 static int pci_ite887x_init(struct pci_dev *dev)
803 {
804 /* inta_addr are the configuration addresses of the ITE */
805 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
806 0x200, 0x280, 0 };
807 int ret, i, type;
808 struct resource *iobase = NULL;
809 u32 miscr, uartbar, ioport;
810
811 /* search for the base-ioport */
812 i = 0;
813 while (inta_addr[i] && iobase == NULL) {
814 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
815 "ite887x");
816 if (iobase != NULL) {
817 /* write POSIO0R - speed | size | ioport */
818 pci_write_config_dword(dev, ITE_887x_POSIO0,
819 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
820 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
821 /* write INTCBAR - ioport */
822 pci_write_config_dword(dev, ITE_887x_INTCBAR,
823 inta_addr[i]);
824 ret = inb(inta_addr[i]);
825 if (ret != 0xff) {
826 /* ioport connected */
827 break;
828 }
829 release_region(iobase->start, ITE_887x_IOSIZE);
830 iobase = NULL;
831 }
832 i++;
833 }
834
835 if (!inta_addr[i]) {
836 printk(KERN_ERR "ite887x: could not find iobase\n");
837 return -ENODEV;
838 }
839
840 /* start of undocumented type checking (see parport_pc.c) */
841 type = inb(iobase->start + 0x18) & 0x0f;
842
843 switch (type) {
844 case 0x2: /* ITE8871 (1P) */
845 case 0xa: /* ITE8875 (1P) */
846 ret = 0;
847 break;
848 case 0xe: /* ITE8872 (2S1P) */
849 ret = 2;
850 break;
851 case 0x6: /* ITE8873 (1S) */
852 ret = 1;
853 break;
854 case 0x8: /* ITE8874 (2S) */
855 ret = 2;
856 break;
857 default:
858 moan_device("Unknown ITE887x", dev);
859 ret = -ENODEV;
860 }
861
862 /* configure all serial ports */
863 for (i = 0; i < ret; i++) {
864 /* read the I/O port from the device */
865 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
866 &ioport);
867 ioport &= 0x0000FF00; /* the actual base address */
868 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
869 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
870 ITE_887x_POSIO_IOSIZE_8 | ioport);
871
872 /* write the ioport to the UARTBAR */
873 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
874 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
875 uartbar |= (ioport << (16 * i)); /* set the ioport */
876 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
877
878 /* get current config */
879 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
880 /* disable interrupts (UARTx_Routing[3:0]) */
881 miscr &= ~(0xf << (12 - 4 * i));
882 /* activate the UART (UARTx_En) */
883 miscr |= 1 << (23 - i);
884 /* write new config with activated UART */
885 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
886 }
887
888 if (ret <= 0) {
889 /* the device has no UARTs if we get here */
890 release_region(iobase->start, ITE_887x_IOSIZE);
891 }
892
893 return ret;
894 }
895
896 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
897 {
898 u32 ioport;
899 /* the ioport is bit 0-15 in POSIO0R */
900 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
901 ioport &= 0xffff;
902 release_region(ioport, ITE_887x_IOSIZE);
903 }
904
905 /*
906 * Oxford Semiconductor Inc.
907 * Check that device is part of the Tornado range of devices, then determine
908 * the number of ports available on the device.
909 */
910 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
911 {
912 u8 __iomem *p;
913 unsigned long deviceID;
914 unsigned int number_uarts = 0;
915
916 /* OxSemi Tornado devices are all 0xCxxx */
917 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
918 (dev->device & 0xF000) != 0xC000)
919 return 0;
920
921 p = pci_iomap(dev, 0, 5);
922 if (p == NULL)
923 return -ENOMEM;
924
925 deviceID = ioread32(p);
926 /* Tornado device */
927 if (deviceID == 0x07000200) {
928 number_uarts = ioread8(p + 4);
929 printk(KERN_DEBUG
930 "%d ports detected on Oxford PCI Express device\n",
931 number_uarts);
932 }
933 pci_iounmap(dev, p);
934 return number_uarts;
935 }
936
937 static int
938 pci_default_setup(struct serial_private *priv,
939 const struct pciserial_board *board,
940 struct uart_port *port, int idx)
941 {
942 unsigned int bar, offset = board->first_offset, maxnr;
943
944 bar = FL_GET_BASE(board->flags);
945 if (board->flags & FL_BASE_BARS)
946 bar += idx;
947 else
948 offset += idx * board->uart_offset;
949
950 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
951 (board->reg_shift + 3);
952
953 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
954 return 1;
955
956 return setup_port(priv, port, bar, offset, board->reg_shift);
957 }
958
959 static int skip_tx_en_setup(struct serial_private *priv,
960 const struct pciserial_board *board,
961 struct uart_port *port, int idx)
962 {
963 port->flags |= UPF_NO_TXEN_TEST;
964 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
965 "[%04x:%04x] subsystem [%04x:%04x]\n",
966 priv->dev->vendor,
967 priv->dev->device,
968 priv->dev->subsystem_vendor,
969 priv->dev->subsystem_device);
970
971 return pci_default_setup(priv, board, port, idx);
972 }
973
974 /* This should be in linux/pci_ids.h */
975 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
976 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
977 #define PCI_DEVICE_ID_OCTPRO 0x0001
978 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
979 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
980 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
981 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
982 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
983 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
984
985 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
986 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
987
988 /*
989 * Master list of serial port init/setup/exit quirks.
990 * This does not describe the general nature of the port.
991 * (ie, baud base, number and location of ports, etc)
992 *
993 * This list is ordered alphabetically by vendor then device.
994 * Specific entries must come before more generic entries.
995 */
996 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
997 /*
998 * ADDI-DATA GmbH communication cards <info@addi-data.com>
999 */
1000 {
1001 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1002 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1003 .subvendor = PCI_ANY_ID,
1004 .subdevice = PCI_ANY_ID,
1005 .setup = addidata_apci7800_setup,
1006 },
1007 /*
1008 * AFAVLAB cards - these may be called via parport_serial
1009 * It is not clear whether this applies to all products.
1010 */
1011 {
1012 .vendor = PCI_VENDOR_ID_AFAVLAB,
1013 .device = PCI_ANY_ID,
1014 .subvendor = PCI_ANY_ID,
1015 .subdevice = PCI_ANY_ID,
1016 .setup = afavlab_setup,
1017 },
1018 /*
1019 * HP Diva
1020 */
1021 {
1022 .vendor = PCI_VENDOR_ID_HP,
1023 .device = PCI_DEVICE_ID_HP_DIVA,
1024 .subvendor = PCI_ANY_ID,
1025 .subdevice = PCI_ANY_ID,
1026 .init = pci_hp_diva_init,
1027 .setup = pci_hp_diva_setup,
1028 },
1029 /*
1030 * Intel
1031 */
1032 {
1033 .vendor = PCI_VENDOR_ID_INTEL,
1034 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1035 .subvendor = 0xe4bf,
1036 .subdevice = PCI_ANY_ID,
1037 .init = pci_inteli960ni_init,
1038 .setup = pci_default_setup,
1039 },
1040 {
1041 .vendor = PCI_VENDOR_ID_INTEL,
1042 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1043 .subvendor = PCI_ANY_ID,
1044 .subdevice = PCI_ANY_ID,
1045 .setup = skip_tx_en_setup,
1046 },
1047 {
1048 .vendor = PCI_VENDOR_ID_INTEL,
1049 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1050 .subvendor = PCI_ANY_ID,
1051 .subdevice = PCI_ANY_ID,
1052 .setup = skip_tx_en_setup,
1053 },
1054 {
1055 .vendor = PCI_VENDOR_ID_INTEL,
1056 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1057 .subvendor = PCI_ANY_ID,
1058 .subdevice = PCI_ANY_ID,
1059 .setup = skip_tx_en_setup,
1060 },
1061 /*
1062 * ITE
1063 */
1064 {
1065 .vendor = PCI_VENDOR_ID_ITE,
1066 .device = PCI_DEVICE_ID_ITE_8872,
1067 .subvendor = PCI_ANY_ID,
1068 .subdevice = PCI_ANY_ID,
1069 .init = pci_ite887x_init,
1070 .setup = pci_default_setup,
1071 .exit = __devexit_p(pci_ite887x_exit),
1072 },
1073 /*
1074 * National Instruments
1075 */
1076 {
1077 .vendor = PCI_VENDOR_ID_NI,
1078 .device = PCI_DEVICE_ID_NI_PCI23216,
1079 .subvendor = PCI_ANY_ID,
1080 .subdevice = PCI_ANY_ID,
1081 .init = pci_ni8420_init,
1082 .setup = pci_default_setup,
1083 .exit = __devexit_p(pci_ni8420_exit),
1084 },
1085 {
1086 .vendor = PCI_VENDOR_ID_NI,
1087 .device = PCI_DEVICE_ID_NI_PCI2328,
1088 .subvendor = PCI_ANY_ID,
1089 .subdevice = PCI_ANY_ID,
1090 .init = pci_ni8420_init,
1091 .setup = pci_default_setup,
1092 .exit = __devexit_p(pci_ni8420_exit),
1093 },
1094 {
1095 .vendor = PCI_VENDOR_ID_NI,
1096 .device = PCI_DEVICE_ID_NI_PCI2324,
1097 .subvendor = PCI_ANY_ID,
1098 .subdevice = PCI_ANY_ID,
1099 .init = pci_ni8420_init,
1100 .setup = pci_default_setup,
1101 .exit = __devexit_p(pci_ni8420_exit),
1102 },
1103 {
1104 .vendor = PCI_VENDOR_ID_NI,
1105 .device = PCI_DEVICE_ID_NI_PCI2322,
1106 .subvendor = PCI_ANY_ID,
1107 .subdevice = PCI_ANY_ID,
1108 .init = pci_ni8420_init,
1109 .setup = pci_default_setup,
1110 .exit = __devexit_p(pci_ni8420_exit),
1111 },
1112 {
1113 .vendor = PCI_VENDOR_ID_NI,
1114 .device = PCI_DEVICE_ID_NI_PCI2324I,
1115 .subvendor = PCI_ANY_ID,
1116 .subdevice = PCI_ANY_ID,
1117 .init = pci_ni8420_init,
1118 .setup = pci_default_setup,
1119 .exit = __devexit_p(pci_ni8420_exit),
1120 },
1121 {
1122 .vendor = PCI_VENDOR_ID_NI,
1123 .device = PCI_DEVICE_ID_NI_PCI2322I,
1124 .subvendor = PCI_ANY_ID,
1125 .subdevice = PCI_ANY_ID,
1126 .init = pci_ni8420_init,
1127 .setup = pci_default_setup,
1128 .exit = __devexit_p(pci_ni8420_exit),
1129 },
1130 {
1131 .vendor = PCI_VENDOR_ID_NI,
1132 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1133 .subvendor = PCI_ANY_ID,
1134 .subdevice = PCI_ANY_ID,
1135 .init = pci_ni8420_init,
1136 .setup = pci_default_setup,
1137 .exit = __devexit_p(pci_ni8420_exit),
1138 },
1139 {
1140 .vendor = PCI_VENDOR_ID_NI,
1141 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1142 .subvendor = PCI_ANY_ID,
1143 .subdevice = PCI_ANY_ID,
1144 .init = pci_ni8420_init,
1145 .setup = pci_default_setup,
1146 .exit = __devexit_p(pci_ni8420_exit),
1147 },
1148 {
1149 .vendor = PCI_VENDOR_ID_NI,
1150 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1151 .subvendor = PCI_ANY_ID,
1152 .subdevice = PCI_ANY_ID,
1153 .init = pci_ni8420_init,
1154 .setup = pci_default_setup,
1155 .exit = __devexit_p(pci_ni8420_exit),
1156 },
1157 {
1158 .vendor = PCI_VENDOR_ID_NI,
1159 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1160 .subvendor = PCI_ANY_ID,
1161 .subdevice = PCI_ANY_ID,
1162 .init = pci_ni8420_init,
1163 .setup = pci_default_setup,
1164 .exit = __devexit_p(pci_ni8420_exit),
1165 },
1166 {
1167 .vendor = PCI_VENDOR_ID_NI,
1168 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .init = pci_ni8420_init,
1172 .setup = pci_default_setup,
1173 .exit = __devexit_p(pci_ni8420_exit),
1174 },
1175 {
1176 .vendor = PCI_VENDOR_ID_NI,
1177 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1178 .subvendor = PCI_ANY_ID,
1179 .subdevice = PCI_ANY_ID,
1180 .init = pci_ni8420_init,
1181 .setup = pci_default_setup,
1182 .exit = __devexit_p(pci_ni8420_exit),
1183 },
1184 {
1185 .vendor = PCI_VENDOR_ID_NI,
1186 .device = PCI_ANY_ID,
1187 .subvendor = PCI_ANY_ID,
1188 .subdevice = PCI_ANY_ID,
1189 .init = pci_ni8430_init,
1190 .setup = pci_ni8430_setup,
1191 .exit = __devexit_p(pci_ni8430_exit),
1192 },
1193 /*
1194 * Panacom
1195 */
1196 {
1197 .vendor = PCI_VENDOR_ID_PANACOM,
1198 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1199 .subvendor = PCI_ANY_ID,
1200 .subdevice = PCI_ANY_ID,
1201 .init = pci_plx9050_init,
1202 .setup = pci_default_setup,
1203 .exit = __devexit_p(pci_plx9050_exit),
1204 },
1205 {
1206 .vendor = PCI_VENDOR_ID_PANACOM,
1207 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1208 .subvendor = PCI_ANY_ID,
1209 .subdevice = PCI_ANY_ID,
1210 .init = pci_plx9050_init,
1211 .setup = pci_default_setup,
1212 .exit = __devexit_p(pci_plx9050_exit),
1213 },
1214 /*
1215 * PLX
1216 */
1217 {
1218 .vendor = PCI_VENDOR_ID_PLX,
1219 .device = PCI_DEVICE_ID_PLX_9030,
1220 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1221 .subdevice = PCI_ANY_ID,
1222 .setup = pci_default_setup,
1223 },
1224 {
1225 .vendor = PCI_VENDOR_ID_PLX,
1226 .device = PCI_DEVICE_ID_PLX_9050,
1227 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1228 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1229 .init = pci_plx9050_init,
1230 .setup = pci_default_setup,
1231 .exit = __devexit_p(pci_plx9050_exit),
1232 },
1233 {
1234 .vendor = PCI_VENDOR_ID_PLX,
1235 .device = PCI_DEVICE_ID_PLX_9050,
1236 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1237 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1238 .init = pci_plx9050_init,
1239 .setup = pci_default_setup,
1240 .exit = __devexit_p(pci_plx9050_exit),
1241 },
1242 {
1243 .vendor = PCI_VENDOR_ID_PLX,
1244 .device = PCI_DEVICE_ID_PLX_9050,
1245 .subvendor = PCI_VENDOR_ID_PLX,
1246 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1247 .init = pci_plx9050_init,
1248 .setup = pci_default_setup,
1249 .exit = __devexit_p(pci_plx9050_exit),
1250 },
1251 {
1252 .vendor = PCI_VENDOR_ID_PLX,
1253 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1254 .subvendor = PCI_VENDOR_ID_PLX,
1255 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1256 .init = pci_plx9050_init,
1257 .setup = pci_default_setup,
1258 .exit = __devexit_p(pci_plx9050_exit),
1259 },
1260 /*
1261 * SBS Technologies, Inc., PMC-OCTALPRO 232
1262 */
1263 {
1264 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1265 .device = PCI_DEVICE_ID_OCTPRO,
1266 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1267 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1268 .init = sbs_init,
1269 .setup = sbs_setup,
1270 .exit = __devexit_p(sbs_exit),
1271 },
1272 /*
1273 * SBS Technologies, Inc., PMC-OCTALPRO 422
1274 */
1275 {
1276 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1277 .device = PCI_DEVICE_ID_OCTPRO,
1278 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1279 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1280 .init = sbs_init,
1281 .setup = sbs_setup,
1282 .exit = __devexit_p(sbs_exit),
1283 },
1284 /*
1285 * SBS Technologies, Inc., P-Octal 232
1286 */
1287 {
1288 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1289 .device = PCI_DEVICE_ID_OCTPRO,
1290 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1291 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1292 .init = sbs_init,
1293 .setup = sbs_setup,
1294 .exit = __devexit_p(sbs_exit),
1295 },
1296 /*
1297 * SBS Technologies, Inc., P-Octal 422
1298 */
1299 {
1300 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1301 .device = PCI_DEVICE_ID_OCTPRO,
1302 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1303 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1304 .init = sbs_init,
1305 .setup = sbs_setup,
1306 .exit = __devexit_p(sbs_exit),
1307 },
1308 /*
1309 * SIIG cards - these may be called via parport_serial
1310 */
1311 {
1312 .vendor = PCI_VENDOR_ID_SIIG,
1313 .device = PCI_ANY_ID,
1314 .subvendor = PCI_ANY_ID,
1315 .subdevice = PCI_ANY_ID,
1316 .init = pci_siig_init,
1317 .setup = pci_siig_setup,
1318 },
1319 /*
1320 * Titan cards
1321 */
1322 {
1323 .vendor = PCI_VENDOR_ID_TITAN,
1324 .device = PCI_DEVICE_ID_TITAN_400L,
1325 .subvendor = PCI_ANY_ID,
1326 .subdevice = PCI_ANY_ID,
1327 .setup = titan_400l_800l_setup,
1328 },
1329 {
1330 .vendor = PCI_VENDOR_ID_TITAN,
1331 .device = PCI_DEVICE_ID_TITAN_800L,
1332 .subvendor = PCI_ANY_ID,
1333 .subdevice = PCI_ANY_ID,
1334 .setup = titan_400l_800l_setup,
1335 },
1336 /*
1337 * Timedia cards
1338 */
1339 {
1340 .vendor = PCI_VENDOR_ID_TIMEDIA,
1341 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1342 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1343 .subdevice = PCI_ANY_ID,
1344 .init = pci_timedia_init,
1345 .setup = pci_timedia_setup,
1346 },
1347 {
1348 .vendor = PCI_VENDOR_ID_TIMEDIA,
1349 .device = PCI_ANY_ID,
1350 .subvendor = PCI_ANY_ID,
1351 .subdevice = PCI_ANY_ID,
1352 .setup = pci_timedia_setup,
1353 },
1354 /*
1355 * Xircom cards
1356 */
1357 {
1358 .vendor = PCI_VENDOR_ID_XIRCOM,
1359 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1360 .subvendor = PCI_ANY_ID,
1361 .subdevice = PCI_ANY_ID,
1362 .init = pci_xircom_init,
1363 .setup = pci_default_setup,
1364 },
1365 /*
1366 * Netmos cards - these may be called via parport_serial
1367 */
1368 {
1369 .vendor = PCI_VENDOR_ID_NETMOS,
1370 .device = PCI_ANY_ID,
1371 .subvendor = PCI_ANY_ID,
1372 .subdevice = PCI_ANY_ID,
1373 .init = pci_netmos_init,
1374 .setup = pci_default_setup,
1375 },
1376 /*
1377 * For Oxford Semiconductor and Mainpine
1378 */
1379 {
1380 .vendor = PCI_VENDOR_ID_OXSEMI,
1381 .device = PCI_ANY_ID,
1382 .subvendor = PCI_ANY_ID,
1383 .subdevice = PCI_ANY_ID,
1384 .init = pci_oxsemi_tornado_init,
1385 .setup = pci_default_setup,
1386 },
1387 {
1388 .vendor = PCI_VENDOR_ID_MAINPINE,
1389 .device = PCI_ANY_ID,
1390 .subvendor = PCI_ANY_ID,
1391 .subdevice = PCI_ANY_ID,
1392 .init = pci_oxsemi_tornado_init,
1393 .setup = pci_default_setup,
1394 },
1395 /*
1396 * Default "match everything" terminator entry
1397 */
1398 {
1399 .vendor = PCI_ANY_ID,
1400 .device = PCI_ANY_ID,
1401 .subvendor = PCI_ANY_ID,
1402 .subdevice = PCI_ANY_ID,
1403 .setup = pci_default_setup,
1404 }
1405 };
1406
1407 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1408 {
1409 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1410 }
1411
1412 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1413 {
1414 struct pci_serial_quirk *quirk;
1415
1416 for (quirk = pci_serial_quirks; ; quirk++)
1417 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1418 quirk_id_matches(quirk->device, dev->device) &&
1419 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1420 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1421 break;
1422 return quirk;
1423 }
1424
1425 static inline int get_pci_irq(struct pci_dev *dev,
1426 const struct pciserial_board *board)
1427 {
1428 if (board->flags & FL_NOIRQ)
1429 return 0;
1430 else
1431 return dev->irq;
1432 }
1433
1434 /*
1435 * This is the configuration table for all of the PCI serial boards
1436 * which we support. It is directly indexed by the pci_board_num_t enum
1437 * value, which is encoded in the pci_device_id PCI probe table's
1438 * driver_data member.
1439 *
1440 * The makeup of these names are:
1441 * pbn_bn{_bt}_n_baud{_offsetinhex}
1442 *
1443 * bn = PCI BAR number
1444 * bt = Index using PCI BARs
1445 * n = number of serial ports
1446 * baud = baud rate
1447 * offsetinhex = offset for each sequential port (in hex)
1448 *
1449 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1450 *
1451 * Please note: in theory if n = 1, _bt infix should make no difference.
1452 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1453 */
1454 enum pci_board_num_t {
1455 pbn_default = 0,
1456
1457 pbn_b0_1_115200,
1458 pbn_b0_2_115200,
1459 pbn_b0_4_115200,
1460 pbn_b0_5_115200,
1461 pbn_b0_8_115200,
1462
1463 pbn_b0_1_921600,
1464 pbn_b0_2_921600,
1465 pbn_b0_4_921600,
1466
1467 pbn_b0_2_1130000,
1468
1469 pbn_b0_4_1152000,
1470
1471 pbn_b0_2_1843200,
1472 pbn_b0_4_1843200,
1473
1474 pbn_b0_2_1843200_200,
1475 pbn_b0_4_1843200_200,
1476 pbn_b0_8_1843200_200,
1477
1478 pbn_b0_1_4000000,
1479
1480 pbn_b0_bt_1_115200,
1481 pbn_b0_bt_2_115200,
1482 pbn_b0_bt_8_115200,
1483
1484 pbn_b0_bt_1_460800,
1485 pbn_b0_bt_2_460800,
1486 pbn_b0_bt_4_460800,
1487
1488 pbn_b0_bt_1_921600,
1489 pbn_b0_bt_2_921600,
1490 pbn_b0_bt_4_921600,
1491 pbn_b0_bt_8_921600,
1492
1493 pbn_b1_1_115200,
1494 pbn_b1_2_115200,
1495 pbn_b1_4_115200,
1496 pbn_b1_8_115200,
1497 pbn_b1_16_115200,
1498
1499 pbn_b1_1_921600,
1500 pbn_b1_2_921600,
1501 pbn_b1_4_921600,
1502 pbn_b1_8_921600,
1503
1504 pbn_b1_2_1250000,
1505
1506 pbn_b1_bt_1_115200,
1507 pbn_b1_bt_2_115200,
1508 pbn_b1_bt_4_115200,
1509
1510 pbn_b1_bt_2_921600,
1511
1512 pbn_b1_1_1382400,
1513 pbn_b1_2_1382400,
1514 pbn_b1_4_1382400,
1515 pbn_b1_8_1382400,
1516
1517 pbn_b2_1_115200,
1518 pbn_b2_2_115200,
1519 pbn_b2_4_115200,
1520 pbn_b2_8_115200,
1521
1522 pbn_b2_1_460800,
1523 pbn_b2_4_460800,
1524 pbn_b2_8_460800,
1525 pbn_b2_16_460800,
1526
1527 pbn_b2_1_921600,
1528 pbn_b2_4_921600,
1529 pbn_b2_8_921600,
1530
1531 pbn_b2_bt_1_115200,
1532 pbn_b2_bt_2_115200,
1533 pbn_b2_bt_4_115200,
1534
1535 pbn_b2_bt_2_921600,
1536 pbn_b2_bt_4_921600,
1537
1538 pbn_b3_2_115200,
1539 pbn_b3_4_115200,
1540 pbn_b3_8_115200,
1541
1542 /*
1543 * Board-specific versions.
1544 */
1545 pbn_panacom,
1546 pbn_panacom2,
1547 pbn_panacom4,
1548 pbn_exsys_4055,
1549 pbn_plx_romulus,
1550 pbn_oxsemi,
1551 pbn_oxsemi_1_4000000,
1552 pbn_oxsemi_2_4000000,
1553 pbn_oxsemi_4_4000000,
1554 pbn_oxsemi_8_4000000,
1555 pbn_intel_i960,
1556 pbn_sgi_ioc3,
1557 pbn_computone_4,
1558 pbn_computone_6,
1559 pbn_computone_8,
1560 pbn_sbsxrsio,
1561 pbn_exar_XR17C152,
1562 pbn_exar_XR17C154,
1563 pbn_exar_XR17C158,
1564 pbn_exar_ibm_saturn,
1565 pbn_pasemi_1682M,
1566 pbn_ni8430_2,
1567 pbn_ni8430_4,
1568 pbn_ni8430_8,
1569 pbn_ni8430_16,
1570 pbn_ADDIDATA_PCIe_1_3906250,
1571 pbn_ADDIDATA_PCIe_2_3906250,
1572 pbn_ADDIDATA_PCIe_4_3906250,
1573 pbn_ADDIDATA_PCIe_8_3906250,
1574 };
1575
1576 /*
1577 * uart_offset - the space between channels
1578 * reg_shift - describes how the UART registers are mapped
1579 * to PCI memory by the card.
1580 * For example IER register on SBS, Inc. PMC-OctPro is located at
1581 * offset 0x10 from the UART base, while UART_IER is defined as 1
1582 * in include/linux/serial_reg.h,
1583 * see first lines of serial_in() and serial_out() in 8250.c
1584 */
1585
1586 static struct pciserial_board pci_boards[] __devinitdata = {
1587 [pbn_default] = {
1588 .flags = FL_BASE0,
1589 .num_ports = 1,
1590 .base_baud = 115200,
1591 .uart_offset = 8,
1592 },
1593 [pbn_b0_1_115200] = {
1594 .flags = FL_BASE0,
1595 .num_ports = 1,
1596 .base_baud = 115200,
1597 .uart_offset = 8,
1598 },
1599 [pbn_b0_2_115200] = {
1600 .flags = FL_BASE0,
1601 .num_ports = 2,
1602 .base_baud = 115200,
1603 .uart_offset = 8,
1604 },
1605 [pbn_b0_4_115200] = {
1606 .flags = FL_BASE0,
1607 .num_ports = 4,
1608 .base_baud = 115200,
1609 .uart_offset = 8,
1610 },
1611 [pbn_b0_5_115200] = {
1612 .flags = FL_BASE0,
1613 .num_ports = 5,
1614 .base_baud = 115200,
1615 .uart_offset = 8,
1616 },
1617 [pbn_b0_8_115200] = {
1618 .flags = FL_BASE0,
1619 .num_ports = 8,
1620 .base_baud = 115200,
1621 .uart_offset = 8,
1622 },
1623 [pbn_b0_1_921600] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 1,
1626 .base_baud = 921600,
1627 .uart_offset = 8,
1628 },
1629 [pbn_b0_2_921600] = {
1630 .flags = FL_BASE0,
1631 .num_ports = 2,
1632 .base_baud = 921600,
1633 .uart_offset = 8,
1634 },
1635 [pbn_b0_4_921600] = {
1636 .flags = FL_BASE0,
1637 .num_ports = 4,
1638 .base_baud = 921600,
1639 .uart_offset = 8,
1640 },
1641
1642 [pbn_b0_2_1130000] = {
1643 .flags = FL_BASE0,
1644 .num_ports = 2,
1645 .base_baud = 1130000,
1646 .uart_offset = 8,
1647 },
1648
1649 [pbn_b0_4_1152000] = {
1650 .flags = FL_BASE0,
1651 .num_ports = 4,
1652 .base_baud = 1152000,
1653 .uart_offset = 8,
1654 },
1655
1656 [pbn_b0_2_1843200] = {
1657 .flags = FL_BASE0,
1658 .num_ports = 2,
1659 .base_baud = 1843200,
1660 .uart_offset = 8,
1661 },
1662 [pbn_b0_4_1843200] = {
1663 .flags = FL_BASE0,
1664 .num_ports = 4,
1665 .base_baud = 1843200,
1666 .uart_offset = 8,
1667 },
1668
1669 [pbn_b0_2_1843200_200] = {
1670 .flags = FL_BASE0,
1671 .num_ports = 2,
1672 .base_baud = 1843200,
1673 .uart_offset = 0x200,
1674 },
1675 [pbn_b0_4_1843200_200] = {
1676 .flags = FL_BASE0,
1677 .num_ports = 4,
1678 .base_baud = 1843200,
1679 .uart_offset = 0x200,
1680 },
1681 [pbn_b0_8_1843200_200] = {
1682 .flags = FL_BASE0,
1683 .num_ports = 8,
1684 .base_baud = 1843200,
1685 .uart_offset = 0x200,
1686 },
1687 [pbn_b0_1_4000000] = {
1688 .flags = FL_BASE0,
1689 .num_ports = 1,
1690 .base_baud = 4000000,
1691 .uart_offset = 8,
1692 },
1693
1694 [pbn_b0_bt_1_115200] = {
1695 .flags = FL_BASE0|FL_BASE_BARS,
1696 .num_ports = 1,
1697 .base_baud = 115200,
1698 .uart_offset = 8,
1699 },
1700 [pbn_b0_bt_2_115200] = {
1701 .flags = FL_BASE0|FL_BASE_BARS,
1702 .num_ports = 2,
1703 .base_baud = 115200,
1704 .uart_offset = 8,
1705 },
1706 [pbn_b0_bt_8_115200] = {
1707 .flags = FL_BASE0|FL_BASE_BARS,
1708 .num_ports = 8,
1709 .base_baud = 115200,
1710 .uart_offset = 8,
1711 },
1712
1713 [pbn_b0_bt_1_460800] = {
1714 .flags = FL_BASE0|FL_BASE_BARS,
1715 .num_ports = 1,
1716 .base_baud = 460800,
1717 .uart_offset = 8,
1718 },
1719 [pbn_b0_bt_2_460800] = {
1720 .flags = FL_BASE0|FL_BASE_BARS,
1721 .num_ports = 2,
1722 .base_baud = 460800,
1723 .uart_offset = 8,
1724 },
1725 [pbn_b0_bt_4_460800] = {
1726 .flags = FL_BASE0|FL_BASE_BARS,
1727 .num_ports = 4,
1728 .base_baud = 460800,
1729 .uart_offset = 8,
1730 },
1731
1732 [pbn_b0_bt_1_921600] = {
1733 .flags = FL_BASE0|FL_BASE_BARS,
1734 .num_ports = 1,
1735 .base_baud = 921600,
1736 .uart_offset = 8,
1737 },
1738 [pbn_b0_bt_2_921600] = {
1739 .flags = FL_BASE0|FL_BASE_BARS,
1740 .num_ports = 2,
1741 .base_baud = 921600,
1742 .uart_offset = 8,
1743 },
1744 [pbn_b0_bt_4_921600] = {
1745 .flags = FL_BASE0|FL_BASE_BARS,
1746 .num_ports = 4,
1747 .base_baud = 921600,
1748 .uart_offset = 8,
1749 },
1750 [pbn_b0_bt_8_921600] = {
1751 .flags = FL_BASE0|FL_BASE_BARS,
1752 .num_ports = 8,
1753 .base_baud = 921600,
1754 .uart_offset = 8,
1755 },
1756
1757 [pbn_b1_1_115200] = {
1758 .flags = FL_BASE1,
1759 .num_ports = 1,
1760 .base_baud = 115200,
1761 .uart_offset = 8,
1762 },
1763 [pbn_b1_2_115200] = {
1764 .flags = FL_BASE1,
1765 .num_ports = 2,
1766 .base_baud = 115200,
1767 .uart_offset = 8,
1768 },
1769 [pbn_b1_4_115200] = {
1770 .flags = FL_BASE1,
1771 .num_ports = 4,
1772 .base_baud = 115200,
1773 .uart_offset = 8,
1774 },
1775 [pbn_b1_8_115200] = {
1776 .flags = FL_BASE1,
1777 .num_ports = 8,
1778 .base_baud = 115200,
1779 .uart_offset = 8,
1780 },
1781 [pbn_b1_16_115200] = {
1782 .flags = FL_BASE1,
1783 .num_ports = 16,
1784 .base_baud = 115200,
1785 .uart_offset = 8,
1786 },
1787
1788 [pbn_b1_1_921600] = {
1789 .flags = FL_BASE1,
1790 .num_ports = 1,
1791 .base_baud = 921600,
1792 .uart_offset = 8,
1793 },
1794 [pbn_b1_2_921600] = {
1795 .flags = FL_BASE1,
1796 .num_ports = 2,
1797 .base_baud = 921600,
1798 .uart_offset = 8,
1799 },
1800 [pbn_b1_4_921600] = {
1801 .flags = FL_BASE1,
1802 .num_ports = 4,
1803 .base_baud = 921600,
1804 .uart_offset = 8,
1805 },
1806 [pbn_b1_8_921600] = {
1807 .flags = FL_BASE1,
1808 .num_ports = 8,
1809 .base_baud = 921600,
1810 .uart_offset = 8,
1811 },
1812 [pbn_b1_2_1250000] = {
1813 .flags = FL_BASE1,
1814 .num_ports = 2,
1815 .base_baud = 1250000,
1816 .uart_offset = 8,
1817 },
1818
1819 [pbn_b1_bt_1_115200] = {
1820 .flags = FL_BASE1|FL_BASE_BARS,
1821 .num_ports = 1,
1822 .base_baud = 115200,
1823 .uart_offset = 8,
1824 },
1825 [pbn_b1_bt_2_115200] = {
1826 .flags = FL_BASE1|FL_BASE_BARS,
1827 .num_ports = 2,
1828 .base_baud = 115200,
1829 .uart_offset = 8,
1830 },
1831 [pbn_b1_bt_4_115200] = {
1832 .flags = FL_BASE1|FL_BASE_BARS,
1833 .num_ports = 4,
1834 .base_baud = 115200,
1835 .uart_offset = 8,
1836 },
1837
1838 [pbn_b1_bt_2_921600] = {
1839 .flags = FL_BASE1|FL_BASE_BARS,
1840 .num_ports = 2,
1841 .base_baud = 921600,
1842 .uart_offset = 8,
1843 },
1844
1845 [pbn_b1_1_1382400] = {
1846 .flags = FL_BASE1,
1847 .num_ports = 1,
1848 .base_baud = 1382400,
1849 .uart_offset = 8,
1850 },
1851 [pbn_b1_2_1382400] = {
1852 .flags = FL_BASE1,
1853 .num_ports = 2,
1854 .base_baud = 1382400,
1855 .uart_offset = 8,
1856 },
1857 [pbn_b1_4_1382400] = {
1858 .flags = FL_BASE1,
1859 .num_ports = 4,
1860 .base_baud = 1382400,
1861 .uart_offset = 8,
1862 },
1863 [pbn_b1_8_1382400] = {
1864 .flags = FL_BASE1,
1865 .num_ports = 8,
1866 .base_baud = 1382400,
1867 .uart_offset = 8,
1868 },
1869
1870 [pbn_b2_1_115200] = {
1871 .flags = FL_BASE2,
1872 .num_ports = 1,
1873 .base_baud = 115200,
1874 .uart_offset = 8,
1875 },
1876 [pbn_b2_2_115200] = {
1877 .flags = FL_BASE2,
1878 .num_ports = 2,
1879 .base_baud = 115200,
1880 .uart_offset = 8,
1881 },
1882 [pbn_b2_4_115200] = {
1883 .flags = FL_BASE2,
1884 .num_ports = 4,
1885 .base_baud = 115200,
1886 .uart_offset = 8,
1887 },
1888 [pbn_b2_8_115200] = {
1889 .flags = FL_BASE2,
1890 .num_ports = 8,
1891 .base_baud = 115200,
1892 .uart_offset = 8,
1893 },
1894
1895 [pbn_b2_1_460800] = {
1896 .flags = FL_BASE2,
1897 .num_ports = 1,
1898 .base_baud = 460800,
1899 .uart_offset = 8,
1900 },
1901 [pbn_b2_4_460800] = {
1902 .flags = FL_BASE2,
1903 .num_ports = 4,
1904 .base_baud = 460800,
1905 .uart_offset = 8,
1906 },
1907 [pbn_b2_8_460800] = {
1908 .flags = FL_BASE2,
1909 .num_ports = 8,
1910 .base_baud = 460800,
1911 .uart_offset = 8,
1912 },
1913 [pbn_b2_16_460800] = {
1914 .flags = FL_BASE2,
1915 .num_ports = 16,
1916 .base_baud = 460800,
1917 .uart_offset = 8,
1918 },
1919
1920 [pbn_b2_1_921600] = {
1921 .flags = FL_BASE2,
1922 .num_ports = 1,
1923 .base_baud = 921600,
1924 .uart_offset = 8,
1925 },
1926 [pbn_b2_4_921600] = {
1927 .flags = FL_BASE2,
1928 .num_ports = 4,
1929 .base_baud = 921600,
1930 .uart_offset = 8,
1931 },
1932 [pbn_b2_8_921600] = {
1933 .flags = FL_BASE2,
1934 .num_ports = 8,
1935 .base_baud = 921600,
1936 .uart_offset = 8,
1937 },
1938
1939 [pbn_b2_bt_1_115200] = {
1940 .flags = FL_BASE2|FL_BASE_BARS,
1941 .num_ports = 1,
1942 .base_baud = 115200,
1943 .uart_offset = 8,
1944 },
1945 [pbn_b2_bt_2_115200] = {
1946 .flags = FL_BASE2|FL_BASE_BARS,
1947 .num_ports = 2,
1948 .base_baud = 115200,
1949 .uart_offset = 8,
1950 },
1951 [pbn_b2_bt_4_115200] = {
1952 .flags = FL_BASE2|FL_BASE_BARS,
1953 .num_ports = 4,
1954 .base_baud = 115200,
1955 .uart_offset = 8,
1956 },
1957
1958 [pbn_b2_bt_2_921600] = {
1959 .flags = FL_BASE2|FL_BASE_BARS,
1960 .num_ports = 2,
1961 .base_baud = 921600,
1962 .uart_offset = 8,
1963 },
1964 [pbn_b2_bt_4_921600] = {
1965 .flags = FL_BASE2|FL_BASE_BARS,
1966 .num_ports = 4,
1967 .base_baud = 921600,
1968 .uart_offset = 8,
1969 },
1970
1971 [pbn_b3_2_115200] = {
1972 .flags = FL_BASE3,
1973 .num_ports = 2,
1974 .base_baud = 115200,
1975 .uart_offset = 8,
1976 },
1977 [pbn_b3_4_115200] = {
1978 .flags = FL_BASE3,
1979 .num_ports = 4,
1980 .base_baud = 115200,
1981 .uart_offset = 8,
1982 },
1983 [pbn_b3_8_115200] = {
1984 .flags = FL_BASE3,
1985 .num_ports = 8,
1986 .base_baud = 115200,
1987 .uart_offset = 8,
1988 },
1989
1990 /*
1991 * Entries following this are board-specific.
1992 */
1993
1994 /*
1995 * Panacom - IOMEM
1996 */
1997 [pbn_panacom] = {
1998 .flags = FL_BASE2,
1999 .num_ports = 2,
2000 .base_baud = 921600,
2001 .uart_offset = 0x400,
2002 .reg_shift = 7,
2003 },
2004 [pbn_panacom2] = {
2005 .flags = FL_BASE2|FL_BASE_BARS,
2006 .num_ports = 2,
2007 .base_baud = 921600,
2008 .uart_offset = 0x400,
2009 .reg_shift = 7,
2010 },
2011 [pbn_panacom4] = {
2012 .flags = FL_BASE2|FL_BASE_BARS,
2013 .num_ports = 4,
2014 .base_baud = 921600,
2015 .uart_offset = 0x400,
2016 .reg_shift = 7,
2017 },
2018
2019 [pbn_exsys_4055] = {
2020 .flags = FL_BASE2,
2021 .num_ports = 4,
2022 .base_baud = 115200,
2023 .uart_offset = 8,
2024 },
2025
2026 /* I think this entry is broken - the first_offset looks wrong --rmk */
2027 [pbn_plx_romulus] = {
2028 .flags = FL_BASE2,
2029 .num_ports = 4,
2030 .base_baud = 921600,
2031 .uart_offset = 8 << 2,
2032 .reg_shift = 2,
2033 .first_offset = 0x03,
2034 },
2035
2036 /*
2037 * This board uses the size of PCI Base region 0 to
2038 * signal now many ports are available
2039 */
2040 [pbn_oxsemi] = {
2041 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2042 .num_ports = 32,
2043 .base_baud = 115200,
2044 .uart_offset = 8,
2045 },
2046 [pbn_oxsemi_1_4000000] = {
2047 .flags = FL_BASE0,
2048 .num_ports = 1,
2049 .base_baud = 4000000,
2050 .uart_offset = 0x200,
2051 .first_offset = 0x1000,
2052 },
2053 [pbn_oxsemi_2_4000000] = {
2054 .flags = FL_BASE0,
2055 .num_ports = 2,
2056 .base_baud = 4000000,
2057 .uart_offset = 0x200,
2058 .first_offset = 0x1000,
2059 },
2060 [pbn_oxsemi_4_4000000] = {
2061 .flags = FL_BASE0,
2062 .num_ports = 4,
2063 .base_baud = 4000000,
2064 .uart_offset = 0x200,
2065 .first_offset = 0x1000,
2066 },
2067 [pbn_oxsemi_8_4000000] = {
2068 .flags = FL_BASE0,
2069 .num_ports = 8,
2070 .base_baud = 4000000,
2071 .uart_offset = 0x200,
2072 .first_offset = 0x1000,
2073 },
2074
2075
2076 /*
2077 * EKF addition for i960 Boards form EKF with serial port.
2078 * Max 256 ports.
2079 */
2080 [pbn_intel_i960] = {
2081 .flags = FL_BASE0,
2082 .num_ports = 32,
2083 .base_baud = 921600,
2084 .uart_offset = 8 << 2,
2085 .reg_shift = 2,
2086 .first_offset = 0x10000,
2087 },
2088 [pbn_sgi_ioc3] = {
2089 .flags = FL_BASE0|FL_NOIRQ,
2090 .num_ports = 1,
2091 .base_baud = 458333,
2092 .uart_offset = 8,
2093 .reg_shift = 0,
2094 .first_offset = 0x20178,
2095 },
2096
2097 /*
2098 * Computone - uses IOMEM.
2099 */
2100 [pbn_computone_4] = {
2101 .flags = FL_BASE0,
2102 .num_ports = 4,
2103 .base_baud = 921600,
2104 .uart_offset = 0x40,
2105 .reg_shift = 2,
2106 .first_offset = 0x200,
2107 },
2108 [pbn_computone_6] = {
2109 .flags = FL_BASE0,
2110 .num_ports = 6,
2111 .base_baud = 921600,
2112 .uart_offset = 0x40,
2113 .reg_shift = 2,
2114 .first_offset = 0x200,
2115 },
2116 [pbn_computone_8] = {
2117 .flags = FL_BASE0,
2118 .num_ports = 8,
2119 .base_baud = 921600,
2120 .uart_offset = 0x40,
2121 .reg_shift = 2,
2122 .first_offset = 0x200,
2123 },
2124 [pbn_sbsxrsio] = {
2125 .flags = FL_BASE0,
2126 .num_ports = 8,
2127 .base_baud = 460800,
2128 .uart_offset = 256,
2129 .reg_shift = 4,
2130 },
2131 /*
2132 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2133 * Only basic 16550A support.
2134 * XR17C15[24] are not tested, but they should work.
2135 */
2136 [pbn_exar_XR17C152] = {
2137 .flags = FL_BASE0,
2138 .num_ports = 2,
2139 .base_baud = 921600,
2140 .uart_offset = 0x200,
2141 },
2142 [pbn_exar_XR17C154] = {
2143 .flags = FL_BASE0,
2144 .num_ports = 4,
2145 .base_baud = 921600,
2146 .uart_offset = 0x200,
2147 },
2148 [pbn_exar_XR17C158] = {
2149 .flags = FL_BASE0,
2150 .num_ports = 8,
2151 .base_baud = 921600,
2152 .uart_offset = 0x200,
2153 },
2154 [pbn_exar_ibm_saturn] = {
2155 .flags = FL_BASE0,
2156 .num_ports = 1,
2157 .base_baud = 921600,
2158 .uart_offset = 0x200,
2159 },
2160
2161 /*
2162 * PA Semi PWRficient PA6T-1682M on-chip UART
2163 */
2164 [pbn_pasemi_1682M] = {
2165 .flags = FL_BASE0,
2166 .num_ports = 1,
2167 .base_baud = 8333333,
2168 },
2169 /*
2170 * National Instruments 843x
2171 */
2172 [pbn_ni8430_16] = {
2173 .flags = FL_BASE0,
2174 .num_ports = 16,
2175 .base_baud = 3686400,
2176 .uart_offset = 0x10,
2177 .first_offset = 0x800,
2178 },
2179 [pbn_ni8430_8] = {
2180 .flags = FL_BASE0,
2181 .num_ports = 8,
2182 .base_baud = 3686400,
2183 .uart_offset = 0x10,
2184 .first_offset = 0x800,
2185 },
2186 [pbn_ni8430_4] = {
2187 .flags = FL_BASE0,
2188 .num_ports = 4,
2189 .base_baud = 3686400,
2190 .uart_offset = 0x10,
2191 .first_offset = 0x800,
2192 },
2193 [pbn_ni8430_2] = {
2194 .flags = FL_BASE0,
2195 .num_ports = 2,
2196 .base_baud = 3686400,
2197 .uart_offset = 0x10,
2198 .first_offset = 0x800,
2199 },
2200 /*
2201 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2202 */
2203 [pbn_ADDIDATA_PCIe_1_3906250] = {
2204 .flags = FL_BASE0,
2205 .num_ports = 1,
2206 .base_baud = 3906250,
2207 .uart_offset = 0x200,
2208 .first_offset = 0x1000,
2209 },
2210 [pbn_ADDIDATA_PCIe_2_3906250] = {
2211 .flags = FL_BASE0,
2212 .num_ports = 2,
2213 .base_baud = 3906250,
2214 .uart_offset = 0x200,
2215 .first_offset = 0x1000,
2216 },
2217 [pbn_ADDIDATA_PCIe_4_3906250] = {
2218 .flags = FL_BASE0,
2219 .num_ports = 4,
2220 .base_baud = 3906250,
2221 .uart_offset = 0x200,
2222 .first_offset = 0x1000,
2223 },
2224 [pbn_ADDIDATA_PCIe_8_3906250] = {
2225 .flags = FL_BASE0,
2226 .num_ports = 8,
2227 .base_baud = 3906250,
2228 .uart_offset = 0x200,
2229 .first_offset = 0x1000,
2230 },
2231 };
2232
2233 static const struct pci_device_id softmodem_blacklist[] = {
2234 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2235 };
2236
2237 /*
2238 * Given a complete unknown PCI device, try to use some heuristics to
2239 * guess what the configuration might be, based on the pitiful PCI
2240 * serial specs. Returns 0 on success, 1 on failure.
2241 */
2242 static int __devinit
2243 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2244 {
2245 const struct pci_device_id *blacklist;
2246 int num_iomem, num_port, first_port = -1, i;
2247
2248 /*
2249 * If it is not a communications device or the programming
2250 * interface is greater than 6, give up.
2251 *
2252 * (Should we try to make guesses for multiport serial devices
2253 * later?)
2254 */
2255 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2256 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2257 (dev->class & 0xff) > 6)
2258 return -ENODEV;
2259
2260 /*
2261 * Do not access blacklisted devices that are known not to
2262 * feature serial ports.
2263 */
2264 for (blacklist = softmodem_blacklist;
2265 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2266 blacklist++) {
2267 if (dev->vendor == blacklist->vendor &&
2268 dev->device == blacklist->device)
2269 return -ENODEV;
2270 }
2271
2272 num_iomem = num_port = 0;
2273 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2274 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2275 num_port++;
2276 if (first_port == -1)
2277 first_port = i;
2278 }
2279 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2280 num_iomem++;
2281 }
2282
2283 /*
2284 * If there is 1 or 0 iomem regions, and exactly one port,
2285 * use it. We guess the number of ports based on the IO
2286 * region size.
2287 */
2288 if (num_iomem <= 1 && num_port == 1) {
2289 board->flags = first_port;
2290 board->num_ports = pci_resource_len(dev, first_port) / 8;
2291 return 0;
2292 }
2293
2294 /*
2295 * Now guess if we've got a board which indexes by BARs.
2296 * Each IO BAR should be 8 bytes, and they should follow
2297 * consecutively.
2298 */
2299 first_port = -1;
2300 num_port = 0;
2301 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2302 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2303 pci_resource_len(dev, i) == 8 &&
2304 (first_port == -1 || (first_port + num_port) == i)) {
2305 num_port++;
2306 if (first_port == -1)
2307 first_port = i;
2308 }
2309 }
2310
2311 if (num_port > 1) {
2312 board->flags = first_port | FL_BASE_BARS;
2313 board->num_ports = num_port;
2314 return 0;
2315 }
2316
2317 return -ENODEV;
2318 }
2319
2320 static inline int
2321 serial_pci_matches(const struct pciserial_board *board,
2322 const struct pciserial_board *guessed)
2323 {
2324 return
2325 board->num_ports == guessed->num_ports &&
2326 board->base_baud == guessed->base_baud &&
2327 board->uart_offset == guessed->uart_offset &&
2328 board->reg_shift == guessed->reg_shift &&
2329 board->first_offset == guessed->first_offset;
2330 }
2331
2332 struct serial_private *
2333 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2334 {
2335 struct uart_port serial_port;
2336 struct serial_private *priv;
2337 struct pci_serial_quirk *quirk;
2338 int rc, nr_ports, i;
2339
2340 nr_ports = board->num_ports;
2341
2342 /*
2343 * Find an init and setup quirks.
2344 */
2345 quirk = find_quirk(dev);
2346
2347 /*
2348 * Run the new-style initialization function.
2349 * The initialization function returns:
2350 * <0 - error
2351 * 0 - use board->num_ports
2352 * >0 - number of ports
2353 */
2354 if (quirk->init) {
2355 rc = quirk->init(dev);
2356 if (rc < 0) {
2357 priv = ERR_PTR(rc);
2358 goto err_out;
2359 }
2360 if (rc)
2361 nr_ports = rc;
2362 }
2363
2364 priv = kzalloc(sizeof(struct serial_private) +
2365 sizeof(unsigned int) * nr_ports,
2366 GFP_KERNEL);
2367 if (!priv) {
2368 priv = ERR_PTR(-ENOMEM);
2369 goto err_deinit;
2370 }
2371
2372 priv->dev = dev;
2373 priv->quirk = quirk;
2374
2375 memset(&serial_port, 0, sizeof(struct uart_port));
2376 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2377 serial_port.uartclk = board->base_baud * 16;
2378 serial_port.irq = get_pci_irq(dev, board);
2379 serial_port.dev = &dev->dev;
2380
2381 for (i = 0; i < nr_ports; i++) {
2382 if (quirk->setup(priv, board, &serial_port, i))
2383 break;
2384
2385 #ifdef SERIAL_DEBUG_PCI
2386 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2387 serial_port.iobase, serial_port.irq, serial_port.iotype);
2388 #endif
2389
2390 priv->line[i] = serial8250_register_port(&serial_port);
2391 if (priv->line[i] < 0) {
2392 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2393 break;
2394 }
2395 }
2396 priv->nr = i;
2397 return priv;
2398
2399 err_deinit:
2400 if (quirk->exit)
2401 quirk->exit(dev);
2402 err_out:
2403 return priv;
2404 }
2405 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2406
2407 void pciserial_remove_ports(struct serial_private *priv)
2408 {
2409 struct pci_serial_quirk *quirk;
2410 int i;
2411
2412 for (i = 0; i < priv->nr; i++)
2413 serial8250_unregister_port(priv->line[i]);
2414
2415 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2416 if (priv->remapped_bar[i])
2417 iounmap(priv->remapped_bar[i]);
2418 priv->remapped_bar[i] = NULL;
2419 }
2420
2421 /*
2422 * Find the exit quirks.
2423 */
2424 quirk = find_quirk(priv->dev);
2425 if (quirk->exit)
2426 quirk->exit(priv->dev);
2427
2428 kfree(priv);
2429 }
2430 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2431
2432 void pciserial_suspend_ports(struct serial_private *priv)
2433 {
2434 int i;
2435
2436 for (i = 0; i < priv->nr; i++)
2437 if (priv->line[i] >= 0)
2438 serial8250_suspend_port(priv->line[i]);
2439 }
2440 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2441
2442 void pciserial_resume_ports(struct serial_private *priv)
2443 {
2444 int i;
2445
2446 /*
2447 * Ensure that the board is correctly configured.
2448 */
2449 if (priv->quirk->init)
2450 priv->quirk->init(priv->dev);
2451
2452 for (i = 0; i < priv->nr; i++)
2453 if (priv->line[i] >= 0)
2454 serial8250_resume_port(priv->line[i]);
2455 }
2456 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2457
2458 /*
2459 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2460 * to the arrangement of serial ports on a PCI card.
2461 */
2462 static int __devinit
2463 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2464 {
2465 struct serial_private *priv;
2466 const struct pciserial_board *board;
2467 struct pciserial_board tmp;
2468 int rc;
2469
2470 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2471 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2472 ent->driver_data);
2473 return -EINVAL;
2474 }
2475
2476 board = &pci_boards[ent->driver_data];
2477
2478 rc = pci_enable_device(dev);
2479 if (rc)
2480 return rc;
2481
2482 if (ent->driver_data == pbn_default) {
2483 /*
2484 * Use a copy of the pci_board entry for this;
2485 * avoid changing entries in the table.
2486 */
2487 memcpy(&tmp, board, sizeof(struct pciserial_board));
2488 board = &tmp;
2489
2490 /*
2491 * We matched one of our class entries. Try to
2492 * determine the parameters of this board.
2493 */
2494 rc = serial_pci_guess_board(dev, &tmp);
2495 if (rc)
2496 goto disable;
2497 } else {
2498 /*
2499 * We matched an explicit entry. If we are able to
2500 * detect this boards settings with our heuristic,
2501 * then we no longer need this entry.
2502 */
2503 memcpy(&tmp, &pci_boards[pbn_default],
2504 sizeof(struct pciserial_board));
2505 rc = serial_pci_guess_board(dev, &tmp);
2506 if (rc == 0 && serial_pci_matches(board, &tmp))
2507 moan_device("Redundant entry in serial pci_table.",
2508 dev);
2509 }
2510
2511 priv = pciserial_init_ports(dev, board);
2512 if (!IS_ERR(priv)) {
2513 pci_set_drvdata(dev, priv);
2514 return 0;
2515 }
2516
2517 rc = PTR_ERR(priv);
2518
2519 disable:
2520 pci_disable_device(dev);
2521 return rc;
2522 }
2523
2524 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2525 {
2526 struct serial_private *priv = pci_get_drvdata(dev);
2527
2528 pci_set_drvdata(dev, NULL);
2529
2530 pciserial_remove_ports(priv);
2531
2532 pci_disable_device(dev);
2533 }
2534
2535 #ifdef CONFIG_PM
2536 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2537 {
2538 struct serial_private *priv = pci_get_drvdata(dev);
2539
2540 if (priv)
2541 pciserial_suspend_ports(priv);
2542
2543 pci_save_state(dev);
2544 pci_set_power_state(dev, pci_choose_state(dev, state));
2545 return 0;
2546 }
2547
2548 static int pciserial_resume_one(struct pci_dev *dev)
2549 {
2550 int err;
2551 struct serial_private *priv = pci_get_drvdata(dev);
2552
2553 pci_set_power_state(dev, PCI_D0);
2554 pci_restore_state(dev);
2555
2556 if (priv) {
2557 /*
2558 * The device may have been disabled. Re-enable it.
2559 */
2560 err = pci_enable_device(dev);
2561 /* FIXME: We cannot simply error out here */
2562 if (err)
2563 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2564 pciserial_resume_ports(priv);
2565 }
2566 return 0;
2567 }
2568 #endif
2569
2570 static struct pci_device_id serial_pci_tbl[] = {
2571 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2572 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2573 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2574 pbn_b2_8_921600 },
2575 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2576 PCI_SUBVENDOR_ID_CONNECT_TECH,
2577 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2578 pbn_b1_8_1382400 },
2579 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2580 PCI_SUBVENDOR_ID_CONNECT_TECH,
2581 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2582 pbn_b1_4_1382400 },
2583 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2584 PCI_SUBVENDOR_ID_CONNECT_TECH,
2585 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2586 pbn_b1_2_1382400 },
2587 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2588 PCI_SUBVENDOR_ID_CONNECT_TECH,
2589 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2590 pbn_b1_8_1382400 },
2591 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2592 PCI_SUBVENDOR_ID_CONNECT_TECH,
2593 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2594 pbn_b1_4_1382400 },
2595 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2596 PCI_SUBVENDOR_ID_CONNECT_TECH,
2597 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2598 pbn_b1_2_1382400 },
2599 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2600 PCI_SUBVENDOR_ID_CONNECT_TECH,
2601 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2602 pbn_b1_8_921600 },
2603 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2604 PCI_SUBVENDOR_ID_CONNECT_TECH,
2605 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2606 pbn_b1_8_921600 },
2607 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2608 PCI_SUBVENDOR_ID_CONNECT_TECH,
2609 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2610 pbn_b1_4_921600 },
2611 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2612 PCI_SUBVENDOR_ID_CONNECT_TECH,
2613 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2614 pbn_b1_4_921600 },
2615 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2616 PCI_SUBVENDOR_ID_CONNECT_TECH,
2617 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2618 pbn_b1_2_921600 },
2619 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2620 PCI_SUBVENDOR_ID_CONNECT_TECH,
2621 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2622 pbn_b1_8_921600 },
2623 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2624 PCI_SUBVENDOR_ID_CONNECT_TECH,
2625 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2626 pbn_b1_8_921600 },
2627 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2628 PCI_SUBVENDOR_ID_CONNECT_TECH,
2629 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2630 pbn_b1_4_921600 },
2631 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2632 PCI_SUBVENDOR_ID_CONNECT_TECH,
2633 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2634 pbn_b1_2_1250000 },
2635 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2636 PCI_SUBVENDOR_ID_CONNECT_TECH,
2637 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2638 pbn_b0_2_1843200 },
2639 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2640 PCI_SUBVENDOR_ID_CONNECT_TECH,
2641 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2642 pbn_b0_4_1843200 },
2643 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2644 PCI_VENDOR_ID_AFAVLAB,
2645 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2646 pbn_b0_4_1152000 },
2647 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2648 PCI_SUBVENDOR_ID_CONNECT_TECH,
2649 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2650 pbn_b0_2_1843200_200 },
2651 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2652 PCI_SUBVENDOR_ID_CONNECT_TECH,
2653 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2654 pbn_b0_4_1843200_200 },
2655 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2656 PCI_SUBVENDOR_ID_CONNECT_TECH,
2657 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2658 pbn_b0_8_1843200_200 },
2659 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2660 PCI_SUBVENDOR_ID_CONNECT_TECH,
2661 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2662 pbn_b0_2_1843200_200 },
2663 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2664 PCI_SUBVENDOR_ID_CONNECT_TECH,
2665 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2666 pbn_b0_4_1843200_200 },
2667 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2668 PCI_SUBVENDOR_ID_CONNECT_TECH,
2669 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2670 pbn_b0_8_1843200_200 },
2671 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2672 PCI_SUBVENDOR_ID_CONNECT_TECH,
2673 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2674 pbn_b0_2_1843200_200 },
2675 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2676 PCI_SUBVENDOR_ID_CONNECT_TECH,
2677 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2678 pbn_b0_4_1843200_200 },
2679 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2680 PCI_SUBVENDOR_ID_CONNECT_TECH,
2681 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2682 pbn_b0_8_1843200_200 },
2683 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2684 PCI_SUBVENDOR_ID_CONNECT_TECH,
2685 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2686 pbn_b0_2_1843200_200 },
2687 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2688 PCI_SUBVENDOR_ID_CONNECT_TECH,
2689 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2690 pbn_b0_4_1843200_200 },
2691 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2692 PCI_SUBVENDOR_ID_CONNECT_TECH,
2693 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2694 pbn_b0_8_1843200_200 },
2695 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2696 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2697 0, 0, pbn_exar_ibm_saturn },
2698
2699 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2701 pbn_b2_bt_1_115200 },
2702 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2704 pbn_b2_bt_2_115200 },
2705 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2707 pbn_b2_bt_4_115200 },
2708 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2710 pbn_b2_bt_2_115200 },
2711 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2713 pbn_b2_bt_4_115200 },
2714 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2716 pbn_b2_8_115200 },
2717 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2719 pbn_b2_8_460800 },
2720 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2722 pbn_b2_8_115200 },
2723
2724 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2726 pbn_b2_bt_2_115200 },
2727 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2729 pbn_b2_bt_2_921600 },
2730 /*
2731 * VScom SPCOM800, from sl@s.pl
2732 */
2733 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2735 pbn_b2_8_921600 },
2736 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2738 pbn_b2_4_921600 },
2739 /* Unknown card - subdevice 0x1584 */
2740 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2741 PCI_VENDOR_ID_PLX,
2742 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2743 pbn_b0_4_115200 },
2744 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2745 PCI_SUBVENDOR_ID_KEYSPAN,
2746 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2747 pbn_panacom },
2748 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2750 pbn_panacom4 },
2751 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2753 pbn_panacom2 },
2754 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2755 PCI_VENDOR_ID_ESDGMBH,
2756 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2757 pbn_b2_4_115200 },
2758 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2759 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2760 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2761 pbn_b2_4_460800 },
2762 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2763 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2764 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2765 pbn_b2_8_460800 },
2766 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2767 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2768 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2769 pbn_b2_16_460800 },
2770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2771 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2772 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2773 pbn_b2_16_460800 },
2774 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2775 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2776 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2777 pbn_b2_4_460800 },
2778 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2779 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2780 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2781 pbn_b2_8_460800 },
2782 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2783 PCI_SUBVENDOR_ID_EXSYS,
2784 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2785 pbn_exsys_4055 },
2786 /*
2787 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2788 * (Exoray@isys.ca)
2789 */
2790 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2791 0x10b5, 0x106a, 0, 0,
2792 pbn_plx_romulus },
2793 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2795 pbn_b1_4_115200 },
2796 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2798 pbn_b1_2_115200 },
2799 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2801 pbn_b1_8_115200 },
2802 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2804 pbn_b1_8_115200 },
2805 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2806 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2807 0, 0,
2808 pbn_b0_4_921600 },
2809 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2810 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2811 0, 0,
2812 pbn_b0_4_1152000 },
2813
2814 /*
2815 * The below card is a little controversial since it is the
2816 * subject of a PCI vendor/device ID clash. (See
2817 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2818 * For now just used the hex ID 0x950a.
2819 */
2820 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2821 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2822 pbn_b0_2_115200 },
2823 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825 pbn_b0_2_1130000 },
2826 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2827 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2828 pbn_b0_1_921600 },
2829 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2831 pbn_b0_4_115200 },
2832 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834 pbn_b0_bt_2_921600 },
2835
2836 /*
2837 * Oxford Semiconductor Inc. Tornado PCI express device range.
2838 */
2839 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2841 pbn_b0_1_4000000 },
2842 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2844 pbn_b0_1_4000000 },
2845 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2847 pbn_oxsemi_1_4000000 },
2848 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2850 pbn_oxsemi_1_4000000 },
2851 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2853 pbn_b0_1_4000000 },
2854 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2856 pbn_b0_1_4000000 },
2857 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2859 pbn_oxsemi_1_4000000 },
2860 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2862 pbn_oxsemi_1_4000000 },
2863 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2865 pbn_b0_1_4000000 },
2866 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2868 pbn_b0_1_4000000 },
2869 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2871 pbn_b0_1_4000000 },
2872 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2874 pbn_b0_1_4000000 },
2875 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2877 pbn_oxsemi_2_4000000 },
2878 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2880 pbn_oxsemi_2_4000000 },
2881 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2883 pbn_oxsemi_4_4000000 },
2884 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2886 pbn_oxsemi_4_4000000 },
2887 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2889 pbn_oxsemi_8_4000000 },
2890 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2892 pbn_oxsemi_8_4000000 },
2893 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2895 pbn_oxsemi_1_4000000 },
2896 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2898 pbn_oxsemi_1_4000000 },
2899 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2901 pbn_oxsemi_1_4000000 },
2902 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_oxsemi_1_4000000 },
2905 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_oxsemi_1_4000000 },
2908 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910 pbn_oxsemi_1_4000000 },
2911 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_oxsemi_1_4000000 },
2914 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_oxsemi_1_4000000 },
2917 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919 pbn_oxsemi_1_4000000 },
2920 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922 pbn_oxsemi_1_4000000 },
2923 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2925 pbn_oxsemi_1_4000000 },
2926 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928 pbn_oxsemi_1_4000000 },
2929 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_oxsemi_1_4000000 },
2932 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2934 pbn_oxsemi_1_4000000 },
2935 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2937 pbn_oxsemi_1_4000000 },
2938 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2940 pbn_oxsemi_1_4000000 },
2941 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2943 pbn_oxsemi_1_4000000 },
2944 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2946 pbn_oxsemi_1_4000000 },
2947 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2949 pbn_oxsemi_1_4000000 },
2950 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2952 pbn_oxsemi_1_4000000 },
2953 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2955 pbn_oxsemi_1_4000000 },
2956 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2958 pbn_oxsemi_1_4000000 },
2959 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2961 pbn_oxsemi_1_4000000 },
2962 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2964 pbn_oxsemi_1_4000000 },
2965 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967 pbn_oxsemi_1_4000000 },
2968 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970 pbn_oxsemi_1_4000000 },
2971 /*
2972 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2973 */
2974 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2975 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2976 pbn_oxsemi_1_4000000 },
2977 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2978 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2979 pbn_oxsemi_2_4000000 },
2980 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2981 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2982 pbn_oxsemi_4_4000000 },
2983 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2984 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2985 pbn_oxsemi_8_4000000 },
2986 /*
2987 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2988 * from skokodyn@yahoo.com
2989 */
2990 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2991 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2992 pbn_sbsxrsio },
2993 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2994 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2995 pbn_sbsxrsio },
2996 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2997 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2998 pbn_sbsxrsio },
2999 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3000 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3001 pbn_sbsxrsio },
3002
3003 /*
3004 * Digitan DS560-558, from jimd@esoft.com
3005 */
3006 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008 pbn_b1_1_115200 },
3009
3010 /*
3011 * Titan Electronic cards
3012 * The 400L and 800L have a custom setup quirk.
3013 */
3014 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3016 pbn_b0_1_921600 },
3017 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3019 pbn_b0_2_921600 },
3020 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3022 pbn_b0_4_921600 },
3023 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3025 pbn_b0_4_921600 },
3026 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028 pbn_b1_1_921600 },
3029 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3031 pbn_b1_bt_2_921600 },
3032 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034 pbn_b0_bt_4_921600 },
3035 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037 pbn_b0_bt_8_921600 },
3038
3039 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3041 pbn_b2_1_460800 },
3042 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3044 pbn_b2_1_460800 },
3045 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047 pbn_b2_1_460800 },
3048 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3050 pbn_b2_bt_2_921600 },
3051 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3053 pbn_b2_bt_2_921600 },
3054 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3056 pbn_b2_bt_2_921600 },
3057 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059 pbn_b2_bt_4_921600 },
3060 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062 pbn_b2_bt_4_921600 },
3063 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3065 pbn_b2_bt_4_921600 },
3066 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3068 pbn_b0_1_921600 },
3069 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071 pbn_b0_1_921600 },
3072 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074 pbn_b0_1_921600 },
3075 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077 pbn_b0_bt_2_921600 },
3078 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080 pbn_b0_bt_2_921600 },
3081 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083 pbn_b0_bt_2_921600 },
3084 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086 pbn_b0_bt_4_921600 },
3087 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089 pbn_b0_bt_4_921600 },
3090 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092 pbn_b0_bt_4_921600 },
3093 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095 pbn_b0_bt_8_921600 },
3096 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098 pbn_b0_bt_8_921600 },
3099 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101 pbn_b0_bt_8_921600 },
3102
3103 /*
3104 * Computone devices submitted by Doug McNash dmcnash@computone.com
3105 */
3106 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3107 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3108 0, 0, pbn_computone_4 },
3109 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3110 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3111 0, 0, pbn_computone_8 },
3112 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3113 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3114 0, 0, pbn_computone_6 },
3115
3116 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_oxsemi },
3119 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3120 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3121 pbn_b0_bt_1_921600 },
3122
3123 /*
3124 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3125 */
3126 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3128 pbn_b0_bt_8_115200 },
3129 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131 pbn_b0_bt_8_115200 },
3132
3133 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 pbn_b0_bt_2_115200 },
3136 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3138 pbn_b0_bt_2_115200 },
3139 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141 pbn_b0_bt_2_115200 },
3142 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144 pbn_b0_bt_2_115200 },
3145 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 pbn_b0_bt_2_115200 },
3148 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 pbn_b0_bt_4_460800 },
3151 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b0_bt_4_460800 },
3154 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_b0_bt_2_460800 },
3157 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b0_bt_2_460800 },
3160 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_b0_bt_2_460800 },
3163 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3165 pbn_b0_bt_1_115200 },
3166 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3168 pbn_b0_bt_1_460800 },
3169
3170 /*
3171 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3172 * Cards are identified by their subsystem vendor IDs, which
3173 * (in hex) match the model number.
3174 *
3175 * Note that JC140x are RS422/485 cards which require ox950
3176 * ACR = 0x10, and as such are not currently fully supported.
3177 */
3178 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3179 0x1204, 0x0004, 0, 0,
3180 pbn_b0_4_921600 },
3181 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3182 0x1208, 0x0004, 0, 0,
3183 pbn_b0_4_921600 },
3184 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3185 0x1402, 0x0002, 0, 0,
3186 pbn_b0_2_921600 }, */
3187 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3188 0x1404, 0x0004, 0, 0,
3189 pbn_b0_4_921600 }, */
3190 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3191 0x1208, 0x0004, 0, 0,
3192 pbn_b0_4_921600 },
3193
3194 /*
3195 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3196 */
3197 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199 pbn_b1_1_1382400 },
3200
3201 /*
3202 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3203 */
3204 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206 pbn_b1_1_1382400 },
3207
3208 /*
3209 * RAStel 2 port modem, gerg@moreton.com.au
3210 */
3211 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213 pbn_b2_bt_2_115200 },
3214
3215 /*
3216 * EKF addition for i960 Boards form EKF with serial port
3217 */
3218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3219 0xE4BF, PCI_ANY_ID, 0, 0,
3220 pbn_intel_i960 },
3221
3222 /*
3223 * Xircom Cardbus/Ethernet combos
3224 */
3225 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_b0_1_115200 },
3228 /*
3229 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3230 */
3231 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_b0_1_115200 },
3234
3235 /*
3236 * Untested PCI modems, sent in from various folks...
3237 */
3238
3239 /*
3240 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3241 */
3242 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3243 0x1048, 0x1500, 0, 0,
3244 pbn_b1_1_115200 },
3245
3246 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3247 0xFF00, 0, 0, 0,
3248 pbn_sgi_ioc3 },
3249
3250 /*
3251 * HP Diva card
3252 */
3253 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3254 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3255 pbn_b1_1_115200 },
3256 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258 pbn_b0_5_115200 },
3259 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261 pbn_b2_1_115200 },
3262
3263 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_b3_2_115200 },
3266 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268 pbn_b3_4_115200 },
3269 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_b3_8_115200 },
3272
3273 /*
3274 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3275 */
3276 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3277 PCI_ANY_ID, PCI_ANY_ID,
3278 0,
3279 0, pbn_exar_XR17C152 },
3280 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3281 PCI_ANY_ID, PCI_ANY_ID,
3282 0,
3283 0, pbn_exar_XR17C154 },
3284 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3285 PCI_ANY_ID, PCI_ANY_ID,
3286 0,
3287 0, pbn_exar_XR17C158 },
3288
3289 /*
3290 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3291 */
3292 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_b0_1_115200 },
3295 /*
3296 * ITE
3297 */
3298 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3299 PCI_ANY_ID, PCI_ANY_ID,
3300 0, 0,
3301 pbn_b1_bt_1_115200 },
3302
3303 /*
3304 * IntaShield IS-200
3305 */
3306 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3308 pbn_b2_2_115200 },
3309 /*
3310 * IntaShield IS-400
3311 */
3312 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3314 pbn_b2_4_115200 },
3315 /*
3316 * Perle PCI-RAS cards
3317 */
3318 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3319 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3320 0, 0, pbn_b2_4_921600 },
3321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3322 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3323 0, 0, pbn_b2_8_921600 },
3324
3325 /*
3326 * Mainpine series cards: Fairly standard layout but fools
3327 * parts of the autodetect in some cases and uses otherwise
3328 * unmatched communications subclasses in the PCI Express case
3329 */
3330
3331 { /* RockForceDUO */
3332 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3333 PCI_VENDOR_ID_MAINPINE, 0x0200,
3334 0, 0, pbn_b0_2_115200 },
3335 { /* RockForceQUATRO */
3336 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3337 PCI_VENDOR_ID_MAINPINE, 0x0300,
3338 0, 0, pbn_b0_4_115200 },
3339 { /* RockForceDUO+ */
3340 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3341 PCI_VENDOR_ID_MAINPINE, 0x0400,
3342 0, 0, pbn_b0_2_115200 },
3343 { /* RockForceQUATRO+ */
3344 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3345 PCI_VENDOR_ID_MAINPINE, 0x0500,
3346 0, 0, pbn_b0_4_115200 },
3347 { /* RockForce+ */
3348 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3349 PCI_VENDOR_ID_MAINPINE, 0x0600,
3350 0, 0, pbn_b0_2_115200 },
3351 { /* RockForce+ */
3352 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3353 PCI_VENDOR_ID_MAINPINE, 0x0700,
3354 0, 0, pbn_b0_4_115200 },
3355 { /* RockForceOCTO+ */
3356 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3357 PCI_VENDOR_ID_MAINPINE, 0x0800,
3358 0, 0, pbn_b0_8_115200 },
3359 { /* RockForceDUO+ */
3360 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3361 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3362 0, 0, pbn_b0_2_115200 },
3363 { /* RockForceQUARTRO+ */
3364 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3365 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3366 0, 0, pbn_b0_4_115200 },
3367 { /* RockForceOCTO+ */
3368 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3369 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3370 0, 0, pbn_b0_8_115200 },
3371 { /* RockForceD1 */
3372 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3373 PCI_VENDOR_ID_MAINPINE, 0x2000,
3374 0, 0, pbn_b0_1_115200 },
3375 { /* RockForceF1 */
3376 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3377 PCI_VENDOR_ID_MAINPINE, 0x2100,
3378 0, 0, pbn_b0_1_115200 },
3379 { /* RockForceD2 */
3380 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3381 PCI_VENDOR_ID_MAINPINE, 0x2200,
3382 0, 0, pbn_b0_2_115200 },
3383 { /* RockForceF2 */
3384 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3385 PCI_VENDOR_ID_MAINPINE, 0x2300,
3386 0, 0, pbn_b0_2_115200 },
3387 { /* RockForceD4 */
3388 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3389 PCI_VENDOR_ID_MAINPINE, 0x2400,
3390 0, 0, pbn_b0_4_115200 },
3391 { /* RockForceF4 */
3392 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3393 PCI_VENDOR_ID_MAINPINE, 0x2500,
3394 0, 0, pbn_b0_4_115200 },
3395 { /* RockForceD8 */
3396 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3397 PCI_VENDOR_ID_MAINPINE, 0x2600,
3398 0, 0, pbn_b0_8_115200 },
3399 { /* RockForceF8 */
3400 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3401 PCI_VENDOR_ID_MAINPINE, 0x2700,
3402 0, 0, pbn_b0_8_115200 },
3403 { /* IQ Express D1 */
3404 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3405 PCI_VENDOR_ID_MAINPINE, 0x3000,
3406 0, 0, pbn_b0_1_115200 },
3407 { /* IQ Express F1 */
3408 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3409 PCI_VENDOR_ID_MAINPINE, 0x3100,
3410 0, 0, pbn_b0_1_115200 },
3411 { /* IQ Express D2 */
3412 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3413 PCI_VENDOR_ID_MAINPINE, 0x3200,
3414 0, 0, pbn_b0_2_115200 },
3415 { /* IQ Express F2 */
3416 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3417 PCI_VENDOR_ID_MAINPINE, 0x3300,
3418 0, 0, pbn_b0_2_115200 },
3419 { /* IQ Express D4 */
3420 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3421 PCI_VENDOR_ID_MAINPINE, 0x3400,
3422 0, 0, pbn_b0_4_115200 },
3423 { /* IQ Express F4 */
3424 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3425 PCI_VENDOR_ID_MAINPINE, 0x3500,
3426 0, 0, pbn_b0_4_115200 },
3427 { /* IQ Express D8 */
3428 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3429 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3430 0, 0, pbn_b0_8_115200 },
3431 { /* IQ Express F8 */
3432 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3433 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3434 0, 0, pbn_b0_8_115200 },
3435
3436
3437 /*
3438 * PA Semi PA6T-1682M on-chip UART
3439 */
3440 { PCI_VENDOR_ID_PASEMI, 0xa004,
3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442 pbn_pasemi_1682M },
3443
3444 /*
3445 * National Instruments
3446 */
3447 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_b1_16_115200 },
3450 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_b1_8_115200 },
3453 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_b1_bt_4_115200 },
3456 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_b1_bt_2_115200 },
3459 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_b1_bt_4_115200 },
3462 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_b1_bt_2_115200 },
3465 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467 pbn_b1_16_115200 },
3468 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470 pbn_b1_8_115200 },
3471 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3473 pbn_b1_bt_4_115200 },
3474 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3476 pbn_b1_bt_2_115200 },
3477 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3479 pbn_b1_bt_4_115200 },
3480 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3482 pbn_b1_bt_2_115200 },
3483 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3485 pbn_ni8430_2 },
3486 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3488 pbn_ni8430_2 },
3489 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3491 pbn_ni8430_4 },
3492 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3494 pbn_ni8430_4 },
3495 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3497 pbn_ni8430_8 },
3498 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500 pbn_ni8430_8 },
3501 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503 pbn_ni8430_16 },
3504 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_ni8430_16 },
3507 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509 pbn_ni8430_2 },
3510 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 pbn_ni8430_2 },
3513 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515 pbn_ni8430_4 },
3516 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518 pbn_ni8430_4 },
3519
3520 /*
3521 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3522 */
3523 { PCI_VENDOR_ID_ADDIDATA,
3524 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3525 PCI_ANY_ID,
3526 PCI_ANY_ID,
3527 0,
3528 0,
3529 pbn_b0_4_115200 },
3530
3531 { PCI_VENDOR_ID_ADDIDATA,
3532 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3533 PCI_ANY_ID,
3534 PCI_ANY_ID,
3535 0,
3536 0,
3537 pbn_b0_2_115200 },
3538
3539 { PCI_VENDOR_ID_ADDIDATA,
3540 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3541 PCI_ANY_ID,
3542 PCI_ANY_ID,
3543 0,
3544 0,
3545 pbn_b0_1_115200 },
3546
3547 { PCI_VENDOR_ID_ADDIDATA_OLD,
3548 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3549 PCI_ANY_ID,
3550 PCI_ANY_ID,
3551 0,
3552 0,
3553 pbn_b1_8_115200 },
3554
3555 { PCI_VENDOR_ID_ADDIDATA,
3556 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3557 PCI_ANY_ID,
3558 PCI_ANY_ID,
3559 0,
3560 0,
3561 pbn_b0_4_115200 },
3562
3563 { PCI_VENDOR_ID_ADDIDATA,
3564 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3565 PCI_ANY_ID,
3566 PCI_ANY_ID,
3567 0,
3568 0,
3569 pbn_b0_2_115200 },
3570
3571 { PCI_VENDOR_ID_ADDIDATA,
3572 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3573 PCI_ANY_ID,
3574 PCI_ANY_ID,
3575 0,
3576 0,
3577 pbn_b0_1_115200 },
3578
3579 { PCI_VENDOR_ID_ADDIDATA,
3580 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3581 PCI_ANY_ID,
3582 PCI_ANY_ID,
3583 0,
3584 0,
3585 pbn_b0_4_115200 },
3586
3587 { PCI_VENDOR_ID_ADDIDATA,
3588 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3589 PCI_ANY_ID,
3590 PCI_ANY_ID,
3591 0,
3592 0,
3593 pbn_b0_2_115200 },
3594
3595 { PCI_VENDOR_ID_ADDIDATA,
3596 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3597 PCI_ANY_ID,
3598 PCI_ANY_ID,
3599 0,
3600 0,
3601 pbn_b0_1_115200 },
3602
3603 { PCI_VENDOR_ID_ADDIDATA,
3604 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3605 PCI_ANY_ID,
3606 PCI_ANY_ID,
3607 0,
3608 0,
3609 pbn_b0_8_115200 },
3610
3611 { PCI_VENDOR_ID_ADDIDATA,
3612 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3613 PCI_ANY_ID,
3614 PCI_ANY_ID,
3615 0,
3616 0,
3617 pbn_ADDIDATA_PCIe_4_3906250 },
3618
3619 { PCI_VENDOR_ID_ADDIDATA,
3620 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3621 PCI_ANY_ID,
3622 PCI_ANY_ID,
3623 0,
3624 0,
3625 pbn_ADDIDATA_PCIe_2_3906250 },
3626
3627 { PCI_VENDOR_ID_ADDIDATA,
3628 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3629 PCI_ANY_ID,
3630 PCI_ANY_ID,
3631 0,
3632 0,
3633 pbn_ADDIDATA_PCIe_1_3906250 },
3634
3635 { PCI_VENDOR_ID_ADDIDATA,
3636 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3637 PCI_ANY_ID,
3638 PCI_ANY_ID,
3639 0,
3640 0,
3641 pbn_ADDIDATA_PCIe_8_3906250 },
3642
3643 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3644 PCI_VENDOR_ID_IBM, 0x0299,
3645 0, 0, pbn_b0_bt_2_115200 },
3646
3647 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3648 0xA000, 0x1000,
3649 0, 0, pbn_b0_1_115200 },
3650
3651 /*
3652 * These entries match devices with class COMMUNICATION_SERIAL,
3653 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3654 */
3655 { PCI_ANY_ID, PCI_ANY_ID,
3656 PCI_ANY_ID, PCI_ANY_ID,
3657 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3658 0xffff00, pbn_default },
3659 { PCI_ANY_ID, PCI_ANY_ID,
3660 PCI_ANY_ID, PCI_ANY_ID,
3661 PCI_CLASS_COMMUNICATION_MODEM << 8,
3662 0xffff00, pbn_default },
3663 { PCI_ANY_ID, PCI_ANY_ID,
3664 PCI_ANY_ID, PCI_ANY_ID,
3665 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3666 0xffff00, pbn_default },
3667 { 0, }
3668 };
3669
3670 static struct pci_driver serial_pci_driver = {
3671 .name = "serial",
3672 .probe = pciserial_init_one,
3673 .remove = __devexit_p(pciserial_remove_one),
3674 #ifdef CONFIG_PM
3675 .suspend = pciserial_suspend_one,
3676 .resume = pciserial_resume_one,
3677 #endif
3678 .id_table = serial_pci_tbl,
3679 };
3680
3681 static int __init serial8250_pci_init(void)
3682 {
3683 return pci_register_driver(&serial_pci_driver);
3684 }
3685
3686 static void __exit serial8250_pci_exit(void)
3687 {
3688 pci_unregister_driver(&serial_pci_driver);
3689 }
3690
3691 module_init(serial8250_pci_init);
3692 module_exit(serial8250_pci_exit);
3693
3694 MODULE_LICENSE("GPL");
3695 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3696 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);