drivers/net/wireless/ath/ath5k/pcu.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Matthew W. S. Bell  <mentor@madwifi.org>
   5  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
   6  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   7  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   8  *
   9  * Permission to use, copy, modify, and distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 /*********************************\
  24 * Protocol Control Unit Functions *
  25 \*********************************/
  26
  27 #include <asm/unaligned.h>
  28
  29 #include "ath5k.h"
  30 #include "reg.h"
  31 #include "debug.h"
  32
  33 /*
  34  * AR5212+ can use higher rates for ack transmission
  35  * based on current tx rate instead of the base rate.
  36  * It does this to better utilize channel usage.
  37  * This is a mapping between G rates (that cover both
  38  * CCK and OFDM) and ack rates that we use when setting
  39  * rate -> duration table. This mapping is hw-based so
  40  * don't change anything.
  41  *
  42  * To enable this functionality we must set
  43  * ah->ah_ack_bitrate_high to true else base rate is
  44  * used (1Mb for CCK, 6Mb for OFDM).
  45  */
  46 static const unsigned int ack_rates_high[] =
  47 /* Tx   -> ACK  */
  48 /* 1Mb  -> 1Mb  */      { 0,
  49 /* 2MB  -> 2Mb  */      1,
  50 /* 5.5Mb -> 2Mb */      1,
  51 /* 11Mb -> 2Mb  */      1,
  52 /* 6Mb  -> 6Mb  */      4,
  53 /* 9Mb  -> 6Mb  */      4,
  54 /* 12Mb -> 12Mb */      6,
  55 /* 18Mb -> 12Mb */      6,
  56 /* 24Mb -> 24Mb */      8,
  57 /* 36Mb -> 24Mb */      8,
  58 /* 48Mb -> 24Mb */      8,
  59 /* 54Mb -> 24Mb */      8 };
  60
  61 /*******************\
  62 * Helper functions *
  63 \*******************/
  64
  65 /**
  66  * ath5k_hw_get_frame_duration - Get tx time of a frame
  67  *
  68  * @ah: The &struct ath5k_hw
  69  * @len: Frame's length in bytes
  70  * @rate: The @struct ieee80211_rate
  71  *
  72  * Calculate tx duration of a frame given it's rate and length
  73  * It extends ieee80211_generic_frame_duration for non standard
  74  * bwmodes.
  75  */
  76 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
  77                 int len, struct ieee80211_rate *rate, bool shortpre)
  78 {
  79         int sifs, preamble, plcp_bits, sym_time;
  80         int bitrate, bits, symbols, symbol_bits;
  81         int dur;
  82
  83         /* Fallback */
  84         if (!ah->ah_bwmode) {
  85                 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,
  86                                         NULL, len, rate);
  87
  88                 /* subtract difference between long and short preamble */
  89                 dur = le16_to_cpu(raw_dur);
  90                 if (shortpre)
  91                         dur -= 96;
  92
  93                 return dur;
  94         }
  95
  96         bitrate = rate->bitrate;
  97         preamble = AR5K_INIT_OFDM_PREAMPLE_TIME;
  98         plcp_bits = AR5K_INIT_OFDM_PLCP_BITS;
  99         sym_time = AR5K_INIT_OFDM_SYMBOL_TIME;
 100
 101         switch (ah->ah_bwmode) {
 102         case AR5K_BWMODE_40MHZ:
 103                 sifs = AR5K_INIT_SIFS_TURBO;
 104                 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN;
 105                 break;
 106         case AR5K_BWMODE_10MHZ:
 107                 sifs = AR5K_INIT_SIFS_HALF_RATE;
 108                 preamble *= 2;
 109                 sym_time *= 2;
 110                 break;
 111         case AR5K_BWMODE_5MHZ:
 112                 sifs = AR5K_INIT_SIFS_QUARTER_RATE;
 113                 preamble *= 4;
 114                 sym_time *= 4;
 115                 break;
 116         default:
 117                 sifs = AR5K_INIT_SIFS_DEFAULT_BG;
 118                 break;
 119         }
 120
 121         bits = plcp_bits + (len << 3);
 122         /* Bit rate is in 100Kbits */
 123         symbol_bits = bitrate * sym_time;
 124         symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
 125
 126         dur = sifs + preamble + (sym_time * symbols);
 127
 128         return dur;
 129 }
 130
 131 /**
 132  * ath5k_hw_get_default_slottime - Get the default slot time for current mode
 133  *
 134  * @ah: The &struct ath5k_hw
 135  */
 136 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
 137 {
 138         struct ieee80211_channel *channel = ah->ah_current_channel;
 139         unsigned int slot_time;
 140
 141         switch (ah->ah_bwmode) {
 142         case AR5K_BWMODE_40MHZ:
 143                 slot_time = AR5K_INIT_SLOT_TIME_TURBO;
 144                 break;
 145         case AR5K_BWMODE_10MHZ:
 146                 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
 147                 break;
 148         case AR5K_BWMODE_5MHZ:
 149                 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
 150                 break;
 151         case AR5K_BWMODE_DEFAULT:
 152         default:
 153                 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
 154                 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot)
 155                         slot_time = AR5K_INIT_SLOT_TIME_B;
 156                 break;
 157         }
 158
 159         return slot_time;
 160 }
 161
 162 /**
 163  * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
 164  *
 165  * @ah: The &struct ath5k_hw
 166  */
 167 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
 168 {
 169         struct ieee80211_channel *channel = ah->ah_current_channel;
 170         unsigned int sifs;
 171
 172         switch (ah->ah_bwmode) {
 173         case AR5K_BWMODE_40MHZ:
 174                 sifs = AR5K_INIT_SIFS_TURBO;
 175                 break;
 176         case AR5K_BWMODE_10MHZ:
 177                 sifs = AR5K_INIT_SIFS_HALF_RATE;
 178                 break;
 179         case AR5K_BWMODE_5MHZ:
 180                 sifs = AR5K_INIT_SIFS_QUARTER_RATE;
 181                 break;
 182         case AR5K_BWMODE_DEFAULT:
 183                 sifs = AR5K_INIT_SIFS_DEFAULT_BG;
 184         default:
 185                 if (channel->band == IEEE80211_BAND_5GHZ)
 186                         sifs = AR5K_INIT_SIFS_DEFAULT_A;
 187                 break;
 188         }
 189
 190         return sifs;
 191 }
 192
 193 /**
 194  * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics)
 195  *
 196  * @ah: The &struct ath5k_hw
 197  *
 198  * Reads MIB counters from PCU and updates sw statistics. Is called after a
 199  * MIB interrupt, because one of these counters might have reached their maximum
 200  * and triggered the MIB interrupt, to let us read and clear the counter.
 201  *
 202  * Is called in interrupt context!
 203  */
 204 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
 205 {
 206         struct ath5k_statistics *stats = &ah->stats;
 207
 208         /* Read-And-Clear */
 209         stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
 210         stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
 211         stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
 212         stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
 213         stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
 214 }
 215
 216
 217 /******************\
 218 * ACK/CTS Timeouts *
 219 \******************/
 220
 221 /**
 222  * ath5k_hw_write_rate_duration - fill rate code to duration table
 223  *
 224  * @ah: the &struct ath5k_hw
 225  * @mode: one of enum ath5k_driver_mode
 226  *
 227  * Write the rate code to duration table upon hw reset. This is a helper for
 228  * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
 229  * the hardware, based on current mode, for each rate. The rates which are
 230  * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
 231  * different rate code so we write their value twice (one for long preamble
 232  * and one for short).
 233  *
 234  * Note: Band doesn't matter here, if we set the values for OFDM it works
 235  * on both a and g modes. So all we have to do is set values for all g rates
 236  * that include all OFDM and CCK rates.
 237  *
 238  */
 239 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
 240 {
 241         struct ieee80211_rate *rate;
 242         unsigned int i;
 243         /* 802.11g covers both OFDM and CCK */
 244         u8 band = IEEE80211_BAND_2GHZ;
 245
 246         /* Write rate duration table */
 247         for (i = 0; i < ah->sbands[band].n_bitrates; i++) {
 248                 u32 reg;
 249                 u16 tx_time;
 250
 251                 if (ah->ah_ack_bitrate_high)
 252                         rate = &ah->sbands[band].bitrates[ack_rates_high[i]];
 253                 /* CCK -> 1Mb */
 254                 else if (i < 4)
 255                         rate = &ah->sbands[band].bitrates[0];
 256                 /* OFDM -> 6Mb */
 257                 else
 258                         rate = &ah->sbands[band].bitrates[4];
 259
 260                 /* Set ACK timeout */
 261                 reg = AR5K_RATE_DUR(rate->hw_value);
 262
 263                 /* An ACK frame consists of 10 bytes. If you add the FCS,
 264                  * which ieee80211_generic_frame_duration() adds,
 265                  * its 14 bytes. Note we use the control rate and not the
 266                  * actual rate for this rate. See mac80211 tx.c
 267                  * ieee80211_duration() for a brief description of
 268                  * what rate we should choose to TX ACKs. */
 269                 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false);
 270
 271                 ath5k_hw_reg_write(ah, tx_time, reg);
 272
 273                 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
 274                         continue;
 275
 276                 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true);
 277                 ath5k_hw_reg_write(ah, tx_time,
 278                         reg + (AR5K_SET_SHORT_PREAMBLE << 2));
 279         }
 280 }
 281
 282 /**
 283  * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
 284  *
 285  * @ah: The &struct ath5k_hw
 286  * @timeout: Timeout in usec
 287  */
 288 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
 289 {
 290         if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
 291                         <= timeout)
 292                 return -EINVAL;
 293
 294         AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
 295                 ath5k_hw_htoclock(ah, timeout));
 296
 297         return 0;
 298 }
 299
 300 /**
 301  * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
 302  *
 303  * @ah: The &struct ath5k_hw
 304  * @timeout: Timeout in usec
 305  */
 306 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
 307 {
 308         if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
 309                         <= timeout)
 310                 return -EINVAL;
 311
 312         AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
 313                         ath5k_hw_htoclock(ah, timeout));
 314
 315         return 0;
 316 }
 317
 318
 319 /*******************\
 320 * RX filter Control *
 321 \*******************/
 322
 323 /**
 324  * ath5k_hw_set_lladdr - Set station id
 325  *
 326  * @ah: The &struct ath5k_hw
 327  * @mac: The card's mac address
 328  *
 329  * Set station id on hw using the provided mac address
 330  */
 331 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
 332 {
 333         struct ath_common *common = ath5k_hw_common(ah);
 334         u32 low_id, high_id;
 335         u32 pcu_reg;
 336
 337         /* Set new station ID */
 338         memcpy(common->macaddr, mac, ETH_ALEN);
 339
 340         pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
 341
 342         low_id = get_unaligned_le32(mac);
 343         high_id = get_unaligned_le16(mac + 4);
 344
 345         ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
 346         ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
 347
 348         return 0;
 349 }
 350
 351 /**
 352  * ath5k_hw_set_bssid - Set current BSSID on hw
 353  *
 354  * @ah: The &struct ath5k_hw
 355  *
 356  * Sets the current BSSID and BSSID mask we have from the
 357  * common struct into the hardware
 358  */
 359 void ath5k_hw_set_bssid(struct ath5k_hw *ah)
 360 {
 361         struct ath_common *common = ath5k_hw_common(ah);
 362         u16 tim_offset = 0;
 363
 364         /*
 365          * Set BSSID mask on 5212
 366          */
 367         if (ah->ah_version == AR5K_AR5212)
 368                 ath_hw_setbssidmask(common);
 369
 370         /*
 371          * Set BSSID
 372          */
 373         ath5k_hw_reg_write(ah,
 374                            get_unaligned_le32(common->curbssid),
 375                            AR5K_BSS_ID0);
 376         ath5k_hw_reg_write(ah,
 377                            get_unaligned_le16(common->curbssid + 4) |
 378                            ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
 379                            AR5K_BSS_ID1);
 380
 381         if (common->curaid == 0) {
 382                 ath5k_hw_disable_pspoll(ah);
 383                 return;
 384         }
 385
 386         AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
 387                             tim_offset ? tim_offset + 4 : 0);
 388
 389         ath5k_hw_enable_pspoll(ah, NULL, 0);
 390 }
 391
 392 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
 393 {
 394         struct ath_common *common = ath5k_hw_common(ah);
 395
 396         /* Cache bssid mask so that we can restore it
 397          * on reset */
 398         memcpy(common->bssidmask, mask, ETH_ALEN);
 399         if (ah->ah_version == AR5K_AR5212)
 400                 ath_hw_setbssidmask(common);
 401 }
 402
 403 /*
 404  * Set multicast filter
 405  */
 406 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
 407 {
 408         ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
 409         ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
 410 }
 411
 412 /**
 413  * ath5k_hw_get_rx_filter - Get current rx filter
 414  *
 415  * @ah: The &struct ath5k_hw
 416  *
 417  * Returns the RX filter by reading rx filter and
 418  * phy error filter registers. RX filter is used
 419  * to set the allowed frame types that PCU will accept
 420  * and pass to the driver. For a list of frame types
 421  * check out reg.h.
 422  */
 423 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
 424 {
 425         u32 data, filter = 0;
 426
 427         filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
 428
 429         /*Radar detection for 5212*/
 430         if (ah->ah_version == AR5K_AR5212) {
 431                 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
 432
 433                 if (data & AR5K_PHY_ERR_FIL_RADAR)
 434                         filter |= AR5K_RX_FILTER_RADARERR;
 435                 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
 436                         filter |= AR5K_RX_FILTER_PHYERR;
 437         }
 438
 439         return filter;
 440 }
 441
 442 /**
 443  * ath5k_hw_set_rx_filter - Set rx filter
 444  *
 445  * @ah: The &struct ath5k_hw
 446  * @filter: RX filter mask (see reg.h)
 447  *
 448  * Sets RX filter register and also handles PHY error filter
 449  * register on 5212 and newer chips so that we have proper PHY
 450  * error reporting.
 451  */
 452 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
 453 {
 454         u32 data = 0;
 455
 456         /* Set PHY error filter register on 5212*/
 457         if (ah->ah_version == AR5K_AR5212) {
 458                 if (filter & AR5K_RX_FILTER_RADARERR)
 459                         data |= AR5K_PHY_ERR_FIL_RADAR;
 460                 if (filter & AR5K_RX_FILTER_PHYERR)
 461                         data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
 462         }
 463
 464         /*
 465          * The AR5210 uses promiscuous mode to detect radar activity
 466          */
 467         if (ah->ah_version == AR5K_AR5210 &&
 468                         (filter & AR5K_RX_FILTER_RADARERR)) {
 469                 filter &= ~AR5K_RX_FILTER_RADARERR;
 470                 filter |= AR5K_RX_FILTER_PROM;
 471         }
 472
 473         /*Zero length DMA (phy error reporting) */
 474         if (data)
 475                 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 476         else
 477                 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
 478
 479         /*Write RX Filter register*/
 480         ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
 481
 482         /*Write PHY error filter register on 5212*/
 483         if (ah->ah_version == AR5K_AR5212)
 484                 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
 485
 486 }
 487
 488
 489 /****************\
 490 * Beacon control *
 491 \****************/
 492
 493 #define ATH5K_MAX_TSF_READ 10
 494
 495 /**
 496  * ath5k_hw_get_tsf64 - Get the full 64bit TSF
 497  *
 498  * @ah: The &struct ath5k_hw
 499  *
 500  * Returns the current TSF
 501  */
 502 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
 503 {
 504         u32 tsf_lower, tsf_upper1, tsf_upper2;
 505         int i;
 506         unsigned long flags;
 507
 508         /* This code is time critical - we don't want to be interrupted here */
 509         local_irq_save(flags);
 510
 511         /*
 512          * While reading TSF upper and then lower part, the clock is still
 513          * counting (or jumping in case of IBSS merge) so we might get
 514          * inconsistent values. To avoid this, we read the upper part again
 515          * and check it has not been changed. We make the hypothesis that a
 516          * maximum of 3 changes can happens in a row (we use 10 as a safe
 517          * value).
 518          *
 519          * Impact on performance is pretty small, since in most cases, only
 520          * 3 register reads are needed.
 521          */
 522
 523         tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
 524         for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
 525                 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
 526                 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
 527                 if (tsf_upper2 == tsf_upper1)
 528                         break;
 529                 tsf_upper1 = tsf_upper2;
 530         }
 531
 532         local_irq_restore(flags);
 533
 534         WARN_ON(i == ATH5K_MAX_TSF_READ);
 535
 536         return ((u64)tsf_upper1 << 32) | tsf_lower;
 537 }
 538
 539 /**
 540  * ath5k_hw_set_tsf64 - Set a new 64bit TSF
 541  *
 542  * @ah: The &struct ath5k_hw
 543  * @tsf64: The new 64bit TSF
 544  *
 545  * Sets the new TSF
 546  */
 547 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
 548 {
 549         ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
 550         ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
 551 }
 552
 553 /**
 554  * ath5k_hw_reset_tsf - Force a TSF reset
 555  *
 556  * @ah: The &struct ath5k_hw
 557  *
 558  * Forces a TSF reset on PCU
 559  */
 560 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
 561 {
 562         u32 val;
 563
 564         val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
 565
 566         /*
 567          * Each write to the RESET_TSF bit toggles a hardware internal
 568          * signal to reset TSF, but if left high it will cause a TSF reset
 569          * on the next chip reset as well.  Thus we always write the value
 570          * twice to clear the signal.
 571          */
 572         ath5k_hw_reg_write(ah, val, AR5K_BEACON);
 573         ath5k_hw_reg_write(ah, val, AR5K_BEACON);
 574 }
 575
 576 /*
 577  * Initialize beacon timers
 578  */
 579 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
 580 {
 581         u32 timer1, timer2, timer3;
 582
 583         /*
 584          * Set the additional timers by mode
 585          */
 586         switch (ah->opmode) {
 587         case NL80211_IFTYPE_MONITOR:
 588         case NL80211_IFTYPE_STATION:
 589                 /* In STA mode timer1 is used as next wakeup
 590                  * timer and timer2 as next CFP duration start
 591                  * timer. Both in 1/8TUs. */
 592                 /* TODO: PCF handling */
 593                 if (ah->ah_version == AR5K_AR5210) {
 594                         timer1 = 0xffffffff;
 595                         timer2 = 0xffffffff;
 596                 } else {
 597                         timer1 = 0x0000ffff;
 598                         timer2 = 0x0007ffff;
 599                 }
 600                 /* Mark associated AP as PCF incapable for now */
 601                 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
 602                 break;
 603         case NL80211_IFTYPE_ADHOC:
 604                 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
 605         default:
 606                 /* On non-STA modes timer1 is used as next DMA
 607                  * beacon alert (DBA) timer and timer2 as next
 608                  * software beacon alert. Both in 1/8TUs. */
 609                 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
 610                 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
 611                 break;
 612         }
 613
 614         /* Timer3 marks the end of our ATIM window
 615          * a zero length window is not allowed because
 616          * we 'll get no beacons */
 617         timer3 = next_beacon + 1;
 618
 619         /*
 620          * Set the beacon register and enable all timers.
 621          */
 622         /* When in AP or Mesh Point mode zero timer0 to start TSF */
 623         if (ah->opmode == NL80211_IFTYPE_AP ||
 624             ah->opmode == NL80211_IFTYPE_MESH_POINT)
 625                 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
 626
 627         ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
 628         ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
 629         ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
 630         ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
 631
 632         /* Force a TSF reset if requested and enable beacons */
 633         if (interval & AR5K_BEACON_RESET_TSF)
 634                 ath5k_hw_reset_tsf(ah);
 635
 636         ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
 637                                         AR5K_BEACON_ENABLE),
 638                                                 AR5K_BEACON);
 639
 640         /* Flush any pending BMISS interrupts on ISR by
 641          * performing a clear-on-write operation on PISR
 642          * register for the BMISS bit (writing a bit on
 643          * ISR toggles a reset for that bit and leaves
 644          * the remaining bits intact) */
 645         if (ah->ah_version == AR5K_AR5210)
 646                 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
 647         else
 648                 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
 649
 650         /* TODO: Set enhanced sleep registers on AR5212
 651          * based on vif->bss_conf params, until then
 652          * disable power save reporting.*/
 653         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
 654
 655 }
 656
 657 /**
 658  * ath5k_check_timer_win - Check if timer B is timer A + window
 659  *
 660  * @a: timer a (before b)
 661  * @b: timer b (after a)
 662  * @window: difference between a and b
 663  * @intval: timers are increased by this interval
 664  *
 665  * This helper function checks if timer B is timer A + window and covers
 666  * cases where timer A or B might have already been updated or wrapped
 667  * around (Timers are 16 bit).
 668  *
 669  * Returns true if O.K.
 670  */
 671 static inline bool
 672 ath5k_check_timer_win(int a, int b, int window, int intval)
 673 {
 674         /*
 675          * 1.) usually B should be A + window
 676          * 2.) A already updated, B not updated yet
 677          * 3.) A already updated and has wrapped around
 678          * 4.) B has wrapped around
 679          */
 680         if ((b - a == window) ||                                /* 1.) */
 681             (a - b == intval - window) ||                       /* 2.) */
 682             ((a | 0x10000) - b == intval - window) ||           /* 3.) */
 683             ((b | 0x10000) - a == window))                      /* 4.) */
 684                 return true; /* O.K. */
 685         return false;
 686 }
 687
 688 /**
 689  * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct
 690  *
 691  * @ah: The &struct ath5k_hw
 692  * @intval: beacon interval
 693  *
 694  * This is a workaround for IBSS mode:
 695  *
 696  * The need for this function arises from the fact that we have 4 separate
 697  * HW timer registers (TIMER0 - TIMER3), which are closely related to the
 698  * next beacon target time (NBTT), and that the HW updates these timers
 699  * separately based on the current TSF value. The hardware increments each
 700  * timer by the beacon interval, when the local TSF converted to TU is equal
 701  * to the value stored in the timer.
 702  *
 703  * The reception of a beacon with the same BSSID can update the local HW TSF
 704  * at any time - this is something we can't avoid. If the TSF jumps to a
 705  * time which is later than the time stored in a timer, this timer will not
 706  * be updated until the TSF in TU wraps around at 16 bit (the size of the
 707  * timers) and reaches the time which is stored in the timer.
 708  *
 709  * The problem is that these timers are closely related to TIMER0 (NBTT) and
 710  * that they define a time "window". When the TSF jumps between two timers
 711  * (e.g. ATIM and NBTT), the one in the past will be left behind (not
 712  * updated), while the one in the future will be updated every beacon
 713  * interval. This causes the window to get larger, until the TSF wraps
 714  * around as described above and the timer which was left behind gets
 715  * updated again. But - because the beacon interval is usually not an exact
 716  * divisor of the size of the timers (16 bit), an unwanted "window" between
 717  * these timers has developed!
 718  *
 719  * This is especially important with the ATIM window, because during
 720  * the ATIM window only ATIM frames and no data frames are allowed to be
 721  * sent, which creates transmission pauses after each beacon. This symptom
 722  * has been described as "ramping ping" because ping times increase linearly
 723  * for some time and then drop down again. A wrong window on the DMA beacon
 724  * timer has the same effect, so we check for these two conditions.
 725  *
 726  * Returns true if O.K.
 727  */
 728 bool
 729 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
 730 {
 731         unsigned int nbtt, atim, dma;
 732
 733         nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
 734         atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
 735         dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
 736
 737         /* NOTE: SWBA is different. Having a wrong window there does not
 738          * stop us from sending data and this condition is caught by
 739          * other means (SWBA interrupt) */
 740
 741         if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
 742             ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
 743                                   intval))
 744                 return true; /* O.K. */
 745         return false;
 746 }
 747
 748 /**
 749  * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
 750  *
 751  * @ah: The &struct ath5k_hw
 752  * @coverage_class: IEEE 802.11 coverage class number
 753  *
 754  * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
 755  */
 756 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
 757 {
 758         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 759         int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
 760         int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
 761         int cts_timeout = ack_timeout;
 762
 763         ath5k_hw_set_ifs_intervals(ah, slot_time);
 764         ath5k_hw_set_ack_timeout(ah, ack_timeout);
 765         ath5k_hw_set_cts_timeout(ah, cts_timeout);
 766
 767         ah->ah_coverage_class = coverage_class;
 768 }
 769
 770 /***************************\
 771 * Init/Start/Stop functions *
 772 \***************************/
 773
 774 /**
 775  * ath5k_hw_start_rx_pcu - Start RX engine
 776  *
 777  * @ah: The &struct ath5k_hw
 778  *
 779  * Starts RX engine on PCU so that hw can process RXed frames
 780  * (ACK etc).
 781  *
 782  * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
 783  */
 784 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
 785 {
 786         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 787 }
 788
 789 /**
 790  * at5k_hw_stop_rx_pcu - Stop RX engine
 791  *
 792  * @ah: The &struct ath5k_hw
 793  *
 794  * Stops RX engine on PCU
 795  */
 796 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
 797 {
 798         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 799 }
 800
 801 /**
 802  * ath5k_hw_set_opmode - Set PCU operating mode
 803  *
 804  * @ah: The &struct ath5k_hw
 805  * @op_mode: &enum nl80211_iftype operating mode
 806  *
 807  * Configure PCU for the various operating modes (AP/STA etc)
 808  */
 809 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
 810 {
 811         struct ath_common *common = ath5k_hw_common(ah);
 812         u32 pcu_reg, beacon_reg, low_id, high_id;
 813
 814         ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
 815
 816         /* Preserve rest settings */
 817         pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
 818         pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
 819                         | AR5K_STA_ID1_KEYSRCH_MODE
 820                         | (ah->ah_version == AR5K_AR5210 ?
 821                         (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
 822
 823         beacon_reg = 0;
 824
 825         switch (op_mode) {
 826         case NL80211_IFTYPE_ADHOC:
 827                 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
 828                 beacon_reg |= AR5K_BCR_ADHOC;
 829                 if (ah->ah_version == AR5K_AR5210)
 830                         pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
 831                 else
 832                         AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
 833                 break;
 834
 835         case NL80211_IFTYPE_AP:
 836         case NL80211_IFTYPE_MESH_POINT:
 837                 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
 838                 beacon_reg |= AR5K_BCR_AP;
 839                 if (ah->ah_version == AR5K_AR5210)
 840                         pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
 841                 else
 842                         AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
 843                 break;
 844
 845         case NL80211_IFTYPE_STATION:
 846                 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
 847                         | (ah->ah_version == AR5K_AR5210 ?
 848                                 AR5K_STA_ID1_PWR_SV : 0);
 849         case NL80211_IFTYPE_MONITOR:
 850                 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
 851                         | (ah->ah_version == AR5K_AR5210 ?
 852                                 AR5K_STA_ID1_NO_PSPOLL : 0);
 853                 break;
 854
 855         default:
 856                 return -EINVAL;
 857         }
 858
 859         /*
 860          * Set PCU registers
 861          */
 862         low_id = get_unaligned_le32(common->macaddr);
 863         high_id = get_unaligned_le16(common->macaddr + 4);
 864         ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
 865         ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
 866
 867         /*
 868          * Set Beacon Control Register on 5210
 869          */
 870         if (ah->ah_version == AR5K_AR5210)
 871                 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
 872
 873         return 0;
 874 }
 875
 876 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
 877                                                                 u8 mode)
 878 {
 879         /* Set bssid and bssid mask */
 880         ath5k_hw_set_bssid(ah);
 881
 882         /* Set PCU config */
 883         ath5k_hw_set_opmode(ah, op_mode);
 884
 885         /* Write rate duration table only on AR5212 and if
 886          * virtual interface has already been brought up
 887          * XXX: rethink this after new mode changes to
 888          * mac80211 are integrated */
 889         if (ah->ah_version == AR5K_AR5212 &&
 890                 ah->nvifs)
 891                 ath5k_hw_write_rate_duration(ah);
 892
 893         /* Set RSSI/BRSSI thresholds
 894          *
 895          * Note: If we decide to set this value
 896          * dynamically, have in mind that when AR5K_RSSI_THR
 897          * register is read it might return 0x40 if we haven't
 898          * wrote anything to it plus BMISS RSSI threshold is zeroed.
 899          * So doing a save/restore procedure here isn't the right
 900          * choice. Instead store it on ath5k_hw */
 901         ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
 902                                 AR5K_TUNE_BMISS_THRES <<
 903                                 AR5K_RSSI_THR_BMISS_S),
 904                                 AR5K_RSSI_THR);
 905
 906         /* MIC QoS support */
 907         if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
 908                 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
 909                 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
 910         }
 911
 912         /* QoS NOACK Policy */
 913         if (ah->ah_version == AR5K_AR5212) {
 914                 ath5k_hw_reg_write(ah,
 915                         AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
 916                         AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
 917                         AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
 918                         AR5K_QOS_NOACK);
 919         }
 920
 921         /* Restore slot time and ACK timeouts */
 922         if (ah->ah_coverage_class > 0)
 923                 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
 924
 925         /* Set ACK bitrate mode (see ack_rates_high) */
 926         if (ah->ah_version == AR5K_AR5212) {
 927                 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
 928                 if (ah->ah_ack_bitrate_high)
 929                         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
 930                 else
 931                         AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
 932         }
 933         return;
 934 }