1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
49 char ixgbe_driver_name
[] = "ixgbe";
50 static const char ixgbe_driver_string
[] =
51 "Intel(R) 10 Gigabit PCI Express Network Driver";
53 #define DRV_VERSION "2.0.44-k2"
54 const char ixgbe_driver_version
[] = DRV_VERSION
;
55 static char ixgbe_copyright
[] = "Copyright (c) 1999-2009 Intel Corporation.";
57 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
58 [board_82598
] = &ixgbe_82598_info
,
59 [board_82599
] = &ixgbe_82599_info
,
62 /* ixgbe_pci_tbl - PCI Device ID Table
64 * Wildcard entries (PCI_ANY_ID) should come last
65 * Last entry must be all 0s
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
70 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
71 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
112 /* required last entry */
115 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
117 #ifdef CONFIG_IXGBE_DCA
118 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
120 static struct notifier_block dca_notifier
= {
121 .notifier_call
= ixgbe_notify_dca
,
127 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
128 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
129 MODULE_LICENSE("GPL");
130 MODULE_VERSION(DRV_VERSION
);
132 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
134 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
138 /* Let firmware take over control of h/w */
139 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
140 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
141 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
144 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
148 /* Let firmware know the driver has taken over */
149 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
150 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
151 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
155 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
156 * @adapter: pointer to adapter struct
157 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
158 * @queue: queue to map the corresponding interrupt to
159 * @msix_vector: the vector to map to the corresponding queue
162 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
163 u8 queue
, u8 msix_vector
)
166 struct ixgbe_hw
*hw
= &adapter
->hw
;
167 switch (hw
->mac
.type
) {
168 case ixgbe_mac_82598EB
:
169 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
172 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
173 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
174 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
175 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
176 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
178 case ixgbe_mac_82599EB
:
179 if (direction
== -1) {
181 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
182 index
= ((queue
& 1) * 8);
183 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
184 ivar
&= ~(0xFF << index
);
185 ivar
|= (msix_vector
<< index
);
186 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
189 /* tx or rx causes */
190 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
191 index
= ((16 * (queue
& 1)) + (8 * direction
));
192 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
193 ivar
&= ~(0xFF << index
);
194 ivar
|= (msix_vector
<< index
);
195 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
203 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
208 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
209 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
210 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
212 mask
= (qmask
& 0xFFFFFFFF);
213 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
214 mask
= (qmask
>> 32);
215 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
219 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
220 struct ixgbe_tx_buffer
223 if (tx_buffer_info
->dma
) {
224 if (tx_buffer_info
->mapped_as_page
)
225 pci_unmap_page(adapter
->pdev
,
227 tx_buffer_info
->length
,
230 pci_unmap_single(adapter
->pdev
,
232 tx_buffer_info
->length
,
234 tx_buffer_info
->dma
= 0;
236 if (tx_buffer_info
->skb
) {
237 dev_kfree_skb_any(tx_buffer_info
->skb
);
238 tx_buffer_info
->skb
= NULL
;
240 tx_buffer_info
->time_stamp
= 0;
241 /* tx_buffer_info must be completely set up in the transmit path */
245 * ixgbe_tx_is_paused - check if the tx ring is paused
246 * @adapter: the ixgbe adapter
247 * @tx_ring: the corresponding tx_ring
249 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
250 * corresponding TC of this tx_ring when checking TFCS.
252 * Returns : true if paused
254 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
255 struct ixgbe_ring
*tx_ring
)
257 u32 txoff
= IXGBE_TFCS_TXOFF
;
259 #ifdef CONFIG_IXGBE_DCB
260 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
262 int reg_idx
= tx_ring
->reg_idx
;
263 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
265 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
267 txoff
= IXGBE_TFCS_TXOFF0
;
268 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
270 txoff
= IXGBE_TFCS_TXOFF
;
274 if (tc
== 2) /* TC2, TC3 */
275 tc
+= (reg_idx
- 64) >> 4;
276 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
277 tc
+= 1 + ((reg_idx
- 96) >> 3);
278 } else if (dcb_i
== 4) {
282 tc
+= (reg_idx
- 64) >> 5;
283 if (tc
== 2) /* TC2, TC3 */
284 tc
+= (reg_idx
- 96) >> 4;
291 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
294 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
295 struct ixgbe_ring
*tx_ring
,
298 struct ixgbe_hw
*hw
= &adapter
->hw
;
300 /* Detect a transmit hang in hardware, this serializes the
301 * check with the clearing of time_stamp and movement of eop */
302 adapter
->detect_tx_hung
= false;
303 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
304 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
305 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
306 /* detected Tx unit hang */
307 union ixgbe_adv_tx_desc
*tx_desc
;
308 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
309 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
311 " TDH, TDT <%x>, <%x>\n"
312 " next_to_use <%x>\n"
313 " next_to_clean <%x>\n"
314 "tx_buffer_info[next_to_clean]\n"
315 " time_stamp <%lx>\n"
317 tx_ring
->queue_index
,
318 IXGBE_READ_REG(hw
, tx_ring
->head
),
319 IXGBE_READ_REG(hw
, tx_ring
->tail
),
320 tx_ring
->next_to_use
, eop
,
321 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
328 #define IXGBE_MAX_TXD_PWR 14
329 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
331 /* Tx Descriptors needed, worst case */
332 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
333 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
334 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
335 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
337 static void ixgbe_tx_timeout(struct net_device
*netdev
);
340 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
341 * @q_vector: structure containing interrupt and ring information
342 * @tx_ring: tx ring to clean
344 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
345 struct ixgbe_ring
*tx_ring
)
347 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
348 struct net_device
*netdev
= adapter
->netdev
;
349 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
350 struct ixgbe_tx_buffer
*tx_buffer_info
;
351 unsigned int i
, eop
, count
= 0;
352 unsigned int total_bytes
= 0, total_packets
= 0;
354 i
= tx_ring
->next_to_clean
;
355 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
356 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
358 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
359 (count
< tx_ring
->work_limit
)) {
360 bool cleaned
= false;
361 for ( ; !cleaned
; count
++) {
363 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
364 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
365 cleaned
= (i
== eop
);
366 skb
= tx_buffer_info
->skb
;
368 if (cleaned
&& skb
) {
369 unsigned int segs
, bytecount
;
370 unsigned int hlen
= skb_headlen(skb
);
372 /* gso_segs is currently only valid for tcp */
373 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
375 /* adjust for FCoE Sequence Offload */
376 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
377 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
379 hlen
= skb_transport_offset(skb
) +
380 sizeof(struct fc_frame_header
) +
381 sizeof(struct fcoe_crc_eof
);
382 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
383 skb_shinfo(skb
)->gso_size
);
385 #endif /* IXGBE_FCOE */
386 /* multiply data chunks by size of headers */
387 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
388 total_packets
+= segs
;
389 total_bytes
+= bytecount
;
392 ixgbe_unmap_and_free_tx_resource(adapter
,
395 tx_desc
->wb
.status
= 0;
398 if (i
== tx_ring
->count
)
402 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
403 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
406 tx_ring
->next_to_clean
= i
;
408 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
409 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
410 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
411 /* Make sure that anybody stopping the queue after this
412 * sees the new next_to_clean.
415 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
416 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
417 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
418 ++tx_ring
->restart_queue
;
422 if (adapter
->detect_tx_hung
) {
423 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
424 /* schedule immediate reset if we believe we hung */
426 "tx hang %d detected, resetting adapter\n",
427 adapter
->tx_timeout_count
+ 1);
428 ixgbe_tx_timeout(adapter
->netdev
);
432 /* re-arm the interrupt */
433 if (count
>= tx_ring
->work_limit
)
434 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
436 tx_ring
->total_bytes
+= total_bytes
;
437 tx_ring
->total_packets
+= total_packets
;
438 tx_ring
->stats
.packets
+= total_packets
;
439 tx_ring
->stats
.bytes
+= total_bytes
;
440 return (count
< tx_ring
->work_limit
);
443 #ifdef CONFIG_IXGBE_DCA
444 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
445 struct ixgbe_ring
*rx_ring
)
449 int q
= rx_ring
- adapter
->rx_ring
;
451 if (rx_ring
->cpu
!= cpu
) {
452 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
453 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
454 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
455 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
456 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
457 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
458 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
459 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
461 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
462 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
463 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
464 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
465 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
466 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
472 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
473 struct ixgbe_ring
*tx_ring
)
477 int q
= tx_ring
- adapter
->tx_ring
;
478 struct ixgbe_hw
*hw
= &adapter
->hw
;
480 if (tx_ring
->cpu
!= cpu
) {
481 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
482 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
483 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
484 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
485 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
486 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
487 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
488 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
489 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
490 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
491 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
492 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
493 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
500 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
504 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
507 /* always use CB2 mode, difference is masked in the CB driver */
508 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
510 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
511 adapter
->tx_ring
[i
].cpu
= -1;
512 ixgbe_update_tx_dca(adapter
, &adapter
->tx_ring
[i
]);
514 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
515 adapter
->rx_ring
[i
].cpu
= -1;
516 ixgbe_update_rx_dca(adapter
, &adapter
->rx_ring
[i
]);
520 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
522 struct net_device
*netdev
= dev_get_drvdata(dev
);
523 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
524 unsigned long event
= *(unsigned long *)data
;
527 case DCA_PROVIDER_ADD
:
528 /* if we're already enabled, don't do it again */
529 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
531 if (dca_add_requester(dev
) == 0) {
532 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
533 ixgbe_setup_dca(adapter
);
536 /* Fall Through since DCA is disabled. */
537 case DCA_PROVIDER_REMOVE
:
538 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
539 dca_remove_requester(dev
);
540 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
541 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
549 #endif /* CONFIG_IXGBE_DCA */
551 * ixgbe_receive_skb - Send a completed packet up the stack
552 * @adapter: board private structure
553 * @skb: packet to send up
554 * @status: hardware indication of status of receive
555 * @rx_ring: rx descriptor ring (for a specific queue) to setup
556 * @rx_desc: rx descriptor
558 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
559 struct sk_buff
*skb
, u8 status
,
560 struct ixgbe_ring
*ring
,
561 union ixgbe_adv_rx_desc
*rx_desc
)
563 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
564 struct napi_struct
*napi
= &q_vector
->napi
;
565 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
566 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
568 skb_record_rx_queue(skb
, ring
->queue_index
);
569 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
570 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
571 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
573 napi_gro_receive(napi
, skb
);
575 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
576 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
583 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
584 * @adapter: address of board private structure
585 * @status_err: hardware indication of status of receive
586 * @skb: skb currently being received and modified
588 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
589 union ixgbe_adv_rx_desc
*rx_desc
,
592 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
594 skb
->ip_summed
= CHECKSUM_NONE
;
596 /* Rx csum disabled */
597 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
600 /* if IP and error */
601 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
602 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
603 adapter
->hw_csum_rx_error
++;
607 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
610 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
611 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
614 * 82599 errata, UDP frames with a 0 checksum can be marked as
617 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
618 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
621 adapter
->hw_csum_rx_error
++;
625 /* It must be a TCP or UDP packet with a valid checksum */
626 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
629 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
630 struct ixgbe_ring
*rx_ring
, u32 val
)
633 * Force memory writes to complete before letting h/w
634 * know there are new descriptors to fetch. (Only
635 * applicable for weak-ordered memory model archs,
639 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
643 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
644 * @adapter: address of board private structure
646 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
647 struct ixgbe_ring
*rx_ring
,
650 struct pci_dev
*pdev
= adapter
->pdev
;
651 union ixgbe_adv_rx_desc
*rx_desc
;
652 struct ixgbe_rx_buffer
*bi
;
655 i
= rx_ring
->next_to_use
;
656 bi
= &rx_ring
->rx_buffer_info
[i
];
658 while (cleaned_count
--) {
659 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
662 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
664 bi
->page
= alloc_page(GFP_ATOMIC
);
666 adapter
->alloc_rx_page_failed
++;
671 /* use a half page if we're re-using */
672 bi
->page_offset
^= (PAGE_SIZE
/ 2);
675 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
683 /* netdev_alloc_skb reserves 32 bytes up front!! */
684 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
685 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
688 adapter
->alloc_rx_buff_failed
++;
692 /* advance the data pointer to the next cache line */
693 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
697 bi
->dma
= pci_map_single(pdev
, skb
->data
,
701 /* Refresh the desc even if buffer_addrs didn't change because
702 * each write-back erases this info. */
703 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
704 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
705 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
707 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
711 if (i
== rx_ring
->count
)
713 bi
= &rx_ring
->rx_buffer_info
[i
];
717 if (rx_ring
->next_to_use
!= i
) {
718 rx_ring
->next_to_use
= i
;
720 i
= (rx_ring
->count
- 1);
722 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
726 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
728 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
731 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
733 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
736 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
738 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
739 IXGBE_RXDADV_RSCCNT_MASK
) >>
740 IXGBE_RXDADV_RSCCNT_SHIFT
;
744 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
745 * @skb: pointer to the last skb in the rsc queue
746 * @count: pointer to number of packets coalesced in this context
748 * This function changes a queue full of hw rsc buffers into a completed
749 * packet. It uses the ->prev pointers to find the first packet and then
750 * turns it into the frag list owner.
752 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
755 unsigned int frag_list_size
= 0;
758 struct sk_buff
*prev
= skb
->prev
;
759 frag_list_size
+= skb
->len
;
765 skb_shinfo(skb
)->frag_list
= skb
->next
;
767 skb
->len
+= frag_list_size
;
768 skb
->data_len
+= frag_list_size
;
769 skb
->truesize
+= frag_list_size
;
773 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
774 struct ixgbe_ring
*rx_ring
,
775 int *work_done
, int work_to_do
)
777 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
778 struct net_device
*netdev
= adapter
->netdev
;
779 struct pci_dev
*pdev
= adapter
->pdev
;
780 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
781 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
783 unsigned int i
, rsc_count
= 0;
786 bool cleaned
= false;
787 int cleaned_count
= 0;
788 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
791 #endif /* IXGBE_FCOE */
793 i
= rx_ring
->next_to_clean
;
794 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
795 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
796 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
798 while (staterr
& IXGBE_RXD_STAT_DD
) {
800 if (*work_done
>= work_to_do
)
804 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
805 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
806 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
807 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
808 if (len
> IXGBE_RX_HDR_SIZE
)
809 len
= IXGBE_RX_HDR_SIZE
;
810 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
812 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
816 skb
= rx_buffer_info
->skb
;
818 rx_buffer_info
->skb
= NULL
;
820 if (rx_buffer_info
->dma
) {
821 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
824 rx_buffer_info
->dma
= 0;
829 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
830 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
831 rx_buffer_info
->page_dma
= 0;
832 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
833 rx_buffer_info
->page
,
834 rx_buffer_info
->page_offset
,
837 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
838 (page_count(rx_buffer_info
->page
) != 1))
839 rx_buffer_info
->page
= NULL
;
841 get_page(rx_buffer_info
->page
);
843 skb
->len
+= upper_len
;
844 skb
->data_len
+= upper_len
;
845 skb
->truesize
+= upper_len
;
849 if (i
== rx_ring
->count
)
852 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
856 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
857 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
860 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
861 IXGBE_RXDADV_NEXTP_SHIFT
;
862 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
864 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
867 if (staterr
& IXGBE_RXD_STAT_EOP
) {
869 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
870 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
871 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
872 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
874 rx_ring
->rsc_count
++;
875 rx_ring
->rsc_flush
++;
877 rx_ring
->stats
.packets
++;
878 rx_ring
->stats
.bytes
+= skb
->len
;
880 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
881 rx_buffer_info
->skb
= next_buffer
->skb
;
882 rx_buffer_info
->dma
= next_buffer
->dma
;
883 next_buffer
->skb
= skb
;
884 next_buffer
->dma
= 0;
886 skb
->next
= next_buffer
->skb
;
887 skb
->next
->prev
= skb
;
889 rx_ring
->non_eop_descs
++;
893 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
894 dev_kfree_skb_irq(skb
);
898 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
900 /* probably a little skewed due to removing CRC */
901 total_rx_bytes
+= skb
->len
;
904 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
906 /* if ddp, not passing to ULD unless for FCP_RSP or error */
907 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
908 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
912 #endif /* IXGBE_FCOE */
913 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
916 rx_desc
->wb
.upper
.status_error
= 0;
918 /* return some buffers to hardware, one at a time is too slow */
919 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
920 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
924 /* use prefetched values */
926 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
928 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
931 rx_ring
->next_to_clean
= i
;
932 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
935 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
938 /* include DDPed FCoE data */
942 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
943 sizeof(struct fc_frame_header
) -
944 sizeof(struct fcoe_crc_eof
);
947 total_rx_bytes
+= ddp_bytes
;
948 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
950 #endif /* IXGBE_FCOE */
952 rx_ring
->total_packets
+= total_rx_packets
;
953 rx_ring
->total_bytes
+= total_rx_bytes
;
954 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
955 netdev
->stats
.rx_packets
+= total_rx_packets
;
960 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
962 * ixgbe_configure_msix - Configure MSI-X hardware
963 * @adapter: board private structure
965 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
968 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
970 struct ixgbe_q_vector
*q_vector
;
971 int i
, j
, q_vectors
, v_idx
, r_idx
;
974 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
977 * Populate the IVAR table and set the ITR values to the
978 * corresponding register.
980 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
981 q_vector
= adapter
->q_vector
[v_idx
];
982 /* XXX for_each_bit(...) */
983 r_idx
= find_first_bit(q_vector
->rxr_idx
,
984 adapter
->num_rx_queues
);
986 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
987 j
= adapter
->rx_ring
[r_idx
].reg_idx
;
988 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
989 r_idx
= find_next_bit(q_vector
->rxr_idx
,
990 adapter
->num_rx_queues
,
993 r_idx
= find_first_bit(q_vector
->txr_idx
,
994 adapter
->num_tx_queues
);
996 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
997 j
= adapter
->tx_ring
[r_idx
].reg_idx
;
998 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
999 r_idx
= find_next_bit(q_vector
->txr_idx
,
1000 adapter
->num_tx_queues
,
1004 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1006 q_vector
->eitr
= adapter
->tx_eitr_param
;
1007 else if (q_vector
->rxr_count
)
1009 q_vector
->eitr
= adapter
->rx_eitr_param
;
1011 ixgbe_write_eitr(q_vector
);
1014 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1015 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1017 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1018 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1019 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1021 /* set up to autoclear timer, and the vectors */
1022 mask
= IXGBE_EIMS_ENABLE_MASK
;
1023 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1024 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1027 enum latency_range
{
1031 latency_invalid
= 255
1035 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1036 * @adapter: pointer to adapter
1037 * @eitr: eitr setting (ints per sec) to give last timeslice
1038 * @itr_setting: current throttle rate in ints/second
1039 * @packets: the number of packets during this measurement interval
1040 * @bytes: the number of bytes during this measurement interval
1042 * Stores a new ITR value based on packets and byte
1043 * counts during the last interrupt. The advantage of per interrupt
1044 * computation is faster updates and more accurate ITR for the current
1045 * traffic pattern. Constants in this function were computed
1046 * based on theoretical maximum wire speed and thresholds were set based
1047 * on testing data as well as attempting to minimize response time
1048 * while increasing bulk throughput.
1049 * this functionality is controlled by the InterruptThrottleRate module
1050 * parameter (see ixgbe_param.c)
1052 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1053 u32 eitr
, u8 itr_setting
,
1054 int packets
, int bytes
)
1056 unsigned int retval
= itr_setting
;
1061 goto update_itr_done
;
1064 /* simple throttlerate management
1065 * 0-20MB/s lowest (100000 ints/s)
1066 * 20-100MB/s low (20000 ints/s)
1067 * 100-1249MB/s bulk (8000 ints/s)
1069 /* what was last interrupt timeslice? */
1070 timepassed_us
= 1000000/eitr
;
1071 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1073 switch (itr_setting
) {
1074 case lowest_latency
:
1075 if (bytes_perint
> adapter
->eitr_low
)
1076 retval
= low_latency
;
1079 if (bytes_perint
> adapter
->eitr_high
)
1080 retval
= bulk_latency
;
1081 else if (bytes_perint
<= adapter
->eitr_low
)
1082 retval
= lowest_latency
;
1085 if (bytes_perint
<= adapter
->eitr_high
)
1086 retval
= low_latency
;
1095 * ixgbe_write_eitr - write EITR register in hardware specific way
1096 * @q_vector: structure containing interrupt and ring information
1098 * This function is made to be called by ethtool and by the driver
1099 * when it needs to update EITR registers at runtime. Hardware
1100 * specific quirks/differences are taken care of here.
1102 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1104 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1105 struct ixgbe_hw
*hw
= &adapter
->hw
;
1106 int v_idx
= q_vector
->v_idx
;
1107 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1109 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1110 /* must write high and low 16 bits to reset counter */
1111 itr_reg
|= (itr_reg
<< 16);
1112 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1114 * set the WDIS bit to not clear the timer bits and cause an
1115 * immediate assertion of the interrupt
1117 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1119 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1122 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1124 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1126 u8 current_itr
, ret_itr
;
1128 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1130 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1131 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1132 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1133 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1135 tx_ring
->total_packets
,
1136 tx_ring
->total_bytes
);
1137 /* if the result for this queue would decrease interrupt
1138 * rate for this vector then use that result */
1139 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1140 q_vector
->tx_itr
- 1 : ret_itr
);
1141 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1145 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1146 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1147 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1148 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1150 rx_ring
->total_packets
,
1151 rx_ring
->total_bytes
);
1152 /* if the result for this queue would decrease interrupt
1153 * rate for this vector then use that result */
1154 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1155 q_vector
->rx_itr
- 1 : ret_itr
);
1156 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1160 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1162 switch (current_itr
) {
1163 /* counts and packets in update_itr are dependent on these numbers */
1164 case lowest_latency
:
1168 new_itr
= 20000; /* aka hwitr = ~200 */
1176 if (new_itr
!= q_vector
->eitr
) {
1177 /* do an exponential smoothing */
1178 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1180 /* save the algorithm value here, not the smoothed one */
1181 q_vector
->eitr
= new_itr
;
1183 ixgbe_write_eitr(q_vector
);
1189 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1191 struct ixgbe_hw
*hw
= &adapter
->hw
;
1193 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1194 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1195 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1196 /* write to clear the interrupt */
1197 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1201 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1203 struct ixgbe_hw
*hw
= &adapter
->hw
;
1205 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1206 /* Clear the interrupt */
1207 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1208 schedule_work(&adapter
->multispeed_fiber_task
);
1209 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1210 /* Clear the interrupt */
1211 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1212 schedule_work(&adapter
->sfp_config_module_task
);
1214 /* Interrupt isn't for us... */
1219 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1221 struct ixgbe_hw
*hw
= &adapter
->hw
;
1224 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1225 adapter
->link_check_timeout
= jiffies
;
1226 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1227 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1228 IXGBE_WRITE_FLUSH(hw
);
1229 schedule_work(&adapter
->watchdog_task
);
1233 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1235 struct net_device
*netdev
= data
;
1236 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1237 struct ixgbe_hw
*hw
= &adapter
->hw
;
1241 * Workaround for Silicon errata. Use clear-by-write instead
1242 * of clear-by-read. Reading with EICS will return the
1243 * interrupt causes without clearing, which later be done
1244 * with the write to EICR.
1246 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1247 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1249 if (eicr
& IXGBE_EICR_LSC
)
1250 ixgbe_check_lsc(adapter
);
1252 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1253 ixgbe_check_fan_failure(adapter
, eicr
);
1255 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1256 ixgbe_check_sfp_event(adapter
, eicr
);
1258 /* Handle Flow Director Full threshold interrupt */
1259 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1261 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1262 /* Disable transmits before FDIR Re-initialization */
1263 netif_tx_stop_all_queues(netdev
);
1264 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1265 struct ixgbe_ring
*tx_ring
=
1266 &adapter
->tx_ring
[i
];
1267 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1268 &tx_ring
->reinit_state
))
1269 schedule_work(&adapter
->fdir_reinit_task
);
1273 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1274 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1279 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1284 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1285 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1286 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1288 mask
= (qmask
& 0xFFFFFFFF);
1289 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1290 mask
= (qmask
>> 32);
1291 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1293 /* skip the flush */
1296 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1301 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1302 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1303 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1305 mask
= (qmask
& 0xFFFFFFFF);
1306 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1307 mask
= (qmask
>> 32);
1308 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1310 /* skip the flush */
1313 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1315 struct ixgbe_q_vector
*q_vector
= data
;
1316 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1317 struct ixgbe_ring
*tx_ring
;
1320 if (!q_vector
->txr_count
)
1323 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1324 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1325 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1326 tx_ring
->total_bytes
= 0;
1327 tx_ring
->total_packets
= 0;
1328 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1332 /* EIAM disabled interrupts (on this vector) for us */
1333 napi_schedule(&q_vector
->napi
);
1339 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1341 * @data: pointer to our q_vector struct for this interrupt vector
1343 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1345 struct ixgbe_q_vector
*q_vector
= data
;
1346 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1347 struct ixgbe_ring
*rx_ring
;
1351 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1352 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1353 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1354 rx_ring
->total_bytes
= 0;
1355 rx_ring
->total_packets
= 0;
1356 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1360 if (!q_vector
->rxr_count
)
1363 /* disable interrupts on this vector only */
1364 /* EIAM disabled interrupts (on this vector) for us */
1365 napi_schedule(&q_vector
->napi
);
1370 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1372 struct ixgbe_q_vector
*q_vector
= data
;
1373 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1374 struct ixgbe_ring
*ring
;
1378 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1381 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1382 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1383 ring
= &(adapter
->tx_ring
[r_idx
]);
1384 ring
->total_bytes
= 0;
1385 ring
->total_packets
= 0;
1386 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1390 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1391 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1392 ring
= &(adapter
->rx_ring
[r_idx
]);
1393 ring
->total_bytes
= 0;
1394 ring
->total_packets
= 0;
1395 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1399 /* EIAM disabled interrupts (on this vector) for us */
1400 napi_schedule(&q_vector
->napi
);
1406 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1407 * @napi: napi struct with our devices info in it
1408 * @budget: amount of work driver is allowed to do this pass, in packets
1410 * This function is optimized for cleaning one queue only on a single
1413 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1415 struct ixgbe_q_vector
*q_vector
=
1416 container_of(napi
, struct ixgbe_q_vector
, napi
);
1417 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1418 struct ixgbe_ring
*rx_ring
= NULL
;
1422 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1423 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1424 #ifdef CONFIG_IXGBE_DCA
1425 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1426 ixgbe_update_rx_dca(adapter
, rx_ring
);
1429 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1431 /* If all Rx work done, exit the polling mode */
1432 if (work_done
< budget
) {
1433 napi_complete(napi
);
1434 if (adapter
->rx_itr_setting
& 1)
1435 ixgbe_set_itr_msix(q_vector
);
1436 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1437 ixgbe_irq_enable_queues(adapter
,
1438 ((u64
)1 << q_vector
->v_idx
));
1445 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1446 * @napi: napi struct with our devices info in it
1447 * @budget: amount of work driver is allowed to do this pass, in packets
1449 * This function will clean more than one rx queue associated with a
1452 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1454 struct ixgbe_q_vector
*q_vector
=
1455 container_of(napi
, struct ixgbe_q_vector
, napi
);
1456 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1457 struct ixgbe_ring
*ring
= NULL
;
1458 int work_done
= 0, i
;
1460 bool tx_clean_complete
= true;
1462 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1463 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1464 ring
= &(adapter
->tx_ring
[r_idx
]);
1465 #ifdef CONFIG_IXGBE_DCA
1466 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1467 ixgbe_update_tx_dca(adapter
, ring
);
1469 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1470 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1474 /* attempt to distribute budget to each queue fairly, but don't allow
1475 * the budget to go below 1 because we'll exit polling */
1476 budget
/= (q_vector
->rxr_count
?: 1);
1477 budget
= max(budget
, 1);
1478 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1479 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1480 ring
= &(adapter
->rx_ring
[r_idx
]);
1481 #ifdef CONFIG_IXGBE_DCA
1482 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1483 ixgbe_update_rx_dca(adapter
, ring
);
1485 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1486 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1490 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1491 ring
= &(adapter
->rx_ring
[r_idx
]);
1492 /* If all Rx work done, exit the polling mode */
1493 if (work_done
< budget
) {
1494 napi_complete(napi
);
1495 if (adapter
->rx_itr_setting
& 1)
1496 ixgbe_set_itr_msix(q_vector
);
1497 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1498 ixgbe_irq_enable_queues(adapter
,
1499 ((u64
)1 << q_vector
->v_idx
));
1507 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1508 * @napi: napi struct with our devices info in it
1509 * @budget: amount of work driver is allowed to do this pass, in packets
1511 * This function is optimized for cleaning one queue only on a single
1514 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1516 struct ixgbe_q_vector
*q_vector
=
1517 container_of(napi
, struct ixgbe_q_vector
, napi
);
1518 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1519 struct ixgbe_ring
*tx_ring
= NULL
;
1523 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1524 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1525 #ifdef CONFIG_IXGBE_DCA
1526 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1527 ixgbe_update_tx_dca(adapter
, tx_ring
);
1530 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1533 /* If all Tx work done, exit the polling mode */
1534 if (work_done
< budget
) {
1535 napi_complete(napi
);
1536 if (adapter
->tx_itr_setting
& 1)
1537 ixgbe_set_itr_msix(q_vector
);
1538 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1539 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1545 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1548 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1550 set_bit(r_idx
, q_vector
->rxr_idx
);
1551 q_vector
->rxr_count
++;
1554 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1557 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1559 set_bit(t_idx
, q_vector
->txr_idx
);
1560 q_vector
->txr_count
++;
1564 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1565 * @adapter: board private structure to initialize
1566 * @vectors: allotted vector count for descriptor rings
1568 * This function maps descriptor rings to the queue-specific vectors
1569 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1570 * one vector per ring/queue, but on a constrained vector budget, we
1571 * group the rings as "efficiently" as possible. You would add new
1572 * mapping configurations in here.
1574 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1578 int rxr_idx
= 0, txr_idx
= 0;
1579 int rxr_remaining
= adapter
->num_rx_queues
;
1580 int txr_remaining
= adapter
->num_tx_queues
;
1585 /* No mapping required if MSI-X is disabled. */
1586 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1590 * The ideal configuration...
1591 * We have enough vectors to map one per queue.
1593 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1594 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1595 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1597 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1598 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1604 * If we don't have enough vectors for a 1-to-1
1605 * mapping, we'll have to group them so there are
1606 * multiple queues per vector.
1608 /* Re-adjusting *qpv takes care of the remainder. */
1609 for (i
= v_start
; i
< vectors
; i
++) {
1610 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1611 for (j
= 0; j
< rqpv
; j
++) {
1612 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1617 for (i
= v_start
; i
< vectors
; i
++) {
1618 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1619 for (j
= 0; j
< tqpv
; j
++) {
1620 map_vector_to_txq(adapter
, i
, txr_idx
);
1631 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1632 * @adapter: board private structure
1634 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1635 * interrupts from the kernel.
1637 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1639 struct net_device
*netdev
= adapter
->netdev
;
1640 irqreturn_t (*handler
)(int, void *);
1641 int i
, vector
, q_vectors
, err
;
1644 /* Decrement for Other and TCP Timer vectors */
1645 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1647 /* Map the Tx/Rx rings to the vectors we were allotted. */
1648 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1652 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1653 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1654 &ixgbe_msix_clean_many)
1655 for (vector
= 0; vector
< q_vectors
; vector
++) {
1656 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1658 if(handler
== &ixgbe_msix_clean_rx
) {
1659 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1660 netdev
->name
, "rx", ri
++);
1662 else if(handler
== &ixgbe_msix_clean_tx
) {
1663 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1664 netdev
->name
, "tx", ti
++);
1667 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1668 netdev
->name
, "TxRx", vector
);
1670 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1671 handler
, 0, adapter
->name
[vector
],
1672 adapter
->q_vector
[vector
]);
1675 "request_irq failed for MSIX interrupt "
1676 "Error: %d\n", err
);
1677 goto free_queue_irqs
;
1681 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1682 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1683 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1686 "request_irq for msix_lsc failed: %d\n", err
);
1687 goto free_queue_irqs
;
1693 for (i
= vector
- 1; i
>= 0; i
--)
1694 free_irq(adapter
->msix_entries
[--vector
].vector
,
1695 adapter
->q_vector
[i
]);
1696 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1697 pci_disable_msix(adapter
->pdev
);
1698 kfree(adapter
->msix_entries
);
1699 adapter
->msix_entries
= NULL
;
1704 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1706 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1708 u32 new_itr
= q_vector
->eitr
;
1709 struct ixgbe_ring
*rx_ring
= &adapter
->rx_ring
[0];
1710 struct ixgbe_ring
*tx_ring
= &adapter
->tx_ring
[0];
1712 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1714 tx_ring
->total_packets
,
1715 tx_ring
->total_bytes
);
1716 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1718 rx_ring
->total_packets
,
1719 rx_ring
->total_bytes
);
1721 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1723 switch (current_itr
) {
1724 /* counts and packets in update_itr are dependent on these numbers */
1725 case lowest_latency
:
1729 new_itr
= 20000; /* aka hwitr = ~200 */
1738 if (new_itr
!= q_vector
->eitr
) {
1739 /* do an exponential smoothing */
1740 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1742 /* save the algorithm value here, not the smoothed one */
1743 q_vector
->eitr
= new_itr
;
1745 ixgbe_write_eitr(q_vector
);
1752 * ixgbe_irq_enable - Enable default interrupt generation settings
1753 * @adapter: board private structure
1755 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1759 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1760 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1761 mask
|= IXGBE_EIMS_GPI_SDP1
;
1762 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1763 mask
|= IXGBE_EIMS_ECC
;
1764 mask
|= IXGBE_EIMS_GPI_SDP1
;
1765 mask
|= IXGBE_EIMS_GPI_SDP2
;
1767 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
1768 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
1769 mask
|= IXGBE_EIMS_FLOW_DIR
;
1771 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1772 ixgbe_irq_enable_queues(adapter
, ~0);
1773 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1777 * ixgbe_intr - legacy mode Interrupt Handler
1778 * @irq: interrupt number
1779 * @data: pointer to a network interface device structure
1781 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1783 struct net_device
*netdev
= data
;
1784 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1785 struct ixgbe_hw
*hw
= &adapter
->hw
;
1786 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1790 * Workaround for silicon errata. Mask the interrupts
1791 * before the read of EICR.
1793 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1795 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1796 * therefore no explict interrupt disable is necessary */
1797 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1799 /* shared interrupt alert!
1800 * make sure interrupts are enabled because the read will
1801 * have disabled interrupts due to EIAM */
1802 ixgbe_irq_enable(adapter
);
1803 return IRQ_NONE
; /* Not our interrupt */
1806 if (eicr
& IXGBE_EICR_LSC
)
1807 ixgbe_check_lsc(adapter
);
1809 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1810 ixgbe_check_sfp_event(adapter
, eicr
);
1812 ixgbe_check_fan_failure(adapter
, eicr
);
1814 if (napi_schedule_prep(&(q_vector
->napi
))) {
1815 adapter
->tx_ring
[0].total_packets
= 0;
1816 adapter
->tx_ring
[0].total_bytes
= 0;
1817 adapter
->rx_ring
[0].total_packets
= 0;
1818 adapter
->rx_ring
[0].total_bytes
= 0;
1819 /* would disable interrupts here but EIAM disabled it */
1820 __napi_schedule(&(q_vector
->napi
));
1826 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1828 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1830 for (i
= 0; i
< q_vectors
; i
++) {
1831 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1832 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1833 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1834 q_vector
->rxr_count
= 0;
1835 q_vector
->txr_count
= 0;
1840 * ixgbe_request_irq - initialize interrupts
1841 * @adapter: board private structure
1843 * Attempts to configure interrupts using the best available
1844 * capabilities of the hardware and kernel.
1846 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1848 struct net_device
*netdev
= adapter
->netdev
;
1851 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1852 err
= ixgbe_request_msix_irqs(adapter
);
1853 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1854 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
1855 netdev
->name
, netdev
);
1857 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
1858 netdev
->name
, netdev
);
1862 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1867 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1869 struct net_device
*netdev
= adapter
->netdev
;
1871 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1874 q_vectors
= adapter
->num_msix_vectors
;
1877 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1880 for (; i
>= 0; i
--) {
1881 free_irq(adapter
->msix_entries
[i
].vector
,
1882 adapter
->q_vector
[i
]);
1885 ixgbe_reset_q_vectors(adapter
);
1887 free_irq(adapter
->pdev
->irq
, netdev
);
1892 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1893 * @adapter: board private structure
1895 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1897 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1898 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1900 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1901 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1902 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1904 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1905 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1907 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1908 synchronize_irq(adapter
->msix_entries
[i
].vector
);
1910 synchronize_irq(adapter
->pdev
->irq
);
1915 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1918 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
1920 struct ixgbe_hw
*hw
= &adapter
->hw
;
1922 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
1923 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
1925 ixgbe_set_ivar(adapter
, 0, 0, 0);
1926 ixgbe_set_ivar(adapter
, 1, 0, 0);
1928 map_vector_to_rxq(adapter
, 0, 0);
1929 map_vector_to_txq(adapter
, 0, 0);
1931 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
1935 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1936 * @adapter: board private structure
1938 * Configure the Tx unit of the MAC after a reset.
1940 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
1943 struct ixgbe_hw
*hw
= &adapter
->hw
;
1944 u32 i
, j
, tdlen
, txctrl
;
1946 /* Setup the HW Tx Head and Tail descriptor pointers */
1947 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1948 struct ixgbe_ring
*ring
= &adapter
->tx_ring
[i
];
1951 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
1952 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
1953 (tdba
& DMA_BIT_MASK(32)));
1954 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
1955 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
1956 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
1957 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
1958 adapter
->tx_ring
[i
].head
= IXGBE_TDH(j
);
1959 adapter
->tx_ring
[i
].tail
= IXGBE_TDT(j
);
1961 * Disable Tx Head Writeback RO bit, since this hoses
1962 * bookkeeping if things aren't delivered in order.
1964 switch (hw
->mac
.type
) {
1965 case ixgbe_mac_82598EB
:
1966 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
1968 case ixgbe_mac_82599EB
:
1970 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
1973 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
1974 switch (hw
->mac
.type
) {
1975 case ixgbe_mac_82598EB
:
1976 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
1978 case ixgbe_mac_82599EB
:
1980 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
1985 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1988 /* disable the arbiter while setting MTQC */
1989 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
1990 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
1991 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
1993 /* We enable 8 traffic classes, DCB only */
1994 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
1995 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, (IXGBE_MTQC_RT_ENA
|
1996 IXGBE_MTQC_8TC_8TQ
));
1998 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2000 /* re-eable the arbiter */
2001 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2002 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2006 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2008 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2009 struct ixgbe_ring
*rx_ring
)
2013 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2015 index
= rx_ring
->reg_idx
;
2016 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2018 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2019 index
= index
& mask
;
2021 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2023 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2024 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2026 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2027 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2029 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2030 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2031 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2033 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2035 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2037 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2038 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2039 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2042 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2045 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2050 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2053 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2054 #ifdef CONFIG_IXGBE_DCB
2055 | IXGBE_FLAG_DCB_ENABLED
2060 case (IXGBE_FLAG_RSS_ENABLED
):
2061 mrqc
= IXGBE_MRQC_RSSEN
;
2063 #ifdef CONFIG_IXGBE_DCB
2064 case (IXGBE_FLAG_DCB_ENABLED
):
2065 mrqc
= IXGBE_MRQC_RT8TCEN
;
2067 #endif /* CONFIG_IXGBE_DCB */
2076 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2077 * @adapter: address of board private structure
2078 * @index: index of ring to set
2080 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2082 struct ixgbe_ring
*rx_ring
;
2083 struct ixgbe_hw
*hw
= &adapter
->hw
;
2088 rx_ring
= &adapter
->rx_ring
[index
];
2089 j
= rx_ring
->reg_idx
;
2090 rx_buf_len
= rx_ring
->rx_buf_len
;
2091 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2092 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2094 * we must limit the number of descriptors so that the
2095 * total size of max desc * buf_len is not greater
2098 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2099 #if (MAX_SKB_FRAGS > 16)
2100 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2101 #elif (MAX_SKB_FRAGS > 8)
2102 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2103 #elif (MAX_SKB_FRAGS > 4)
2104 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2106 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2109 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2110 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2111 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2112 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2114 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2116 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2120 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2121 * @adapter: board private structure
2123 * Configure the Rx unit of the MAC after a reset.
2125 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2128 struct ixgbe_hw
*hw
= &adapter
->hw
;
2129 struct ixgbe_ring
*rx_ring
;
2130 struct net_device
*netdev
= adapter
->netdev
;
2131 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2133 u32 rdlen
, rxctrl
, rxcsum
;
2134 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2135 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2136 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2138 u32 reta
= 0, mrqc
= 0;
2142 /* Decide whether to use packet split mode or not */
2143 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2145 /* Set the RX buffer length according to the mode */
2146 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2147 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2148 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2149 /* PSRTYPE must be initialized in 82599 */
2150 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2151 IXGBE_PSRTYPE_UDPHDR
|
2152 IXGBE_PSRTYPE_IPV4HDR
|
2153 IXGBE_PSRTYPE_IPV6HDR
|
2154 IXGBE_PSRTYPE_L2HDR
;
2155 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(0), psrtype
);
2158 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2159 (netdev
->mtu
<= ETH_DATA_LEN
))
2160 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2162 rx_buf_len
= ALIGN(max_frame
, 1024);
2165 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2166 fctrl
|= IXGBE_FCTRL_BAM
;
2167 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2168 fctrl
|= IXGBE_FCTRL_PMCF
;
2169 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2171 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2172 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2173 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2175 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2177 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2178 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2180 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2182 rdlen
= adapter
->rx_ring
[0].count
* sizeof(union ixgbe_adv_rx_desc
);
2183 /* disable receives while setting up the descriptors */
2184 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2185 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2188 * Setup the HW Rx Head and Tail Descriptor Pointers and
2189 * the Base and Length of the Rx Descriptor Ring
2191 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2192 rx_ring
= &adapter
->rx_ring
[i
];
2193 rdba
= rx_ring
->dma
;
2194 j
= rx_ring
->reg_idx
;
2195 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2196 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2197 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2198 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2199 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2200 rx_ring
->head
= IXGBE_RDH(j
);
2201 rx_ring
->tail
= IXGBE_RDT(j
);
2202 rx_ring
->rx_buf_len
= rx_buf_len
;
2204 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2205 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2207 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2210 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2211 struct ixgbe_ring_feature
*f
;
2212 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2213 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2214 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2215 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2216 rx_ring
->rx_buf_len
=
2217 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2221 #endif /* IXGBE_FCOE */
2222 ixgbe_configure_srrctl(adapter
, rx_ring
);
2225 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2227 * For VMDq support of different descriptor types or
2228 * buffer sizes through the use of multiple SRRCTL
2229 * registers, RDRXCTL.MVMEN must be set to 1
2231 * also, the manual doesn't mention it clearly but DCA hints
2232 * will only use queue 0's tags unless this bit is set. Side
2233 * effects of setting this bit are only that SRRCTL must be
2234 * fully programmed [0..15]
2236 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2237 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2238 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2241 /* Program MRQC for the distribution of queues */
2242 mrqc
= ixgbe_setup_mrqc(adapter
);
2244 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2245 /* Fill out redirection table */
2246 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2247 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2249 /* reta = 4-byte sliding window of
2250 * 0x00..(indices-1)(indices-1)00..etc. */
2251 reta
= (reta
<< 8) | (j
* 0x11);
2253 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2256 /* Fill out hash function seeds */
2257 for (i
= 0; i
< 10; i
++)
2258 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2260 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2261 mrqc
|= IXGBE_MRQC_RSSEN
;
2262 /* Perform hash on these packet types */
2263 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2264 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2265 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2266 | IXGBE_MRQC_RSS_FIELD_IPV6
2267 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2268 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2270 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2272 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2274 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2275 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2276 /* Disable indicating checksum in descriptor, enables
2278 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2280 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2281 /* Enable IPv4 payload checksum for UDP fragments
2282 * if PCSD is not set */
2283 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2286 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2288 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2289 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2290 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2291 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2292 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2295 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2296 /* Enable 82599 HW-RSC */
2297 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2298 ixgbe_configure_rscctl(adapter
, i
);
2300 /* Disable RSC for ACK packets */
2301 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2302 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2306 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2308 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2309 struct ixgbe_hw
*hw
= &adapter
->hw
;
2311 /* add VID to filter table */
2312 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, true);
2315 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2317 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2318 struct ixgbe_hw
*hw
= &adapter
->hw
;
2320 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2321 ixgbe_irq_disable(adapter
);
2323 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2325 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2326 ixgbe_irq_enable(adapter
);
2328 /* remove VID from filter table */
2329 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, 0, false);
2332 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2333 struct vlan_group
*grp
)
2335 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2339 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2340 ixgbe_irq_disable(adapter
);
2341 adapter
->vlgrp
= grp
;
2344 * For a DCB driver, always enable VLAN tag stripping so we can
2345 * still receive traffic from a DCB-enabled host even if we're
2348 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2350 /* Disable CFI check */
2351 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2353 /* enable VLAN tag stripping */
2354 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2355 ctrl
|= IXGBE_VLNCTRL_VME
;
2356 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2357 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2359 j
= adapter
->rx_ring
[i
].reg_idx
;
2360 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2361 ctrl
|= IXGBE_RXDCTL_VME
;
2362 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2366 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2368 ixgbe_vlan_rx_add_vid(netdev
, 0);
2370 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2371 ixgbe_irq_enable(adapter
);
2374 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2376 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2378 if (adapter
->vlgrp
) {
2380 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2381 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2383 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2388 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2390 struct dev_mc_list
*mc_ptr
;
2391 u8
*addr
= *mc_addr_ptr
;
2394 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2396 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2398 *mc_addr_ptr
= NULL
;
2404 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2405 * @netdev: network interface device structure
2407 * The set_rx_method entry point is called whenever the unicast/multicast
2408 * address list or the network interface flags are updated. This routine is
2409 * responsible for configuring the hardware for proper unicast, multicast and
2412 static void ixgbe_set_rx_mode(struct net_device
*netdev
)
2414 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2415 struct ixgbe_hw
*hw
= &adapter
->hw
;
2417 u8
*addr_list
= NULL
;
2420 /* Check for Promiscuous and All Multicast modes */
2422 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2423 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2425 if (netdev
->flags
& IFF_PROMISC
) {
2426 hw
->addr_ctrl
.user_set_promisc
= 1;
2427 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2428 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2430 if (netdev
->flags
& IFF_ALLMULTI
) {
2431 fctrl
|= IXGBE_FCTRL_MPE
;
2432 fctrl
&= ~IXGBE_FCTRL_UPE
;
2434 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2436 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2437 hw
->addr_ctrl
.user_set_promisc
= 0;
2440 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2441 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2443 /* reprogram secondary unicast list */
2444 hw
->mac
.ops
.update_uc_addr_list(hw
, &netdev
->uc
.list
);
2446 /* reprogram multicast list */
2447 addr_count
= netdev
->mc_count
;
2449 addr_list
= netdev
->mc_list
->dmi_addr
;
2450 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2451 ixgbe_addr_list_itr
);
2454 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2457 struct ixgbe_q_vector
*q_vector
;
2458 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2460 /* legacy and MSI only use one vector */
2461 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2464 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2465 struct napi_struct
*napi
;
2466 q_vector
= adapter
->q_vector
[q_idx
];
2467 napi
= &q_vector
->napi
;
2468 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2469 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2470 if (q_vector
->txr_count
== 1)
2471 napi
->poll
= &ixgbe_clean_txonly
;
2472 else if (q_vector
->rxr_count
== 1)
2473 napi
->poll
= &ixgbe_clean_rxonly
;
2481 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2484 struct ixgbe_q_vector
*q_vector
;
2485 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2487 /* legacy and MSI only use one vector */
2488 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2491 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2492 q_vector
= adapter
->q_vector
[q_idx
];
2493 napi_disable(&q_vector
->napi
);
2497 #ifdef CONFIG_IXGBE_DCB
2499 * ixgbe_configure_dcb - Configure DCB hardware
2500 * @adapter: ixgbe adapter struct
2502 * This is called by the driver on open to configure the DCB hardware.
2503 * This is also called by the gennetlink interface when reconfiguring
2506 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2508 struct ixgbe_hw
*hw
= &adapter
->hw
;
2509 u32 txdctl
, vlnctrl
;
2512 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2513 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2514 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2516 /* reconfigure the hardware */
2517 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2519 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2520 j
= adapter
->tx_ring
[i
].reg_idx
;
2521 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2522 /* PThresh workaround for Tx hang with DFP enabled. */
2524 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2526 /* Enable VLAN tag insert/strip */
2527 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2528 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2529 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2530 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2531 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2532 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2533 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2534 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2535 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2536 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2537 j
= adapter
->rx_ring
[i
].reg_idx
;
2538 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2539 vlnctrl
|= IXGBE_RXDCTL_VME
;
2540 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2543 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2547 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2549 struct net_device
*netdev
= adapter
->netdev
;
2550 struct ixgbe_hw
*hw
= &adapter
->hw
;
2553 ixgbe_set_rx_mode(netdev
);
2555 ixgbe_restore_vlan(adapter
);
2556 #ifdef CONFIG_IXGBE_DCB
2557 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2558 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2559 netif_set_gso_max_size(netdev
, 32768);
2561 netif_set_gso_max_size(netdev
, 65536);
2562 ixgbe_configure_dcb(adapter
);
2564 netif_set_gso_max_size(netdev
, 65536);
2567 netif_set_gso_max_size(netdev
, 65536);
2571 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2572 ixgbe_configure_fcoe(adapter
);
2574 #endif /* IXGBE_FCOE */
2575 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2576 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2577 adapter
->tx_ring
[i
].atr_sample_rate
=
2578 adapter
->atr_sample_rate
;
2579 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
2580 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
2581 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
2584 ixgbe_configure_tx(adapter
);
2585 ixgbe_configure_rx(adapter
);
2586 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2587 ixgbe_alloc_rx_buffers(adapter
, &adapter
->rx_ring
[i
],
2588 (adapter
->rx_ring
[i
].count
- 1));
2591 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2593 switch (hw
->phy
.type
) {
2594 case ixgbe_phy_sfp_avago
:
2595 case ixgbe_phy_sfp_ftl
:
2596 case ixgbe_phy_sfp_intel
:
2597 case ixgbe_phy_sfp_unknown
:
2598 case ixgbe_phy_tw_tyco
:
2599 case ixgbe_phy_tw_unknown
:
2607 * ixgbe_sfp_link_config - set up SFP+ link
2608 * @adapter: pointer to private adapter struct
2610 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2612 struct ixgbe_hw
*hw
= &adapter
->hw
;
2614 if (hw
->phy
.multispeed_fiber
) {
2616 * In multispeed fiber setups, the device may not have
2617 * had a physical connection when the driver loaded.
2618 * If that's the case, the initial link configuration
2619 * couldn't get the MAC into 10G or 1G mode, so we'll
2620 * never have a link status change interrupt fire.
2621 * We need to try and force an autonegotiation
2622 * session, then bring up link.
2624 hw
->mac
.ops
.setup_sfp(hw
);
2625 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2626 schedule_work(&adapter
->multispeed_fiber_task
);
2629 * Direct Attach Cu and non-multispeed fiber modules
2630 * still need to be configured properly prior to
2633 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2634 schedule_work(&adapter
->sfp_config_module_task
);
2639 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2640 * @hw: pointer to private hardware struct
2642 * Returns 0 on success, negative on failure
2644 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2647 bool negotiation
, link_up
= false;
2648 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2650 if (hw
->mac
.ops
.check_link
)
2651 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2656 if (hw
->mac
.ops
.get_link_capabilities
)
2657 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
2661 if (hw
->mac
.ops
.setup_link
)
2662 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
2667 #define IXGBE_MAX_RX_DESC_POLL 10
2668 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2671 int j
= adapter
->rx_ring
[rxr
].reg_idx
;
2674 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2675 if (IXGBE_READ_REG(&adapter
->hw
,
2676 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2681 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2682 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2683 "not set within the polling period\n", rxr
);
2685 ixgbe_release_rx_desc(&adapter
->hw
, &adapter
->rx_ring
[rxr
],
2686 (adapter
->rx_ring
[rxr
].count
- 1));
2689 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2691 struct net_device
*netdev
= adapter
->netdev
;
2692 struct ixgbe_hw
*hw
= &adapter
->hw
;
2694 int num_rx_rings
= adapter
->num_rx_queues
;
2696 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2697 u32 txdctl
, rxdctl
, mhadd
;
2701 ixgbe_get_hw_control(adapter
);
2703 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2704 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2705 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2706 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2707 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2712 /* XXX: to interrupt immediately for EICS writes, enable this */
2713 /* gpie |= IXGBE_GPIE_EIMEN; */
2714 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2717 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2719 * use EIAM to auto-mask when MSI-X interrupt is asserted
2720 * this saves a register write for every interrupt
2722 switch (hw
->mac
.type
) {
2723 case ixgbe_mac_82598EB
:
2724 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2727 case ixgbe_mac_82599EB
:
2728 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2729 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2733 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2734 * specifically only auto mask tx and rx interrupts */
2735 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2738 /* Enable fan failure interrupt if media type is copper */
2739 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2740 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2741 gpie
|= IXGBE_SDP1_GPIEN
;
2742 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2745 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2746 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2747 gpie
|= IXGBE_SDP1_GPIEN
;
2748 gpie
|= IXGBE_SDP2_GPIEN
;
2749 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2753 /* adjust max frame to be able to do baby jumbo for FCoE */
2754 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
2755 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2756 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2758 #endif /* IXGBE_FCOE */
2759 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2760 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2761 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2762 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2764 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2767 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2768 j
= adapter
->tx_ring
[i
].reg_idx
;
2769 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2770 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2771 txdctl
|= (8 << 16);
2772 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2775 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2776 /* DMATXCTL.EN must be set after all Tx queue config is done */
2777 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2778 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2779 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2781 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2782 j
= adapter
->tx_ring
[i
].reg_idx
;
2783 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2784 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2785 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2788 for (i
= 0; i
< num_rx_rings
; i
++) {
2789 j
= adapter
->rx_ring
[i
].reg_idx
;
2790 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2791 /* enable PTHRESH=32 descriptors (half the internal cache)
2792 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2793 * this also removes a pesky rx_no_buffer_count increment */
2795 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2796 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2797 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2798 ixgbe_rx_desc_queue_enable(adapter
, i
);
2800 /* enable all receives */
2801 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2802 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2803 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2805 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2806 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2808 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2809 ixgbe_configure_msix(adapter
);
2811 ixgbe_configure_msi_and_legacy(adapter
);
2813 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2814 ixgbe_napi_enable_all(adapter
);
2816 /* clear any pending interrupts, may auto mask */
2817 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2819 ixgbe_irq_enable(adapter
);
2822 * If this adapter has a fan, check to see if we had a failure
2823 * before we enabled the interrupt.
2825 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2826 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2827 if (esdp
& IXGBE_ESDP_SDP1
)
2829 "Fan has stopped, replace the adapter\n");
2833 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2834 * arrived before interrupts were enabled but after probe. Such
2835 * devices wouldn't have their type identified yet. We need to
2836 * kick off the SFP+ module setup first, then try to bring up link.
2837 * If we're not hot-pluggable SFP+, we just need to configure link
2840 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
2841 err
= hw
->phy
.ops
.identify(hw
);
2842 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
2844 * Take the device down and schedule the sfp tasklet
2845 * which will unregister_netdev and log it.
2847 ixgbe_down(adapter
);
2848 schedule_work(&adapter
->sfp_config_module_task
);
2853 if (ixgbe_is_sfp(hw
)) {
2854 ixgbe_sfp_link_config(adapter
);
2856 err
= ixgbe_non_sfp_link_config(hw
);
2858 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
2861 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2862 set_bit(__IXGBE_FDIR_INIT_DONE
,
2863 &(adapter
->tx_ring
[i
].reinit_state
));
2865 /* enable transmits */
2866 netif_tx_start_all_queues(netdev
);
2868 /* bring the link up in the watchdog, this could race with our first
2869 * link up interrupt but shouldn't be a problem */
2870 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
2871 adapter
->link_check_timeout
= jiffies
;
2872 mod_timer(&adapter
->watchdog_timer
, jiffies
);
2876 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
2878 WARN_ON(in_interrupt());
2879 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
2881 ixgbe_down(adapter
);
2883 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
2886 int ixgbe_up(struct ixgbe_adapter
*adapter
)
2888 /* hardware has been reset, we need to reload some things */
2889 ixgbe_configure(adapter
);
2891 return ixgbe_up_complete(adapter
);
2894 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
2896 struct ixgbe_hw
*hw
= &adapter
->hw
;
2899 err
= hw
->mac
.ops
.init_hw(hw
);
2902 case IXGBE_ERR_SFP_NOT_PRESENT
:
2904 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
2905 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
2907 case IXGBE_ERR_EEPROM_VERSION
:
2908 /* We are running on a pre-production device, log a warning */
2909 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
2910 "adapter/LOM. Please be aware there may be issues "
2911 "associated with your hardware. If you are "
2912 "experiencing problems please contact your Intel or "
2913 "hardware representative who provided you with this "
2917 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
2920 /* reprogram the RAR[0] in case user changed it. */
2921 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
2925 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2926 * @adapter: board private structure
2927 * @rx_ring: ring to free buffers from
2929 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
2930 struct ixgbe_ring
*rx_ring
)
2932 struct pci_dev
*pdev
= adapter
->pdev
;
2936 /* Free all the Rx ring sk_buffs */
2938 for (i
= 0; i
< rx_ring
->count
; i
++) {
2939 struct ixgbe_rx_buffer
*rx_buffer_info
;
2941 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
2942 if (rx_buffer_info
->dma
) {
2943 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
2944 rx_ring
->rx_buf_len
,
2945 PCI_DMA_FROMDEVICE
);
2946 rx_buffer_info
->dma
= 0;
2948 if (rx_buffer_info
->skb
) {
2949 struct sk_buff
*skb
= rx_buffer_info
->skb
;
2950 rx_buffer_info
->skb
= NULL
;
2952 struct sk_buff
*this = skb
;
2954 dev_kfree_skb(this);
2957 if (!rx_buffer_info
->page
)
2959 if (rx_buffer_info
->page_dma
) {
2960 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
2961 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
2962 rx_buffer_info
->page_dma
= 0;
2964 put_page(rx_buffer_info
->page
);
2965 rx_buffer_info
->page
= NULL
;
2966 rx_buffer_info
->page_offset
= 0;
2969 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
2970 memset(rx_ring
->rx_buffer_info
, 0, size
);
2972 /* Zero out the descriptor ring */
2973 memset(rx_ring
->desc
, 0, rx_ring
->size
);
2975 rx_ring
->next_to_clean
= 0;
2976 rx_ring
->next_to_use
= 0;
2979 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
2981 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
2985 * ixgbe_clean_tx_ring - Free Tx Buffers
2986 * @adapter: board private structure
2987 * @tx_ring: ring to be cleaned
2989 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
2990 struct ixgbe_ring
*tx_ring
)
2992 struct ixgbe_tx_buffer
*tx_buffer_info
;
2996 /* Free all the Tx ring sk_buffs */
2998 for (i
= 0; i
< tx_ring
->count
; i
++) {
2999 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3000 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3003 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3004 memset(tx_ring
->tx_buffer_info
, 0, size
);
3006 /* Zero out the descriptor ring */
3007 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3009 tx_ring
->next_to_use
= 0;
3010 tx_ring
->next_to_clean
= 0;
3013 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3015 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3019 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3020 * @adapter: board private structure
3022 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3026 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3027 ixgbe_clean_rx_ring(adapter
, &adapter
->rx_ring
[i
]);
3031 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3032 * @adapter: board private structure
3034 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3038 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3039 ixgbe_clean_tx_ring(adapter
, &adapter
->tx_ring
[i
]);
3042 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3044 struct net_device
*netdev
= adapter
->netdev
;
3045 struct ixgbe_hw
*hw
= &adapter
->hw
;
3050 /* signal that we are down to the interrupt handler */
3051 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3053 /* disable receives */
3054 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3055 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3057 netif_tx_disable(netdev
);
3059 IXGBE_WRITE_FLUSH(hw
);
3062 netif_tx_stop_all_queues(netdev
);
3064 ixgbe_irq_disable(adapter
);
3066 ixgbe_napi_disable_all(adapter
);
3068 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3069 del_timer_sync(&adapter
->sfp_timer
);
3070 del_timer_sync(&adapter
->watchdog_timer
);
3071 cancel_work_sync(&adapter
->watchdog_task
);
3073 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3074 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3075 cancel_work_sync(&adapter
->fdir_reinit_task
);
3077 /* disable transmits in the hardware now that interrupts are off */
3078 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3079 j
= adapter
->tx_ring
[i
].reg_idx
;
3080 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3081 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3082 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3084 /* Disable the Tx DMA engine on 82599 */
3085 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3086 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3087 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3088 ~IXGBE_DMATXCTL_TE
));
3090 netif_carrier_off(netdev
);
3092 if (!pci_channel_offline(adapter
->pdev
))
3093 ixgbe_reset(adapter
);
3094 ixgbe_clean_all_tx_rings(adapter
);
3095 ixgbe_clean_all_rx_rings(adapter
);
3097 #ifdef CONFIG_IXGBE_DCA
3098 /* since we reset the hardware DCA settings were cleared */
3099 ixgbe_setup_dca(adapter
);
3104 * ixgbe_poll - NAPI Rx polling callback
3105 * @napi: structure for representing this polling device
3106 * @budget: how many packets driver is allowed to clean
3108 * This function is used for legacy and MSI, NAPI mode
3110 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3112 struct ixgbe_q_vector
*q_vector
=
3113 container_of(napi
, struct ixgbe_q_vector
, napi
);
3114 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3115 int tx_clean_complete
, work_done
= 0;
3117 #ifdef CONFIG_IXGBE_DCA
3118 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3119 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
);
3120 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
);
3124 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
);
3125 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
, &work_done
, budget
);
3127 if (!tx_clean_complete
)
3130 /* If budget not fully consumed, exit the polling mode */
3131 if (work_done
< budget
) {
3132 napi_complete(napi
);
3133 if (adapter
->rx_itr_setting
& 1)
3134 ixgbe_set_itr(adapter
);
3135 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3136 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3142 * ixgbe_tx_timeout - Respond to a Tx Hang
3143 * @netdev: network interface device structure
3145 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3147 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3149 /* Do the reset outside of interrupt context */
3150 schedule_work(&adapter
->reset_task
);
3153 static void ixgbe_reset_task(struct work_struct
*work
)
3155 struct ixgbe_adapter
*adapter
;
3156 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3158 /* If we're already down or resetting, just bail */
3159 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3160 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3163 adapter
->tx_timeout_count
++;
3165 ixgbe_reinit_locked(adapter
);
3168 #ifdef CONFIG_IXGBE_DCB
3169 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3172 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3174 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3178 adapter
->num_rx_queues
= f
->indices
;
3179 adapter
->num_tx_queues
= f
->indices
;
3187 * ixgbe_set_rss_queues: Allocate queues for RSS
3188 * @adapter: board private structure to initialize
3190 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3191 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3194 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3197 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3199 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3201 adapter
->num_rx_queues
= f
->indices
;
3202 adapter
->num_tx_queues
= f
->indices
;
3212 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3213 * @adapter: board private structure to initialize
3215 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3216 * to the original CPU that initiated the Tx session. This runs in addition
3217 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3218 * Rx load across CPUs using RSS.
3221 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3224 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3226 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3229 /* Flow Director must have RSS enabled */
3230 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3231 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3232 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3233 adapter
->num_tx_queues
= f_fdir
->indices
;
3234 adapter
->num_rx_queues
= f_fdir
->indices
;
3237 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3238 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3245 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3246 * @adapter: board private structure to initialize
3248 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3249 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3250 * rx queues out of the max number of rx queues, instead, it is used as the
3251 * index of the first rx queue used by FCoE.
3254 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3257 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3259 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3260 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3261 adapter
->num_rx_queues
= 1;
3262 adapter
->num_tx_queues
= 1;
3263 #ifdef CONFIG_IXGBE_DCB
3264 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3265 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB \n");
3266 ixgbe_set_dcb_queues(adapter
);
3269 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3270 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS \n");
3271 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3272 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3273 ixgbe_set_fdir_queues(adapter
);
3275 ixgbe_set_rss_queues(adapter
);
3277 /* adding FCoE rx rings to the end */
3278 f
->mask
= adapter
->num_rx_queues
;
3279 adapter
->num_rx_queues
+= f
->indices
;
3280 adapter
->num_tx_queues
+= f
->indices
;
3288 #endif /* IXGBE_FCOE */
3290 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3291 * @adapter: board private structure to initialize
3293 * This is the top level queue allocation routine. The order here is very
3294 * important, starting with the "most" number of features turned on at once,
3295 * and ending with the smallest set of features. This way large combinations
3296 * can be allocated if they're turned on, and smaller combinations are the
3297 * fallthrough conditions.
3300 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3303 if (ixgbe_set_fcoe_queues(adapter
))
3306 #endif /* IXGBE_FCOE */
3307 #ifdef CONFIG_IXGBE_DCB
3308 if (ixgbe_set_dcb_queues(adapter
))
3312 if (ixgbe_set_fdir_queues(adapter
))
3315 if (ixgbe_set_rss_queues(adapter
))
3318 /* fallback to base case */
3319 adapter
->num_rx_queues
= 1;
3320 adapter
->num_tx_queues
= 1;
3323 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3324 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3327 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3330 int err
, vector_threshold
;
3332 /* We'll want at least 3 (vector_threshold):
3335 * 3) Other (Link Status Change, etc.)
3336 * 4) TCP Timer (optional)
3338 vector_threshold
= MIN_MSIX_COUNT
;
3340 /* The more we get, the more we will assign to Tx/Rx Cleanup
3341 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3342 * Right now, we simply care about how many we'll get; we'll
3343 * set them up later while requesting irq's.
3345 while (vectors
>= vector_threshold
) {
3346 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3348 if (!err
) /* Success in acquiring all requested vectors. */
3351 vectors
= 0; /* Nasty failure, quit now */
3352 else /* err == number of vectors we should try again with */
3356 if (vectors
< vector_threshold
) {
3357 /* Can't allocate enough MSI-X interrupts? Oh well.
3358 * This just means we'll go with either a single MSI
3359 * vector or fall back to legacy interrupts.
3361 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3362 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3363 kfree(adapter
->msix_entries
);
3364 adapter
->msix_entries
= NULL
;
3366 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3368 * Adjust for only the vectors we'll use, which is minimum
3369 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3370 * vectors we were allocated.
3372 adapter
->num_msix_vectors
= min(vectors
,
3373 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3378 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3379 * @adapter: board private structure to initialize
3381 * Cache the descriptor ring offsets for RSS to the assigned rings.
3384 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3389 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3390 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3391 adapter
->rx_ring
[i
].reg_idx
= i
;
3392 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3393 adapter
->tx_ring
[i
].reg_idx
= i
;
3402 #ifdef CONFIG_IXGBE_DCB
3404 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3405 * @adapter: board private structure to initialize
3407 * Cache the descriptor ring offsets for DCB to the assigned rings.
3410 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3414 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3416 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3417 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3418 /* the number of queues is assumed to be symmetric */
3419 for (i
= 0; i
< dcb_i
; i
++) {
3420 adapter
->rx_ring
[i
].reg_idx
= i
<< 3;
3421 adapter
->tx_ring
[i
].reg_idx
= i
<< 2;
3424 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3427 * Tx TC0 starts at: descriptor queue 0
3428 * Tx TC1 starts at: descriptor queue 32
3429 * Tx TC2 starts at: descriptor queue 64
3430 * Tx TC3 starts at: descriptor queue 80
3431 * Tx TC4 starts at: descriptor queue 96
3432 * Tx TC5 starts at: descriptor queue 104
3433 * Tx TC6 starts at: descriptor queue 112
3434 * Tx TC7 starts at: descriptor queue 120
3436 * Rx TC0-TC7 are offset by 16 queues each
3438 for (i
= 0; i
< 3; i
++) {
3439 adapter
->tx_ring
[i
].reg_idx
= i
<< 5;
3440 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3442 for ( ; i
< 5; i
++) {
3443 adapter
->tx_ring
[i
].reg_idx
=
3445 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3447 for ( ; i
< dcb_i
; i
++) {
3448 adapter
->tx_ring
[i
].reg_idx
=
3450 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3454 } else if (dcb_i
== 4) {
3456 * Tx TC0 starts at: descriptor queue 0
3457 * Tx TC1 starts at: descriptor queue 64
3458 * Tx TC2 starts at: descriptor queue 96
3459 * Tx TC3 starts at: descriptor queue 112
3461 * Rx TC0-TC3 are offset by 32 queues each
3463 adapter
->tx_ring
[0].reg_idx
= 0;
3464 adapter
->tx_ring
[1].reg_idx
= 64;
3465 adapter
->tx_ring
[2].reg_idx
= 96;
3466 adapter
->tx_ring
[3].reg_idx
= 112;
3467 for (i
= 0 ; i
< dcb_i
; i
++)
3468 adapter
->rx_ring
[i
].reg_idx
= i
<< 5;
3486 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3487 * @adapter: board private structure to initialize
3489 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3492 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
3497 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3498 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3499 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
3500 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3501 adapter
->rx_ring
[i
].reg_idx
= i
;
3502 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3503 adapter
->tx_ring
[i
].reg_idx
= i
;
3512 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3513 * @adapter: board private structure to initialize
3515 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3518 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3520 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
3522 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3524 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3525 #ifdef CONFIG_IXGBE_DCB
3526 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3527 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
3529 ixgbe_cache_ring_dcb(adapter
);
3530 /* find out queues in TC for FCoE */
3531 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
].reg_idx
+ 1;
3532 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
].reg_idx
+ 1;
3534 * In 82599, the number of Tx queues for each traffic
3535 * class for both 8-TC and 4-TC modes are:
3536 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3537 * 8 TCs: 32 32 16 16 8 8 8 8
3538 * 4 TCs: 64 64 32 32
3539 * We have max 8 queues for FCoE, where 8 the is
3540 * FCoE redirection table size. If TC for FCoE is
3541 * less than or equal to TC3, we have enough queues
3542 * to add max of 8 queues for FCoE, so we start FCoE
3543 * tx descriptor from the next one, i.e., reg_idx + 1.
3544 * If TC for FCoE is above TC3, implying 8 TC mode,
3545 * and we need 8 for FCoE, we have to take all queues
3546 * in that traffic class for FCoE.
3548 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
3551 #endif /* CONFIG_IXGBE_DCB */
3552 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3553 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3554 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3555 ixgbe_cache_ring_fdir(adapter
);
3557 ixgbe_cache_ring_rss(adapter
);
3559 fcoe_rx_i
= f
->mask
;
3560 fcoe_tx_i
= f
->mask
;
3562 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
3563 adapter
->rx_ring
[f
->mask
+ i
].reg_idx
= fcoe_rx_i
;
3564 adapter
->tx_ring
[f
->mask
+ i
].reg_idx
= fcoe_tx_i
;
3571 #endif /* IXGBE_FCOE */
3573 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3574 * @adapter: board private structure to initialize
3576 * Once we know the feature-set enabled for the device, we'll cache
3577 * the register offset the descriptor ring is assigned to.
3579 * Note, the order the various feature calls is important. It must start with
3580 * the "most" features enabled at the same time, then trickle down to the
3581 * least amount of features turned on at once.
3583 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3585 /* start with default case */
3586 adapter
->rx_ring
[0].reg_idx
= 0;
3587 adapter
->tx_ring
[0].reg_idx
= 0;
3590 if (ixgbe_cache_ring_fcoe(adapter
))
3593 #endif /* IXGBE_FCOE */
3594 #ifdef CONFIG_IXGBE_DCB
3595 if (ixgbe_cache_ring_dcb(adapter
))
3599 if (ixgbe_cache_ring_fdir(adapter
))
3602 if (ixgbe_cache_ring_rss(adapter
))
3607 * ixgbe_alloc_queues - Allocate memory for all rings
3608 * @adapter: board private structure to initialize
3610 * We allocate one ring per queue at run-time since we don't know the
3611 * number of queues at compile-time. The polling_netdev array is
3612 * intended for Multiqueue, but should work fine with a single queue.
3614 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3618 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
3619 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3620 if (!adapter
->tx_ring
)
3621 goto err_tx_ring_allocation
;
3623 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
3624 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3625 if (!adapter
->rx_ring
)
3626 goto err_rx_ring_allocation
;
3628 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3629 adapter
->tx_ring
[i
].count
= adapter
->tx_ring_count
;
3630 adapter
->tx_ring
[i
].queue_index
= i
;
3633 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3634 adapter
->rx_ring
[i
].count
= adapter
->rx_ring_count
;
3635 adapter
->rx_ring
[i
].queue_index
= i
;
3638 ixgbe_cache_ring_register(adapter
);
3642 err_rx_ring_allocation
:
3643 kfree(adapter
->tx_ring
);
3644 err_tx_ring_allocation
:
3649 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3650 * @adapter: board private structure to initialize
3652 * Attempt to configure the interrupts using the best available
3653 * capabilities of the hardware and the kernel.
3655 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3657 struct ixgbe_hw
*hw
= &adapter
->hw
;
3659 int vector
, v_budget
;
3662 * It's easy to be greedy for MSI-X vectors, but it really
3663 * doesn't do us much good if we have a lot more vectors
3664 * than CPU's. So let's be conservative and only ask for
3665 * (roughly) the same number of vectors as there are CPU's.
3667 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3668 (int)num_online_cpus()) + NON_Q_VECTORS
;
3671 * At the same time, hardware can only support a maximum of
3672 * hw.mac->max_msix_vectors vectors. With features
3673 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3674 * descriptor queues supported by our device. Thus, we cap it off in
3675 * those rare cases where the cpu count also exceeds our vector limit.
3677 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3679 /* A failure in MSI-X entry allocation isn't fatal, but it does
3680 * mean we disable MSI-X capabilities of the adapter. */
3681 adapter
->msix_entries
= kcalloc(v_budget
,
3682 sizeof(struct msix_entry
), GFP_KERNEL
);
3683 if (adapter
->msix_entries
) {
3684 for (vector
= 0; vector
< v_budget
; vector
++)
3685 adapter
->msix_entries
[vector
].entry
= vector
;
3687 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3689 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3693 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3694 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3695 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3696 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3697 adapter
->atr_sample_rate
= 0;
3698 ixgbe_set_num_queues(adapter
);
3700 err
= pci_enable_msi(adapter
->pdev
);
3702 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3704 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3705 "falling back to legacy. Error: %d\n", err
);
3715 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3716 * @adapter: board private structure to initialize
3718 * We allocate one q_vector per queue interrupt. If allocation fails we
3721 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
3723 int q_idx
, num_q_vectors
;
3724 struct ixgbe_q_vector
*q_vector
;
3726 int (*poll
)(struct napi_struct
*, int);
3728 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3729 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3730 napi_vectors
= adapter
->num_rx_queues
;
3731 poll
= &ixgbe_clean_rxtx_many
;
3738 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3739 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
), GFP_KERNEL
);
3742 q_vector
->adapter
= adapter
;
3743 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
3744 q_vector
->eitr
= adapter
->tx_eitr_param
;
3746 q_vector
->eitr
= adapter
->rx_eitr_param
;
3747 q_vector
->v_idx
= q_idx
;
3748 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
3749 adapter
->q_vector
[q_idx
] = q_vector
;
3757 q_vector
= adapter
->q_vector
[q_idx
];
3758 netif_napi_del(&q_vector
->napi
);
3760 adapter
->q_vector
[q_idx
] = NULL
;
3766 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3767 * @adapter: board private structure to initialize
3769 * This function frees the memory allocated to the q_vectors. In addition if
3770 * NAPI is enabled it will delete any references to the NAPI struct prior
3771 * to freeing the q_vector.
3773 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
3775 int q_idx
, num_q_vectors
;
3777 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3778 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3782 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3783 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
3784 adapter
->q_vector
[q_idx
] = NULL
;
3785 netif_napi_del(&q_vector
->napi
);
3790 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
3792 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3793 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3794 pci_disable_msix(adapter
->pdev
);
3795 kfree(adapter
->msix_entries
);
3796 adapter
->msix_entries
= NULL
;
3797 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
3798 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
3799 pci_disable_msi(adapter
->pdev
);
3805 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3806 * @adapter: board private structure to initialize
3808 * We determine which interrupt scheme to use based on...
3809 * - Kernel support (MSI, MSI-X)
3810 * - which can be user-defined (via MODULE_PARAM)
3811 * - Hardware queue count (num_*_queues)
3812 * - defined by miscellaneous hardware support/features (RSS, etc.)
3814 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3818 /* Number of supported queues */
3819 ixgbe_set_num_queues(adapter
);
3821 err
= ixgbe_set_interrupt_capability(adapter
);
3823 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
3824 goto err_set_interrupt
;
3827 err
= ixgbe_alloc_q_vectors(adapter
);
3829 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
3831 goto err_alloc_q_vectors
;
3834 err
= ixgbe_alloc_queues(adapter
);
3836 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
3837 goto err_alloc_queues
;
3840 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
3841 "Tx Queue count = %u\n",
3842 (adapter
->num_rx_queues
> 1) ? "Enabled" :
3843 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
3845 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3850 ixgbe_free_q_vectors(adapter
);
3851 err_alloc_q_vectors
:
3852 ixgbe_reset_interrupt_capability(adapter
);
3858 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3859 * @adapter: board private structure to clear interrupt scheme on
3861 * We go through and clear interrupt specific resources and reset the structure
3862 * to pre-load conditions
3864 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
3866 kfree(adapter
->tx_ring
);
3867 kfree(adapter
->rx_ring
);
3868 adapter
->tx_ring
= NULL
;
3869 adapter
->rx_ring
= NULL
;
3871 ixgbe_free_q_vectors(adapter
);
3872 ixgbe_reset_interrupt_capability(adapter
);
3876 * ixgbe_sfp_timer - worker thread to find a missing module
3877 * @data: pointer to our adapter struct
3879 static void ixgbe_sfp_timer(unsigned long data
)
3881 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
3884 * Do the sfp_timer outside of interrupt context due to the
3885 * delays that sfp+ detection requires
3887 schedule_work(&adapter
->sfp_task
);
3891 * ixgbe_sfp_task - worker thread to find a missing module
3892 * @work: pointer to work_struct containing our data
3894 static void ixgbe_sfp_task(struct work_struct
*work
)
3896 struct ixgbe_adapter
*adapter
= container_of(work
,
3897 struct ixgbe_adapter
,
3899 struct ixgbe_hw
*hw
= &adapter
->hw
;
3901 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
3902 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
3903 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
3904 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
3906 ret
= hw
->phy
.ops
.reset(hw
);
3907 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3908 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
3909 "because an unsupported SFP+ module type "
3911 "Reload the driver after installing a "
3912 "supported module.\n");
3913 unregister_netdev(adapter
->netdev
);
3915 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
3918 /* don't need this routine any more */
3919 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3923 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
3924 mod_timer(&adapter
->sfp_timer
,
3925 round_jiffies(jiffies
+ (2 * HZ
)));
3929 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3930 * @adapter: board private structure to initialize
3932 * ixgbe_sw_init initializes the Adapter private data structure.
3933 * Fields are initialized based on PCI device information and
3934 * OS network device settings (MTU size).
3936 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
3938 struct ixgbe_hw
*hw
= &adapter
->hw
;
3939 struct pci_dev
*pdev
= adapter
->pdev
;
3941 #ifdef CONFIG_IXGBE_DCB
3943 struct tc_configuration
*tc
;
3946 /* PCI config space info */
3948 hw
->vendor_id
= pdev
->vendor
;
3949 hw
->device_id
= pdev
->device
;
3950 hw
->revision_id
= pdev
->revision
;
3951 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
3952 hw
->subsystem_device_id
= pdev
->subsystem_device
;
3954 /* Set capability flags */
3955 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
3956 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
3957 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
3958 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
3959 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3960 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
3961 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
3962 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
3963 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3964 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
3965 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
3966 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
3967 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3968 adapter
->ring_feature
[RING_F_FDIR
].indices
=
3969 IXGBE_MAX_FDIR_INDICES
;
3970 adapter
->atr_sample_rate
= 20;
3971 adapter
->fdir_pballoc
= 0;
3973 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
3974 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
3975 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
3976 #ifdef CONFIG_IXGBE_DCB
3977 /* Default traffic class to use for FCoE */
3978 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
3980 #endif /* IXGBE_FCOE */
3983 #ifdef CONFIG_IXGBE_DCB
3984 /* Configure DCB traffic classes */
3985 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
3986 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
3987 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
3988 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3989 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
3990 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
3991 tc
->dcb_pfc
= pfc_disabled
;
3993 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
3994 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
3995 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
3996 adapter
->dcb_cfg
.pfc_mode_enable
= false;
3997 adapter
->dcb_cfg
.round_robin_enable
= false;
3998 adapter
->dcb_set_bitmap
= 0x00;
3999 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4000 adapter
->ring_feature
[RING_F_DCB
].indices
);
4004 /* default flow control settings */
4005 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4006 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4008 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4010 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4011 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4012 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4013 hw
->fc
.send_xon
= true;
4014 hw
->fc
.disable_fc_autoneg
= false;
4016 /* enable itr by default in dynamic mode */
4017 adapter
->rx_itr_setting
= 1;
4018 adapter
->rx_eitr_param
= 20000;
4019 adapter
->tx_itr_setting
= 1;
4020 adapter
->tx_eitr_param
= 10000;
4022 /* set defaults for eitr in MegaBytes */
4023 adapter
->eitr_low
= 10;
4024 adapter
->eitr_high
= 20;
4026 /* set default ring sizes */
4027 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4028 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4030 /* initialize eeprom parameters */
4031 if (ixgbe_init_eeprom_params_generic(hw
)) {
4032 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4036 /* enable rx csum by default */
4037 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4039 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4045 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4046 * @adapter: board private structure
4047 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4049 * Return 0 on success, negative on failure
4051 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4052 struct ixgbe_ring
*tx_ring
)
4054 struct pci_dev
*pdev
= adapter
->pdev
;
4057 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4058 tx_ring
->tx_buffer_info
= vmalloc(size
);
4059 if (!tx_ring
->tx_buffer_info
)
4061 memset(tx_ring
->tx_buffer_info
, 0, size
);
4063 /* round up to nearest 4K */
4064 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4065 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4067 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
4072 tx_ring
->next_to_use
= 0;
4073 tx_ring
->next_to_clean
= 0;
4074 tx_ring
->work_limit
= tx_ring
->count
;
4078 vfree(tx_ring
->tx_buffer_info
);
4079 tx_ring
->tx_buffer_info
= NULL
;
4080 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4081 "descriptor ring\n");
4086 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4087 * @adapter: board private structure
4089 * If this function returns with an error, then it's possible one or
4090 * more of the rings is populated (while the rest are not). It is the
4091 * callers duty to clean those orphaned rings.
4093 * Return 0 on success, negative on failure
4095 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4099 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4100 err
= ixgbe_setup_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
4103 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4111 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4112 * @adapter: board private structure
4113 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4115 * Returns 0 on success, negative on failure
4117 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4118 struct ixgbe_ring
*rx_ring
)
4120 struct pci_dev
*pdev
= adapter
->pdev
;
4123 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4124 rx_ring
->rx_buffer_info
= vmalloc(size
);
4125 if (!rx_ring
->rx_buffer_info
) {
4127 "vmalloc allocation failed for the rx desc ring\n");
4130 memset(rx_ring
->rx_buffer_info
, 0, size
);
4132 /* Round up to nearest 4K */
4133 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4134 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4136 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
4138 if (!rx_ring
->desc
) {
4140 "Memory allocation failed for the rx desc ring\n");
4141 vfree(rx_ring
->rx_buffer_info
);
4145 rx_ring
->next_to_clean
= 0;
4146 rx_ring
->next_to_use
= 0;
4155 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4156 * @adapter: board private structure
4158 * If this function returns with an error, then it's possible one or
4159 * more of the rings is populated (while the rest are not). It is the
4160 * callers duty to clean those orphaned rings.
4162 * Return 0 on success, negative on failure
4165 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4169 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4170 err
= ixgbe_setup_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
4173 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4181 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4182 * @adapter: board private structure
4183 * @tx_ring: Tx descriptor ring for a specific queue
4185 * Free all transmit software resources
4187 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4188 struct ixgbe_ring
*tx_ring
)
4190 struct pci_dev
*pdev
= adapter
->pdev
;
4192 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4194 vfree(tx_ring
->tx_buffer_info
);
4195 tx_ring
->tx_buffer_info
= NULL
;
4197 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
4199 tx_ring
->desc
= NULL
;
4203 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4204 * @adapter: board private structure
4206 * Free all transmit software resources
4208 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4212 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4213 if (adapter
->tx_ring
[i
].desc
)
4214 ixgbe_free_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
4218 * ixgbe_free_rx_resources - Free Rx Resources
4219 * @adapter: board private structure
4220 * @rx_ring: ring to clean the resources from
4222 * Free all receive software resources
4224 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4225 struct ixgbe_ring
*rx_ring
)
4227 struct pci_dev
*pdev
= adapter
->pdev
;
4229 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4231 vfree(rx_ring
->rx_buffer_info
);
4232 rx_ring
->rx_buffer_info
= NULL
;
4234 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
4236 rx_ring
->desc
= NULL
;
4240 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4241 * @adapter: board private structure
4243 * Free all receive software resources
4245 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4249 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4250 if (adapter
->rx_ring
[i
].desc
)
4251 ixgbe_free_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
4255 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4256 * @netdev: network interface device structure
4257 * @new_mtu: new value for maximum frame size
4259 * Returns 0 on success, negative on failure
4261 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4263 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4264 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4266 /* MTU < 68 is an error and causes problems on some kernels */
4267 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4270 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4271 netdev
->mtu
, new_mtu
);
4272 /* must set new MTU before calling down or up */
4273 netdev
->mtu
= new_mtu
;
4275 if (netif_running(netdev
))
4276 ixgbe_reinit_locked(adapter
);
4282 * ixgbe_open - Called when a network interface is made active
4283 * @netdev: network interface device structure
4285 * Returns 0 on success, negative value on failure
4287 * The open entry point is called when a network interface is made
4288 * active by the system (IFF_UP). At this point all resources needed
4289 * for transmit and receive operations are allocated, the interrupt
4290 * handler is registered with the OS, the watchdog timer is started,
4291 * and the stack is notified that the interface is ready.
4293 static int ixgbe_open(struct net_device
*netdev
)
4295 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4298 /* disallow open during test */
4299 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4302 netif_carrier_off(netdev
);
4304 /* allocate transmit descriptors */
4305 err
= ixgbe_setup_all_tx_resources(adapter
);
4309 /* allocate receive descriptors */
4310 err
= ixgbe_setup_all_rx_resources(adapter
);
4314 ixgbe_configure(adapter
);
4316 err
= ixgbe_request_irq(adapter
);
4320 err
= ixgbe_up_complete(adapter
);
4324 netif_tx_start_all_queues(netdev
);
4329 ixgbe_release_hw_control(adapter
);
4330 ixgbe_free_irq(adapter
);
4333 ixgbe_free_all_rx_resources(adapter
);
4335 ixgbe_free_all_tx_resources(adapter
);
4336 ixgbe_reset(adapter
);
4342 * ixgbe_close - Disables a network interface
4343 * @netdev: network interface device structure
4345 * Returns 0, this is not allowed to fail
4347 * The close entry point is called when an interface is de-activated
4348 * by the OS. The hardware is still under the drivers control, but
4349 * needs to be disabled. A global MAC reset is issued to stop the
4350 * hardware, and all transmit and receive resources are freed.
4352 static int ixgbe_close(struct net_device
*netdev
)
4354 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4356 ixgbe_down(adapter
);
4357 ixgbe_free_irq(adapter
);
4359 ixgbe_free_all_tx_resources(adapter
);
4360 ixgbe_free_all_rx_resources(adapter
);
4362 ixgbe_release_hw_control(adapter
);
4368 static int ixgbe_resume(struct pci_dev
*pdev
)
4370 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4371 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4374 pci_set_power_state(pdev
, PCI_D0
);
4375 pci_restore_state(pdev
);
4377 err
= pci_enable_device_mem(pdev
);
4379 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
4383 pci_set_master(pdev
);
4385 pci_wake_from_d3(pdev
, false);
4387 err
= ixgbe_init_interrupt_scheme(adapter
);
4389 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
4394 ixgbe_reset(adapter
);
4396 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
4398 if (netif_running(netdev
)) {
4399 err
= ixgbe_open(adapter
->netdev
);
4404 netif_device_attach(netdev
);
4408 #endif /* CONFIG_PM */
4410 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
4412 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4413 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4414 struct ixgbe_hw
*hw
= &adapter
->hw
;
4416 u32 wufc
= adapter
->wol
;
4421 netif_device_detach(netdev
);
4423 if (netif_running(netdev
)) {
4424 ixgbe_down(adapter
);
4425 ixgbe_free_irq(adapter
);
4426 ixgbe_free_all_tx_resources(adapter
);
4427 ixgbe_free_all_rx_resources(adapter
);
4429 ixgbe_clear_interrupt_scheme(adapter
);
4432 retval
= pci_save_state(pdev
);
4438 ixgbe_set_rx_mode(netdev
);
4440 /* turn on all-multi mode if wake on multicast is enabled */
4441 if (wufc
& IXGBE_WUFC_MC
) {
4442 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4443 fctrl
|= IXGBE_FCTRL_MPE
;
4444 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4447 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4448 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4449 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4451 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4453 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4454 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4457 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4458 pci_wake_from_d3(pdev
, true);
4460 pci_wake_from_d3(pdev
, false);
4462 *enable_wake
= !!wufc
;
4464 ixgbe_release_hw_control(adapter
);
4466 pci_disable_device(pdev
);
4472 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4477 retval
= __ixgbe_shutdown(pdev
, &wake
);
4482 pci_prepare_to_sleep(pdev
);
4484 pci_wake_from_d3(pdev
, false);
4485 pci_set_power_state(pdev
, PCI_D3hot
);
4490 #endif /* CONFIG_PM */
4492 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4496 __ixgbe_shutdown(pdev
, &wake
);
4498 if (system_state
== SYSTEM_POWER_OFF
) {
4499 pci_wake_from_d3(pdev
, wake
);
4500 pci_set_power_state(pdev
, PCI_D3hot
);
4505 * ixgbe_update_stats - Update the board statistics counters.
4506 * @adapter: board private structure
4508 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4510 struct net_device
*netdev
= adapter
->netdev
;
4511 struct ixgbe_hw
*hw
= &adapter
->hw
;
4513 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4514 u64 non_eop_descs
= 0, restart_queue
= 0;
4516 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
4519 for (i
= 0; i
< 16; i
++)
4520 adapter
->hw_rx_no_dma_resources
+=
4521 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4522 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4523 rsc_count
+= adapter
->rx_ring
[i
].rsc_count
;
4524 rsc_flush
+= adapter
->rx_ring
[i
].rsc_flush
;
4526 adapter
->rsc_total_count
= rsc_count
;
4527 adapter
->rsc_total_flush
= rsc_flush
;
4530 /* gather some stats to the adapter struct that are per queue */
4531 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4532 restart_queue
+= adapter
->tx_ring
[i
].restart_queue
;
4533 adapter
->restart_queue
= restart_queue
;
4535 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4536 non_eop_descs
+= adapter
->rx_ring
[i
].non_eop_descs
;
4537 adapter
->non_eop_descs
= non_eop_descs
;
4539 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4540 for (i
= 0; i
< 8; i
++) {
4541 /* for packet buffers not used, the register should read 0 */
4542 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4544 adapter
->stats
.mpc
[i
] += mpc
;
4545 total_mpc
+= adapter
->stats
.mpc
[i
];
4546 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4547 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4548 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4549 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4550 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4551 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4552 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4553 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4554 IXGBE_PXONRXCNT(i
));
4555 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4556 IXGBE_PXOFFRXCNT(i
));
4557 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4559 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4561 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4564 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4566 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4569 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4570 /* work around hardware counting issue */
4571 adapter
->stats
.gprc
-= missed_rx
;
4573 /* 82598 hardware only has a 32 bit counter in the high register */
4574 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4576 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4577 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
4578 adapter
->stats
.gorc
+= (tmp
<< 32);
4579 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4580 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
4581 adapter
->stats
.gotc
+= (tmp
<< 32);
4582 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4583 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4584 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4585 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4586 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
4587 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
4589 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4590 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4591 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4592 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4593 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4594 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4595 #endif /* IXGBE_FCOE */
4597 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4598 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4599 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4600 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4601 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4603 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4604 adapter
->stats
.bprc
+= bprc
;
4605 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4606 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4607 adapter
->stats
.mprc
-= bprc
;
4608 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4609 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4610 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4611 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4612 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4613 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4614 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4615 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4616 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4617 adapter
->stats
.lxontxc
+= lxon
;
4618 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4619 adapter
->stats
.lxofftxc
+= lxoff
;
4620 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4621 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4622 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4624 * 82598 errata - tx of flow control packets is included in tx counters
4626 xon_off_tot
= lxon
+ lxoff
;
4627 adapter
->stats
.gptc
-= xon_off_tot
;
4628 adapter
->stats
.mptc
-= xon_off_tot
;
4629 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4630 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4631 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4632 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4633 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4634 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4635 adapter
->stats
.ptc64
-= xon_off_tot
;
4636 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4637 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4638 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4639 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4640 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4641 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4643 /* Fill out the OS statistics structure */
4644 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
4647 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
4648 adapter
->stats
.rlec
;
4649 netdev
->stats
.rx_dropped
= 0;
4650 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
4651 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4652 netdev
->stats
.rx_missed_errors
= total_mpc
;
4656 * ixgbe_watchdog - Timer Call-back
4657 * @data: pointer to adapter cast into an unsigned long
4659 static void ixgbe_watchdog(unsigned long data
)
4661 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4662 struct ixgbe_hw
*hw
= &adapter
->hw
;
4667 * Do the watchdog outside of interrupt context due to the lovely
4668 * delays that some of the newer hardware requires
4671 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
4672 goto watchdog_short_circuit
;
4674 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
4676 * for legacy and MSI interrupts don't set any bits
4677 * that are enabled for EIAM, because this operation
4678 * would set *both* EIMS and EICS for any bit in EIAM
4680 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4681 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4682 goto watchdog_reschedule
;
4685 /* get one bit for every active tx/rx interrupt vector */
4686 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
4687 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
4688 if (qv
->rxr_count
|| qv
->txr_count
)
4689 eics
|= ((u64
)1 << i
);
4692 /* Cause software interrupt to ensure rx rings are cleaned */
4693 ixgbe_irq_rearm_queues(adapter
, eics
);
4695 watchdog_reschedule
:
4696 /* Reset the timer */
4697 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
4699 watchdog_short_circuit
:
4700 schedule_work(&adapter
->watchdog_task
);
4704 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4705 * @work: pointer to work_struct containing our data
4707 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
4709 struct ixgbe_adapter
*adapter
= container_of(work
,
4710 struct ixgbe_adapter
,
4711 multispeed_fiber_task
);
4712 struct ixgbe_hw
*hw
= &adapter
->hw
;
4716 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
4717 autoneg
= hw
->phy
.autoneg_advertised
;
4718 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
4719 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
4720 if (hw
->mac
.ops
.setup_link
)
4721 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
4722 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
4723 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
4727 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4728 * @work: pointer to work_struct containing our data
4730 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
4732 struct ixgbe_adapter
*adapter
= container_of(work
,
4733 struct ixgbe_adapter
,
4734 sfp_config_module_task
);
4735 struct ixgbe_hw
*hw
= &adapter
->hw
;
4738 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
4740 /* Time for electrical oscillations to settle down */
4742 err
= hw
->phy
.ops
.identify_sfp(hw
);
4744 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4745 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
4746 "an unsupported SFP+ module type was detected.\n"
4747 "Reload the driver after installing a supported "
4749 unregister_netdev(adapter
->netdev
);
4752 hw
->mac
.ops
.setup_sfp(hw
);
4754 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
4755 /* This will also work for DA Twinax connections */
4756 schedule_work(&adapter
->multispeed_fiber_task
);
4757 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
4761 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4762 * @work: pointer to work_struct containing our data
4764 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
4766 struct ixgbe_adapter
*adapter
= container_of(work
,
4767 struct ixgbe_adapter
,
4769 struct ixgbe_hw
*hw
= &adapter
->hw
;
4772 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
4773 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4774 set_bit(__IXGBE_FDIR_INIT_DONE
,
4775 &(adapter
->tx_ring
[i
].reinit_state
));
4777 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
4778 "ignored adding FDIR ATR filters \n");
4780 /* Done FDIR Re-initialization, enable transmits */
4781 netif_tx_start_all_queues(adapter
->netdev
);
4785 * ixgbe_watchdog_task - worker thread to bring link up
4786 * @work: pointer to work_struct containing our data
4788 static void ixgbe_watchdog_task(struct work_struct
*work
)
4790 struct ixgbe_adapter
*adapter
= container_of(work
,
4791 struct ixgbe_adapter
,
4793 struct net_device
*netdev
= adapter
->netdev
;
4794 struct ixgbe_hw
*hw
= &adapter
->hw
;
4795 u32 link_speed
= adapter
->link_speed
;
4796 bool link_up
= adapter
->link_up
;
4798 struct ixgbe_ring
*tx_ring
;
4799 int some_tx_pending
= 0;
4801 adapter
->flags
|= IXGBE_FLAG_IN_WATCHDOG_TASK
;
4803 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
4804 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
4807 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4808 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
4809 hw
->mac
.ops
.fc_enable(hw
, i
);
4811 hw
->mac
.ops
.fc_enable(hw
, 0);
4814 hw
->mac
.ops
.fc_enable(hw
, 0);
4819 time_after(jiffies
, (adapter
->link_check_timeout
+
4820 IXGBE_TRY_LINK_TIMEOUT
))) {
4821 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4822 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
4824 adapter
->link_up
= link_up
;
4825 adapter
->link_speed
= link_speed
;
4829 if (!netif_carrier_ok(netdev
)) {
4830 bool flow_rx
, flow_tx
;
4832 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4833 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
4834 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
4835 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
4836 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
4838 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4839 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
4840 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
4841 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
4844 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
4845 "Flow Control: %s\n",
4847 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
4849 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
4850 "1 Gbps" : "unknown speed")),
4851 ((flow_rx
&& flow_tx
) ? "RX/TX" :
4853 (flow_tx
? "TX" : "None"))));
4855 netif_carrier_on(netdev
);
4857 /* Force detection of hung controller */
4858 adapter
->detect_tx_hung
= true;
4861 adapter
->link_up
= false;
4862 adapter
->link_speed
= 0;
4863 if (netif_carrier_ok(netdev
)) {
4864 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
4866 netif_carrier_off(netdev
);
4870 if (!netif_carrier_ok(netdev
)) {
4871 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4872 tx_ring
= &adapter
->tx_ring
[i
];
4873 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
4874 some_tx_pending
= 1;
4879 if (some_tx_pending
) {
4880 /* We've lost link, so the controller stops DMA,
4881 * but we've got queued Tx work that's never going
4882 * to get done, so reset controller to flush Tx.
4883 * (Do the reset outside of interrupt context).
4885 schedule_work(&adapter
->reset_task
);
4889 ixgbe_update_stats(adapter
);
4890 adapter
->flags
&= ~IXGBE_FLAG_IN_WATCHDOG_TASK
;
4893 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
4894 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
4895 u32 tx_flags
, u8
*hdr_len
)
4897 struct ixgbe_adv_tx_context_desc
*context_desc
;
4900 struct ixgbe_tx_buffer
*tx_buffer_info
;
4901 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
4902 u32 mss_l4len_idx
, l4len
;
4904 if (skb_is_gso(skb
)) {
4905 if (skb_header_cloned(skb
)) {
4906 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
4910 l4len
= tcp_hdrlen(skb
);
4913 if (skb
->protocol
== htons(ETH_P_IP
)) {
4914 struct iphdr
*iph
= ip_hdr(skb
);
4917 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
4921 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
4922 ipv6_hdr(skb
)->payload_len
= 0;
4923 tcp_hdr(skb
)->check
=
4924 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
4925 &ipv6_hdr(skb
)->daddr
,
4929 i
= tx_ring
->next_to_use
;
4931 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4932 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4934 /* VLAN MACLEN IPLEN */
4935 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4937 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4938 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
4939 IXGBE_ADVTXD_MACLEN_SHIFT
);
4940 *hdr_len
+= skb_network_offset(skb
);
4942 (skb_transport_header(skb
) - skb_network_header(skb
));
4944 (skb_transport_header(skb
) - skb_network_header(skb
));
4945 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
4946 context_desc
->seqnum_seed
= 0;
4948 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4949 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
4950 IXGBE_ADVTXD_DTYP_CTXT
);
4952 if (skb
->protocol
== htons(ETH_P_IP
))
4953 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
4954 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
4955 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
4959 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
4960 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
4961 /* use index 1 for TSO */
4962 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
4963 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
4965 tx_buffer_info
->time_stamp
= jiffies
;
4966 tx_buffer_info
->next_to_watch
= i
;
4969 if (i
== tx_ring
->count
)
4971 tx_ring
->next_to_use
= i
;
4978 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
4979 struct ixgbe_ring
*tx_ring
,
4980 struct sk_buff
*skb
, u32 tx_flags
)
4982 struct ixgbe_adv_tx_context_desc
*context_desc
;
4984 struct ixgbe_tx_buffer
*tx_buffer_info
;
4985 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
4987 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
4988 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
4989 i
= tx_ring
->next_to_use
;
4990 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4991 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
4993 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
4995 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
4996 vlan_macip_lens
|= (skb_network_offset(skb
) <<
4997 IXGBE_ADVTXD_MACLEN_SHIFT
);
4998 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
4999 vlan_macip_lens
|= (skb_transport_header(skb
) -
5000 skb_network_header(skb
));
5002 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5003 context_desc
->seqnum_seed
= 0;
5005 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5006 IXGBE_ADVTXD_DTYP_CTXT
);
5008 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5011 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5012 const struct vlan_ethhdr
*vhdr
=
5013 (const struct vlan_ethhdr
*)skb
->data
;
5015 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5017 protocol
= skb
->protocol
;
5021 case cpu_to_be16(ETH_P_IP
):
5022 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5023 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5025 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5026 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5028 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5030 case cpu_to_be16(ETH_P_IPV6
):
5031 /* XXX what about other V6 headers?? */
5032 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5034 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5035 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5037 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5040 if (unlikely(net_ratelimit())) {
5041 DPRINTK(PROBE
, WARNING
,
5042 "partial checksum but proto=%x!\n",
5049 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5050 /* use index zero for tx checksum offload */
5051 context_desc
->mss_l4len_idx
= 0;
5053 tx_buffer_info
->time_stamp
= jiffies
;
5054 tx_buffer_info
->next_to_watch
= i
;
5057 if (i
== tx_ring
->count
)
5059 tx_ring
->next_to_use
= i
;
5067 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5068 struct ixgbe_ring
*tx_ring
,
5069 struct sk_buff
*skb
, u32 tx_flags
,
5072 struct pci_dev
*pdev
= adapter
->pdev
;
5073 struct ixgbe_tx_buffer
*tx_buffer_info
;
5075 unsigned int total
= skb
->len
;
5076 unsigned int offset
= 0, size
, count
= 0, i
;
5077 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5080 i
= tx_ring
->next_to_use
;
5082 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5083 /* excluding fcoe_crc_eof for FCoE */
5084 total
-= sizeof(struct fcoe_crc_eof
);
5086 len
= min(skb_headlen(skb
), total
);
5088 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5089 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5091 tx_buffer_info
->length
= size
;
5092 tx_buffer_info
->mapped_as_page
= false;
5093 tx_buffer_info
->dma
= pci_map_single(pdev
,
5095 size
, PCI_DMA_TODEVICE
);
5096 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5098 tx_buffer_info
->time_stamp
= jiffies
;
5099 tx_buffer_info
->next_to_watch
= i
;
5108 if (i
== tx_ring
->count
)
5113 for (f
= 0; f
< nr_frags
; f
++) {
5114 struct skb_frag_struct
*frag
;
5116 frag
= &skb_shinfo(skb
)->frags
[f
];
5117 len
= min((unsigned int)frag
->size
, total
);
5118 offset
= frag
->page_offset
;
5122 if (i
== tx_ring
->count
)
5125 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5126 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5128 tx_buffer_info
->length
= size
;
5129 tx_buffer_info
->dma
= pci_map_page(adapter
->pdev
,
5133 tx_buffer_info
->mapped_as_page
= true;
5134 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5136 tx_buffer_info
->time_stamp
= jiffies
;
5137 tx_buffer_info
->next_to_watch
= i
;
5148 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5149 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5154 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5156 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5157 tx_buffer_info
->dma
= 0;
5158 tx_buffer_info
->time_stamp
= 0;
5159 tx_buffer_info
->next_to_watch
= 0;
5162 /* clear timestamp and dma mappings for remaining portion of packet */
5163 while (count
>= 0) {
5167 i
+= tx_ring
->count
;
5168 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5169 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5175 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5176 struct ixgbe_ring
*tx_ring
,
5177 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5179 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5180 struct ixgbe_tx_buffer
*tx_buffer_info
;
5181 u32 olinfo_status
= 0, cmd_type_len
= 0;
5183 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5185 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5187 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5189 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5190 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5192 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5193 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5195 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5196 IXGBE_ADVTXD_POPTS_SHIFT
;
5198 /* use index 1 context for tso */
5199 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5200 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5201 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5202 IXGBE_ADVTXD_POPTS_SHIFT
;
5204 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5205 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5206 IXGBE_ADVTXD_POPTS_SHIFT
;
5208 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5209 olinfo_status
|= IXGBE_ADVTXD_CC
;
5210 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5211 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5212 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5215 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5217 i
= tx_ring
->next_to_use
;
5219 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5220 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5221 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5222 tx_desc
->read
.cmd_type_len
=
5223 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5224 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5226 if (i
== tx_ring
->count
)
5230 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5233 * Force memory writes to complete before letting h/w
5234 * know there are new descriptors to fetch. (Only
5235 * applicable for weak-ordered memory model archs,
5240 tx_ring
->next_to_use
= i
;
5241 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5244 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5245 int queue
, u32 tx_flags
)
5247 /* Right now, we support IPv4 only */
5248 struct ixgbe_atr_input atr_input
;
5250 struct iphdr
*iph
= ip_hdr(skb
);
5251 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5252 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5253 u32 src_ipv4_addr
, dst_ipv4_addr
;
5256 /* check if we're UDP or TCP */
5257 if (iph
->protocol
== IPPROTO_TCP
) {
5259 src_port
= th
->source
;
5260 dst_port
= th
->dest
;
5261 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5262 /* l4type IPv4 type is 0, no need to assign */
5264 /* Unsupported L4 header, just bail here */
5268 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5270 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5271 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5272 src_ipv4_addr
= iph
->saddr
;
5273 dst_ipv4_addr
= iph
->daddr
;
5274 flex_bytes
= eth
->h_proto
;
5276 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5277 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5278 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5279 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5280 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5281 /* src and dst are inverted, think how the receiver sees them */
5282 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5283 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5285 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5286 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5289 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5290 struct ixgbe_ring
*tx_ring
, int size
)
5292 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5293 /* Herbert's original patch had:
5294 * smp_mb__after_netif_stop_queue();
5295 * but since that doesn't exist yet, just open code it. */
5298 /* We need to check again in a case another CPU has just
5299 * made room available. */
5300 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
5303 /* A reprieve! - use start_queue because it doesn't call schedule */
5304 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
5305 ++tx_ring
->restart_queue
;
5309 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5310 struct ixgbe_ring
*tx_ring
, int size
)
5312 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
5314 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
5317 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
5319 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5320 int txq
= smp_processor_id();
5322 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
5326 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5327 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5328 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
5329 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
5333 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5334 return (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
) >> 13;
5336 return skb_tx_hash(dev
, skb
);
5339 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
5340 struct net_device
*netdev
)
5342 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5343 struct ixgbe_ring
*tx_ring
;
5344 struct netdev_queue
*txq
;
5346 unsigned int tx_flags
= 0;
5352 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
5353 tx_flags
|= vlan_tx_tag_get(skb
);
5354 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5355 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
5356 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5358 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5359 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5360 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5361 if (skb
->priority
!= TC_PRIO_CONTROL
) {
5362 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5363 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5364 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5366 skb
->queue_mapping
=
5367 adapter
->ring_feature
[RING_F_DCB
].indices
-1;
5371 tx_ring
= &adapter
->tx_ring
[skb
->queue_mapping
];
5373 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5374 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5375 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
5377 #ifdef CONFIG_IXGBE_DCB
5378 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5379 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5380 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
5381 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5385 /* four things can cause us to need a context descriptor */
5386 if (skb_is_gso(skb
) ||
5387 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
5388 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
5389 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
5392 count
+= TXD_USE_COUNT(skb_headlen(skb
));
5393 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
5394 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
5396 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
5398 return NETDEV_TX_BUSY
;
5401 first
= tx_ring
->next_to_use
;
5402 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5404 /* setup tx offload for FCoE */
5405 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5407 dev_kfree_skb_any(skb
);
5408 return NETDEV_TX_OK
;
5411 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
5412 #endif /* IXGBE_FCOE */
5414 if (skb
->protocol
== htons(ETH_P_IP
))
5415 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
5416 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5418 dev_kfree_skb_any(skb
);
5419 return NETDEV_TX_OK
;
5423 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
5424 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
5425 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
5426 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
5429 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
5431 /* add the ATR filter if ATR is on */
5432 if (tx_ring
->atr_sample_rate
) {
5433 ++tx_ring
->atr_count
;
5434 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
5435 test_bit(__IXGBE_FDIR_INIT_DONE
,
5436 &tx_ring
->reinit_state
)) {
5437 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
5439 tx_ring
->atr_count
= 0;
5442 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
5443 txq
->tx_bytes
+= skb
->len
;
5445 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
5447 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
5450 dev_kfree_skb_any(skb
);
5451 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
5452 tx_ring
->next_to_use
= first
;
5455 return NETDEV_TX_OK
;
5459 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5460 * @netdev: network interface device structure
5461 * @p: pointer to an address structure
5463 * Returns 0 on success, negative on failure
5465 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
5467 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5468 struct ixgbe_hw
*hw
= &adapter
->hw
;
5469 struct sockaddr
*addr
= p
;
5471 if (!is_valid_ether_addr(addr
->sa_data
))
5472 return -EADDRNOTAVAIL
;
5474 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
5475 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
5477 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
5483 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
5485 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5486 struct ixgbe_hw
*hw
= &adapter
->hw
;
5490 if (prtad
!= hw
->phy
.mdio
.prtad
)
5492 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
5498 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
5499 u16 addr
, u16 value
)
5501 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5502 struct ixgbe_hw
*hw
= &adapter
->hw
;
5504 if (prtad
!= hw
->phy
.mdio
.prtad
)
5506 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
5509 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
5511 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5513 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
5517 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5519 * @netdev: network interface device structure
5521 * Returns non-zero on failure
5523 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
5526 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5527 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5529 if (is_valid_ether_addr(mac
->san_addr
)) {
5531 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5538 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5540 * @netdev: network interface device structure
5542 * Returns non-zero on failure
5544 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
5547 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5548 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5550 if (is_valid_ether_addr(mac
->san_addr
)) {
5552 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5558 #ifdef CONFIG_NET_POLL_CONTROLLER
5560 * Polling 'interrupt' - used by things like netconsole to send skbs
5561 * without having to re-enable interrupts. It's not called while
5562 * the interrupt routine is executing.
5564 static void ixgbe_netpoll(struct net_device
*netdev
)
5566 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5569 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5570 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5571 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5572 for (i
= 0; i
< num_q_vectors
; i
++) {
5573 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
5574 ixgbe_msix_clean_many(0, q_vector
);
5577 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5579 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5583 static const struct net_device_ops ixgbe_netdev_ops
= {
5584 .ndo_open
= ixgbe_open
,
5585 .ndo_stop
= ixgbe_close
,
5586 .ndo_start_xmit
= ixgbe_xmit_frame
,
5587 .ndo_select_queue
= ixgbe_select_queue
,
5588 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5589 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5590 .ndo_validate_addr
= eth_validate_addr
,
5591 .ndo_set_mac_address
= ixgbe_set_mac
,
5592 .ndo_change_mtu
= ixgbe_change_mtu
,
5593 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5594 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5595 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5596 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5597 .ndo_do_ioctl
= ixgbe_ioctl
,
5598 #ifdef CONFIG_NET_POLL_CONTROLLER
5599 .ndo_poll_controller
= ixgbe_netpoll
,
5602 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5603 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5604 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
5605 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
5606 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
5607 #endif /* IXGBE_FCOE */
5611 * ixgbe_probe - Device Initialization Routine
5612 * @pdev: PCI device information struct
5613 * @ent: entry in ixgbe_pci_tbl
5615 * Returns 0 on success, negative on failure
5617 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5618 * The OS initialization, configuring of the adapter private structure,
5619 * and a hardware reset occur.
5621 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
5622 const struct pci_device_id
*ent
)
5624 struct net_device
*netdev
;
5625 struct ixgbe_adapter
*adapter
= NULL
;
5626 struct ixgbe_hw
*hw
;
5627 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
5628 static int cards_found
;
5629 int i
, err
, pci_using_dac
;
5635 err
= pci_enable_device_mem(pdev
);
5639 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
5640 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
5643 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
5645 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
5647 dev_err(&pdev
->dev
, "No usable DMA "
5648 "configuration, aborting\n");
5655 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
5656 IORESOURCE_MEM
), ixgbe_driver_name
);
5659 "pci_request_selected_regions failed 0x%x\n", err
);
5663 pci_enable_pcie_error_reporting(pdev
);
5665 pci_set_master(pdev
);
5666 pci_save_state(pdev
);
5668 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), MAX_TX_QUEUES
);
5671 goto err_alloc_etherdev
;
5674 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
5676 pci_set_drvdata(pdev
, netdev
);
5677 adapter
= netdev_priv(netdev
);
5679 adapter
->netdev
= netdev
;
5680 adapter
->pdev
= pdev
;
5683 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
5685 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
5686 pci_resource_len(pdev
, 0));
5692 for (i
= 1; i
<= 5; i
++) {
5693 if (pci_resource_len(pdev
, i
) == 0)
5697 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
5698 ixgbe_set_ethtool_ops(netdev
);
5699 netdev
->watchdog_timeo
= 5 * HZ
;
5700 strcpy(netdev
->name
, pci_name(pdev
));
5702 adapter
->bd_number
= cards_found
;
5705 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
5706 hw
->mac
.type
= ii
->mac
;
5709 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
5710 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
5711 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5712 if (!(eec
& (1 << 8)))
5713 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
5716 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
5717 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
5718 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5719 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
5720 hw
->phy
.mdio
.mmds
= 0;
5721 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
5722 hw
->phy
.mdio
.dev
= netdev
;
5723 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
5724 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
5726 /* set up this timer and work struct before calling get_invariants
5727 * which might start the timer
5729 init_timer(&adapter
->sfp_timer
);
5730 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
5731 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
5733 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
5735 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5736 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
5738 /* a new SFP+ module arrival, called from GPI SDP2 context */
5739 INIT_WORK(&adapter
->sfp_config_module_task
,
5740 ixgbe_sfp_config_module_task
);
5742 ii
->get_invariants(hw
);
5744 /* setup the private structure */
5745 err
= ixgbe_sw_init(adapter
);
5750 * If there is a fan on this device and it has failed log the
5753 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
5754 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
5755 if (esdp
& IXGBE_ESDP_SDP1
)
5756 DPRINTK(PROBE
, CRIT
,
5757 "Fan has stopped, replace the adapter\n");
5760 /* reset_hw fills in the perm_addr as well */
5761 err
= hw
->mac
.ops
.reset_hw(hw
);
5762 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
5763 hw
->mac
.type
== ixgbe_mac_82598EB
) {
5765 * Start a kernel thread to watch for a module to arrive.
5766 * Only do this for 82598, since 82599 will generate
5767 * interrupts on module arrival.
5769 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5770 mod_timer(&adapter
->sfp_timer
,
5771 round_jiffies(jiffies
+ (2 * HZ
)));
5773 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5774 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
5775 "an unsupported SFP+ module type was detected.\n"
5776 "Reload the driver after installing a supported "
5780 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
5784 netdev
->features
= NETIF_F_SG
|
5786 NETIF_F_HW_VLAN_TX
|
5787 NETIF_F_HW_VLAN_RX
|
5788 NETIF_F_HW_VLAN_FILTER
;
5790 netdev
->features
|= NETIF_F_IPV6_CSUM
;
5791 netdev
->features
|= NETIF_F_TSO
;
5792 netdev
->features
|= NETIF_F_TSO6
;
5793 netdev
->features
|= NETIF_F_GRO
;
5795 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
5796 netdev
->features
|= NETIF_F_SCTP_CSUM
;
5798 netdev
->vlan_features
|= NETIF_F_TSO
;
5799 netdev
->vlan_features
|= NETIF_F_TSO6
;
5800 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
5801 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
5802 netdev
->vlan_features
|= NETIF_F_SG
;
5804 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5805 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
5807 #ifdef CONFIG_IXGBE_DCB
5808 netdev
->dcbnl_ops
= &dcbnl_ops
;
5812 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
5813 if (hw
->mac
.ops
.get_device_caps
) {
5814 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
5815 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
5816 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
5819 #endif /* IXGBE_FCOE */
5821 netdev
->features
|= NETIF_F_HIGHDMA
;
5823 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
5824 netdev
->features
|= NETIF_F_LRO
;
5826 /* make sure the EEPROM is good */
5827 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
5828 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
5833 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5834 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
5836 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
5837 dev_err(&pdev
->dev
, "invalid MAC address\n");
5842 init_timer(&adapter
->watchdog_timer
);
5843 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
5844 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
5846 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
5847 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
5849 err
= ixgbe_init_interrupt_scheme(adapter
);
5853 switch (pdev
->device
) {
5854 case IXGBE_DEV_ID_82599_KX4
:
5855 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
5856 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
5857 /* Enable ACPI wakeup in GRC */
5858 IXGBE_WRITE_REG(hw
, IXGBE_GRC
,
5859 (IXGBE_READ_REG(hw
, IXGBE_GRC
) & ~IXGBE_GRC_APME
));
5865 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
5867 /* pick up the PCI bus settings for reporting later */
5868 hw
->mac
.ops
.get_bus_info(hw
);
5870 /* print bus type/speed/width info */
5871 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
5872 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
5873 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
5874 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
5875 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
5876 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
5879 ixgbe_read_pba_num_generic(hw
, &part_num
);
5880 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
5881 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5882 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
5883 (part_num
>> 8), (part_num
& 0xff));
5885 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5886 hw
->mac
.type
, hw
->phy
.type
,
5887 (part_num
>> 8), (part_num
& 0xff));
5889 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
5890 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
5891 "this card is not sufficient for optimal "
5893 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
5894 "PCI-Express slot is required.\n");
5897 /* save off EEPROM version number */
5898 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
5900 /* reset the hardware with the new settings */
5901 err
= hw
->mac
.ops
.start_hw(hw
);
5903 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
5904 /* We are running on a pre-production device, log a warning */
5905 dev_warn(&pdev
->dev
, "This device is a pre-production "
5906 "adapter/LOM. Please be aware there may be issues "
5907 "associated with your hardware. If you are "
5908 "experiencing problems please contact your Intel or "
5909 "hardware representative who provided you with this "
5912 strcpy(netdev
->name
, "eth%d");
5913 err
= register_netdev(netdev
);
5917 /* carrier off reporting is important to ethtool even BEFORE open */
5918 netif_carrier_off(netdev
);
5920 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
5921 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
5922 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
5924 #ifdef CONFIG_IXGBE_DCA
5925 if (dca_add_requester(&pdev
->dev
) == 0) {
5926 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
5927 ixgbe_setup_dca(adapter
);
5930 /* add san mac addr to netdev */
5931 ixgbe_add_sanmac_netdev(netdev
);
5933 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
5938 ixgbe_release_hw_control(adapter
);
5939 ixgbe_clear_interrupt_scheme(adapter
);
5942 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5943 del_timer_sync(&adapter
->sfp_timer
);
5944 cancel_work_sync(&adapter
->sfp_task
);
5945 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5946 cancel_work_sync(&adapter
->sfp_config_module_task
);
5947 iounmap(hw
->hw_addr
);
5949 free_netdev(netdev
);
5951 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
5955 pci_disable_device(pdev
);
5960 * ixgbe_remove - Device Removal Routine
5961 * @pdev: PCI device information struct
5963 * ixgbe_remove is called by the PCI subsystem to alert the driver
5964 * that it should release a PCI device. The could be caused by a
5965 * Hot-Plug event, or because the driver is going to be removed from
5968 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
5970 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5971 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5973 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5974 /* clear the module not found bit to make sure the worker won't
5977 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5978 del_timer_sync(&adapter
->watchdog_timer
);
5980 del_timer_sync(&adapter
->sfp_timer
);
5981 cancel_work_sync(&adapter
->watchdog_task
);
5982 cancel_work_sync(&adapter
->sfp_task
);
5983 cancel_work_sync(&adapter
->multispeed_fiber_task
);
5984 cancel_work_sync(&adapter
->sfp_config_module_task
);
5985 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
5986 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
5987 cancel_work_sync(&adapter
->fdir_reinit_task
);
5988 flush_scheduled_work();
5990 #ifdef CONFIG_IXGBE_DCA
5991 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
5992 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
5993 dca_remove_requester(&pdev
->dev
);
5994 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
5999 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6000 ixgbe_cleanup_fcoe(adapter
);
6002 #endif /* IXGBE_FCOE */
6004 /* remove the added san mac */
6005 ixgbe_del_sanmac_netdev(netdev
);
6007 if (netdev
->reg_state
== NETREG_REGISTERED
)
6008 unregister_netdev(netdev
);
6010 ixgbe_clear_interrupt_scheme(adapter
);
6012 ixgbe_release_hw_control(adapter
);
6014 iounmap(adapter
->hw
.hw_addr
);
6015 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6018 DPRINTK(PROBE
, INFO
, "complete\n");
6020 free_netdev(netdev
);
6022 pci_disable_pcie_error_reporting(pdev
);
6024 pci_disable_device(pdev
);
6028 * ixgbe_io_error_detected - called when PCI error is detected
6029 * @pdev: Pointer to PCI device
6030 * @state: The current pci connection state
6032 * This function is called after a PCI bus error affecting
6033 * this device has been detected.
6035 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6036 pci_channel_state_t state
)
6038 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6039 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6041 netif_device_detach(netdev
);
6043 if (state
== pci_channel_io_perm_failure
)
6044 return PCI_ERS_RESULT_DISCONNECT
;
6046 if (netif_running(netdev
))
6047 ixgbe_down(adapter
);
6048 pci_disable_device(pdev
);
6050 /* Request a slot reset. */
6051 return PCI_ERS_RESULT_NEED_RESET
;
6055 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6056 * @pdev: Pointer to PCI device
6058 * Restart the card from scratch, as if from a cold-boot.
6060 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6062 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6063 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6064 pci_ers_result_t result
;
6067 if (pci_enable_device_mem(pdev
)) {
6069 "Cannot re-enable PCI device after reset.\n");
6070 result
= PCI_ERS_RESULT_DISCONNECT
;
6072 pci_set_master(pdev
);
6073 pci_restore_state(pdev
);
6074 pci_save_state(pdev
);
6076 pci_wake_from_d3(pdev
, false);
6078 ixgbe_reset(adapter
);
6079 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6080 result
= PCI_ERS_RESULT_RECOVERED
;
6083 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6086 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6087 /* non-fatal, continue */
6094 * ixgbe_io_resume - called when traffic can start flowing again.
6095 * @pdev: Pointer to PCI device
6097 * This callback is called when the error recovery driver tells us that
6098 * its OK to resume normal operation.
6100 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6102 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6103 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6105 if (netif_running(netdev
)) {
6106 if (ixgbe_up(adapter
)) {
6107 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6112 netif_device_attach(netdev
);
6115 static struct pci_error_handlers ixgbe_err_handler
= {
6116 .error_detected
= ixgbe_io_error_detected
,
6117 .slot_reset
= ixgbe_io_slot_reset
,
6118 .resume
= ixgbe_io_resume
,
6121 static struct pci_driver ixgbe_driver
= {
6122 .name
= ixgbe_driver_name
,
6123 .id_table
= ixgbe_pci_tbl
,
6124 .probe
= ixgbe_probe
,
6125 .remove
= __devexit_p(ixgbe_remove
),
6127 .suspend
= ixgbe_suspend
,
6128 .resume
= ixgbe_resume
,
6130 .shutdown
= ixgbe_shutdown
,
6131 .err_handler
= &ixgbe_err_handler
6135 * ixgbe_init_module - Driver Registration Routine
6137 * ixgbe_init_module is the first routine called when the driver is
6138 * loaded. All it does is register with the PCI subsystem.
6140 static int __init
ixgbe_init_module(void)
6143 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6144 ixgbe_driver_string
, ixgbe_driver_version
);
6146 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6148 #ifdef CONFIG_IXGBE_DCA
6149 dca_register_notify(&dca_notifier
);
6152 ret
= pci_register_driver(&ixgbe_driver
);
6156 module_init(ixgbe_init_module
);
6159 * ixgbe_exit_module - Driver Exit Cleanup Routine
6161 * ixgbe_exit_module is called just before the driver is removed
6164 static void __exit
ixgbe_exit_module(void)
6166 #ifdef CONFIG_IXGBE_DCA
6167 dca_unregister_notify(&dca_notifier
);
6169 pci_unregister_driver(&ixgbe_driver
);
6172 #ifdef CONFIG_IXGBE_DCA
6173 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6178 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6179 __ixgbe_notify_dca
);
6181 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6184 #endif /* CONFIG_IXGBE_DCA */
6187 * ixgbe_get_hw_dev_name - return device name string
6188 * used by hardware layer to print debugging information
6190 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
6192 struct ixgbe_adapter
*adapter
= hw
->back
;
6193 return adapter
->netdev
->name
;
6197 module_exit(ixgbe_exit_module
);