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[pohmelfs.git] / include / linux / usb / r8a66597.h
blob55805f9dcf212c4f921a856dfe7ceaf5c03b7c9a
1 /*
2 * R8A66597 driver platform data
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23 #ifndef __LINUX_USB_R8A66597_H
24 #define __LINUX_USB_R8A66597_H
25
26 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
27 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
28 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
29
30 struct r8a66597_platdata {
31 /* This callback can control port power instead of DVSTCTR register. */
32 void (*port_power)(int port, int power);
33
34 /* This parameter is for BUSWAIT */
35 u16 buswait;
36
37 /* set one = on chip controller, set zero = external controller */
38 unsigned on_chip:1;
39
40 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
41 unsigned xtal:2;
42
43 /* set one = 3.3V, set zero = 1.5V */
44 unsigned vif:1;
45
46 /* set one = big endian, set zero = little endian */
47 unsigned endian:1;
48
49 /* (external controller only) set one = WR0_N shorted to WR1_N */
50 unsigned wr0_shorted_to_wr1:1;
51
52 /* set one = using SUDMAC */
53 unsigned sudmac:1;
54 };
55
56 /* Register definitions */
57 #define SYSCFG0 0x00
58 #define SYSCFG1 0x02
59 #define SYSSTS0 0x04
60 #define SYSSTS1 0x06
61 #define DVSTCTR0 0x08
62 #define DVSTCTR1 0x0A
63 #define TESTMODE 0x0C
64 #define PINCFG 0x0E
65 #define DMA0CFG 0x10
66 #define DMA1CFG 0x12
67 #define CFIFO 0x14
68 #define D0FIFO 0x18
69 #define D1FIFO 0x1C
70 #define CFIFOSEL 0x20
71 #define CFIFOCTR 0x22
72 #define CFIFOSIE 0x24
73 #define D0FIFOSEL 0x28
74 #define D0FIFOCTR 0x2A
75 #define D1FIFOSEL 0x2C
76 #define D1FIFOCTR 0x2E
77 #define INTENB0 0x30
78 #define INTENB1 0x32
79 #define INTENB2 0x34
80 #define BRDYENB 0x36
81 #define NRDYENB 0x38
82 #define BEMPENB 0x3A
83 #define SOFCFG 0x3C
84 #define INTSTS0 0x40
85 #define INTSTS1 0x42
86 #define INTSTS2 0x44
87 #define BRDYSTS 0x46
88 #define NRDYSTS 0x48
89 #define BEMPSTS 0x4A
90 #define FRMNUM 0x4C
91 #define UFRMNUM 0x4E
92 #define USBADDR 0x50
93 #define USBREQ 0x54
94 #define USBVAL 0x56
95 #define USBINDX 0x58
96 #define USBLENG 0x5A
97 #define DCPCFG 0x5C
98 #define DCPMAXP 0x5E
99 #define DCPCTR 0x60
100 #define PIPESEL 0x64
101 #define PIPECFG 0x68
102 #define PIPEBUF 0x6A
103 #define PIPEMAXP 0x6C
104 #define PIPEPERI 0x6E
105 #define PIPE1CTR 0x70
106 #define PIPE2CTR 0x72
107 #define PIPE3CTR 0x74
108 #define PIPE4CTR 0x76
109 #define PIPE5CTR 0x78
110 #define PIPE6CTR 0x7A
111 #define PIPE7CTR 0x7C
112 #define PIPE8CTR 0x7E
113 #define PIPE9CTR 0x80
114 #define PIPE1TRE 0x90
115 #define PIPE1TRN 0x92
116 #define PIPE2TRE 0x94
117 #define PIPE2TRN 0x96
118 #define PIPE3TRE 0x98
119 #define PIPE3TRN 0x9A
120 #define PIPE4TRE 0x9C
121 #define PIPE4TRN 0x9E
122 #define PIPE5TRE 0xA0
123 #define PIPE5TRN 0xA2
124 #define DEVADD0 0xD0
125 #define DEVADD1 0xD2
126 #define DEVADD2 0xD4
127 #define DEVADD3 0xD6
128 #define DEVADD4 0xD8
129 #define DEVADD5 0xDA
130 #define DEVADD6 0xDC
131 #define DEVADD7 0xDE
132 #define DEVADD8 0xE0
133 #define DEVADD9 0xE2
134 #define DEVADDA 0xE4
135
136 /* System Configuration Control Register */
137 #define XTAL 0xC000 /* b15-14: Crystal selection */
138 #define XTAL48 0x8000 /* 48MHz */
139 #define XTAL24 0x4000 /* 24MHz */
140 #define XTAL12 0x0000 /* 12MHz */
141 #define XCKE 0x2000 /* b13: External clock enable */
142 #define PLLC 0x0800 /* b11: PLL control */
143 #define SCKE 0x0400 /* b10: USB clock enable */
144 #define PCSDIS 0x0200 /* b9: not CS wakeup */
145 #define LPSME 0x0100 /* b8: Low power sleep mode */
146 #define HSE 0x0080 /* b7: Hi-speed enable */
147 #define DCFM 0x0040 /* b6: Controller function select */
148 #define DRPD 0x0020 /* b5: D+/- pull down control */
149 #define DPRPU 0x0010 /* b4: D+ pull up control */
150 #define USBE 0x0001 /* b0: USB module operation enable */
151
152 /* System Configuration Status Register */
153 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
154 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
155 #define SOFEA 0x0020 /* b5: SOF monitor */
156 #define IDMON 0x0004 /* b3: ID-pin monitor */
157 #define LNST 0x0003 /* b1-0: D+, D- line status */
158 #define SE1 0x0003 /* SE1 */
159 #define FS_KSTS 0x0002 /* Full-Speed K State */
160 #define FS_JSTS 0x0001 /* Full-Speed J State */
161 #define LS_JSTS 0x0002 /* Low-Speed J State */
162 #define LS_KSTS 0x0001 /* Low-Speed K State */
163 #define SE0 0x0000 /* SE0 */
164
165 /* Device State Control Register */
166 #define EXTLP0 0x0400 /* b10: External port */
167 #define VBOUT 0x0200 /* b9: VBUS output */
168 #define WKUP 0x0100 /* b8: Remote wakeup */
169 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
170 #define USBRST 0x0040 /* b6: USB reset enable */
171 #define RESUME 0x0020 /* b5: Resume enable */
172 #define UACT 0x0010 /* b4: USB bus enable */
173 #define RHST 0x0007 /* b1-0: Reset handshake status */
174 #define HSPROC 0x0004 /* HS handshake is processing */
175 #define HSMODE 0x0003 /* Hi-Speed mode */
176 #define FSMODE 0x0002 /* Full-Speed mode */
177 #define LSMODE 0x0001 /* Low-Speed mode */
178 #define UNDECID 0x0000 /* Undecided */
179
180 /* Test Mode Register */
181 #define UTST 0x000F /* b3-0: Test select */
182 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
183 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
184 #define H_TST_K 0x000A /* HOST TEST K */
185 #define H_TST_J 0x0009 /* HOST TEST J */
186 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
187 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
188 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
189 #define P_TST_K 0x0002 /* PERI TEST K */
190 #define P_TST_J 0x0001 /* PERI TEST J */
191 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
192
193 /* Data Pin Configuration Register */
194 #define LDRV 0x8000 /* b15: Drive Current Adjust */
195 #define VIF1 0x0000 /* VIF = 1.8V */
196 #define VIF3 0x8000 /* VIF = 3.3V */
197 #define INTA 0x0001 /* b1: USB INT-pin active */
198
199 /* DMAx Pin Configuration Register */
200 #define DREQA 0x4000 /* b14: Dreq active select */
201 #define BURST 0x2000 /* b13: Burst mode */
202 #define DACKA 0x0400 /* b10: Dack active select */
203 #define DFORM 0x0380 /* b9-7: DMA mode select */
204 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
205 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
206 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
207 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
208 #define DENDA 0x0040 /* b6: Dend active select */
209 #define PKTM 0x0020 /* b5: Packet mode */
210 #define DENDE 0x0010 /* b4: Dend enable */
211 #define OBUS 0x0004 /* b2: OUTbus mode */
212
213 /* CFIFO/DxFIFO Port Select Register */
214 #define RCNT 0x8000 /* b15: Read count mode */
215 #define REW 0x4000 /* b14: Buffer rewind */
216 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
217 #define DREQE 0x1000 /* b12: DREQ output enable */
218 #define MBW_8 0x0000 /* 8bit */
219 #define MBW_16 0x0400 /* 16bit */
220 #define MBW_32 0x0800 /* 32bit */
221 #define BIGEND 0x0100 /* b8: Big endian mode */
222 #define BYTE_LITTLE 0x0000 /* little dendian */
223 #define BYTE_BIG 0x0100 /* big endifan */
224 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
225 #define CURPIPE 0x000F /* b2-0: PIPE select */
226
227 /* CFIFO/DxFIFO Port Control Register */
228 #define BVAL 0x8000 /* b15: Buffer valid flag */
229 #define BCLR 0x4000 /* b14: Buffer clear */
230 #define FRDY 0x2000 /* b13: FIFO ready */
231 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
232
233 /* Interrupt Enable Register 0 */
234 #define VBSE 0x8000 /* b15: VBUS interrupt */
235 #define RSME 0x4000 /* b14: Resume interrupt */
236 #define SOFE 0x2000 /* b13: Frame update interrupt */
237 #define DVSE 0x1000 /* b12: Device state transition interrupt */
238 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
239 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
240 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
241 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
242
243 /* Interrupt Enable Register 1 */
244 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
245 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
246 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
247 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
248 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
249 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
250 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
251
252 /* BRDY Interrupt Enable/Status Register */
253 #define BRDY9 0x0200 /* b9: PIPE9 */
254 #define BRDY8 0x0100 /* b8: PIPE8 */
255 #define BRDY7 0x0080 /* b7: PIPE7 */
256 #define BRDY6 0x0040 /* b6: PIPE6 */
257 #define BRDY5 0x0020 /* b5: PIPE5 */
258 #define BRDY4 0x0010 /* b4: PIPE4 */
259 #define BRDY3 0x0008 /* b3: PIPE3 */
260 #define BRDY2 0x0004 /* b2: PIPE2 */
261 #define BRDY1 0x0002 /* b1: PIPE1 */
262 #define BRDY0 0x0001 /* b1: PIPE0 */
263
264 /* NRDY Interrupt Enable/Status Register */
265 #define NRDY9 0x0200 /* b9: PIPE9 */
266 #define NRDY8 0x0100 /* b8: PIPE8 */
267 #define NRDY7 0x0080 /* b7: PIPE7 */
268 #define NRDY6 0x0040 /* b6: PIPE6 */
269 #define NRDY5 0x0020 /* b5: PIPE5 */
270 #define NRDY4 0x0010 /* b4: PIPE4 */
271 #define NRDY3 0x0008 /* b3: PIPE3 */
272 #define NRDY2 0x0004 /* b2: PIPE2 */
273 #define NRDY1 0x0002 /* b1: PIPE1 */
274 #define NRDY0 0x0001 /* b1: PIPE0 */
275
276 /* BEMP Interrupt Enable/Status Register */
277 #define BEMP9 0x0200 /* b9: PIPE9 */
278 #define BEMP8 0x0100 /* b8: PIPE8 */
279 #define BEMP7 0x0080 /* b7: PIPE7 */
280 #define BEMP6 0x0040 /* b6: PIPE6 */
281 #define BEMP5 0x0020 /* b5: PIPE5 */
282 #define BEMP4 0x0010 /* b4: PIPE4 */
283 #define BEMP3 0x0008 /* b3: PIPE3 */
284 #define BEMP2 0x0004 /* b2: PIPE2 */
285 #define BEMP1 0x0002 /* b1: PIPE1 */
286 #define BEMP0 0x0001 /* b0: PIPE0 */
287
288 /* SOF Pin Configuration Register */
289 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
290 #define BRDYM 0x0040 /* b6: BRDY clear timing */
291 #define INTL 0x0020 /* b5: Interrupt sense select */
292 #define EDGESTS 0x0010 /* b4: */
293 #define SOFMODE 0x000C /* b3-2: SOF pin select */
294 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
295 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
296 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
297
298 /* Interrupt Status Register 0 */
299 #define VBINT 0x8000 /* b15: VBUS interrupt */
300 #define RESM 0x4000 /* b14: Resume interrupt */
301 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
302 #define DVST 0x1000 /* b12: Device state transition interrupt */
303 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
304 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
305 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
306 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
307 #define VBSTS 0x0080 /* b7: VBUS input port */
308 #define DVSQ 0x0070 /* b6-4: Device state */
309 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
310 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
311 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
312 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
313 #define DS_SUSP 0x0040 /* Suspend */
314 #define DS_CNFG 0x0030 /* Configured */
315 #define DS_ADDS 0x0020 /* Address */
316 #define DS_DFLT 0x0010 /* Default */
317 #define DS_POWR 0x0000 /* Powered */
318 #define DVSQS 0x0030 /* b5-4: Device state */
319 #define VALID 0x0008 /* b3: Setup packet detected flag */
320 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
321 #define CS_SQER 0x0006 /* Sequence error */
322 #define CS_WRND 0x0005 /* Control write nodata status stage */
323 #define CS_WRSS 0x0004 /* Control write status stage */
324 #define CS_WRDS 0x0003 /* Control write data stage */
325 #define CS_RDSS 0x0002 /* Control read status stage */
326 #define CS_RDDS 0x0001 /* Control read data stage */
327 #define CS_IDST 0x0000 /* Idle or setup stage */
328
329 /* Interrupt Status Register 1 */
330 #define OVRCR 0x8000 /* b15: Over-current interrupt */
331 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
332 #define DTCH 0x1000 /* b12: Detach sense interrupt */
333 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
334 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
335 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
336 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
337
338 /* Frame Number Register */
339 #define OVRN 0x8000 /* b15: Overrun error */
340 #define CRCE 0x4000 /* b14: Received data error */
341 #define FRNM 0x07FF /* b10-0: Frame number */
342
343 /* Micro Frame Number Register */
344 #define UFRNM 0x0007 /* b2-0: Micro frame number */
345
346 /* Default Control Pipe Maxpacket Size Register */
347 /* Pipe Maxpacket Size Register */
348 #define DEVSEL 0xF000 /* b15-14: Device address select */
349 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
350
351 /* Default Control Pipe Control Register */
352 #define BSTS 0x8000 /* b15: Buffer status */
353 #define SUREQ 0x4000 /* b14: Send USB request */
354 #define CSCLR 0x2000 /* b13: complete-split status clear */
355 #define CSSTS 0x1000 /* b12: complete-split status */
356 #define SUREQCLR 0x0800 /* b11: stop setup request */
357 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
358 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
359 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
360 #define PBUSY 0x0020 /* b5: pipe busy */
361 #define PINGE 0x0010 /* b4: ping enable */
362 #define CCPL 0x0004 /* b2: Enable control transfer complete */
363 #define PID 0x0003 /* b1-0: Response PID */
364 #define PID_STALL11 0x0003 /* STALL */
365 #define PID_STALL 0x0002 /* STALL */
366 #define PID_BUF 0x0001 /* BUF */
367 #define PID_NAK 0x0000 /* NAK */
368
369 /* Pipe Window Select Register */
370 #define PIPENM 0x0007 /* b2-0: Pipe select */
371
372 /* Pipe Configuration Register */
373 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
374 #define R8A66597_ISO 0xC000 /* Isochronous */
375 #define R8A66597_INT 0x8000 /* Interrupt */
376 #define R8A66597_BULK 0x4000 /* Bulk */
377 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
378 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
379 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
380 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
381 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
382 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
383
384 /* Pipe Buffer Configuration Register */
385 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
386 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
387 #define PIPE0BUF 256
388 #define PIPExBUF 64
389
390 /* Pipe Maxpacket Size Register */
391 #define MXPS 0x07FF /* b10-0: Maxpacket size */
392
393 /* Pipe Cycle Configuration Register */
394 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
395 #define IITV 0x0007 /* b2-0: Isochronous interval */
396
397 /* Pipex Control Register */
398 #define BSTS 0x8000 /* b15: Buffer status */
399 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
400 #define CSCLR 0x2000 /* b13: complete-split status clear */
401 #define CSSTS 0x1000 /* b12: complete-split status */
402 #define ATREPM 0x0400 /* b10: Auto repeat mode */
403 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
404 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
405 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
406 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
407 #define PBUSY 0x0020 /* b5: pipe busy */
408 #define PID 0x0003 /* b1-0: Response PID */
409
410 /* PIPExTRE */
411 #define TRENB 0x0200 /* b9: Transaction counter enable */
412 #define TRCLR 0x0100 /* b8: Transaction counter clear */
413
414 /* PIPExTRN */
415 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
416
417 /* DEVADDx */
418 #define UPPHUB 0x7800
419 #define HUBPORT 0x0700
420 #define USBSPD 0x00C0
421 #define RTPORT 0x0001
422
423 /* SUDMAC registers */
424 #define CH0CFG 0x00
425 #define CH1CFG 0x04
426 #define CH0BA 0x10
427 #define CH1BA 0x14
428 #define CH0BBC 0x18
429 #define CH1BBC 0x1C
430 #define CH0CA 0x20
431 #define CH1CA 0x24
432 #define CH0CBC 0x28
433 #define CH1CBC 0x2C
434 #define CH0DEN 0x30
435 #define CH1DEN 0x34
436 #define DSTSCLR 0x38
437 #define DBUFCTRL 0x3C
438 #define DINTCTRL 0x40
439 #define DINTSTS 0x44
440 #define DINTSTSCLR 0x48
441 #define CH0SHCTRL 0x50
442 #define CH1SHCTRL 0x54
443
444 /* SUDMAC Configuration Registers */
445 #define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
446 #define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
447 #define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
448
449 /* DMA Enable Registers */
450 #define DEN 0x0001 /* b1: DMA Transfer Enable */
451
452 /* DMA Status Clear Register */
453 #define CH1STCLR 0x0002 /* b2: Ch1 DMA Status Clear */
454 #define CH0STCLR 0x0001 /* b1: Ch0 DMA Status Clear */
455
456 /* DMA Buffer Control Register */
457 #define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
458 #define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
459 #define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
460 #define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
461
462 /* DMA Interrupt Control Register */
463 #define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
464 #define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
465 #define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
466 #define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
467
468 /* DMA Interrupt Status Register */
469 #define CH1ERRS 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
470 #define CH0ERRS 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
471 #define CH1ENDS 0x0002 /* b2: Ch1 DMA Transfer End Int Status */
472 #define CH0ENDS 0x0001 /* b1: Ch0 DMA Transfer End Int Status */
473
474 /* DMA Interrupt Status Clear Register */
475 #define CH1ERRC 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
476 #define CH0ERRC 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
477 #define CH1ENDC 0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
478 #define CH0ENDC 0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */
479
480 #endif /* __LINUX_USB_R8A66597_H */
481