include/asm-sh/hw_irq.h

   1 #ifndef __ASM_SH_HW_IRQ_H
   2 #define __ASM_SH_HW_IRQ_H
   3
   4 #include <linux/init.h>
   5 #include <asm/atomic.h>
   6
   7 extern atomic_t irq_err_count;
   8
   9 struct intc2_data {
  10         unsigned short irq;
  11         unsigned char ipr_offset, ipr_shift;
  12         unsigned char msk_offset, msk_shift;
  13         unsigned char priority;
  14 };
  15
  16 struct intc2_desc {
  17         unsigned long prio_base;
  18         unsigned long msk_base;
  19         unsigned long mskclr_base;
  20         struct intc2_data *intc2_data;
  21         unsigned int nr_irqs;
  22         struct irq_chip chip;
  23 };
  24
  25 void register_intc2_controller(struct intc2_desc *);
  26
  27 struct ipr_data {
  28         unsigned char irq;
  29         unsigned char ipr_idx;          /* Index for the IPR registered */
  30         unsigned char shift;            /* Number of bits to shift the data */
  31         unsigned char priority;         /* The priority */
  32 };
  33
  34 struct ipr_desc {
  35         unsigned long *ipr_offsets;
  36         unsigned int nr_offsets;
  37         struct ipr_data *ipr_data;
  38         unsigned int nr_irqs;
  39         struct irq_chip chip;
  40 };
  41
  42 void register_ipr_controller(struct ipr_desc *);
  43
  44 /*
  45  * Enable individual interrupt mode for external IPR IRQs.
  46  */
  47 void __init ipr_irq_enable_irlm(void);
  48
  49 typedef unsigned char intc_enum;
  50
  51 struct intc_vect {
  52         intc_enum enum_id;
  53         unsigned short vect;
  54 };
  55
  56 #define INTC_VECT(enum_id, vect) { enum_id, vect }
  57
  58 struct intc_prio {
  59         intc_enum enum_id;
  60         unsigned char priority;
  61 };
  62
  63 #define INTC_PRIO(enum_id, prio) { enum_id, prio }
  64
  65 struct intc_group {
  66         intc_enum enum_id;
  67         intc_enum *enum_ids;
  68 };
  69
  70 #define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
  71
  72 struct intc_mask_reg {
  73         unsigned long set_reg, clr_reg, reg_width;
  74         intc_enum enum_ids[32];
  75 };
  76
  77 struct intc_prio_reg {
  78         unsigned long reg, reg_width, field_width;
  79         intc_enum enum_ids[16];
  80 };
  81
  82 struct intc_sense_reg {
  83         unsigned long reg, reg_width, field_width;
  84         intc_enum enum_ids[16];
  85 };
  86
  87 struct intc_desc {
  88         struct intc_vect *vectors;
  89         unsigned int nr_vectors;
  90         struct intc_group *groups;
  91         unsigned int nr_groups;
  92         struct intc_prio *priorities;
  93         unsigned int nr_priorities;
  94         struct intc_mask_reg *mask_regs;
  95         unsigned int nr_mask_regs;
  96         struct intc_prio_reg *prio_regs;
  97         unsigned int nr_prio_regs;
  98         struct intc_sense_reg *sense_regs;
  99         unsigned int nr_sense_regs;
 100         struct irq_chip chip;
 101 };
 102
 103 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
 104 #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,            \
 105         priorities, mask_regs, prio_regs, sense_regs)                   \
 106 struct intc_desc symbol = {                                             \
 107         _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
 108         _INTC_ARRAY(priorities),                                        \
 109         _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
 110         _INTC_ARRAY(sense_regs),                                        \
 111         .chip.name = chipname,                                          \
 112 }
 113
 114 void __init register_intc_controller(struct intc_desc *desc);
 115
 116 void __init plat_irq_setup(void);
 117
 118 enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
 119 void __init plat_irq_setup_pins(int mode);
 120
 121 #endif /* __ASM_SH_HW_IRQ_H */