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brcm80211: fmac: remove unnecessary 4329 chip specific code
[pohmelfs.git] / drivers / net / wireless / brcm80211 / brcmfmac / dhd_sdio.c
blob2c409ca68ea70ce50f4e24b226a6edae919b084e
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <asm/unaligned.h>
32 #include <defs.h>
33 #include <brcmu_wifi.h>
34 #include <brcmu_utils.h>
35 #include <brcm_hw_ids.h>
36 #include <soc.h>
37 #include "sdio_host.h"
38
39 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
40
41 #ifdef BCMDBG
42
43 #define BRCMF_TRAP_INFO_SIZE 80
44
45 #define CBUF_LEN (128)
46
47 struct rte_log_le {
48 __le32 buf; /* Can't be pointer on (64-bit) hosts */
49 __le32 buf_size;
50 __le32 idx;
51 char *_buf_compat; /* Redundant pointer for backward compat. */
52 };
53
54 struct rte_console {
55 /* Virtual UART
56 * When there is no UART (e.g. Quickturn),
57 * the host should write a complete
58 * input line directly into cbuf and then write
59 * the length into vcons_in.
60 * This may also be used when there is a real UART
61 * (at risk of conflicting with
62 * the real UART). vcons_out is currently unused.
63 */
64 uint vcons_in;
65 uint vcons_out;
66
67 /* Output (logging) buffer
68 * Console output is written to a ring buffer log_buf at index log_idx.
69 * The host may read the output when it sees log_idx advance.
70 * Output will be lost if the output wraps around faster than the host
71 * polls.
72 */
73 struct rte_log_le log_le;
74
75 /* Console input line buffer
76 * Characters are read one at a time into cbuf
77 * until <CR> is received, then
78 * the buffer is processed as a command line.
79 * Also used for virtual UART.
80 */
81 uint cbuf_idx;
82 char cbuf[CBUF_LEN];
83 };
84
85 #endif /* BCMDBG */
86 #include <chipcommon.h>
87
88 #include "dhd.h"
89 #include "dhd_bus.h"
90 #include "dhd_proto.h"
91 #include "dhd_dbg.h"
92 #include <bcmchip.h>
93
94 #define TXQLEN 2048 /* bulk tx queue length */
95 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
96 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
97 #define PRIOMASK 7
98
99 #define TXRETRIES 2 /* # of retries for tx frames */
100
101 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
102 one scheduling */
103
104 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
105 one scheduling */
106
107 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
108
109 #define MEMBLOCK 2048 /* Block size used for downloading
110 of dongle image */
111 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
112 biggest possible glom */
113
114 #define BRCMF_FIRSTREAD (1 << 6)
115
116
117 /* SBSDIO_DEVICE_CTL */
118
119 /* 1: device will assert busy signal when receiving CMD53 */
120 #define SBSDIO_DEVCTL_SETBUSY 0x01
121 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
122 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
123 /* 1: mask all interrupts to host except the chipActive (rev 8) */
124 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
125 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
126 * sdio bus power cycle to clear (rev 9) */
127 #define SBSDIO_DEVCTL_PADS_ISO 0x08
128 /* Force SD->SB reset mapping (rev 11) */
129 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
130 /* Determined by CoreControl bit */
131 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
132 /* Force backplane reset */
133 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
134 /* Force no backplane reset */
135 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
136
137 /* SBSDIO_FUNC1_CHIPCLKCSR */
138
139 /* Force ALP request to backplane */
140 #define SBSDIO_FORCE_ALP 0x01
141 /* Force HT request to backplane */
142 #define SBSDIO_FORCE_HT 0x02
143 /* Force ILP request to backplane */
144 #define SBSDIO_FORCE_ILP 0x04
145 /* Make ALP ready (power up xtal) */
146 #define SBSDIO_ALP_AVAIL_REQ 0x08
147 /* Make HT ready (power up PLL) */
148 #define SBSDIO_HT_AVAIL_REQ 0x10
149 /* Squelch clock requests from HW */
150 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
151 /* Status: ALP is ready */
152 #define SBSDIO_ALP_AVAIL 0x40
153 /* Status: HT is ready */
154 #define SBSDIO_HT_AVAIL 0x80
155
156 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
157 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
158 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
159 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
160
161 #define SBSDIO_CLKAV(regval, alponly) \
162 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
163
164 /* direct(mapped) cis space */
165
166 /* MAPPED common CIS address */
167 #define SBSDIO_CIS_BASE_COMMON 0x1000
168 /* maximum bytes in one CIS */
169 #define SBSDIO_CIS_SIZE_LIMIT 0x200
170 /* cis offset addr is < 17 bits */
171 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
172
173 /* manfid tuple length, include tuple, link bytes */
174 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
175
176 /* intstatus */
177 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
178 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
179 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
180 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
181 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
182 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
183 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
184 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
185 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
186 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
187 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
188 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
189 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
190 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
191 #define I_PC (1 << 10) /* descriptor error */
192 #define I_PD (1 << 11) /* data error */
193 #define I_DE (1 << 12) /* Descriptor protocol Error */
194 #define I_RU (1 << 13) /* Receive descriptor Underflow */
195 #define I_RO (1 << 14) /* Receive fifo Overflow */
196 #define I_XU (1 << 15) /* Transmit fifo Underflow */
197 #define I_RI (1 << 16) /* Receive Interrupt */
198 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
199 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
200 #define I_XI (1 << 24) /* Transmit Interrupt */
201 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
202 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
203 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
204 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
205 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
206 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
207 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
208 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
209 #define I_DMA (I_RI | I_XI | I_ERRORS)
210
211 /* corecontrol */
212 #define CC_CISRDY (1 << 0) /* CIS Ready */
213 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
214 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
215 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
216 #define CC_XMTDATAAVAIL_MODE (1 << 4)
217 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
218
219 /* SDA_FRAMECTRL */
220 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
221 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
222 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
223 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
224
225 /* HW frame tag */
226 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
227
228 /* Total length of frame header for dongle protocol */
229 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
230 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
231
232 /*
233 * Software allocation of To SB Mailbox resources
234 */
235
236 /* tosbmailbox bits corresponding to intstatus bits */
237 #define SMB_NAK (1 << 0) /* Frame NAK */
238 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
239 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
240 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
241
242 /* tosbmailboxdata */
243 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
244
245 /*
246 * Software allocation of To Host Mailbox resources
247 */
248
249 /* intstatus bits */
250 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
251 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
252 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
253 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
254
255 /* tohostmailboxdata */
256 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
257 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
258 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
259 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
260
261 #define HMB_DATA_FCDATA_MASK 0xff000000
262 #define HMB_DATA_FCDATA_SHIFT 24
263
264 #define HMB_DATA_VERSION_MASK 0x00ff0000
265 #define HMB_DATA_VERSION_SHIFT 16
266
267 /*
268 * Software-defined protocol header
269 */
270
271 /* Current protocol version */
272 #define SDPCM_PROT_VERSION 4
273
274 /* SW frame header */
275 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
276
277 #define SDPCM_CHANNEL_MASK 0x00000f00
278 #define SDPCM_CHANNEL_SHIFT 8
279 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
280
281 #define SDPCM_NEXTLEN_OFFSET 2
282
283 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
284 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
285 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
286 #define SDPCM_DOFFSET_MASK 0xff000000
287 #define SDPCM_DOFFSET_SHIFT 24
288 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
289 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
290 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
291 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
292
293 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
294
295 /* logical channel numbers */
296 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
297 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
298 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
299 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
300 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
301
302 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
303
304 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
305
306 /*
307 * Shared structure between dongle and the host.
308 * The structure contains pointers to trap or assert information.
309 */
310 #define SDPCM_SHARED_VERSION 0x0002
311 #define SDPCM_SHARED_VERSION_MASK 0x00FF
312 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
313 #define SDPCM_SHARED_ASSERT 0x0200
314 #define SDPCM_SHARED_TRAP 0x0400
315
316 /* Space for header read, limit for data packets */
317 #define MAX_HDR_READ (1 << 6)
318 #define MAX_RX_DATASZ 2048
319
320 /* Maximum milliseconds to wait for F2 to come up */
321 #define BRCMF_WAIT_F2RDY 3000
322
323 /* Bump up limit on waiting for HT to account for first startup;
324 * if the image is doing a CRC calculation before programming the PMU
325 * for HT availability, it could take a couple hundred ms more, so
326 * max out at a 1 second (1000000us).
327 */
328 #undef PMU_MAX_TRANSITION_DLY
329 #define PMU_MAX_TRANSITION_DLY 1000000
330
331 /* Value for ChipClockCSR during initial setup */
332 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
333 SBSDIO_ALP_AVAIL_REQ)
334
335 /* Flags for SDH calls */
336 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
337
338 /* sbimstate */
339 #define SBIM_IBE 0x20000 /* inbanderror */
340 #define SBIM_TO 0x40000 /* timeout */
341 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
342 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
343
344 /* sbtmstatelow */
345
346 /* reset */
347 #define SBTML_RESET 0x0001
348 /* reject field */
349 #define SBTML_REJ_MASK 0x0006
350 /* reject */
351 #define SBTML_REJ 0x0002
352 /* temporary reject, for error recovery */
353 #define SBTML_TMPREJ 0x0004
354
355 /* Shift to locate the SI control flags in sbtml */
356 #define SBTML_SICF_SHIFT 16
357
358 /* sbtmstatehigh */
359 #define SBTMH_SERR 0x0001 /* serror */
360 #define SBTMH_INT 0x0002 /* interrupt */
361 #define SBTMH_BUSY 0x0004 /* busy */
362 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
363
364 /* Shift to locate the SI status flags in sbtmh */
365 #define SBTMH_SISF_SHIFT 16
366
367 /* sbidlow */
368 #define SBIDL_INIT 0x80 /* initiator */
369
370 /* sbidhigh */
371 #define SBIDH_RC_MASK 0x000f /* revision code */
372 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
373 #define SBIDH_RCE_SHIFT 8
374 #define SBCOREREV(sbidh) \
375 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
376 ((sbidh) & SBIDH_RC_MASK))
377 #define SBIDH_CC_MASK 0x8ff0 /* core code */
378 #define SBIDH_CC_SHIFT 4
379 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
380 #define SBIDH_VC_SHIFT 16
381
382 /*
383 * Conversion of 802.1D priority to precedence level
384 */
385 static uint prio2prec(u32 prio)
386 {
387 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
388 (prio^2) : prio;
389 }
390
391 /*
392 * Core reg address translation.
393 * Both macro's returns a 32 bits byte address on the backplane bus.
394 */
395 #define CORE_CC_REG(base, field) \
396 (base + offsetof(struct chipcregs, field))
397 #define CORE_BUS_REG(base, field) \
398 (base + offsetof(struct sdpcmd_regs, field))
399 #define CORE_SB(base, field) \
400 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
401
402 /* core registers */
403 struct sdpcmd_regs {
404 u32 corecontrol; /* 0x00, rev8 */
405 u32 corestatus; /* rev8 */
406 u32 PAD[1];
407 u32 biststatus; /* rev8 */
408
409 /* PCMCIA access */
410 u16 pcmciamesportaladdr; /* 0x010, rev8 */
411 u16 PAD[1];
412 u16 pcmciamesportalmask; /* rev8 */
413 u16 PAD[1];
414 u16 pcmciawrframebc; /* rev8 */
415 u16 PAD[1];
416 u16 pcmciaunderflowtimer; /* rev8 */
417 u16 PAD[1];
418
419 /* interrupt */
420 u32 intstatus; /* 0x020, rev8 */
421 u32 hostintmask; /* rev8 */
422 u32 intmask; /* rev8 */
423 u32 sbintstatus; /* rev8 */
424 u32 sbintmask; /* rev8 */
425 u32 funcintmask; /* rev4 */
426 u32 PAD[2];
427 u32 tosbmailbox; /* 0x040, rev8 */
428 u32 tohostmailbox; /* rev8 */
429 u32 tosbmailboxdata; /* rev8 */
430 u32 tohostmailboxdata; /* rev8 */
431
432 /* synchronized access to registers in SDIO clock domain */
433 u32 sdioaccess; /* 0x050, rev8 */
434 u32 PAD[3];
435
436 /* PCMCIA frame control */
437 u8 pcmciaframectrl; /* 0x060, rev8 */
438 u8 PAD[3];
439 u8 pcmciawatermark; /* rev8 */
440 u8 PAD[155];
441
442 /* interrupt batching control */
443 u32 intrcvlazy; /* 0x100, rev8 */
444 u32 PAD[3];
445
446 /* counters */
447 u32 cmd52rd; /* 0x110, rev8 */
448 u32 cmd52wr; /* rev8 */
449 u32 cmd53rd; /* rev8 */
450 u32 cmd53wr; /* rev8 */
451 u32 abort; /* rev8 */
452 u32 datacrcerror; /* rev8 */
453 u32 rdoutofsync; /* rev8 */
454 u32 wroutofsync; /* rev8 */
455 u32 writebusy; /* rev8 */
456 u32 readwait; /* rev8 */
457 u32 readterm; /* rev8 */
458 u32 writeterm; /* rev8 */
459 u32 PAD[40];
460 u32 clockctlstatus; /* rev8 */
461 u32 PAD[7];
462
463 u32 PAD[128]; /* DMA engines */
464
465 /* SDIO/PCMCIA CIS region */
466 char cis[512]; /* 0x400-0x5ff, rev6 */
467
468 /* PCMCIA function control registers */
469 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
470 u16 PAD[55];
471
472 /* PCMCIA backplane access */
473 u16 backplanecsr; /* 0x76E, rev6 */
474 u16 backplaneaddr0; /* rev6 */
475 u16 backplaneaddr1; /* rev6 */
476 u16 backplaneaddr2; /* rev6 */
477 u16 backplaneaddr3; /* rev6 */
478 u16 backplanedata0; /* rev6 */
479 u16 backplanedata1; /* rev6 */
480 u16 backplanedata2; /* rev6 */
481 u16 backplanedata3; /* rev6 */
482 u16 PAD[31];
483
484 /* sprom "size" & "blank" info */
485 u16 spromstatus; /* 0x7BE, rev2 */
486 u32 PAD[464];
487
488 u16 PAD[0x80];
489 };
490
491 #ifdef BCMDBG
492 /* Device console log buffer state */
493 struct brcmf_console {
494 uint count; /* Poll interval msec counter */
495 uint log_addr; /* Log struct address (fixed) */
496 struct rte_log_le log_le; /* Log struct (host copy) */
497 uint bufsize; /* Size of log buffer */
498 u8 *buf; /* Log buffer (host copy) */
499 uint last; /* Last buffer read index */
500 };
501 #endif /* BCMDBG */
502
503 struct sdpcm_shared {
504 u32 flags;
505 u32 trap_addr;
506 u32 assert_exp_addr;
507 u32 assert_file_addr;
508 u32 assert_line;
509 u32 console_addr; /* Address of struct rte_console */
510 u32 msgtrace_addr;
511 u8 tag[32];
512 };
513
514 struct sdpcm_shared_le {
515 __le32 flags;
516 __le32 trap_addr;
517 __le32 assert_exp_addr;
518 __le32 assert_file_addr;
519 __le32 assert_line;
520 __le32 console_addr; /* Address of struct rte_console */
521 __le32 msgtrace_addr;
522 u8 tag[32];
523 };
524
525
526 /* misc chip info needed by some of the routines */
527 struct chip_info {
528 u32 chip;
529 u32 chiprev;
530 u32 cccorebase;
531 u32 ccrev;
532 u32 cccaps;
533 u32 buscorebase; /* 32 bits backplane bus address */
534 u32 buscorerev;
535 u32 buscoretype;
536 u32 ramcorebase;
537 u32 armcorebase;
538 u32 pmurev;
539 u32 ramsize;
540 };
541
542 /* Private data for SDIO bus interaction */
543 struct brcmf_bus {
544 struct brcmf_pub *drvr;
545
546 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
547 struct chip_info *ci; /* Chip info struct */
548 char *vars; /* Variables (from CIS and/or other) */
549 uint varsz; /* Size of variables buffer */
550
551 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
552
553 u32 hostintmask; /* Copy of Host Interrupt Mask */
554 u32 intstatus; /* Intstatus bits (events) pending */
555 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
556 bool fcstate; /* State of dongle flow-control */
557
558 uint blocksize; /* Block size of SDIO transfers */
559 uint roundup; /* Max roundup limit */
560
561 struct pktq txq; /* Queue length used for flow-control */
562 u8 flowcontrol; /* per prio flow control bitmask */
563 u8 tx_seq; /* Transmit sequence number (next) */
564 u8 tx_max; /* Maximum transmit sequence allowed */
565
566 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
567 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
568 u16 nextlen; /* Next Read Len from last header */
569 u8 rx_seq; /* Receive sequence number (expected) */
570 bool rxskip; /* Skip receive (awaiting NAK ACK) */
571
572 uint rxbound; /* Rx frames to read before resched */
573 uint txbound; /* Tx frames to send before resched */
574 uint txminmax;
575
576 struct sk_buff *glomd; /* Packet containing glomming descriptor */
577 struct sk_buff_head glom; /* Packet list for glommed superframe */
578 uint glomerr; /* Glom packet read errors */
579
580 u8 *rxbuf; /* Buffer for receiving control packets */
581 uint rxblen; /* Allocated length of rxbuf */
582 u8 *rxctl; /* Aligned pointer into rxbuf */
583 u8 *databuf; /* Buffer for receiving big glom packet */
584 u8 *dataptr; /* Aligned pointer into databuf */
585 uint rxlen; /* Length of valid data in buffer */
586
587 u8 sdpcm_ver; /* Bus protocol reported by dongle */
588
589 bool intr; /* Use interrupts */
590 bool poll; /* Use polling */
591 bool ipend; /* Device interrupt is pending */
592 uint intrcount; /* Count of device interrupt callbacks */
593 uint lastintrs; /* Count as of last watchdog timer */
594 uint spurious; /* Count of spurious interrupts */
595 uint pollrate; /* Ticks between device polls */
596 uint polltick; /* Tick counter */
597 uint pollcnt; /* Count of active polls */
598
599 #ifdef BCMDBG
600 uint console_interval;
601 struct brcmf_console console; /* Console output polling support */
602 uint console_addr; /* Console address from shared struct */
603 #endif /* BCMDBG */
604
605 uint regfails; /* Count of R_REG failures */
606
607 uint clkstate; /* State of sd and backplane clock(s) */
608 bool activity; /* Activity flag for clock down */
609 s32 idletime; /* Control for activity timeout */
610 s32 idlecount; /* Activity timeout counter */
611 s32 idleclock; /* How to set bus driver when idle */
612 s32 sd_rxchain;
613 bool use_rxchain; /* If brcmf should use PKT chains */
614 bool sleeping; /* Is SDIO bus sleeping? */
615 bool rxflow_mode; /* Rx flow control mode */
616 bool rxflow; /* Is rx flow control on */
617 bool alp_only; /* Don't use HT clock (ALP only) */
618 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
619 bool usebufpool;
620
621 /* Some additional counters */
622 uint tx_sderrs; /* Count of tx attempts with sd errors */
623 uint fcqueued; /* Tx packets that got queued */
624 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
625 uint rx_toolong; /* Receive frames too long to receive */
626 uint rxc_errors; /* SDIO errors when reading control frames */
627 uint rx_hdrfail; /* SDIO errors on header reads */
628 uint rx_badhdr; /* Bad received headers (roosync?) */
629 uint rx_badseq; /* Mismatched rx sequence number */
630 uint fc_rcvd; /* Number of flow-control events received */
631 uint fc_xoff; /* Number which turned on flow-control */
632 uint fc_xon; /* Number which turned off flow-control */
633 uint rxglomfail; /* Failed deglom attempts */
634 uint rxglomframes; /* Number of glom frames (superframes) */
635 uint rxglompkts; /* Number of packets from glom frames */
636 uint f2rxhdrs; /* Number of header reads */
637 uint f2rxdata; /* Number of frame data reads */
638 uint f2txdata; /* Number of f2 frame writes */
639 uint f1regdata; /* Number of f1 register accesses */
640
641 u8 *ctrl_frame_buf;
642 u32 ctrl_frame_len;
643 bool ctrl_frame_stat;
644
645 spinlock_t txqlock;
646 wait_queue_head_t ctrl_wait;
647 wait_queue_head_t dcmd_resp_wait;
648
649 struct timer_list timer;
650 struct completion watchdog_wait;
651 struct task_struct *watchdog_tsk;
652 bool wd_timer_valid;
653 uint save_ms;
654
655 struct task_struct *dpc_tsk;
656 struct completion dpc_wait;
657
658 struct semaphore sdsem;
659
660 const char *fw_name;
661 const struct firmware *firmware;
662 const char *nv_name;
663 u32 fw_ptr;
664 };
665
666 struct sbconfig {
667 u32 PAD[2];
668 u32 sbipsflag; /* initiator port ocp slave flag */
669 u32 PAD[3];
670 u32 sbtpsflag; /* target port ocp slave flag */
671 u32 PAD[11];
672 u32 sbtmerrloga; /* (sonics >= 2.3) */
673 u32 PAD;
674 u32 sbtmerrlog; /* (sonics >= 2.3) */
675 u32 PAD[3];
676 u32 sbadmatch3; /* address match3 */
677 u32 PAD;
678 u32 sbadmatch2; /* address match2 */
679 u32 PAD;
680 u32 sbadmatch1; /* address match1 */
681 u32 PAD[7];
682 u32 sbimstate; /* initiator agent state */
683 u32 sbintvec; /* interrupt mask */
684 u32 sbtmstatelow; /* target state */
685 u32 sbtmstatehigh; /* target state */
686 u32 sbbwa0; /* bandwidth allocation table0 */
687 u32 PAD;
688 u32 sbimconfiglow; /* initiator configuration */
689 u32 sbimconfighigh; /* initiator configuration */
690 u32 sbadmatch0; /* address match0 */
691 u32 PAD;
692 u32 sbtmconfiglow; /* target configuration */
693 u32 sbtmconfighigh; /* target configuration */
694 u32 sbbconfig; /* broadcast configuration */
695 u32 PAD;
696 u32 sbbstate; /* broadcast state */
697 u32 PAD[3];
698 u32 sbactcnfg; /* activate configuration */
699 u32 PAD[3];
700 u32 sbflagst; /* current sbflags */
701 u32 PAD[3];
702 u32 sbidlow; /* identification */
703 u32 sbidhigh; /* identification */
704 };
705
706 /* clkstate */
707 #define CLK_NONE 0
708 #define CLK_SDONLY 1
709 #define CLK_PENDING 2 /* Not used yet */
710 #define CLK_AVAIL 3
711
712 #ifdef BCMDBG
713 static int qcount[NUMPRIO];
714 static int tx_packets[NUMPRIO];
715 #endif /* BCMDBG */
716
717 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
718
719 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
720
721 /* Retry count for register access failures */
722 static const uint retry_limit = 2;
723
724 /* Limit on rounding up frames */
725 static const uint max_roundup = 512;
726
727 #define ALIGNMENT 4
728
729 static void pkt_align(struct sk_buff *p, int len, int align)
730 {
731 uint datalign;
732 datalign = (unsigned long)(p->data);
733 datalign = roundup(datalign, (align)) - datalign;
734 if (datalign)
735 skb_pull(p, datalign);
736 __skb_trim(p, len);
737 }
738
739 /* To check if there's window offered */
740 static bool data_ok(struct brcmf_bus *bus)
741 {
742 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
743 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
744 }
745
746 /*
747 * Reads a register in the SDIO hardware block. This block occupies a series of
748 * adresses on the 32 bit backplane bus.
749 */
750 static void
751 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
752 {
753 *retryvar = 0;
754 do {
755 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
756 bus->ci->buscorebase + reg_offset, sizeof(u32));
757 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
758 (++(*retryvar) <= retry_limit));
759 if (*retryvar) {
760 bus->regfails += (*retryvar-1);
761 if (*retryvar > retry_limit) {
762 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
763 *regvar = 0;
764 }
765 }
766 }
767
768 static void
769 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
770 {
771 *retryvar = 0;
772 do {
773 brcmf_sdcard_reg_write(bus->sdiodev,
774 bus->ci->buscorebase + reg_offset,
775 sizeof(u32), regval);
776 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
777 (++(*retryvar) <= retry_limit));
778 if (*retryvar) {
779 bus->regfails += (*retryvar-1);
780 if (*retryvar > retry_limit)
781 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
782 reg_offset);
783 }
784 }
785
786 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
787
788 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
789
790 /* Packet free applicable unconditionally for sdio and sdspi.
791 * Conditional if bufpool was present for gspi bus.
792 */
793 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
794 {
795 if (bus->usebufpool)
796 brcmu_pkt_buf_free_skb(pkt);
797 }
798
799 /* Turn backplane clock on or off */
800 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
801 {
802 int err;
803 u8 clkctl, clkreq, devctl;
804 unsigned long timeout;
805
806 brcmf_dbg(TRACE, "Enter\n");
807
808 clkctl = 0;
809
810 if (on) {
811 /* Request HT Avail */
812 clkreq =
813 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
814
815 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
816 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
817 if (err) {
818 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
819 return -EBADE;
820 }
821
822 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
823 && (bus->ci->buscorerev == 9))) {
824 u32 dummy, retries;
825 r_sdreg32(bus, &dummy,
826 offsetof(struct sdpcmd_regs, clockctlstatus),
827 &retries);
828 }
829
830 /* Check current status */
831 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
832 SBSDIO_FUNC1_CHIPCLKCSR, &err);
833 if (err) {
834 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
835 return -EBADE;
836 }
837
838 /* Go to pending and await interrupt if appropriate */
839 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
840 /* Allow only clock-available interrupt */
841 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
842 SDIO_FUNC_1,
843 SBSDIO_DEVICE_CTL, &err);
844 if (err) {
845 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
846 err);
847 return -EBADE;
848 }
849
850 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
851 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
852 SBSDIO_DEVICE_CTL, devctl, &err);
853 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
854 bus->clkstate = CLK_PENDING;
855
856 return 0;
857 } else if (bus->clkstate == CLK_PENDING) {
858 /* Cancel CA-only interrupt filter */
859 devctl =
860 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
861 SBSDIO_DEVICE_CTL, &err);
862 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
863 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
864 SBSDIO_DEVICE_CTL, devctl, &err);
865 }
866
867 /* Otherwise, wait here (polling) for HT Avail */
868 timeout = jiffies +
869 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
870 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
871 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
872 SDIO_FUNC_1,
873 SBSDIO_FUNC1_CHIPCLKCSR,
874 &err);
875 if (time_after(jiffies, timeout))
876 break;
877 else
878 usleep_range(5000, 10000);
879 }
880 if (err) {
881 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
882 return -EBADE;
883 }
884 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
885 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
886 PMU_MAX_TRANSITION_DLY, clkctl);
887 return -EBADE;
888 }
889
890 /* Mark clock available */
891 bus->clkstate = CLK_AVAIL;
892 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
893
894 #if defined(BCMDBG)
895 if (bus->alp_only != true) {
896 if (SBSDIO_ALPONLY(clkctl))
897 brcmf_dbg(ERROR, "HT Clock should be on\n");
898 }
899 #endif /* defined (BCMDBG) */
900
901 bus->activity = true;
902 } else {
903 clkreq = 0;
904
905 if (bus->clkstate == CLK_PENDING) {
906 /* Cancel CA-only interrupt filter */
907 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
908 SDIO_FUNC_1,
909 SBSDIO_DEVICE_CTL, &err);
910 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
911 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
912 SBSDIO_DEVICE_CTL, devctl, &err);
913 }
914
915 bus->clkstate = CLK_SDONLY;
916 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
917 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
918 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
919 if (err) {
920 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
921 err);
922 return -EBADE;
923 }
924 }
925 return 0;
926 }
927
928 /* Change idle/active SD state */
929 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
930 {
931 brcmf_dbg(TRACE, "Enter\n");
932
933 if (on)
934 bus->clkstate = CLK_SDONLY;
935 else
936 bus->clkstate = CLK_NONE;
937
938 return 0;
939 }
940
941 /* Transition SD and backplane clock readiness */
942 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
943 {
944 #ifdef BCMDBG
945 uint oldstate = bus->clkstate;
946 #endif /* BCMDBG */
947
948 brcmf_dbg(TRACE, "Enter\n");
949
950 /* Early exit if we're already there */
951 if (bus->clkstate == target) {
952 if (target == CLK_AVAIL) {
953 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
954 bus->activity = true;
955 }
956 return 0;
957 }
958
959 switch (target) {
960 case CLK_AVAIL:
961 /* Make sure SD clock is available */
962 if (bus->clkstate == CLK_NONE)
963 brcmf_sdbrcm_sdclk(bus, true);
964 /* Now request HT Avail on the backplane */
965 brcmf_sdbrcm_htclk(bus, true, pendok);
966 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
967 bus->activity = true;
968 break;
969
970 case CLK_SDONLY:
971 /* Remove HT request, or bring up SD clock */
972 if (bus->clkstate == CLK_NONE)
973 brcmf_sdbrcm_sdclk(bus, true);
974 else if (bus->clkstate == CLK_AVAIL)
975 brcmf_sdbrcm_htclk(bus, false, false);
976 else
977 brcmf_dbg(ERROR, "request for %d -> %d\n",
978 bus->clkstate, target);
979 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
980 break;
981
982 case CLK_NONE:
983 /* Make sure to remove HT request */
984 if (bus->clkstate == CLK_AVAIL)
985 brcmf_sdbrcm_htclk(bus, false, false);
986 /* Now remove the SD clock */
987 brcmf_sdbrcm_sdclk(bus, false);
988 brcmf_sdbrcm_wd_timer(bus, 0);
989 break;
990 }
991 #ifdef BCMDBG
992 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
993 #endif /* BCMDBG */
994
995 return 0;
996 }
997
998 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
999 {
1000 uint retries = 0;
1001
1002 brcmf_dbg(INFO, "request %s (currently %s)\n",
1003 sleep ? "SLEEP" : "WAKE",
1004 bus->sleeping ? "SLEEP" : "WAKE");
1005
1006 /* Done if we're already in the requested state */
1007 if (sleep == bus->sleeping)
1008 return 0;
1009
1010 /* Going to sleep: set the alarm and turn off the lights... */
1011 if (sleep) {
1012 /* Don't sleep if something is pending */
1013 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1014 return -EBUSY;
1015
1016 /* Make sure the controller has the bus up */
1017 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1018
1019 /* Tell device to start using OOB wakeup */
1020 w_sdreg32(bus, SMB_USE_OOB,
1021 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1022 if (retries > retry_limit)
1023 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1024
1025 /* Turn off our contribution to the HT clock request */
1026 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1027
1028 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1029 SBSDIO_FUNC1_CHIPCLKCSR,
1030 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1031
1032 /* Isolate the bus */
1033 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1034 SBSDIO_DEVICE_CTL,
1035 SBSDIO_DEVCTL_PADS_ISO, NULL);
1036
1037 /* Change state */
1038 bus->sleeping = true;
1039
1040 } else {
1041 /* Waking up: bus power up is ok, set local state */
1042
1043 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1044 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1045
1046 /* Force pad isolation off if possible
1047 (in case power never toggled) */
1048 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1049 && (bus->ci->buscorerev >= 10))
1050 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1051 SBSDIO_DEVICE_CTL, 0, NULL);
1052
1053 /* Make sure the controller has the bus up */
1054 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1055
1056 /* Send misc interrupt to indicate OOB not needed */
1057 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1058 &retries);
1059 if (retries <= retry_limit)
1060 w_sdreg32(bus, SMB_DEV_INT,
1061 offsetof(struct sdpcmd_regs, tosbmailbox),
1062 &retries);
1063
1064 if (retries > retry_limit)
1065 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1066
1067 /* Make sure we have SD bus access */
1068 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1069
1070 /* Change state */
1071 bus->sleeping = false;
1072 }
1073
1074 return 0;
1075 }
1076
1077 static void bus_wake(struct brcmf_bus *bus)
1078 {
1079 if (bus->sleeping)
1080 brcmf_sdbrcm_bussleep(bus, false);
1081 }
1082
1083 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1084 {
1085 u32 intstatus = 0;
1086 u32 hmb_data;
1087 u8 fcbits;
1088 uint retries = 0;
1089
1090 brcmf_dbg(TRACE, "Enter\n");
1091
1092 /* Read mailbox data and ack that we did so */
1093 r_sdreg32(bus, &hmb_data,
1094 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1095
1096 if (retries <= retry_limit)
1097 w_sdreg32(bus, SMB_INT_ACK,
1098 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1099 bus->f1regdata += 2;
1100
1101 /* Dongle recomposed rx frames, accept them again */
1102 if (hmb_data & HMB_DATA_NAKHANDLED) {
1103 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1104 bus->rx_seq);
1105 if (!bus->rxskip)
1106 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1107
1108 bus->rxskip = false;
1109 intstatus |= I_HMB_FRAME_IND;
1110 }
1111
1112 /*
1113 * DEVREADY does not occur with gSPI.
1114 */
1115 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1116 bus->sdpcm_ver =
1117 (hmb_data & HMB_DATA_VERSION_MASK) >>
1118 HMB_DATA_VERSION_SHIFT;
1119 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1120 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1121 "expecting %d\n",
1122 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1123 else
1124 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1125 bus->sdpcm_ver);
1126 }
1127
1128 /*
1129 * Flow Control has been moved into the RX headers and this out of band
1130 * method isn't used any more.
1131 * remaining backward compatible with older dongles.
1132 */
1133 if (hmb_data & HMB_DATA_FC) {
1134 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1135 HMB_DATA_FCDATA_SHIFT;
1136
1137 if (fcbits & ~bus->flowcontrol)
1138 bus->fc_xoff++;
1139
1140 if (bus->flowcontrol & ~fcbits)
1141 bus->fc_xon++;
1142
1143 bus->fc_rcvd++;
1144 bus->flowcontrol = fcbits;
1145 }
1146
1147 /* Shouldn't be any others */
1148 if (hmb_data & ~(HMB_DATA_DEVREADY |
1149 HMB_DATA_NAKHANDLED |
1150 HMB_DATA_FC |
1151 HMB_DATA_FWREADY |
1152 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1153 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1154 hmb_data);
1155
1156 return intstatus;
1157 }
1158
1159 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1160 {
1161 uint retries = 0;
1162 u16 lastrbc;
1163 u8 hi, lo;
1164 int err;
1165
1166 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1167 abort ? "abort command, " : "",
1168 rtx ? ", send NAK" : "");
1169
1170 if (abort)
1171 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1172
1173 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1174 SBSDIO_FUNC1_FRAMECTRL,
1175 SFC_RF_TERM, &err);
1176 bus->f1regdata++;
1177
1178 /* Wait until the packet has been flushed (device/FIFO stable) */
1179 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1180 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1181 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1182 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1183 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1184 bus->f1regdata += 2;
1185
1186 if ((hi == 0) && (lo == 0))
1187 break;
1188
1189 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1190 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1191 lastrbc, (hi << 8) + lo);
1192 }
1193 lastrbc = (hi << 8) + lo;
1194 }
1195
1196 if (!retries)
1197 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1198 else
1199 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1200
1201 if (rtx) {
1202 bus->rxrtx++;
1203 w_sdreg32(bus, SMB_NAK,
1204 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1205
1206 bus->f1regdata++;
1207 if (retries <= retry_limit)
1208 bus->rxskip = true;
1209 }
1210
1211 /* Clear partial in any case */
1212 bus->nextlen = 0;
1213
1214 /* If we can't reach the device, signal failure */
1215 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1216 bus->drvr->busstate = BRCMF_BUS_DOWN;
1217 }
1218
1219 /* copy a buffer into a pkt buffer chain */
1220 static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
1221 {
1222 uint n, ret = 0;
1223 struct sk_buff *p;
1224 u8 *buf;
1225
1226 buf = bus->dataptr;
1227
1228 /* copy the data */
1229 skb_queue_walk(&bus->glom, p) {
1230 n = min_t(uint, p->len, len);
1231 memcpy(p->data, buf, n);
1232 buf += n;
1233 len -= n;
1234 ret += n;
1235 if (!len)
1236 break;
1237 }
1238
1239 return ret;
1240 }
1241
1242 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1243 {
1244 u16 dlen, totlen;
1245 u8 *dptr, num = 0;
1246
1247 u16 sublen, check;
1248 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1249
1250 int errcode;
1251 u8 chan, seq, doff, sfdoff;
1252 u8 txmax;
1253
1254 int ifidx = 0;
1255 bool usechain = bus->use_rxchain;
1256
1257 /* If packets, issue read(s) and send up packet chain */
1258 /* Return sequence numbers consumed? */
1259
1260 brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
1261 bus->glomd, skb_peek(&bus->glom));
1262
1263 /* If there's a descriptor, generate the packet chain */
1264 if (bus->glomd) {
1265 pfirst = plast = pnext = NULL;
1266 dlen = (u16) (bus->glomd->len);
1267 dptr = bus->glomd->data;
1268 if (!dlen || (dlen & 1)) {
1269 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1270 dlen);
1271 dlen = 0;
1272 }
1273
1274 for (totlen = num = 0; dlen; num++) {
1275 /* Get (and move past) next length */
1276 sublen = get_unaligned_le16(dptr);
1277 dlen -= sizeof(u16);
1278 dptr += sizeof(u16);
1279 if ((sublen < SDPCM_HDRLEN) ||
1280 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1281 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1282 num, sublen);
1283 pnext = NULL;
1284 break;
1285 }
1286 if (sublen % BRCMF_SDALIGN) {
1287 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1288 sublen, BRCMF_SDALIGN);
1289 usechain = false;
1290 }
1291 totlen += sublen;
1292
1293 /* For last frame, adjust read len so total
1294 is a block multiple */
1295 if (!dlen) {
1296 sublen +=
1297 (roundup(totlen, bus->blocksize) - totlen);
1298 totlen = roundup(totlen, bus->blocksize);
1299 }
1300
1301 /* Allocate/chain packet for next subframe */
1302 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1303 if (pnext == NULL) {
1304 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1305 num, sublen);
1306 break;
1307 }
1308 skb_queue_tail(&bus->glom, pnext);
1309
1310 /* Adhere to start alignment requirements */
1311 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1312 }
1313
1314 /* If all allocations succeeded, save packet chain
1315 in bus structure */
1316 if (pnext) {
1317 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1318 totlen, num);
1319 if (BRCMF_GLOM_ON() && bus->nextlen &&
1320 totlen != bus->nextlen) {
1321 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1322 bus->nextlen, totlen, rxseq);
1323 }
1324 pfirst = pnext = NULL;
1325 } else {
1326 if (!skb_queue_empty(&bus->glom))
1327 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1328 skb_unlink(pfirst, &bus->glom);
1329 brcmu_pkt_buf_free_skb(pfirst);
1330 }
1331 num = 0;
1332 }
1333
1334 /* Done with descriptor packet */
1335 brcmu_pkt_buf_free_skb(bus->glomd);
1336 bus->glomd = NULL;
1337 bus->nextlen = 0;
1338 }
1339
1340 /* Ok -- either we just generated a packet chain,
1341 or had one from before */
1342 if (!skb_queue_empty(&bus->glom)) {
1343 if (BRCMF_GLOM_ON()) {
1344 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1345 skb_queue_walk(&bus->glom, pnext) {
1346 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1347 pnext, (u8 *) (pnext->data),
1348 pnext->len, pnext->len);
1349 }
1350 }
1351
1352 pfirst = skb_peek(&bus->glom);
1353 dlen = (u16) brcmu_pkttotlen(pfirst);
1354
1355 /* Do an SDIO read for the superframe. Configurable iovar to
1356 * read directly into the chained packet, or allocate a large
1357 * packet and and copy into the chain.
1358 */
1359 if (usechain) {
1360 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1361 bus->sdiodev->sbwad,
1362 SDIO_FUNC_2,
1363 F2SYNC, (u8 *) pfirst->data, dlen,
1364 pfirst);
1365 } else if (bus->dataptr) {
1366 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1367 bus->sdiodev->sbwad,
1368 SDIO_FUNC_2,
1369 F2SYNC, bus->dataptr, dlen,
1370 NULL);
1371 sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
1372 if (sublen != dlen) {
1373 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1374 dlen, sublen);
1375 errcode = -1;
1376 }
1377 pnext = NULL;
1378 } else {
1379 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1380 dlen);
1381 errcode = -1;
1382 }
1383 bus->f2rxdata++;
1384
1385 /* On failure, kill the superframe, allow a couple retries */
1386 if (errcode < 0) {
1387 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1388 dlen, errcode);
1389 bus->drvr->rx_errors++;
1390
1391 if (bus->glomerr++ < 3) {
1392 brcmf_sdbrcm_rxfail(bus, true, true);
1393 } else {
1394 bus->glomerr = 0;
1395 brcmf_sdbrcm_rxfail(bus, true, false);
1396 bus->rxglomfail++;
1397 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1398 skb_unlink(pfirst, &bus->glom);
1399 brcmu_pkt_buf_free_skb(pfirst);
1400 }
1401 }
1402 return 0;
1403 }
1404 #ifdef BCMDBG
1405 if (BRCMF_GLOM_ON()) {
1406 printk(KERN_DEBUG "SUPERFRAME:\n");
1407 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1408 pfirst->data, min_t(int, pfirst->len, 48));
1409 }
1410 #endif
1411
1412 /* Validate the superframe header */
1413 dptr = (u8 *) (pfirst->data);
1414 sublen = get_unaligned_le16(dptr);
1415 check = get_unaligned_le16(dptr + sizeof(u16));
1416
1417 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1418 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1419 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1420 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1421 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1422 bus->nextlen, seq);
1423 bus->nextlen = 0;
1424 }
1425 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1426 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1427
1428 errcode = 0;
1429 if ((u16)~(sublen ^ check)) {
1430 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1431 sublen, check);
1432 errcode = -1;
1433 } else if (roundup(sublen, bus->blocksize) != dlen) {
1434 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1435 sublen, roundup(sublen, bus->blocksize),
1436 dlen);
1437 errcode = -1;
1438 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1439 SDPCM_GLOM_CHANNEL) {
1440 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1441 SDPCM_PACKET_CHANNEL(
1442 &dptr[SDPCM_FRAMETAG_LEN]));
1443 errcode = -1;
1444 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1445 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1446 errcode = -1;
1447 } else if ((doff < SDPCM_HDRLEN) ||
1448 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1449 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1450 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1451 errcode = -1;
1452 }
1453
1454 /* Check sequence number of superframe SW header */
1455 if (rxseq != seq) {
1456 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1457 seq, rxseq);
1458 bus->rx_badseq++;
1459 rxseq = seq;
1460 }
1461
1462 /* Check window for sanity */
1463 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1464 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1465 txmax, bus->tx_seq);
1466 txmax = bus->tx_seq + 2;
1467 }
1468 bus->tx_max = txmax;
1469
1470 /* Remove superframe header, remember offset */
1471 skb_pull(pfirst, doff);
1472 sfdoff = doff;
1473
1474 /* Validate all the subframe headers */
1475 for (num = 0, pnext = pfirst; pnext && !errcode;
1476 num++, pnext = pnext->next) {
1477 dptr = (u8 *) (pnext->data);
1478 dlen = (u16) (pnext->len);
1479 sublen = get_unaligned_le16(dptr);
1480 check = get_unaligned_le16(dptr + sizeof(u16));
1481 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1482 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1483 #ifdef BCMDBG
1484 if (BRCMF_GLOM_ON()) {
1485 printk(KERN_DEBUG "subframe:\n");
1486 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1487 dptr, 32);
1488 }
1489 #endif
1490
1491 if ((u16)~(sublen ^ check)) {
1492 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1493 num, sublen, check);
1494 errcode = -1;
1495 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1496 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1497 num, sublen, dlen);
1498 errcode = -1;
1499 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1500 (chan != SDPCM_EVENT_CHANNEL)) {
1501 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1502 num, chan);
1503 errcode = -1;
1504 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1505 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1506 num, doff, sublen, SDPCM_HDRLEN);
1507 errcode = -1;
1508 }
1509 }
1510
1511 if (errcode) {
1512 /* Terminate frame on error, request
1513 a couple retries */
1514 if (bus->glomerr++ < 3) {
1515 /* Restore superframe header space */
1516 skb_push(pfirst, sfdoff);
1517 brcmf_sdbrcm_rxfail(bus, true, true);
1518 } else {
1519 bus->glomerr = 0;
1520 brcmf_sdbrcm_rxfail(bus, true, false);
1521 bus->rxglomfail++;
1522 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1523 skb_unlink(pfirst, &bus->glom);
1524 brcmu_pkt_buf_free_skb(pfirst);
1525 }
1526 }
1527 bus->nextlen = 0;
1528 return 0;
1529 }
1530
1531 /* Basic SD framing looks ok - process each packet (header) */
1532 save_pfirst = pfirst;
1533 plast = NULL;
1534
1535 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1536 pnext = pfirst->next;
1537 pfirst->next = NULL;
1538
1539 dptr = (u8 *) (pfirst->data);
1540 sublen = get_unaligned_le16(dptr);
1541 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1542 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1543 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1544
1545 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1546 num, pfirst, pfirst->data,
1547 pfirst->len, sublen, chan, seq);
1548
1549 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1550 chan == SDPCM_EVENT_CHANNEL */
1551
1552 if (rxseq != seq) {
1553 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1554 seq, rxseq);
1555 bus->rx_badseq++;
1556 rxseq = seq;
1557 }
1558 #ifdef BCMDBG
1559 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1560 printk(KERN_DEBUG "Rx Subframe Data:\n");
1561 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1562 dptr, dlen);
1563 }
1564 #endif
1565
1566 __skb_trim(pfirst, sublen);
1567 skb_pull(pfirst, doff);
1568
1569 if (pfirst->len == 0) {
1570 brcmu_pkt_buf_free_skb(pfirst);
1571 if (plast)
1572 plast->next = pnext;
1573 else
1574 save_pfirst = pnext;
1575
1576 continue;
1577 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1578 pfirst) != 0) {
1579 brcmf_dbg(ERROR, "rx protocol error\n");
1580 bus->drvr->rx_errors++;
1581 brcmu_pkt_buf_free_skb(pfirst);
1582 if (plast)
1583 plast->next = pnext;
1584 else
1585 save_pfirst = pnext;
1586
1587 continue;
1588 }
1589
1590 /* this packet will go up, link back into
1591 chain and count it */
1592 pfirst->next = pnext;
1593 plast = pfirst;
1594 num++;
1595
1596 #ifdef BCMDBG
1597 if (BRCMF_GLOM_ON()) {
1598 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1599 num, pfirst, pfirst->data,
1600 pfirst->len, pfirst->next,
1601 pfirst->prev);
1602 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1603 pfirst->data,
1604 min_t(int, pfirst->len, 32));
1605 }
1606 #endif /* BCMDBG */
1607 }
1608 if (num) {
1609 up(&bus->sdsem);
1610 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1611 down(&bus->sdsem);
1612 }
1613
1614 bus->rxglomframes++;
1615 bus->rxglompkts += num;
1616 }
1617 return num;
1618 }
1619
1620 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1621 bool *pending)
1622 {
1623 DECLARE_WAITQUEUE(wait, current);
1624 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1625
1626 /* Wait until control frame is available */
1627 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1628 set_current_state(TASK_INTERRUPTIBLE);
1629
1630 while (!(*condition) && (!signal_pending(current) && timeout))
1631 timeout = schedule_timeout(timeout);
1632
1633 if (signal_pending(current))
1634 *pending = true;
1635
1636 set_current_state(TASK_RUNNING);
1637 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1638
1639 return timeout;
1640 }
1641
1642 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1643 {
1644 if (waitqueue_active(&bus->dcmd_resp_wait))
1645 wake_up_interruptible(&bus->dcmd_resp_wait);
1646
1647 return 0;
1648 }
1649 static void
1650 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1651 {
1652 uint rdlen, pad;
1653
1654 int sdret;
1655
1656 brcmf_dbg(TRACE, "Enter\n");
1657
1658 /* Set rxctl for frame (w/optional alignment) */
1659 bus->rxctl = bus->rxbuf;
1660 bus->rxctl += BRCMF_FIRSTREAD;
1661 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1662 if (pad)
1663 bus->rxctl += (BRCMF_SDALIGN - pad);
1664 bus->rxctl -= BRCMF_FIRSTREAD;
1665
1666 /* Copy the already-read portion over */
1667 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1668 if (len <= BRCMF_FIRSTREAD)
1669 goto gotpkt;
1670
1671 /* Raise rdlen to next SDIO block to avoid tail command */
1672 rdlen = len - BRCMF_FIRSTREAD;
1673 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1674 pad = bus->blocksize - (rdlen % bus->blocksize);
1675 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1676 ((len + pad) < bus->drvr->maxctl))
1677 rdlen += pad;
1678 } else if (rdlen % BRCMF_SDALIGN) {
1679 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1680 }
1681
1682 /* Satisfy length-alignment requirements */
1683 if (rdlen & (ALIGNMENT - 1))
1684 rdlen = roundup(rdlen, ALIGNMENT);
1685
1686 /* Drop if the read is too big or it exceeds our maximum */
1687 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1688 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1689 rdlen, bus->drvr->maxctl);
1690 bus->drvr->rx_errors++;
1691 brcmf_sdbrcm_rxfail(bus, false, false);
1692 goto done;
1693 }
1694
1695 if ((len - doff) > bus->drvr->maxctl) {
1696 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1697 len, len - doff, bus->drvr->maxctl);
1698 bus->drvr->rx_errors++;
1699 bus->rx_toolong++;
1700 brcmf_sdbrcm_rxfail(bus, false, false);
1701 goto done;
1702 }
1703
1704 /* Read remainder of frame body into the rxctl buffer */
1705 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1706 bus->sdiodev->sbwad,
1707 SDIO_FUNC_2,
1708 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1709 NULL);
1710 bus->f2rxdata++;
1711
1712 /* Control frame failures need retransmission */
1713 if (sdret < 0) {
1714 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1715 rdlen, sdret);
1716 bus->rxc_errors++;
1717 brcmf_sdbrcm_rxfail(bus, true, true);
1718 goto done;
1719 }
1720
1721 gotpkt:
1722
1723 #ifdef BCMDBG
1724 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1725 printk(KERN_DEBUG "RxCtrl:\n");
1726 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1727 }
1728 #endif
1729
1730 /* Point to valid data and indicate its length */
1731 bus->rxctl += doff;
1732 bus->rxlen = len - doff;
1733
1734 done:
1735 /* Awake any waiters */
1736 brcmf_sdbrcm_dcmd_resp_wake(bus);
1737 }
1738
1739 /* Pad read to blocksize for efficiency */
1740 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1741 {
1742 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1743 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1744 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1745 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1746 *rdlen += *pad;
1747 } else if (*rdlen % BRCMF_SDALIGN) {
1748 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1749 }
1750 }
1751
1752 static void
1753 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1754 struct sk_buff **pkt, u8 **rxbuf)
1755 {
1756 int sdret; /* Return code from calls */
1757
1758 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1759 if (*pkt == NULL)
1760 return;
1761
1762 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1763 *rxbuf = (u8 *) ((*pkt)->data);
1764 /* Read the entire frame */
1765 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1766 SDIO_FUNC_2, F2SYNC,
1767 *rxbuf, rdlen, *pkt);
1768 bus->f2rxdata++;
1769
1770 if (sdret < 0) {
1771 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1772 rdlen, sdret);
1773 brcmu_pkt_buf_free_skb(*pkt);
1774 bus->drvr->rx_errors++;
1775 /* Force retry w/normal header read.
1776 * Don't attempt NAK for
1777 * gSPI
1778 */
1779 brcmf_sdbrcm_rxfail(bus, true, true);
1780 *pkt = NULL;
1781 }
1782 }
1783
1784 /* Checks the header */
1785 static int
1786 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1787 u8 rxseq, u16 nextlen, u16 *len)
1788 {
1789 u16 check;
1790 bool len_consistent; /* Result of comparing readahead len and
1791 len from hw-hdr */
1792
1793 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1794
1795 /* Extract hardware header fields */
1796 *len = get_unaligned_le16(bus->rxhdr);
1797 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1798
1799 /* All zeros means readahead info was bad */
1800 if (!(*len | check)) {
1801 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1802 goto fail;
1803 }
1804
1805 /* Validate check bytes */
1806 if ((u16)~(*len ^ check)) {
1807 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1808 nextlen, *len, check);
1809 bus->rx_badhdr++;
1810 brcmf_sdbrcm_rxfail(bus, false, false);
1811 goto fail;
1812 }
1813
1814 /* Validate frame length */
1815 if (*len < SDPCM_HDRLEN) {
1816 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1817 *len);
1818 goto fail;
1819 }
1820
1821 /* Check for consistency with readahead info */
1822 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1823 if (len_consistent) {
1824 /* Mismatch, force retry w/normal
1825 header (may be >4K) */
1826 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1827 nextlen, *len, roundup(*len, 16),
1828 rxseq);
1829 brcmf_sdbrcm_rxfail(bus, true, true);
1830 goto fail;
1831 }
1832
1833 return 0;
1834
1835 fail:
1836 brcmf_sdbrcm_pktfree2(bus, pkt);
1837 return -EINVAL;
1838 }
1839
1840 /* Return true if there may be more frames to read */
1841 static uint
1842 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1843 {
1844 u16 len, check; /* Extracted hardware header fields */
1845 u8 chan, seq, doff; /* Extracted software header fields */
1846 u8 fcbits; /* Extracted fcbits from software header */
1847
1848 struct sk_buff *pkt; /* Packet for event or data frames */
1849 u16 pad; /* Number of pad bytes to read */
1850 u16 rdlen; /* Total number of bytes to read */
1851 u8 rxseq; /* Next sequence number to expect */
1852 uint rxleft = 0; /* Remaining number of frames allowed */
1853 int sdret; /* Return code from calls */
1854 u8 txmax; /* Maximum tx sequence offered */
1855 u8 *rxbuf;
1856 int ifidx = 0;
1857 uint rxcount = 0; /* Total frames read */
1858
1859 brcmf_dbg(TRACE, "Enter\n");
1860
1861 /* Not finished unless we encounter no more frames indication */
1862 *finished = false;
1863
1864 for (rxseq = bus->rx_seq, rxleft = maxframes;
1865 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1866 rxseq++, rxleft--) {
1867
1868 /* Handle glomming separately */
1869 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1870 u8 cnt;
1871 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1872 bus->glomd, skb_peek(&bus->glom));
1873 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1874 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1875 rxseq += cnt - 1;
1876 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1877 continue;
1878 }
1879
1880 /* Try doing single read if we can */
1881 if (bus->nextlen) {
1882 u16 nextlen = bus->nextlen;
1883 bus->nextlen = 0;
1884
1885 rdlen = len = nextlen << 4;
1886 brcmf_pad(bus, &pad, &rdlen);
1887
1888 /*
1889 * After the frame is received we have to
1890 * distinguish whether it is data
1891 * or non-data frame.
1892 */
1893 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1894 if (pkt == NULL) {
1895 /* Give up on data, request rtx of events */
1896 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1897 len, rdlen, rxseq);
1898 continue;
1899 }
1900
1901 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1902 &len) < 0)
1903 continue;
1904
1905 /* Extract software header fields */
1906 chan = SDPCM_PACKET_CHANNEL(
1907 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1908 seq = SDPCM_PACKET_SEQUENCE(
1909 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1910 doff = SDPCM_DOFFSET_VALUE(
1911 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1912 txmax = SDPCM_WINDOW_VALUE(
1913 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1914
1915 bus->nextlen =
1916 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1917 SDPCM_NEXTLEN_OFFSET];
1918 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1919 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1920 bus->nextlen, seq);
1921 bus->nextlen = 0;
1922 }
1923
1924 bus->drvr->rx_readahead_cnt++;
1925
1926 /* Handle Flow Control */
1927 fcbits = SDPCM_FCMASK_VALUE(
1928 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1929
1930 if (bus->flowcontrol != fcbits) {
1931 if (~bus->flowcontrol & fcbits)
1932 bus->fc_xoff++;
1933
1934 if (bus->flowcontrol & ~fcbits)
1935 bus->fc_xon++;
1936
1937 bus->fc_rcvd++;
1938 bus->flowcontrol = fcbits;
1939 }
1940
1941 /* Check and update sequence number */
1942 if (rxseq != seq) {
1943 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1944 seq, rxseq);
1945 bus->rx_badseq++;
1946 rxseq = seq;
1947 }
1948
1949 /* Check window for sanity */
1950 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1951 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1952 txmax, bus->tx_seq);
1953 txmax = bus->tx_seq + 2;
1954 }
1955 bus->tx_max = txmax;
1956
1957 #ifdef BCMDBG
1958 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1959 printk(KERN_DEBUG "Rx Data:\n");
1960 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1961 rxbuf, len);
1962 } else if (BRCMF_HDRS_ON()) {
1963 printk(KERN_DEBUG "RxHdr:\n");
1964 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1965 bus->rxhdr, SDPCM_HDRLEN);
1966 }
1967 #endif
1968
1969 if (chan == SDPCM_CONTROL_CHANNEL) {
1970 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1971 seq);
1972 /* Force retry w/normal header read */
1973 bus->nextlen = 0;
1974 brcmf_sdbrcm_rxfail(bus, false, true);
1975 brcmf_sdbrcm_pktfree2(bus, pkt);
1976 continue;
1977 }
1978
1979 /* Validate data offset */
1980 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1981 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1982 doff, len, SDPCM_HDRLEN);
1983 brcmf_sdbrcm_rxfail(bus, false, false);
1984 brcmf_sdbrcm_pktfree2(bus, pkt);
1985 continue;
1986 }
1987
1988 /* All done with this one -- now deliver the packet */
1989 goto deliver;
1990 }
1991
1992 /* Read frame header (hardware and software) */
1993 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1994 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1995 BRCMF_FIRSTREAD, NULL);
1996 bus->f2rxhdrs++;
1997
1998 if (sdret < 0) {
1999 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
2000 bus->rx_hdrfail++;
2001 brcmf_sdbrcm_rxfail(bus, true, true);
2002 continue;
2003 }
2004 #ifdef BCMDBG
2005 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
2006 printk(KERN_DEBUG "RxHdr:\n");
2007 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2008 bus->rxhdr, SDPCM_HDRLEN);
2009 }
2010 #endif
2011
2012 /* Extract hardware header fields */
2013 len = get_unaligned_le16(bus->rxhdr);
2014 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
2015
2016 /* All zeros means no more frames */
2017 if (!(len | check)) {
2018 *finished = true;
2019 break;
2020 }
2021
2022 /* Validate check bytes */
2023 if ((u16) ~(len ^ check)) {
2024 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2025 len, check);
2026 bus->rx_badhdr++;
2027 brcmf_sdbrcm_rxfail(bus, false, false);
2028 continue;
2029 }
2030
2031 /* Validate frame length */
2032 if (len < SDPCM_HDRLEN) {
2033 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2034 continue;
2035 }
2036
2037 /* Extract software header fields */
2038 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2039 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2040 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2041 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2042
2043 /* Validate data offset */
2044 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2045 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2046 doff, len, SDPCM_HDRLEN, seq);
2047 bus->rx_badhdr++;
2048 brcmf_sdbrcm_rxfail(bus, false, false);
2049 continue;
2050 }
2051
2052 /* Save the readahead length if there is one */
2053 bus->nextlen =
2054 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2055 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2056 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2057 bus->nextlen, seq);
2058 bus->nextlen = 0;
2059 }
2060
2061 /* Handle Flow Control */
2062 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2063
2064 if (bus->flowcontrol != fcbits) {
2065 if (~bus->flowcontrol & fcbits)
2066 bus->fc_xoff++;
2067
2068 if (bus->flowcontrol & ~fcbits)
2069 bus->fc_xon++;
2070
2071 bus->fc_rcvd++;
2072 bus->flowcontrol = fcbits;
2073 }
2074
2075 /* Check and update sequence number */
2076 if (rxseq != seq) {
2077 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2078 bus->rx_badseq++;
2079 rxseq = seq;
2080 }
2081
2082 /* Check window for sanity */
2083 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2084 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2085 txmax, bus->tx_seq);
2086 txmax = bus->tx_seq + 2;
2087 }
2088 bus->tx_max = txmax;
2089
2090 /* Call a separate function for control frames */
2091 if (chan == SDPCM_CONTROL_CHANNEL) {
2092 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2093 continue;
2094 }
2095
2096 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2097 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2098 SDPCM_GLOM_CHANNEL */
2099
2100 /* Length to read */
2101 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2102
2103 /* May pad read to blocksize for efficiency */
2104 if (bus->roundup && bus->blocksize &&
2105 (rdlen > bus->blocksize)) {
2106 pad = bus->blocksize - (rdlen % bus->blocksize);
2107 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2108 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2109 rdlen += pad;
2110 } else if (rdlen % BRCMF_SDALIGN) {
2111 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2112 }
2113
2114 /* Satisfy length-alignment requirements */
2115 if (rdlen & (ALIGNMENT - 1))
2116 rdlen = roundup(rdlen, ALIGNMENT);
2117
2118 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2119 /* Too long -- skip this frame */
2120 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2121 len, rdlen);
2122 bus->drvr->rx_errors++;
2123 bus->rx_toolong++;
2124 brcmf_sdbrcm_rxfail(bus, false, false);
2125 continue;
2126 }
2127
2128 pkt = brcmu_pkt_buf_get_skb(rdlen +
2129 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2130 if (!pkt) {
2131 /* Give up on data, request rtx of events */
2132 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2133 rdlen, chan);
2134 bus->drvr->rx_dropped++;
2135 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2136 continue;
2137 }
2138
2139 /* Leave room for what we already read, and align remainder */
2140 skb_pull(pkt, BRCMF_FIRSTREAD);
2141 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2142
2143 /* Read the remaining frame data */
2144 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2145 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2146 rdlen, pkt);
2147 bus->f2rxdata++;
2148
2149 if (sdret < 0) {
2150 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2151 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2152 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2153 : "test")), sdret);
2154 brcmu_pkt_buf_free_skb(pkt);
2155 bus->drvr->rx_errors++;
2156 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2157 continue;
2158 }
2159
2160 /* Copy the already-read portion */
2161 skb_push(pkt, BRCMF_FIRSTREAD);
2162 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2163
2164 #ifdef BCMDBG
2165 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2166 printk(KERN_DEBUG "Rx Data:\n");
2167 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2168 pkt->data, len);
2169 }
2170 #endif
2171
2172 deliver:
2173 /* Save superframe descriptor and allocate packet frame */
2174 if (chan == SDPCM_GLOM_CHANNEL) {
2175 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2176 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2177 len);
2178 #ifdef BCMDBG
2179 if (BRCMF_GLOM_ON()) {
2180 printk(KERN_DEBUG "Glom Data:\n");
2181 print_hex_dump_bytes("",
2182 DUMP_PREFIX_OFFSET,
2183 pkt->data, len);
2184 }
2185 #endif
2186 __skb_trim(pkt, len);
2187 skb_pull(pkt, SDPCM_HDRLEN);
2188 bus->glomd = pkt;
2189 } else {
2190 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2191 "descriptor!\n", __func__);
2192 brcmf_sdbrcm_rxfail(bus, false, false);
2193 }
2194 continue;
2195 }
2196
2197 /* Fill in packet len and prio, deliver upward */
2198 __skb_trim(pkt, len);
2199 skb_pull(pkt, doff);
2200
2201 if (pkt->len == 0) {
2202 brcmu_pkt_buf_free_skb(pkt);
2203 continue;
2204 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2205 brcmf_dbg(ERROR, "rx protocol error\n");
2206 brcmu_pkt_buf_free_skb(pkt);
2207 bus->drvr->rx_errors++;
2208 continue;
2209 }
2210
2211 /* Unlock during rx call */
2212 up(&bus->sdsem);
2213 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2214 down(&bus->sdsem);
2215 }
2216 rxcount = maxframes - rxleft;
2217 #ifdef BCMDBG
2218 /* Message if we hit the limit */
2219 if (!rxleft)
2220 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2221 maxframes);
2222 else
2223 #endif /* BCMDBG */
2224 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2225 /* Back off rxseq if awaiting rtx, update rx_seq */
2226 if (bus->rxskip)
2227 rxseq--;
2228 bus->rx_seq = rxseq;
2229
2230 return rxcount;
2231 }
2232
2233 static int
2234 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2235 u8 *buf, uint nbytes, struct sk_buff *pkt)
2236 {
2237 return brcmf_sdcard_send_buf
2238 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2239 }
2240
2241 static void
2242 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2243 {
2244 up(&bus->sdsem);
2245 wait_event_interruptible_timeout(bus->ctrl_wait,
2246 (*lockvar == false), HZ * 2);
2247 down(&bus->sdsem);
2248 return;
2249 }
2250
2251 static void
2252 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2253 {
2254 if (waitqueue_active(&bus->ctrl_wait))
2255 wake_up_interruptible(&bus->ctrl_wait);
2256 return;
2257 }
2258
2259 /* Writes a HW/SW header into the packet and sends it. */
2260 /* Assumes: (a) header space already there, (b) caller holds lock */
2261 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2262 uint chan, bool free_pkt)
2263 {
2264 int ret;
2265 u8 *frame;
2266 u16 len, pad = 0;
2267 u32 swheader;
2268 struct sk_buff *new;
2269 int i;
2270
2271 brcmf_dbg(TRACE, "Enter\n");
2272
2273 frame = (u8 *) (pkt->data);
2274
2275 /* Add alignment padding, allocate new packet if needed */
2276 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2277 if (pad) {
2278 if (skb_headroom(pkt) < pad) {
2279 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2280 skb_headroom(pkt), pad);
2281 bus->drvr->tx_realloc++;
2282 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2283 if (!new) {
2284 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2285 pkt->len + BRCMF_SDALIGN);
2286 ret = -ENOMEM;
2287 goto done;
2288 }
2289
2290 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2291 memcpy(new->data, pkt->data, pkt->len);
2292 if (free_pkt)
2293 brcmu_pkt_buf_free_skb(pkt);
2294 /* free the pkt if canned one is not used */
2295 free_pkt = true;
2296 pkt = new;
2297 frame = (u8 *) (pkt->data);
2298 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2299 pad = 0;
2300 } else {
2301 skb_push(pkt, pad);
2302 frame = (u8 *) (pkt->data);
2303 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2304 memset(frame, 0, pad + SDPCM_HDRLEN);
2305 }
2306 }
2307 /* precondition: pad < BRCMF_SDALIGN */
2308
2309 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2310 len = (u16) (pkt->len);
2311 *(__le16 *) frame = cpu_to_le16(len);
2312 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2313
2314 /* Software tag: channel, sequence number, data offset */
2315 swheader =
2316 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2317 (((pad +
2318 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2319
2320 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2321 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2322
2323 #ifdef BCMDBG
2324 tx_packets[pkt->priority]++;
2325 if (BRCMF_BYTES_ON() &&
2326 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2327 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2328 printk(KERN_DEBUG "Tx Frame:\n");
2329 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2330 } else if (BRCMF_HDRS_ON()) {
2331 printk(KERN_DEBUG "TxHdr:\n");
2332 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2333 frame, min_t(u16, len, 16));
2334 }
2335 #endif
2336
2337 /* Raise len to next SDIO block to eliminate tail command */
2338 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2339 u16 pad = bus->blocksize - (len % bus->blocksize);
2340 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2341 len += pad;
2342 } else if (len % BRCMF_SDALIGN) {
2343 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2344 }
2345
2346 /* Some controllers have trouble with odd bytes -- round to even */
2347 if (len & (ALIGNMENT - 1))
2348 len = roundup(len, ALIGNMENT);
2349
2350 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2351 SDIO_FUNC_2, F2SYNC, frame,
2352 len, pkt);
2353 bus->f2txdata++;
2354
2355 if (ret < 0) {
2356 /* On failure, abort the command and terminate the frame */
2357 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2358 ret);
2359 bus->tx_sderrs++;
2360
2361 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2362 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2363 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2364 NULL);
2365 bus->f1regdata++;
2366
2367 for (i = 0; i < 3; i++) {
2368 u8 hi, lo;
2369 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2370 SDIO_FUNC_1,
2371 SBSDIO_FUNC1_WFRAMEBCHI,
2372 NULL);
2373 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2374 SDIO_FUNC_1,
2375 SBSDIO_FUNC1_WFRAMEBCLO,
2376 NULL);
2377 bus->f1regdata += 2;
2378 if ((hi == 0) && (lo == 0))
2379 break;
2380 }
2381
2382 }
2383 if (ret == 0)
2384 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2385
2386 done:
2387 /* restore pkt buffer pointer before calling tx complete routine */
2388 skb_pull(pkt, SDPCM_HDRLEN + pad);
2389 up(&bus->sdsem);
2390 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2391 down(&bus->sdsem);
2392
2393 if (free_pkt)
2394 brcmu_pkt_buf_free_skb(pkt);
2395
2396 return ret;
2397 }
2398
2399 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2400 {
2401 struct sk_buff *pkt;
2402 u32 intstatus = 0;
2403 uint retries = 0;
2404 int ret = 0, prec_out;
2405 uint cnt = 0;
2406 uint datalen;
2407 u8 tx_prec_map;
2408
2409 struct brcmf_pub *drvr = bus->drvr;
2410
2411 brcmf_dbg(TRACE, "Enter\n");
2412
2413 tx_prec_map = ~bus->flowcontrol;
2414
2415 /* Send frames until the limit or some other event */
2416 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2417 spin_lock_bh(&bus->txqlock);
2418 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2419 if (pkt == NULL) {
2420 spin_unlock_bh(&bus->txqlock);
2421 break;
2422 }
2423 spin_unlock_bh(&bus->txqlock);
2424 datalen = pkt->len - SDPCM_HDRLEN;
2425
2426 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2427 if (ret)
2428 bus->drvr->tx_errors++;
2429 else
2430 bus->drvr->dstats.tx_bytes += datalen;
2431
2432 /* In poll mode, need to check for other events */
2433 if (!bus->intr && cnt) {
2434 /* Check device status, signal pending interrupt */
2435 r_sdreg32(bus, &intstatus,
2436 offsetof(struct sdpcmd_regs, intstatus),
2437 &retries);
2438 bus->f2txdata++;
2439 if (brcmf_sdcard_regfail(bus->sdiodev))
2440 break;
2441 if (intstatus & bus->hostintmask)
2442 bus->ipend = true;
2443 }
2444 }
2445
2446 /* Deflow-control stack if needed */
2447 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2448 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2449 brcmf_txflowcontrol(drvr, 0, OFF);
2450
2451 return cnt;
2452 }
2453
2454 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2455 {
2456 u32 intstatus, newstatus = 0;
2457 uint retries = 0;
2458 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2459 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2460 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2461 bool rxdone = true; /* Flag for no more read data */
2462 bool resched = false; /* Flag indicating resched wanted */
2463
2464 brcmf_dbg(TRACE, "Enter\n");
2465
2466 /* Start with leftover status bits */
2467 intstatus = bus->intstatus;
2468
2469 down(&bus->sdsem);
2470
2471 /* If waiting for HTAVAIL, check status */
2472 if (bus->clkstate == CLK_PENDING) {
2473 int err;
2474 u8 clkctl, devctl = 0;
2475
2476 #ifdef BCMDBG
2477 /* Check for inconsistent device control */
2478 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2479 SBSDIO_DEVICE_CTL, &err);
2480 if (err) {
2481 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2482 bus->drvr->busstate = BRCMF_BUS_DOWN;
2483 }
2484 #endif /* BCMDBG */
2485
2486 /* Read CSR, if clock on switch to AVAIL, else ignore */
2487 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2488 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2489 if (err) {
2490 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2491 err);
2492 bus->drvr->busstate = BRCMF_BUS_DOWN;
2493 }
2494
2495 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2496 devctl, clkctl);
2497
2498 if (SBSDIO_HTAV(clkctl)) {
2499 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2500 SDIO_FUNC_1,
2501 SBSDIO_DEVICE_CTL, &err);
2502 if (err) {
2503 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2504 err);
2505 bus->drvr->busstate = BRCMF_BUS_DOWN;
2506 }
2507 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2508 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2509 SBSDIO_DEVICE_CTL, devctl, &err);
2510 if (err) {
2511 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2512 err);
2513 bus->drvr->busstate = BRCMF_BUS_DOWN;
2514 }
2515 bus->clkstate = CLK_AVAIL;
2516 } else {
2517 goto clkwait;
2518 }
2519 }
2520
2521 bus_wake(bus);
2522
2523 /* Make sure backplane clock is on */
2524 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2525 if (bus->clkstate == CLK_PENDING)
2526 goto clkwait;
2527
2528 /* Pending interrupt indicates new device status */
2529 if (bus->ipend) {
2530 bus->ipend = false;
2531 r_sdreg32(bus, &newstatus,
2532 offsetof(struct sdpcmd_regs, intstatus), &retries);
2533 bus->f1regdata++;
2534 if (brcmf_sdcard_regfail(bus->sdiodev))
2535 newstatus = 0;
2536 newstatus &= bus->hostintmask;
2537 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2538 if (newstatus) {
2539 w_sdreg32(bus, newstatus,
2540 offsetof(struct sdpcmd_regs, intstatus),
2541 &retries);
2542 bus->f1regdata++;
2543 }
2544 }
2545
2546 /* Merge new bits with previous */
2547 intstatus |= newstatus;
2548 bus->intstatus = 0;
2549
2550 /* Handle flow-control change: read new state in case our ack
2551 * crossed another change interrupt. If change still set, assume
2552 * FC ON for safety, let next loop through do the debounce.
2553 */
2554 if (intstatus & I_HMB_FC_CHANGE) {
2555 intstatus &= ~I_HMB_FC_CHANGE;
2556 w_sdreg32(bus, I_HMB_FC_CHANGE,
2557 offsetof(struct sdpcmd_regs, intstatus), &retries);
2558
2559 r_sdreg32(bus, &newstatus,
2560 offsetof(struct sdpcmd_regs, intstatus), &retries);
2561 bus->f1regdata += 2;
2562 bus->fcstate =
2563 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2564 intstatus |= (newstatus & bus->hostintmask);
2565 }
2566
2567 /* Handle host mailbox indication */
2568 if (intstatus & I_HMB_HOST_INT) {
2569 intstatus &= ~I_HMB_HOST_INT;
2570 intstatus |= brcmf_sdbrcm_hostmail(bus);
2571 }
2572
2573 /* Generally don't ask for these, can get CRC errors... */
2574 if (intstatus & I_WR_OOSYNC) {
2575 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2576 intstatus &= ~I_WR_OOSYNC;
2577 }
2578
2579 if (intstatus & I_RD_OOSYNC) {
2580 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2581 intstatus &= ~I_RD_OOSYNC;
2582 }
2583
2584 if (intstatus & I_SBINT) {
2585 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2586 intstatus &= ~I_SBINT;
2587 }
2588
2589 /* Would be active due to wake-wlan in gSPI */
2590 if (intstatus & I_CHIPACTIVE) {
2591 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2592 intstatus &= ~I_CHIPACTIVE;
2593 }
2594
2595 /* Ignore frame indications if rxskip is set */
2596 if (bus->rxskip)
2597 intstatus &= ~I_HMB_FRAME_IND;
2598
2599 /* On frame indication, read available frames */
2600 if (PKT_AVAILABLE()) {
2601 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2602 if (rxdone || bus->rxskip)
2603 intstatus &= ~I_HMB_FRAME_IND;
2604 rxlimit -= min(framecnt, rxlimit);
2605 }
2606
2607 /* Keep still-pending events for next scheduling */
2608 bus->intstatus = intstatus;
2609
2610 clkwait:
2611 if (data_ok(bus) && bus->ctrl_frame_stat &&
2612 (bus->clkstate == CLK_AVAIL)) {
2613 int ret, i;
2614
2615 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2616 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2617 (u32) bus->ctrl_frame_len, NULL);
2618
2619 if (ret < 0) {
2620 /* On failure, abort the command and
2621 terminate the frame */
2622 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2623 ret);
2624 bus->tx_sderrs++;
2625
2626 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2627
2628 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2629 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2630 NULL);
2631 bus->f1regdata++;
2632
2633 for (i = 0; i < 3; i++) {
2634 u8 hi, lo;
2635 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2636 SDIO_FUNC_1,
2637 SBSDIO_FUNC1_WFRAMEBCHI,
2638 NULL);
2639 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2640 SDIO_FUNC_1,
2641 SBSDIO_FUNC1_WFRAMEBCLO,
2642 NULL);
2643 bus->f1regdata += 2;
2644 if ((hi == 0) && (lo == 0))
2645 break;
2646 }
2647
2648 }
2649 if (ret == 0)
2650 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2651
2652 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2653 bus->ctrl_frame_stat = false;
2654 brcmf_sdbrcm_wait_event_wakeup(bus);
2655 }
2656 /* Send queued frames (limit 1 if rx may still be pending) */
2657 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2658 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2659 && data_ok(bus)) {
2660 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2661 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2662 txlimit -= framecnt;
2663 }
2664
2665 /* Resched if events or tx frames are pending,
2666 else await next interrupt */
2667 /* On failed register access, all bets are off:
2668 no resched or interrupts */
2669 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2670 brcmf_sdcard_regfail(bus->sdiodev)) {
2671 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2672 brcmf_sdcard_regfail(bus->sdiodev));
2673 bus->drvr->busstate = BRCMF_BUS_DOWN;
2674 bus->intstatus = 0;
2675 } else if (bus->clkstate == CLK_PENDING) {
2676 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2677 resched = true;
2678 } else if (bus->intstatus || bus->ipend ||
2679 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2680 && data_ok(bus)) || PKT_AVAILABLE()) {
2681 resched = true;
2682 }
2683
2684 bus->dpc_sched = resched;
2685
2686 /* If we're done for now, turn off clock request. */
2687 if ((bus->clkstate != CLK_PENDING)
2688 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2689 bus->activity = false;
2690 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2691 }
2692
2693 up(&bus->sdsem);
2694
2695 return resched;
2696 }
2697
2698 static int brcmf_sdbrcm_dpc_thread(void *data)
2699 {
2700 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2701
2702 allow_signal(SIGTERM);
2703 /* Run until signal received */
2704 while (1) {
2705 if (kthread_should_stop())
2706 break;
2707 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2708 /* Call bus dpc unless it indicated down
2709 (then clean stop) */
2710 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2711 if (brcmf_sdbrcm_dpc(bus))
2712 complete(&bus->dpc_wait);
2713 } else {
2714 /* after stopping the bus, exit thread */
2715 brcmf_sdbrcm_bus_stop(bus);
2716 bus->dpc_tsk = NULL;
2717 break;
2718 }
2719 } else
2720 break;
2721 }
2722 return 0;
2723 }
2724
2725 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2726 {
2727 int ret = -EBADE;
2728 uint datalen, prec;
2729
2730 brcmf_dbg(TRACE, "Enter\n");
2731
2732 datalen = pkt->len;
2733
2734 /* Add space for the header */
2735 skb_push(pkt, SDPCM_HDRLEN);
2736 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2737
2738 prec = prio2prec((pkt->priority & PRIOMASK));
2739
2740 /* Check for existing queue, current flow-control,
2741 pending event, or pending clock */
2742 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2743 bus->fcqueued++;
2744
2745 /* Priority based enq */
2746 spin_lock_bh(&bus->txqlock);
2747 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2748 skb_pull(pkt, SDPCM_HDRLEN);
2749 brcmf_txcomplete(bus->drvr, pkt, false);
2750 brcmu_pkt_buf_free_skb(pkt);
2751 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2752 ret = -ENOSR;
2753 } else {
2754 ret = 0;
2755 }
2756 spin_unlock_bh(&bus->txqlock);
2757
2758 if (pktq_len(&bus->txq) >= TXHI)
2759 brcmf_txflowcontrol(bus->drvr, 0, ON);
2760
2761 #ifdef BCMDBG
2762 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2763 qcount[prec] = pktq_plen(&bus->txq, prec);
2764 #endif
2765 /* Schedule DPC if needed to send queued packet(s) */
2766 if (!bus->dpc_sched) {
2767 bus->dpc_sched = true;
2768 if (bus->dpc_tsk)
2769 complete(&bus->dpc_wait);
2770 }
2771
2772 return ret;
2773 }
2774
2775 static int
2776 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2777 uint size)
2778 {
2779 int bcmerror = 0;
2780 u32 sdaddr;
2781 uint dsize;
2782
2783 /* Determine initial transfer parameters */
2784 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2785 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2786 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2787 else
2788 dsize = size;
2789
2790 /* Set the backplane window to include the start address */
2791 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2792 if (bcmerror) {
2793 brcmf_dbg(ERROR, "window change failed\n");
2794 goto xfer_done;
2795 }
2796
2797 /* Do the transfer(s) */
2798 while (size) {
2799 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2800 write ? "write" : "read", dsize,
2801 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2802 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2803 sdaddr, data, dsize);
2804 if (bcmerror) {
2805 brcmf_dbg(ERROR, "membytes transfer failed\n");
2806 break;
2807 }
2808
2809 /* Adjust for next transfer (if any) */
2810 size -= dsize;
2811 if (size) {
2812 data += dsize;
2813 address += dsize;
2814 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2815 address);
2816 if (bcmerror) {
2817 brcmf_dbg(ERROR, "window change failed\n");
2818 break;
2819 }
2820 sdaddr = 0;
2821 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2822 }
2823 }
2824
2825 xfer_done:
2826 /* Return the window to backplane enumeration space for core access */
2827 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2828 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2829 bus->sdiodev->sbwad);
2830
2831 return bcmerror;
2832 }
2833
2834 #ifdef BCMDBG
2835 #define CONSOLE_LINE_MAX 192
2836
2837 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2838 {
2839 struct brcmf_console *c = &bus->console;
2840 u8 line[CONSOLE_LINE_MAX], ch;
2841 u32 n, idx, addr;
2842 int rv;
2843
2844 /* Don't do anything until FWREADY updates console address */
2845 if (bus->console_addr == 0)
2846 return 0;
2847
2848 /* Read console log struct */
2849 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2850 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2851 sizeof(c->log_le));
2852 if (rv < 0)
2853 return rv;
2854
2855 /* Allocate console buffer (one time only) */
2856 if (c->buf == NULL) {
2857 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2858 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2859 if (c->buf == NULL)
2860 return -ENOMEM;
2861 }
2862
2863 idx = le32_to_cpu(c->log_le.idx);
2864
2865 /* Protect against corrupt value */
2866 if (idx > c->bufsize)
2867 return -EBADE;
2868
2869 /* Skip reading the console buffer if the index pointer
2870 has not moved */
2871 if (idx == c->last)
2872 return 0;
2873
2874 /* Read the console buffer */
2875 addr = le32_to_cpu(c->log_le.buf);
2876 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2877 if (rv < 0)
2878 return rv;
2879
2880 while (c->last != idx) {
2881 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2882 if (c->last == idx) {
2883 /* This would output a partial line.
2884 * Instead, back up
2885 * the buffer pointer and output this
2886 * line next time around.
2887 */
2888 if (c->last >= n)
2889 c->last -= n;
2890 else
2891 c->last = c->bufsize - n;
2892 goto break2;
2893 }
2894 ch = c->buf[c->last];
2895 c->last = (c->last + 1) % c->bufsize;
2896 if (ch == '\n')
2897 break;
2898 line[n] = ch;
2899 }
2900
2901 if (n > 0) {
2902 if (line[n - 1] == '\r')
2903 n--;
2904 line[n] = 0;
2905 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2906 }
2907 }
2908 break2:
2909
2910 return 0;
2911 }
2912 #endif /* BCMDBG */
2913
2914 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2915 {
2916 int i;
2917 int ret;
2918
2919 bus->ctrl_frame_stat = false;
2920 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2921 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2922
2923 if (ret < 0) {
2924 /* On failure, abort the command and terminate the frame */
2925 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2926 ret);
2927 bus->tx_sderrs++;
2928
2929 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2930
2931 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2932 SBSDIO_FUNC1_FRAMECTRL,
2933 SFC_WF_TERM, NULL);
2934 bus->f1regdata++;
2935
2936 for (i = 0; i < 3; i++) {
2937 u8 hi, lo;
2938 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2939 SBSDIO_FUNC1_WFRAMEBCHI,
2940 NULL);
2941 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2942 SBSDIO_FUNC1_WFRAMEBCLO,
2943 NULL);
2944 bus->f1regdata += 2;
2945 if (hi == 0 && lo == 0)
2946 break;
2947 }
2948 return ret;
2949 }
2950
2951 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2952
2953 return ret;
2954 }
2955
2956 int
2957 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2958 {
2959 u8 *frame;
2960 u16 len;
2961 u32 swheader;
2962 uint retries = 0;
2963 u8 doff = 0;
2964 int ret = -1;
2965
2966 brcmf_dbg(TRACE, "Enter\n");
2967
2968 /* Back the pointer to make a room for bus header */
2969 frame = msg - SDPCM_HDRLEN;
2970 len = (msglen += SDPCM_HDRLEN);
2971
2972 /* Add alignment padding (optional for ctl frames) */
2973 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2974 if (doff) {
2975 frame -= doff;
2976 len += doff;
2977 msglen += doff;
2978 memset(frame, 0, doff + SDPCM_HDRLEN);
2979 }
2980 /* precondition: doff < BRCMF_SDALIGN */
2981 doff += SDPCM_HDRLEN;
2982
2983 /* Round send length to next SDIO block */
2984 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2985 u16 pad = bus->blocksize - (len % bus->blocksize);
2986 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2987 len += pad;
2988 } else if (len % BRCMF_SDALIGN) {
2989 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2990 }
2991
2992 /* Satisfy length-alignment requirements */
2993 if (len & (ALIGNMENT - 1))
2994 len = roundup(len, ALIGNMENT);
2995
2996 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2997
2998 /* Need to lock here to protect txseq and SDIO tx calls */
2999 down(&bus->sdsem);
3000
3001 bus_wake(bus);
3002
3003 /* Make sure backplane clock is on */
3004 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3005
3006 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
3007 *(__le16 *) frame = cpu_to_le16((u16) msglen);
3008 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
3009
3010 /* Software tag: channel, sequence number, data offset */
3011 swheader =
3012 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
3013 SDPCM_CHANNEL_MASK)
3014 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
3015 SDPCM_DOFFSET_MASK);
3016 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3017 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3018
3019 if (!data_ok(bus)) {
3020 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3021 bus->tx_max, bus->tx_seq);
3022 bus->ctrl_frame_stat = true;
3023 /* Send from dpc */
3024 bus->ctrl_frame_buf = frame;
3025 bus->ctrl_frame_len = len;
3026
3027 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3028
3029 if (bus->ctrl_frame_stat == false) {
3030 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3031 ret = 0;
3032 } else {
3033 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3034 ret = -1;
3035 }
3036 }
3037
3038 if (ret == -1) {
3039 #ifdef BCMDBG
3040 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3041 printk(KERN_DEBUG "Tx Frame:\n");
3042 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3043 frame, len);
3044 } else if (BRCMF_HDRS_ON()) {
3045 printk(KERN_DEBUG "TxHdr:\n");
3046 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3047 frame, min_t(u16, len, 16));
3048 }
3049 #endif
3050
3051 do {
3052 ret = brcmf_tx_frame(bus, frame, len);
3053 } while (ret < 0 && retries++ < TXRETRIES);
3054 }
3055
3056 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3057 bus->activity = false;
3058 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3059 }
3060
3061 up(&bus->sdsem);
3062
3063 if (ret)
3064 bus->drvr->tx_ctlerrs++;
3065 else
3066 bus->drvr->tx_ctlpkts++;
3067
3068 return ret ? -EIO : 0;
3069 }
3070
3071 int
3072 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3073 {
3074 int timeleft;
3075 uint rxlen = 0;
3076 bool pending;
3077
3078 brcmf_dbg(TRACE, "Enter\n");
3079
3080 /* Wait until control frame is available */
3081 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3082
3083 down(&bus->sdsem);
3084 rxlen = bus->rxlen;
3085 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3086 bus->rxlen = 0;
3087 up(&bus->sdsem);
3088
3089 if (rxlen) {
3090 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3091 rxlen, msglen);
3092 } else if (timeleft == 0) {
3093 brcmf_dbg(ERROR, "resumed on timeout\n");
3094 } else if (pending == true) {
3095 brcmf_dbg(CTL, "cancelled\n");
3096 return -ERESTARTSYS;
3097 } else {
3098 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3099 }
3100
3101 if (rxlen)
3102 bus->drvr->rx_ctlpkts++;
3103 else
3104 bus->drvr->rx_ctlerrs++;
3105
3106 return rxlen ? (int)rxlen : -ETIMEDOUT;
3107 }
3108
3109 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3110 {
3111 int bcmerror = 0;
3112
3113 brcmf_dbg(TRACE, "Enter\n");
3114
3115 /* Basic sanity checks */
3116 if (bus->drvr->up) {
3117 bcmerror = -EISCONN;
3118 goto err;
3119 }
3120 if (!len) {
3121 bcmerror = -EOVERFLOW;
3122 goto err;
3123 }
3124
3125 /* Free the old ones and replace with passed variables */
3126 kfree(bus->vars);
3127
3128 bus->vars = kmalloc(len, GFP_ATOMIC);
3129 bus->varsz = bus->vars ? len : 0;
3130 if (bus->vars == NULL) {
3131 bcmerror = -ENOMEM;
3132 goto err;
3133 }
3134
3135 /* Copy the passed variables, which should include the
3136 terminating double-null */
3137 memcpy(bus->vars, arg, bus->varsz);
3138 err:
3139 return bcmerror;
3140 }
3141
3142 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3143 {
3144 int bcmerror = 0;
3145 u32 varsize;
3146 u32 varaddr;
3147 u8 *vbuffer;
3148 u32 varsizew;
3149 __le32 varsizew_le;
3150 #ifdef BCMDBG
3151 char *nvram_ularray;
3152 #endif /* BCMDBG */
3153
3154 /* Even if there are no vars are to be written, we still
3155 need to set the ramsize. */
3156 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3157 varaddr = (bus->ramsize - 4) - varsize;
3158
3159 if (bus->vars) {
3160 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3161 if (!vbuffer)
3162 return -ENOMEM;
3163
3164 memcpy(vbuffer, bus->vars, bus->varsz);
3165
3166 /* Write the vars list */
3167 bcmerror =
3168 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3169 #ifdef BCMDBG
3170 /* Verify NVRAM bytes */
3171 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3172 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3173 if (!nvram_ularray)
3174 return -ENOMEM;
3175
3176 /* Upload image to verify downloaded contents. */
3177 memset(nvram_ularray, 0xaa, varsize);
3178
3179 /* Read the vars list to temp buffer for comparison */
3180 bcmerror =
3181 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3182 varsize);
3183 if (bcmerror) {
3184 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3185 bcmerror, varsize, varaddr);
3186 }
3187 /* Compare the org NVRAM with the one read from RAM */
3188 if (memcmp(vbuffer, nvram_ularray, varsize))
3189 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3190 else
3191 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3192
3193 kfree(nvram_ularray);
3194 #endif /* BCMDBG */
3195
3196 kfree(vbuffer);
3197 }
3198
3199 /* adjust to the user specified RAM */
3200 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3201 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3202 varaddr, varsize);
3203 varsize = ((bus->ramsize - 4) - varaddr);
3204
3205 /*
3206 * Determine the length token:
3207 * Varsize, converted to words, in lower 16-bits, checksum
3208 * in upper 16-bits.
3209 */
3210 if (bcmerror) {
3211 varsizew = 0;
3212 varsizew_le = cpu_to_le32(0);
3213 } else {
3214 varsizew = varsize / 4;
3215 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3216 varsizew_le = cpu_to_le32(varsizew);
3217 }
3218
3219 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3220 varsize, varsizew);
3221
3222 /* Write the length token to the last word */
3223 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3224 (u8 *)&varsizew_le, 4);
3225
3226 return bcmerror;
3227 }
3228
3229 static void
3230 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3231 {
3232 u32 regdata;
3233
3234 regdata = brcmf_sdcard_reg_read(sdiodev,
3235 CORE_SB(corebase, sbtmstatelow), 4);
3236 if (regdata & SBTML_RESET)
3237 return;
3238
3239 regdata = brcmf_sdcard_reg_read(sdiodev,
3240 CORE_SB(corebase, sbtmstatelow), 4);
3241 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3242 /*
3243 * set target reject and spin until busy is clear
3244 * (preserve core-specific bits)
3245 */
3246 regdata = brcmf_sdcard_reg_read(sdiodev,
3247 CORE_SB(corebase, sbtmstatelow), 4);
3248 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3249 4, regdata | SBTML_REJ);
3250
3251 regdata = brcmf_sdcard_reg_read(sdiodev,
3252 CORE_SB(corebase, sbtmstatelow), 4);
3253 udelay(1);
3254 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3255 CORE_SB(corebase, sbtmstatehigh), 4) &
3256 SBTMH_BUSY), 100000);
3257
3258 regdata = brcmf_sdcard_reg_read(sdiodev,
3259 CORE_SB(corebase, sbtmstatehigh), 4);
3260 if (regdata & SBTMH_BUSY)
3261 brcmf_dbg(ERROR, "ARM core still busy\n");
3262
3263 regdata = brcmf_sdcard_reg_read(sdiodev,
3264 CORE_SB(corebase, sbidlow), 4);
3265 if (regdata & SBIDL_INIT) {
3266 regdata = brcmf_sdcard_reg_read(sdiodev,
3267 CORE_SB(corebase, sbimstate), 4) |
3268 SBIM_RJ;
3269 brcmf_sdcard_reg_write(sdiodev,
3270 CORE_SB(corebase, sbimstate), 4,
3271 regdata);
3272 regdata = brcmf_sdcard_reg_read(sdiodev,
3273 CORE_SB(corebase, sbimstate), 4);
3274 udelay(1);
3275 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3276 CORE_SB(corebase, sbimstate), 4) &
3277 SBIM_BY), 100000);
3278 }
3279
3280 /* set reset and reject while enabling the clocks */
3281 brcmf_sdcard_reg_write(sdiodev,
3282 CORE_SB(corebase, sbtmstatelow), 4,
3283 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3284 SBTML_REJ | SBTML_RESET));
3285 regdata = brcmf_sdcard_reg_read(sdiodev,
3286 CORE_SB(corebase, sbtmstatelow), 4);
3287 udelay(10);
3288
3289 /* clear the initiator reject bit */
3290 regdata = brcmf_sdcard_reg_read(sdiodev,
3291 CORE_SB(corebase, sbidlow), 4);
3292 if (regdata & SBIDL_INIT) {
3293 regdata = brcmf_sdcard_reg_read(sdiodev,
3294 CORE_SB(corebase, sbimstate), 4) &
3295 ~SBIM_RJ;
3296 brcmf_sdcard_reg_write(sdiodev,
3297 CORE_SB(corebase, sbimstate), 4,
3298 regdata);
3299 }
3300 }
3301
3302 /* leave reset and reject asserted */
3303 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3304 (SBTML_REJ | SBTML_RESET));
3305 udelay(1);
3306 }
3307
3308 static void
3309 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3310 {
3311 u32 regdata;
3312
3313 /*
3314 * Must do the disable sequence first to work for
3315 * arbitrary current core state.
3316 */
3317 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3318
3319 /*
3320 * Now do the initialization sequence.
3321 * set reset while enabling the clock and
3322 * forcing them on throughout the core
3323 */
3324 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3325 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3326 SBTML_RESET);
3327 udelay(1);
3328
3329 regdata = brcmf_sdcard_reg_read(sdiodev,
3330 CORE_SB(corebase, sbtmstatehigh), 4);
3331 if (regdata & SBTMH_SERR)
3332 brcmf_sdcard_reg_write(sdiodev,
3333 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3334
3335 regdata = brcmf_sdcard_reg_read(sdiodev,
3336 CORE_SB(corebase, sbimstate), 4);
3337 if (regdata & (SBIM_IBE | SBIM_TO))
3338 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3339 regdata & ~(SBIM_IBE | SBIM_TO));
3340
3341 /* clear reset and allow it to propagate throughout the core */
3342 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3343 (SICF_FGC << SBTML_SICF_SHIFT) |
3344 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3345 udelay(1);
3346
3347 /* leave clock enabled */
3348 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3349 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3350 udelay(1);
3351 }
3352
3353 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3354 {
3355 uint retries;
3356 u32 regdata;
3357 int bcmerror = 0;
3358
3359 /* To enter download state, disable ARM and reset SOCRAM.
3360 * To exit download state, simply reset ARM (default is RAM boot).
3361 */
3362 if (enter) {
3363 bus->alp_only = true;
3364
3365 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3366 bus->ci->armcorebase);
3367
3368 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3369
3370 /* Clear the top bit of memory */
3371 if (bus->ramsize) {
3372 u32 zeros = 0;
3373 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3374 (u8 *)&zeros, 4);
3375 }
3376 } else {
3377 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3378 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3379 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3380 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3381 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3382 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3383 bcmerror = -EBADE;
3384 goto fail;
3385 }
3386
3387 bcmerror = brcmf_sdbrcm_write_vars(bus);
3388 if (bcmerror) {
3389 brcmf_dbg(ERROR, "no vars written to RAM\n");
3390 bcmerror = 0;
3391 }
3392
3393 w_sdreg32(bus, 0xFFFFFFFF,
3394 offsetof(struct sdpcmd_regs, intstatus), &retries);
3395
3396 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3397
3398 /* Allow HT Clock now that the ARM is running. */
3399 bus->alp_only = false;
3400
3401 bus->drvr->busstate = BRCMF_BUS_LOAD;
3402 }
3403 fail:
3404 return bcmerror;
3405 }
3406
3407 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3408 {
3409 if (bus->firmware->size < bus->fw_ptr + len)
3410 len = bus->firmware->size - bus->fw_ptr;
3411
3412 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3413 bus->fw_ptr += len;
3414 return len;
3415 }
3416
3417 MODULE_FIRMWARE(BCM4329_FW_NAME);
3418 MODULE_FIRMWARE(BCM4329_NV_NAME);
3419
3420 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3421 {
3422 int offset = 0;
3423 uint len;
3424 u8 *memblock = NULL, *memptr;
3425 int ret;
3426
3427 brcmf_dbg(INFO, "Enter\n");
3428
3429 bus->fw_name = BCM4329_FW_NAME;
3430 ret = request_firmware(&bus->firmware, bus->fw_name,
3431 &bus->sdiodev->func[2]->dev);
3432 if (ret) {
3433 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3434 return ret;
3435 }
3436 bus->fw_ptr = 0;
3437
3438 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3439 if (memblock == NULL) {
3440 ret = -ENOMEM;
3441 goto err;
3442 }
3443 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3444 memptr += (BRCMF_SDALIGN -
3445 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3446
3447 /* Download image */
3448 while ((len =
3449 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3450 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3451 if (ret) {
3452 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3453 ret, MEMBLOCK, offset);
3454 goto err;
3455 }
3456
3457 offset += MEMBLOCK;
3458 }
3459
3460 err:
3461 kfree(memblock);
3462
3463 release_firmware(bus->firmware);
3464 bus->fw_ptr = 0;
3465
3466 return ret;
3467 }
3468
3469 /*
3470 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3471 * and ending in a NUL.
3472 * Removes carriage returns, empty lines, comment lines, and converts
3473 * newlines to NULs.
3474 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3475 * by two NULs.
3476 */
3477
3478 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3479 {
3480 char *dp;
3481 bool findNewline;
3482 int column;
3483 uint buf_len, n;
3484
3485 dp = varbuf;
3486
3487 findNewline = false;
3488 column = 0;
3489
3490 for (n = 0; n < len; n++) {
3491 if (varbuf[n] == 0)
3492 break;
3493 if (varbuf[n] == '\r')
3494 continue;
3495 if (findNewline && varbuf[n] != '\n')
3496 continue;
3497 findNewline = false;
3498 if (varbuf[n] == '#') {
3499 findNewline = true;
3500 continue;
3501 }
3502 if (varbuf[n] == '\n') {
3503 if (column == 0)
3504 continue;
3505 *dp++ = 0;
3506 column = 0;
3507 continue;
3508 }
3509 *dp++ = varbuf[n];
3510 column++;
3511 }
3512 buf_len = dp - varbuf;
3513
3514 while (dp < varbuf + n)
3515 *dp++ = 0;
3516
3517 return buf_len;
3518 }
3519
3520 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3521 {
3522 uint len;
3523 char *memblock = NULL;
3524 char *bufp;
3525 int ret;
3526
3527 bus->nv_name = BCM4329_NV_NAME;
3528 ret = request_firmware(&bus->firmware, bus->nv_name,
3529 &bus->sdiodev->func[2]->dev);
3530 if (ret) {
3531 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3532 return ret;
3533 }
3534 bus->fw_ptr = 0;
3535
3536 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3537 if (memblock == NULL) {
3538 ret = -ENOMEM;
3539 goto err;
3540 }
3541
3542 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3543
3544 if (len > 0 && len < MEMBLOCK) {
3545 bufp = (char *)memblock;
3546 bufp[len] = 0;
3547 len = brcmf_process_nvram_vars(bufp, len);
3548 bufp += len;
3549 *bufp++ = 0;
3550 if (len)
3551 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3552 if (ret)
3553 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3554 } else {
3555 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3556 ret = -EIO;
3557 }
3558
3559 err:
3560 kfree(memblock);
3561
3562 release_firmware(bus->firmware);
3563 bus->fw_ptr = 0;
3564
3565 return ret;
3566 }
3567
3568 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3569 {
3570 int bcmerror = -1;
3571
3572 /* Keep arm in reset */
3573 if (brcmf_sdbrcm_download_state(bus, true)) {
3574 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3575 goto err;
3576 }
3577
3578 /* External image takes precedence if specified */
3579 if (brcmf_sdbrcm_download_code_file(bus)) {
3580 brcmf_dbg(ERROR, "dongle image file download failed\n");
3581 goto err;
3582 }
3583
3584 /* External nvram takes precedence if specified */
3585 if (brcmf_sdbrcm_download_nvram(bus))
3586 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3587
3588 /* Take arm out of reset */
3589 if (brcmf_sdbrcm_download_state(bus, false)) {
3590 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3591 goto err;
3592 }
3593
3594 bcmerror = 0;
3595
3596 err:
3597 return bcmerror;
3598 }
3599
3600 static bool
3601 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3602 {
3603 bool ret;
3604
3605 /* Download the firmware */
3606 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3607
3608 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3609
3610 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3611
3612 return ret;
3613 }
3614
3615 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3616 {
3617 u32 local_hostintmask;
3618 u8 saveclk;
3619 uint retries;
3620 int err;
3621 struct sk_buff *cur;
3622 struct sk_buff *next;
3623
3624 brcmf_dbg(TRACE, "Enter\n");
3625
3626 if (bus->watchdog_tsk) {
3627 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3628 kthread_stop(bus->watchdog_tsk);
3629 bus->watchdog_tsk = NULL;
3630 }
3631
3632 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3633 send_sig(SIGTERM, bus->dpc_tsk, 1);
3634 kthread_stop(bus->dpc_tsk);
3635 bus->dpc_tsk = NULL;
3636 }
3637
3638 down(&bus->sdsem);
3639
3640 bus_wake(bus);
3641
3642 /* Enable clock for device interrupts */
3643 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3644
3645 /* Disable and clear interrupts at the chip level also */
3646 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3647 local_hostintmask = bus->hostintmask;
3648 bus->hostintmask = 0;
3649
3650 /* Change our idea of bus state */
3651 bus->drvr->busstate = BRCMF_BUS_DOWN;
3652
3653 /* Force clocks on backplane to be sure F2 interrupt propagates */
3654 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3655 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3656 if (!err) {
3657 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3658 SBSDIO_FUNC1_CHIPCLKCSR,
3659 (saveclk | SBSDIO_FORCE_HT), &err);
3660 }
3661 if (err)
3662 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3663
3664 /* Turn off the bus (F2), free any pending packets */
3665 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3666 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3667 SDIO_FUNC_ENABLE_1, NULL);
3668
3669 /* Clear any pending interrupts now that F2 is disabled */
3670 w_sdreg32(bus, local_hostintmask,
3671 offsetof(struct sdpcmd_regs, intstatus), &retries);
3672
3673 /* Turn off the backplane clock (only) */
3674 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3675
3676 /* Clear the data packet queues */
3677 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3678
3679 /* Clear any held glomming stuff */
3680 if (bus->glomd)
3681 brcmu_pkt_buf_free_skb(bus->glomd);
3682 if (!skb_queue_empty(&bus->glom))
3683 skb_queue_walk_safe(&bus->glom, cur, next) {
3684 skb_unlink(cur, &bus->glom);
3685 brcmu_pkt_buf_free_skb(cur);
3686 }
3687
3688 /* Clear rx control and wake any waiters */
3689 bus->rxlen = 0;
3690 brcmf_sdbrcm_dcmd_resp_wake(bus);
3691
3692 /* Reset some F2 state stuff */
3693 bus->rxskip = false;
3694 bus->tx_seq = bus->rx_seq = 0;
3695
3696 up(&bus->sdsem);
3697 }
3698
3699 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3700 {
3701 struct brcmf_bus *bus = drvr->bus;
3702 unsigned long timeout;
3703 uint retries = 0;
3704 u8 ready, enable;
3705 int err, ret = 0;
3706 u8 saveclk;
3707
3708 brcmf_dbg(TRACE, "Enter\n");
3709
3710 /* try to download image and nvram to the dongle */
3711 if (drvr->busstate == BRCMF_BUS_DOWN) {
3712 if (!(brcmf_sdbrcm_download_firmware(bus)))
3713 return -1;
3714 }
3715
3716 if (!bus->drvr)
3717 return 0;
3718
3719 /* Start the watchdog timer */
3720 bus->drvr->tickcnt = 0;
3721 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3722
3723 down(&bus->sdsem);
3724
3725 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3726 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3727 if (bus->clkstate != CLK_AVAIL)
3728 goto exit;
3729
3730 /* Force clocks on backplane to be sure F2 interrupt propagates */
3731 saveclk =
3732 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3733 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3734 if (!err) {
3735 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3736 SBSDIO_FUNC1_CHIPCLKCSR,
3737 (saveclk | SBSDIO_FORCE_HT), &err);
3738 }
3739 if (err) {
3740 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3741 goto exit;
3742 }
3743
3744 /* Enable function 2 (frame transfers) */
3745 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3746 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3747 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3748
3749 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3750 enable, NULL);
3751
3752 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3753 ready = 0;
3754 while (enable != ready) {
3755 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3756 SDIO_CCCR_IORx, NULL);
3757 if (time_after(jiffies, timeout))
3758 break;
3759 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3760 /* prevent busy waiting if it takes too long */
3761 msleep_interruptible(20);
3762 }
3763
3764 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3765
3766 /* If F2 successfully enabled, set core and enable interrupts */
3767 if (ready == enable) {
3768 /* Set up the interrupt mask and enable interrupts */
3769 bus->hostintmask = HOSTINTMASK;
3770 w_sdreg32(bus, bus->hostintmask,
3771 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3772
3773 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3774 SBSDIO_WATERMARK, 8, &err);
3775
3776 /* Set bus state according to enable result */
3777 drvr->busstate = BRCMF_BUS_DATA;
3778 }
3779
3780 else {
3781 /* Disable F2 again */
3782 enable = SDIO_FUNC_ENABLE_1;
3783 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3784 SDIO_CCCR_IOEx, enable, NULL);
3785 }
3786
3787 /* Restore previous clock setting */
3788 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3789 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3790
3791 /* If we didn't come up, turn off backplane clock */
3792 if (drvr->busstate != BRCMF_BUS_DATA)
3793 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3794
3795 exit:
3796 up(&bus->sdsem);
3797
3798 return ret;
3799 }
3800
3801 void brcmf_sdbrcm_isr(void *arg)
3802 {
3803 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3804
3805 brcmf_dbg(TRACE, "Enter\n");
3806
3807 if (!bus) {
3808 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3809 return;
3810 }
3811
3812 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3813 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3814 return;
3815 }
3816 /* Count the interrupt call */
3817 bus->intrcount++;
3818 bus->ipend = true;
3819
3820 /* Shouldn't get this interrupt if we're sleeping? */
3821 if (bus->sleeping) {
3822 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3823 return;
3824 }
3825
3826 /* Disable additional interrupts (is this needed now)? */
3827 if (!bus->intr)
3828 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3829
3830 bus->dpc_sched = true;
3831 if (bus->dpc_tsk)
3832 complete(&bus->dpc_wait);
3833 }
3834
3835 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3836 {
3837 struct brcmf_bus *bus;
3838
3839 brcmf_dbg(TIMER, "Enter\n");
3840
3841 bus = drvr->bus;
3842
3843 /* Ignore the timer if simulating bus down */
3844 if (bus->sleeping)
3845 return false;
3846
3847 down(&bus->sdsem);
3848
3849 /* Poll period: check device if appropriate. */
3850 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3851 u32 intstatus = 0;
3852
3853 /* Reset poll tick */
3854 bus->polltick = 0;
3855
3856 /* Check device if no interrupts */
3857 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3858
3859 if (!bus->dpc_sched) {
3860 u8 devpend;
3861 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3862 SDIO_FUNC_0, SDIO_CCCR_INTx,
3863 NULL);
3864 intstatus =
3865 devpend & (INTR_STATUS_FUNC1 |
3866 INTR_STATUS_FUNC2);
3867 }
3868
3869 /* If there is something, make like the ISR and
3870 schedule the DPC */
3871 if (intstatus) {
3872 bus->pollcnt++;
3873 bus->ipend = true;
3874
3875 bus->dpc_sched = true;
3876 if (bus->dpc_tsk)
3877 complete(&bus->dpc_wait);
3878 }
3879 }
3880
3881 /* Update interrupt tracking */
3882 bus->lastintrs = bus->intrcount;
3883 }
3884 #ifdef BCMDBG
3885 /* Poll for console output periodically */
3886 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3887 bus->console.count += BRCMF_WD_POLL_MS;
3888 if (bus->console.count >= bus->console_interval) {
3889 bus->console.count -= bus->console_interval;
3890 /* Make sure backplane clock is on */
3891 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3892 if (brcmf_sdbrcm_readconsole(bus) < 0)
3893 /* stop on error */
3894 bus->console_interval = 0;
3895 }
3896 }
3897 #endif /* BCMDBG */
3898
3899 /* On idle timeout clear activity flag and/or turn off clock */
3900 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3901 if (++bus->idlecount >= bus->idletime) {
3902 bus->idlecount = 0;
3903 if (bus->activity) {
3904 bus->activity = false;
3905 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3906 } else {
3907 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3908 }
3909 }
3910 }
3911
3912 up(&bus->sdsem);
3913
3914 return bus->ipend;
3915 }
3916
3917 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3918 {
3919 if (chipid == BCM4329_CHIP_ID)
3920 return true;
3921 return false;
3922 }
3923
3924 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3925 {
3926 brcmf_dbg(TRACE, "Enter\n");
3927
3928 kfree(bus->rxbuf);
3929 bus->rxctl = bus->rxbuf = NULL;
3930 bus->rxlen = 0;
3931
3932 kfree(bus->databuf);
3933 bus->databuf = NULL;
3934 }
3935
3936 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3937 {
3938 brcmf_dbg(TRACE, "Enter\n");
3939
3940 if (bus->drvr->maxctl) {
3941 bus->rxblen =
3942 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3943 ALIGNMENT) + BRCMF_SDALIGN;
3944 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3945 if (!(bus->rxbuf))
3946 goto fail;
3947 }
3948
3949 /* Allocate buffer to receive glomed packet */
3950 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3951 if (!(bus->databuf)) {
3952 /* release rxbuf which was already located as above */
3953 if (!bus->rxblen)
3954 kfree(bus->rxbuf);
3955 goto fail;
3956 }
3957
3958 /* Align the buffer */
3959 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3960 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3961 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3962 else
3963 bus->dataptr = bus->databuf;
3964
3965 return true;
3966
3967 fail:
3968 return false;
3969 }
3970
3971 /* SDIO Pad drive strength to select value mappings */
3972 struct sdiod_drive_str {
3973 u8 strength; /* Pad Drive Strength in mA */
3974 u8 sel; /* Chip-specific select value */
3975 };
3976
3977 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3978 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3979 {
3980 4, 0x2}, {
3981 2, 0x3}, {
3982 1, 0x0}, {
3983 0, 0x0}
3984 };
3985
3986 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3987 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3988 {
3989 12, 0x7}, {
3990 10, 0x6}, {
3991 8, 0x5}, {
3992 6, 0x4}, {
3993 4, 0x2}, {
3994 2, 0x1}, {
3995 0, 0x0}
3996 };
3997
3998 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3999 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
4000 {
4001 32, 0x7}, {
4002 26, 0x6}, {
4003 22, 0x5}, {
4004 16, 0x4}, {
4005 12, 0x3}, {
4006 8, 0x2}, {
4007 4, 0x1}, {
4008 0, 0x0}
4009 };
4010
4011 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
4012
4013 static char *brcmf_chipname(uint chipid, char *buf, uint len)
4014 {
4015 const char *fmt;
4016
4017 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
4018 snprintf(buf, len, fmt, chipid);
4019 return buf;
4020 }
4021
4022 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4023 u32 drivestrength) {
4024 struct sdiod_drive_str *str_tab = NULL;
4025 u32 str_mask = 0;
4026 u32 str_shift = 0;
4027 char chn[8];
4028
4029 if (!(bus->ci->cccaps & CC_CAP_PMU))
4030 return;
4031
4032 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4033 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4034 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4035 str_mask = 0x30000000;
4036 str_shift = 28;
4037 break;
4038 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4039 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4040 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4041 str_mask = 0x00003800;
4042 str_shift = 11;
4043 break;
4044 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4045 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4046 str_mask = 0x00003800;
4047 str_shift = 11;
4048 break;
4049 default:
4050 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4051 brcmf_chipname(bus->ci->chip, chn, 8),
4052 bus->ci->chiprev, bus->ci->pmurev);
4053 break;
4054 }
4055
4056 if (str_tab != NULL) {
4057 u32 drivestrength_sel = 0;
4058 u32 cc_data_temp;
4059 int i;
4060
4061 for (i = 0; str_tab[i].strength != 0; i++) {
4062 if (drivestrength >= str_tab[i].strength) {
4063 drivestrength_sel = str_tab[i].sel;
4064 break;
4065 }
4066 }
4067
4068 brcmf_sdcard_reg_write(bus->sdiodev,
4069 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4070 4, 1);
4071 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4072 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4073 cc_data_temp &= ~str_mask;
4074 drivestrength_sel <<= str_shift;
4075 cc_data_temp |= drivestrength_sel;
4076 brcmf_sdcard_reg_write(bus->sdiodev,
4077 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4078 4, cc_data_temp);
4079
4080 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4081 drivestrength, cc_data_temp);
4082 }
4083 }
4084
4085 static int
4086 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4087 struct chip_info *ci, u32 regs)
4088 {
4089 u32 regdata;
4090
4091 /*
4092 * Get CC core rev
4093 * Chipid is assume to be at offset 0 from regs arg
4094 * For different chiptypes or old sdio hosts w/o chipcommon,
4095 * other ways of recognition should be added here.
4096 */
4097 ci->cccorebase = regs;
4098 regdata = brcmf_sdcard_reg_read(sdiodev,
4099 CORE_CC_REG(ci->cccorebase, chipid), 4);
4100 ci->chip = regdata & CID_ID_MASK;
4101 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4102
4103 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4104
4105 /* Address of cores for new chips should be added here */
4106 switch (ci->chip) {
4107 case BCM4329_CHIP_ID:
4108 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4109 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4110 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4111 ci->ramsize = BCM4329_RAMSIZE;
4112 break;
4113 default:
4114 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4115 return -ENODEV;
4116 }
4117
4118 regdata = brcmf_sdcard_reg_read(sdiodev,
4119 CORE_SB(ci->cccorebase, sbidhigh), 4);
4120 ci->ccrev = SBCOREREV(regdata);
4121
4122 regdata = brcmf_sdcard_reg_read(sdiodev,
4123 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4124 ci->pmurev = regdata & PCAP_REV_MASK;
4125
4126 regdata = brcmf_sdcard_reg_read(sdiodev,
4127 CORE_SB(ci->buscorebase, sbidhigh), 4);
4128 ci->buscorerev = SBCOREREV(regdata);
4129 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4130
4131 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4132 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4133
4134 /* get chipcommon capabilites */
4135 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4136 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4137
4138 return 0;
4139 }
4140
4141 static int
4142 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4143 {
4144 struct chip_info *ci;
4145 int err;
4146 u8 clkval, clkset;
4147
4148 brcmf_dbg(TRACE, "Enter\n");
4149
4150 /* alloc chip_info_t */
4151 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4152 if (NULL == ci)
4153 return -ENOMEM;
4154
4155 /* bus/core/clk setup for register access */
4156 /* Try forcing SDIO core to do ALPAvail request only */
4157 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4158 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4159 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4160 if (err) {
4161 brcmf_dbg(ERROR, "error writing for HT off\n");
4162 goto fail;
4163 }
4164
4165 /* If register supported, wait for ALPAvail and then force ALP */
4166 /* This may take up to 15 milliseconds */
4167 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4168 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4169 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4170 SPINWAIT(((clkval =
4171 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4172 SBSDIO_FUNC1_CHIPCLKCSR,
4173 NULL)),
4174 !SBSDIO_ALPAV(clkval)),
4175 PMU_MAX_TRANSITION_DLY);
4176 if (!SBSDIO_ALPAV(clkval)) {
4177 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4178 clkval);
4179 err = -EBUSY;
4180 goto fail;
4181 }
4182 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4183 SBSDIO_FORCE_ALP;
4184 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4185 SBSDIO_FUNC1_CHIPCLKCSR,
4186 clkset, &err);
4187 udelay(65);
4188 } else {
4189 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4190 clkset, clkval);
4191 err = -EACCES;
4192 goto fail;
4193 }
4194
4195 /* Also, disable the extra SDIO pull-ups */
4196 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4197 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4198
4199 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4200 if (err)
4201 goto fail;
4202
4203 /*
4204 * Make sure any on-chip ARM is off (in case strapping is wrong),
4205 * or downloaded code was already running.
4206 */
4207 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4208
4209 brcmf_sdcard_reg_write(bus->sdiodev,
4210 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4211 brcmf_sdcard_reg_write(bus->sdiodev,
4212 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4213
4214 /* Disable F2 to clear any intermediate frame state on the dongle */
4215 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4216 SDIO_FUNC_ENABLE_1, NULL);
4217
4218 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4219 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4220 0, NULL);
4221
4222 /* Done with backplane-dependent accesses, can drop clock... */
4223 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4224 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4225
4226 bus->ci = ci;
4227 return 0;
4228 fail:
4229 bus->ci = NULL;
4230 kfree(ci);
4231 return err;
4232 }
4233
4234 static bool
4235 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4236 {
4237 u8 clkctl = 0;
4238 int err = 0;
4239 int reg_addr;
4240 u32 reg_val;
4241
4242 bus->alp_only = true;
4243
4244 /* Return the window to backplane enumeration space for core access */
4245 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4246 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4247
4248 #ifdef BCMDBG
4249 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4250 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4251
4252 #endif /* BCMDBG */
4253
4254 /*
4255 * Force PLL off until brcmf_sdbrcm_chip_attach()
4256 * programs PLL control regs
4257 */
4258
4259 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4260 SBSDIO_FUNC1_CHIPCLKCSR,
4261 BRCMF_INIT_CLKCTL1, &err);
4262 if (!err)
4263 clkctl =
4264 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4265 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4266
4267 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4268 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4269 err, BRCMF_INIT_CLKCTL1, clkctl);
4270 goto fail;
4271 }
4272
4273 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4274 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4275 goto fail;
4276 }
4277
4278 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4279 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4280 goto fail;
4281 }
4282
4283 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4284
4285 /* Get info on the ARM and SOCRAM cores... */
4286 brcmf_sdcard_reg_read(bus->sdiodev,
4287 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4288 bus->ramsize = bus->ci->ramsize;
4289 if (!(bus->ramsize)) {
4290 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4291 goto fail;
4292 }
4293
4294 /* Set core control so an SDIO reset does a backplane reset */
4295 reg_addr = bus->ci->buscorebase +
4296 offsetof(struct sdpcmd_regs, corecontrol);
4297 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4298 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4299 reg_val | CC_BPRESEN);
4300
4301 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4302
4303 /* Locate an appropriately-aligned portion of hdrbuf */
4304 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4305 BRCMF_SDALIGN);
4306
4307 /* Set the poll and/or interrupt flags */
4308 bus->intr = true;
4309 bus->poll = false;
4310 if (bus->poll)
4311 bus->pollrate = 1;
4312
4313 return true;
4314
4315 fail:
4316 return false;
4317 }
4318
4319 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4320 {
4321 brcmf_dbg(TRACE, "Enter\n");
4322
4323 /* Disable F2 to clear any intermediate frame state on the dongle */
4324 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4325 SDIO_FUNC_ENABLE_1, NULL);
4326
4327 bus->drvr->busstate = BRCMF_BUS_DOWN;
4328 bus->sleeping = false;
4329 bus->rxflow = false;
4330
4331 /* Done with backplane-dependent accesses, can drop clock... */
4332 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4333 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4334
4335 /* ...and initialize clock/power states */
4336 bus->clkstate = CLK_SDONLY;
4337 bus->idletime = BRCMF_IDLE_INTERVAL;
4338 bus->idleclock = BRCMF_IDLE_ACTIVE;
4339
4340 /* Query the F2 block size, set roundup accordingly */
4341 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4342 bus->roundup = min(max_roundup, bus->blocksize);
4343
4344 /* bus module does not support packet chaining */
4345 bus->use_rxchain = false;
4346 bus->sd_rxchain = false;
4347
4348 return true;
4349 }
4350
4351 static int
4352 brcmf_sdbrcm_watchdog_thread(void *data)
4353 {
4354 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4355
4356 allow_signal(SIGTERM);
4357 /* Run until signal received */
4358 while (1) {
4359 if (kthread_should_stop())
4360 break;
4361 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4362 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4363 /* Count the tick for reference */
4364 bus->drvr->tickcnt++;
4365 } else
4366 break;
4367 }
4368 return 0;
4369 }
4370
4371 static void
4372 brcmf_sdbrcm_watchdog(unsigned long data)
4373 {
4374 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4375
4376 if (bus->watchdog_tsk) {
4377 complete(&bus->watchdog_wait);
4378 /* Reschedule the watchdog */
4379 if (bus->wd_timer_valid)
4380 mod_timer(&bus->timer,
4381 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4382 }
4383 }
4384
4385 static void
4386 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4387 {
4388 brcmf_dbg(TRACE, "Enter\n");
4389
4390 kfree(bus->ci);
4391 bus->ci = NULL;
4392 }
4393
4394 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4395 {
4396 brcmf_dbg(TRACE, "Enter\n");
4397
4398 if (bus->ci) {
4399 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4400 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4401 brcmf_sdbrcm_chip_detach(bus);
4402 if (bus->vars && bus->varsz)
4403 kfree(bus->vars);
4404 bus->vars = NULL;
4405 }
4406
4407 brcmf_dbg(TRACE, "Disconnected\n");
4408 }
4409
4410 /* Detach and free everything */
4411 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4412 {
4413 brcmf_dbg(TRACE, "Enter\n");
4414
4415 if (bus) {
4416 /* De-register interrupt handler */
4417 brcmf_sdcard_intr_dereg(bus->sdiodev);
4418
4419 if (bus->drvr) {
4420 brcmf_detach(bus->drvr);
4421 brcmf_sdbrcm_release_dongle(bus);
4422 bus->drvr = NULL;
4423 }
4424
4425 brcmf_sdbrcm_release_malloc(bus);
4426
4427 kfree(bus);
4428 }
4429
4430 brcmf_dbg(TRACE, "Disconnected\n");
4431 }
4432
4433 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4434 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4435 {
4436 int ret;
4437 struct brcmf_bus *bus;
4438
4439 /* Init global variables at run-time, not as part of the declaration.
4440 * This is required to support init/de-init of the driver.
4441 * Initialization
4442 * of globals as part of the declaration results in non-deterministic
4443 * behavior since the value of the globals may be different on the
4444 * first time that the driver is initialized vs subsequent
4445 * initializations.
4446 */
4447 brcmf_c_init();
4448
4449 brcmf_dbg(TRACE, "Enter\n");
4450
4451 /* We make an assumption about address window mappings:
4452 * regsva == SI_ENUM_BASE*/
4453
4454 /* Allocate private bus interface state */
4455 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4456 if (!bus)
4457 goto fail;
4458
4459 bus->sdiodev = sdiodev;
4460 sdiodev->bus = bus;
4461 skb_queue_head_init(&bus->glom);
4462 bus->txbound = BRCMF_TXBOUND;
4463 bus->rxbound = BRCMF_RXBOUND;
4464 bus->txminmax = BRCMF_TXMINMAX;
4465 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4466 bus->usebufpool = false; /* Use bufpool if allocated,
4467 else use locally malloced rxbuf */
4468
4469 /* attempt to attach to the dongle */
4470 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4471 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4472 goto fail;
4473 }
4474
4475 spin_lock_init(&bus->txqlock);
4476 init_waitqueue_head(&bus->ctrl_wait);
4477 init_waitqueue_head(&bus->dcmd_resp_wait);
4478
4479 /* Set up the watchdog timer */
4480 init_timer(&bus->timer);
4481 bus->timer.data = (unsigned long)bus;
4482 bus->timer.function = brcmf_sdbrcm_watchdog;
4483
4484 /* Initialize thread based operation and lock */
4485 sema_init(&bus->sdsem, 1);
4486
4487 /* Initialize watchdog thread */
4488 init_completion(&bus->watchdog_wait);
4489 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4490 bus, "brcmf_watchdog");
4491 if (IS_ERR(bus->watchdog_tsk)) {
4492 printk(KERN_WARNING
4493 "brcmf_watchdog thread failed to start\n");
4494 bus->watchdog_tsk = NULL;
4495 }
4496 /* Initialize DPC thread */
4497 init_completion(&bus->dpc_wait);
4498 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4499 bus, "brcmf_dpc");
4500 if (IS_ERR(bus->dpc_tsk)) {
4501 printk(KERN_WARNING
4502 "brcmf_dpc thread failed to start\n");
4503 bus->dpc_tsk = NULL;
4504 }
4505
4506 /* Attach to the brcmf/OS/network interface */
4507 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4508 if (!bus->drvr) {
4509 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4510 goto fail;
4511 }
4512
4513 /* Allocate buffers */
4514 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4515 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4516 goto fail;
4517 }
4518
4519 if (!(brcmf_sdbrcm_probe_init(bus))) {
4520 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4521 goto fail;
4522 }
4523
4524 /* Register interrupt callback, but mask it (not operational yet). */
4525 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4526 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4527 if (ret != 0) {
4528 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4529 goto fail;
4530 }
4531 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4532
4533 brcmf_dbg(INFO, "completed!!\n");
4534
4535 /* if firmware path present try to download and bring up bus */
4536 ret = brcmf_bus_start(bus->drvr);
4537 if (ret != 0) {
4538 if (ret == -ENOLINK) {
4539 brcmf_dbg(ERROR, "dongle is not responding\n");
4540 goto fail;
4541 }
4542 }
4543
4544 /* add interface and open for business */
4545 if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
4546 brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
4547 goto fail;
4548 }
4549
4550 return bus;
4551
4552 fail:
4553 brcmf_sdbrcm_release(bus);
4554 return NULL;
4555 }
4556
4557 void brcmf_sdbrcm_disconnect(void *ptr)
4558 {
4559 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4560
4561 brcmf_dbg(TRACE, "Enter\n");
4562
4563 if (bus)
4564 brcmf_sdbrcm_release(bus);
4565
4566 brcmf_dbg(TRACE, "Disconnected\n");
4567 }
4568
4569 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4570 {
4571 return &bus->sdiodev->func[2]->dev;
4572 }
4573
4574 void
4575 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4576 {
4577 /* Totally stop the timer */
4578 if (!wdtick && bus->wd_timer_valid == true) {
4579 del_timer_sync(&bus->timer);
4580 bus->wd_timer_valid = false;
4581 bus->save_ms = wdtick;
4582 return;
4583 }
4584
4585 /* don't start the wd until fw is loaded */
4586 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4587 return;
4588
4589 if (wdtick) {
4590 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4591 if (bus->wd_timer_valid == true)
4592 /* Stop timer and restart at new value */
4593 del_timer_sync(&bus->timer);
4594
4595 /* Create timer again when watchdog period is
4596 dynamically changed or in the first instance
4597 */
4598 bus->timer.expires =
4599 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4600 add_timer(&bus->timer);
4601
4602 } else {
4603 /* Re arm the timer, at last watchdog period */
4604 mod_timer(&bus->timer,
4605 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4606 }
4607
4608 bus->wd_timer_valid = true;
4609 bus->save_ms = wdtick;
4610 }
4611 }