2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
14 int intel_agp_enabled
;
15 EXPORT_SYMBOL(intel_agp_enabled
);
18 * If we have Intel graphics, we're not going to have anything other than
19 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
20 * on the Intel IOMMU support (CONFIG_DMAR).
21 * Only newer chipsets need to bother with this, of course.
24 #define USE_PCI_DMA_API 1
27 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
28 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
29 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
30 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
31 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
32 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
33 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
34 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
35 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
36 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
37 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
38 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
39 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
40 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
41 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
42 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
43 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
44 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
45 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
46 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
47 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
48 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
49 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
50 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
51 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
52 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
53 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
54 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
55 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
56 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
57 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
58 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
59 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
60 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
61 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
62 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
63 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
64 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
65 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
66 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
67 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
68 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
69 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
70 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
71 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
72 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
73 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104
74 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106
76 /* cover 915 and 945 variants */
77 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
84 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
91 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
97 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
100 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
103 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
104 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
106 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
113 extern int agp_memory_reserved
;
116 /* Intel 815 register */
117 #define INTEL_815_APCONT 0x51
118 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
120 /* Intel i820 registers */
121 #define INTEL_I820_RDCR 0x51
122 #define INTEL_I820_ERRSTS 0xc8
124 /* Intel i840 registers */
125 #define INTEL_I840_MCHCFG 0x50
126 #define INTEL_I840_ERRSTS 0xc8
128 /* Intel i850 registers */
129 #define INTEL_I850_MCHCFG 0x50
130 #define INTEL_I850_ERRSTS 0xc8
132 /* intel 915G registers */
133 #define I915_GMADDR 0x18
134 #define I915_MMADDR 0x10
135 #define I915_PTEADDR 0x1C
136 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
137 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
138 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
139 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
140 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
141 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
142 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
143 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
145 #define I915_IFPADDR 0x60
147 /* Intel 965G registers */
148 #define I965_MSAC 0x62
149 #define I965_IFPADDR 0x70
151 /* Intel 7505 registers */
152 #define INTEL_I7505_APSIZE 0x74
153 #define INTEL_I7505_NCAPID 0x60
154 #define INTEL_I7505_NISTAT 0x6c
155 #define INTEL_I7505_ATTBASE 0x78
156 #define INTEL_I7505_ERRSTS 0x42
157 #define INTEL_I7505_AGPCTRL 0x70
158 #define INTEL_I7505_MCHCFG 0x50
160 #define SNB_GMCH_CTRL 0x50
161 #define SNB_GMCH_GMS_STOLEN_MASK 0xF8
162 #define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
163 #define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
164 #define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
165 #define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
166 #define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
167 #define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
168 #define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
169 #define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
170 #define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
171 #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
172 #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
173 #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
174 #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
175 #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
176 #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
177 #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
179 static const struct aper_size_info_fixed intel_i810_sizes
[] =
182 /* The 32M mode still requires a 64k gatt */
186 #define AGP_DCACHE_MEMORY 1
187 #define AGP_PHYS_MEMORY 2
188 #define INTEL_AGP_CACHED_MEMORY 3
190 static struct gatt_mask intel_i810_masks
[] =
192 {.mask
= I810_PTE_VALID
, .type
= 0},
193 {.mask
= (I810_PTE_VALID
| I810_PTE_LOCAL
), .type
= AGP_DCACHE_MEMORY
},
194 {.mask
= I810_PTE_VALID
, .type
= 0},
195 {.mask
= I810_PTE_VALID
| I830_PTE_SYSTEM_CACHED
,
196 .type
= INTEL_AGP_CACHED_MEMORY
}
199 static struct _intel_private
{
200 struct pci_dev
*pcidev
; /* device one */
201 u8 __iomem
*registers
;
202 u32 __iomem
*gtt
; /* I915G */
203 int num_dcache_entries
;
204 /* gtt_entries is the number of gtt entries that are already mapped
205 * to stolen memory. Stolen memory is larger than the memory mapped
206 * through gtt_entries, as it includes some reserved space for the BIOS
207 * popup and for the GTT.
209 int gtt_entries
; /* i830+ */
212 void __iomem
*i9xx_flush_page
;
213 void *i8xx_flush_page
;
215 struct page
*i8xx_page
;
216 struct resource ifp_resource
;
220 #ifdef USE_PCI_DMA_API
221 static int intel_agp_map_page(struct page
*page
, dma_addr_t
*ret
)
223 *ret
= pci_map_page(intel_private
.pcidev
, page
, 0,
224 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
225 if (pci_dma_mapping_error(intel_private
.pcidev
, *ret
))
230 static void intel_agp_unmap_page(struct page
*page
, dma_addr_t dma
)
232 pci_unmap_page(intel_private
.pcidev
, dma
,
233 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
236 static void intel_agp_free_sglist(struct agp_memory
*mem
)
240 st
.sgl
= mem
->sg_list
;
241 st
.orig_nents
= st
.nents
= mem
->page_count
;
249 static int intel_agp_map_memory(struct agp_memory
*mem
)
252 struct scatterlist
*sg
;
255 DBG("try mapping %lu pages\n", (unsigned long)mem
->page_count
);
257 if (sg_alloc_table(&st
, mem
->page_count
, GFP_KERNEL
))
260 mem
->sg_list
= sg
= st
.sgl
;
262 for (i
= 0 ; i
< mem
->page_count
; i
++, sg
= sg_next(sg
))
263 sg_set_page(sg
, mem
->pages
[i
], PAGE_SIZE
, 0);
265 mem
->num_sg
= pci_map_sg(intel_private
.pcidev
, mem
->sg_list
,
266 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
267 if (unlikely(!mem
->num_sg
)) {
268 intel_agp_free_sglist(mem
);
274 static void intel_agp_unmap_memory(struct agp_memory
*mem
)
276 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
278 pci_unmap_sg(intel_private
.pcidev
, mem
->sg_list
,
279 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
280 intel_agp_free_sglist(mem
);
283 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
284 off_t pg_start
, int mask_type
)
286 struct scatterlist
*sg
;
291 WARN_ON(!mem
->num_sg
);
293 if (mem
->num_sg
== mem
->page_count
) {
294 for_each_sg(mem
->sg_list
, sg
, mem
->page_count
, i
) {
295 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
296 sg_dma_address(sg
), mask_type
),
297 intel_private
.gtt
+j
);
301 /* sg may merge pages, but we have to separate
302 * per-page addr for GTT */
305 for_each_sg(mem
->sg_list
, sg
, mem
->num_sg
, i
) {
306 len
= sg_dma_len(sg
) / PAGE_SIZE
;
307 for (m
= 0; m
< len
; m
++) {
308 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
309 sg_dma_address(sg
) + m
* PAGE_SIZE
,
311 intel_private
.gtt
+j
);
316 readl(intel_private
.gtt
+j
-1);
321 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
322 off_t pg_start
, int mask_type
)
327 if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
||
328 agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
)
330 cache_bits
= I830_PTE_SYSTEM_CACHED
;
333 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
334 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
335 page_to_phys(mem
->pages
[i
]), mask_type
),
336 intel_private
.gtt
+j
);
339 readl(intel_private
.gtt
+j
-1);
344 static int intel_i810_fetch_size(void)
347 struct aper_size_info_fixed
*values
;
349 pci_read_config_dword(agp_bridge
->dev
, I810_SMRAM_MISCC
, &smram_miscc
);
350 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
352 if ((smram_miscc
& I810_GMS
) == I810_GMS_DISABLE
) {
353 dev_warn(&agp_bridge
->dev
->dev
, "i810 is disabled\n");
356 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
) == I810_GFX_MEM_WIN_32M
) {
357 agp_bridge
->previous_size
=
358 agp_bridge
->current_size
= (void *) (values
+ 1);
359 agp_bridge
->aperture_size_idx
= 1;
360 return values
[1].size
;
362 agp_bridge
->previous_size
=
363 agp_bridge
->current_size
= (void *) (values
);
364 agp_bridge
->aperture_size_idx
= 0;
365 return values
[0].size
;
371 static int intel_i810_configure(void)
373 struct aper_size_info_fixed
*current_size
;
377 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
379 if (!intel_private
.registers
) {
380 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
383 intel_private
.registers
= ioremap(temp
, 128 * 4096);
384 if (!intel_private
.registers
) {
385 dev_err(&intel_private
.pcidev
->dev
,
386 "can't remap memory\n");
391 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
392 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
393 /* This will need to be dynamically assigned */
394 dev_info(&intel_private
.pcidev
->dev
,
395 "detected 4MB dedicated video ram\n");
396 intel_private
.num_dcache_entries
= 1024;
398 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
399 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
400 writel(agp_bridge
->gatt_bus_addr
| I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
401 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
403 if (agp_bridge
->driver
->needs_scratch_page
) {
404 for (i
= 0; i
< current_size
->num_entries
; i
++) {
405 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
407 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI posting. */
409 global_cache_flush();
413 static void intel_i810_cleanup(void)
415 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
416 readl(intel_private
.registers
); /* PCI Posting. */
417 iounmap(intel_private
.registers
);
420 static void intel_i810_tlbflush(struct agp_memory
*mem
)
425 static void intel_i810_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
430 /* Exists to support ARGB cursors */
431 static struct page
*i8xx_alloc_pages(void)
435 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
439 if (set_pages_uc(page
, 4) < 0) {
440 set_pages_wb(page
, 4);
441 __free_pages(page
, 2);
445 atomic_inc(&agp_bridge
->current_memory_agp
);
449 static void i8xx_destroy_pages(struct page
*page
)
454 set_pages_wb(page
, 4);
456 __free_pages(page
, 2);
457 atomic_dec(&agp_bridge
->current_memory_agp
);
460 static int intel_i830_type_to_mask_type(struct agp_bridge_data
*bridge
,
463 if (type
< AGP_USER_TYPES
)
465 else if (type
== AGP_USER_CACHED_MEMORY
)
466 return INTEL_AGP_CACHED_MEMORY
;
471 static int intel_i810_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
474 int i
, j
, num_entries
;
479 if (mem
->page_count
== 0)
482 temp
= agp_bridge
->current_size
;
483 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
485 if ((pg_start
+ mem
->page_count
) > num_entries
)
489 for (j
= pg_start
; j
< (pg_start
+ mem
->page_count
); j
++) {
490 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
))) {
496 if (type
!= mem
->type
)
499 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
502 case AGP_DCACHE_MEMORY
:
503 if (!mem
->is_flushed
)
504 global_cache_flush();
505 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
506 writel((i
*4096)|I810_PTE_LOCAL
|I810_PTE_VALID
,
507 intel_private
.registers
+I810_PTE_BASE
+(i
*4));
509 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
511 case AGP_PHYS_MEMORY
:
512 case AGP_NORMAL_MEMORY
:
513 if (!mem
->is_flushed
)
514 global_cache_flush();
515 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
516 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
517 page_to_phys(mem
->pages
[i
]), mask_type
),
518 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
520 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
526 agp_bridge
->driver
->tlb_flush(mem
);
530 mem
->is_flushed
= true;
534 static int intel_i810_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
539 if (mem
->page_count
== 0)
542 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
543 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
545 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
547 agp_bridge
->driver
->tlb_flush(mem
);
552 * The i810/i830 requires a physical address to program its mouse
553 * pointer into hardware.
554 * However the Xserver still writes to it through the agp aperture.
556 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
558 struct agp_memory
*new;
562 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
565 /* kludge to get 4 physical pages for ARGB cursor */
566 page
= i8xx_alloc_pages();
575 new = agp_create_memory(pg_count
);
579 new->pages
[0] = page
;
581 /* kludge to get 4 physical pages for ARGB cursor */
582 new->pages
[1] = new->pages
[0] + 1;
583 new->pages
[2] = new->pages
[1] + 1;
584 new->pages
[3] = new->pages
[2] + 1;
586 new->page_count
= pg_count
;
587 new->num_scratch_pages
= pg_count
;
588 new->type
= AGP_PHYS_MEMORY
;
589 new->physical
= page_to_phys(new->pages
[0]);
593 static struct agp_memory
*intel_i810_alloc_by_type(size_t pg_count
, int type
)
595 struct agp_memory
*new;
597 if (type
== AGP_DCACHE_MEMORY
) {
598 if (pg_count
!= intel_private
.num_dcache_entries
)
601 new = agp_create_memory(1);
605 new->type
= AGP_DCACHE_MEMORY
;
606 new->page_count
= pg_count
;
607 new->num_scratch_pages
= 0;
608 agp_free_page_array(new);
611 if (type
== AGP_PHYS_MEMORY
)
612 return alloc_agpphysmem_i8xx(pg_count
, type
);
616 static void intel_i810_free_by_type(struct agp_memory
*curr
)
618 agp_free_key(curr
->key
);
619 if (curr
->type
== AGP_PHYS_MEMORY
) {
620 if (curr
->page_count
== 4)
621 i8xx_destroy_pages(curr
->pages
[0]);
623 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
624 AGP_PAGE_DESTROY_UNMAP
);
625 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
626 AGP_PAGE_DESTROY_FREE
);
628 agp_free_page_array(curr
);
633 static unsigned long intel_i810_mask_memory(struct agp_bridge_data
*bridge
,
634 dma_addr_t addr
, int type
)
636 /* Type checking must be done elsewhere */
637 return addr
| bridge
->driver
->masks
[type
].mask
;
640 static struct aper_size_info_fixed intel_i830_sizes
[] =
643 /* The 64M mode still requires a 128k gatt */
649 static void intel_i830_init_gtt_entries(void)
655 static const int ddt
[4] = { 0, 16, 32, 64 };
656 int size
; /* reserved space (in kb) at the top of stolen memory */
658 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
662 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
664 /* The 965 has a field telling us the size of the GTT,
665 * which may be larger than what is necessary to map the
668 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
669 case I965_PGETBL_SIZE_128KB
:
672 case I965_PGETBL_SIZE_256KB
:
675 case I965_PGETBL_SIZE_512KB
:
678 case I965_PGETBL_SIZE_1MB
:
681 case I965_PGETBL_SIZE_2MB
:
684 case I965_PGETBL_SIZE_1_5MB
:
688 dev_info(&intel_private
.pcidev
->dev
,
689 "unknown page table size, assuming 512KB\n");
692 size
+= 4; /* add in BIOS popup space */
693 } else if (IS_G33
&& !IS_PINEVIEW
) {
694 /* G33's GTT size defined in gmch_ctrl */
695 switch (gmch_ctrl
& G33_PGETBL_SIZE_MASK
) {
696 case G33_PGETBL_SIZE_1M
:
699 case G33_PGETBL_SIZE_2M
:
703 dev_info(&agp_bridge
->dev
->dev
,
704 "unknown page table size 0x%x, assuming 512KB\n",
705 (gmch_ctrl
& G33_PGETBL_SIZE_MASK
));
709 } else if (IS_G4X
|| IS_PINEVIEW
) {
710 /* On 4 series hardware, GTT stolen is separate from graphics
711 * stolen, ignore it in stolen gtt entries counting. However,
712 * 4KB of the stolen memory doesn't get mapped to the GTT.
716 /* On previous hardware, the GTT size was just what was
717 * required to map the aperture.
719 size
= agp_bridge
->driver
->fetch_size() + 4;
722 if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
723 agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
724 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
725 case I830_GMCH_GMS_STOLEN_512
:
726 gtt_entries
= KB(512) - KB(size
);
728 case I830_GMCH_GMS_STOLEN_1024
:
729 gtt_entries
= MB(1) - KB(size
);
731 case I830_GMCH_GMS_STOLEN_8192
:
732 gtt_entries
= MB(8) - KB(size
);
734 case I830_GMCH_GMS_LOCAL
:
735 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
736 gtt_entries
= (I830_RDRAM_ND(rdct
) + 1) *
737 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
744 } else if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
||
745 agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
) {
747 * SandyBridge has new memory control reg at 0x50.w
750 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
751 switch (snb_gmch_ctl
& SNB_GMCH_GMS_STOLEN_MASK
) {
752 case SNB_GMCH_GMS_STOLEN_32M
:
753 gtt_entries
= MB(32) - KB(size
);
755 case SNB_GMCH_GMS_STOLEN_64M
:
756 gtt_entries
= MB(64) - KB(size
);
758 case SNB_GMCH_GMS_STOLEN_96M
:
759 gtt_entries
= MB(96) - KB(size
);
761 case SNB_GMCH_GMS_STOLEN_128M
:
762 gtt_entries
= MB(128) - KB(size
);
764 case SNB_GMCH_GMS_STOLEN_160M
:
765 gtt_entries
= MB(160) - KB(size
);
767 case SNB_GMCH_GMS_STOLEN_192M
:
768 gtt_entries
= MB(192) - KB(size
);
770 case SNB_GMCH_GMS_STOLEN_224M
:
771 gtt_entries
= MB(224) - KB(size
);
773 case SNB_GMCH_GMS_STOLEN_256M
:
774 gtt_entries
= MB(256) - KB(size
);
776 case SNB_GMCH_GMS_STOLEN_288M
:
777 gtt_entries
= MB(288) - KB(size
);
779 case SNB_GMCH_GMS_STOLEN_320M
:
780 gtt_entries
= MB(320) - KB(size
);
782 case SNB_GMCH_GMS_STOLEN_352M
:
783 gtt_entries
= MB(352) - KB(size
);
785 case SNB_GMCH_GMS_STOLEN_384M
:
786 gtt_entries
= MB(384) - KB(size
);
788 case SNB_GMCH_GMS_STOLEN_416M
:
789 gtt_entries
= MB(416) - KB(size
);
791 case SNB_GMCH_GMS_STOLEN_448M
:
792 gtt_entries
= MB(448) - KB(size
);
794 case SNB_GMCH_GMS_STOLEN_480M
:
795 gtt_entries
= MB(480) - KB(size
);
797 case SNB_GMCH_GMS_STOLEN_512M
:
798 gtt_entries
= MB(512) - KB(size
);
802 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
803 case I855_GMCH_GMS_STOLEN_1M
:
804 gtt_entries
= MB(1) - KB(size
);
806 case I855_GMCH_GMS_STOLEN_4M
:
807 gtt_entries
= MB(4) - KB(size
);
809 case I855_GMCH_GMS_STOLEN_8M
:
810 gtt_entries
= MB(8) - KB(size
);
812 case I855_GMCH_GMS_STOLEN_16M
:
813 gtt_entries
= MB(16) - KB(size
);
815 case I855_GMCH_GMS_STOLEN_32M
:
816 gtt_entries
= MB(32) - KB(size
);
818 case I915_GMCH_GMS_STOLEN_48M
:
819 /* Check it's really I915G */
820 if (IS_I915
|| IS_I965
|| IS_G33
|| IS_G4X
)
821 gtt_entries
= MB(48) - KB(size
);
825 case I915_GMCH_GMS_STOLEN_64M
:
826 /* Check it's really I915G */
827 if (IS_I915
|| IS_I965
|| IS_G33
|| IS_G4X
)
828 gtt_entries
= MB(64) - KB(size
);
832 case G33_GMCH_GMS_STOLEN_128M
:
833 if (IS_G33
|| IS_I965
|| IS_G4X
)
834 gtt_entries
= MB(128) - KB(size
);
838 case G33_GMCH_GMS_STOLEN_256M
:
839 if (IS_G33
|| IS_I965
|| IS_G4X
)
840 gtt_entries
= MB(256) - KB(size
);
844 case INTEL_GMCH_GMS_STOLEN_96M
:
845 if (IS_I965
|| IS_G4X
)
846 gtt_entries
= MB(96) - KB(size
);
850 case INTEL_GMCH_GMS_STOLEN_160M
:
851 if (IS_I965
|| IS_G4X
)
852 gtt_entries
= MB(160) - KB(size
);
856 case INTEL_GMCH_GMS_STOLEN_224M
:
857 if (IS_I965
|| IS_G4X
)
858 gtt_entries
= MB(224) - KB(size
);
862 case INTEL_GMCH_GMS_STOLEN_352M
:
863 if (IS_I965
|| IS_G4X
)
864 gtt_entries
= MB(352) - KB(size
);
873 if (gtt_entries
> 0) {
874 dev_info(&agp_bridge
->dev
->dev
, "detected %dK %s memory\n",
875 gtt_entries
/ KB(1), local
? "local" : "stolen");
876 gtt_entries
/= KB(4);
878 dev_info(&agp_bridge
->dev
->dev
,
879 "no pre-allocated video memory detected\n");
883 intel_private
.gtt_entries
= gtt_entries
;
886 static void intel_i830_fini_flush(void)
888 kunmap(intel_private
.i8xx_page
);
889 intel_private
.i8xx_flush_page
= NULL
;
890 unmap_page_from_agp(intel_private
.i8xx_page
);
892 __free_page(intel_private
.i8xx_page
);
893 intel_private
.i8xx_page
= NULL
;
896 static void intel_i830_setup_flush(void)
898 /* return if we've already set the flush mechanism up */
899 if (intel_private
.i8xx_page
)
902 intel_private
.i8xx_page
= alloc_page(GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
);
903 if (!intel_private
.i8xx_page
)
906 intel_private
.i8xx_flush_page
= kmap(intel_private
.i8xx_page
);
907 if (!intel_private
.i8xx_flush_page
)
908 intel_i830_fini_flush();
911 /* The chipset_flush interface needs to get data that has already been
912 * flushed out of the CPU all the way out to main memory, because the GPU
913 * doesn't snoop those buffers.
915 * The 8xx series doesn't have the same lovely interface for flushing the
916 * chipset write buffers that the later chips do. According to the 865
917 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
918 * that buffer out, we just fill 1KB and clflush it out, on the assumption
919 * that it'll push whatever was in there out. It appears to work.
921 static void intel_i830_chipset_flush(struct agp_bridge_data
*bridge
)
923 unsigned int *pg
= intel_private
.i8xx_flush_page
;
928 clflush_cache_range(pg
, 1024);
929 else if (wbinvd_on_all_cpus() != 0)
930 printk(KERN_ERR
"Timed out waiting for cache flush.\n");
933 /* The intel i830 automatically initializes the agp aperture during POST.
934 * Use the memory already set aside for in the GTT.
936 static int intel_i830_create_gatt_table(struct agp_bridge_data
*bridge
)
939 struct aper_size_info_fixed
*size
;
943 size
= agp_bridge
->current_size
;
944 page_order
= size
->page_order
;
945 num_entries
= size
->num_entries
;
946 agp_bridge
->gatt_table_real
= NULL
;
948 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
951 intel_private
.registers
= ioremap(temp
, 128 * 4096);
952 if (!intel_private
.registers
)
955 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
956 global_cache_flush(); /* FIXME: ?? */
958 /* we have to call this as early as possible after the MMIO base address is known */
959 intel_i830_init_gtt_entries();
961 agp_bridge
->gatt_table
= NULL
;
963 agp_bridge
->gatt_bus_addr
= temp
;
968 /* Return the gatt table to a sane state. Use the top of stolen
969 * memory for the GTT.
971 static int intel_i830_free_gatt_table(struct agp_bridge_data
*bridge
)
976 static int intel_i830_fetch_size(void)
979 struct aper_size_info_fixed
*values
;
981 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
983 if (agp_bridge
->dev
->device
!= PCI_DEVICE_ID_INTEL_82830_HB
&&
984 agp_bridge
->dev
->device
!= PCI_DEVICE_ID_INTEL_82845G_HB
) {
985 /* 855GM/852GM/865G has 128MB aperture size */
986 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) values
;
987 agp_bridge
->aperture_size_idx
= 0;
988 return values
[0].size
;
991 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
993 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_128M
) {
994 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) values
;
995 agp_bridge
->aperture_size_idx
= 0;
996 return values
[0].size
;
998 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) (values
+ 1);
999 agp_bridge
->aperture_size_idx
= 1;
1000 return values
[1].size
;
1006 static int intel_i830_configure(void)
1008 struct aper_size_info_fixed
*current_size
;
1013 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
1015 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
1016 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1018 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1019 gmch_ctrl
|= I830_GMCH_ENABLED
;
1020 pci_write_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, gmch_ctrl
);
1022 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
1023 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
1025 if (agp_bridge
->driver
->needs_scratch_page
) {
1026 for (i
= intel_private
.gtt_entries
; i
< current_size
->num_entries
; i
++) {
1027 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
1029 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI Posting. */
1032 global_cache_flush();
1034 intel_i830_setup_flush();
1038 static void intel_i830_cleanup(void)
1040 iounmap(intel_private
.registers
);
1043 static int intel_i830_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1046 int i
, j
, num_entries
;
1051 if (mem
->page_count
== 0)
1054 temp
= agp_bridge
->current_size
;
1055 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1057 if (pg_start
< intel_private
.gtt_entries
) {
1058 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1059 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1060 pg_start
, intel_private
.gtt_entries
);
1062 dev_info(&intel_private
.pcidev
->dev
,
1063 "trying to insert into local/stolen memory\n");
1067 if ((pg_start
+ mem
->page_count
) > num_entries
)
1070 /* The i830 can't check the GTT for entries since its read only,
1071 * depend on the caller to make the correct offset decisions.
1074 if (type
!= mem
->type
)
1077 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1079 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
1080 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1083 if (!mem
->is_flushed
)
1084 global_cache_flush();
1086 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
1087 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
1088 page_to_phys(mem
->pages
[i
]), mask_type
),
1089 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
1091 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
1092 agp_bridge
->driver
->tlb_flush(mem
);
1097 mem
->is_flushed
= true;
1101 static int intel_i830_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1106 if (mem
->page_count
== 0)
1109 if (pg_start
< intel_private
.gtt_entries
) {
1110 dev_info(&intel_private
.pcidev
->dev
,
1111 "trying to disable local/stolen memory\n");
1115 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
1116 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
1118 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
1120 agp_bridge
->driver
->tlb_flush(mem
);
1124 static struct agp_memory
*intel_i830_alloc_by_type(size_t pg_count
, int type
)
1126 if (type
== AGP_PHYS_MEMORY
)
1127 return alloc_agpphysmem_i8xx(pg_count
, type
);
1128 /* always return NULL for other allocation types for now */
1132 static int intel_alloc_chipset_flush_resource(void)
1135 ret
= pci_bus_alloc_resource(agp_bridge
->dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1136 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1137 pcibios_align_resource
, agp_bridge
->dev
);
1142 static void intel_i915_setup_chipset_flush(void)
1147 pci_read_config_dword(agp_bridge
->dev
, I915_IFPADDR
, &temp
);
1148 if (!(temp
& 0x1)) {
1149 intel_alloc_chipset_flush_resource();
1150 intel_private
.resource_valid
= 1;
1151 pci_write_config_dword(agp_bridge
->dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1155 intel_private
.resource_valid
= 1;
1156 intel_private
.ifp_resource
.start
= temp
;
1157 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1158 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1159 /* some BIOSes reserve this area in a pnp some don't */
1161 intel_private
.resource_valid
= 0;
1165 static void intel_i965_g33_setup_chipset_flush(void)
1167 u32 temp_hi
, temp_lo
;
1170 pci_read_config_dword(agp_bridge
->dev
, I965_IFPADDR
+ 4, &temp_hi
);
1171 pci_read_config_dword(agp_bridge
->dev
, I965_IFPADDR
, &temp_lo
);
1173 if (!(temp_lo
& 0x1)) {
1175 intel_alloc_chipset_flush_resource();
1177 intel_private
.resource_valid
= 1;
1178 pci_write_config_dword(agp_bridge
->dev
, I965_IFPADDR
+ 4,
1179 upper_32_bits(intel_private
.ifp_resource
.start
));
1180 pci_write_config_dword(agp_bridge
->dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1185 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1187 intel_private
.resource_valid
= 1;
1188 intel_private
.ifp_resource
.start
= l64
;
1189 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1190 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1191 /* some BIOSes reserve this area in a pnp some don't */
1193 intel_private
.resource_valid
= 0;
1197 static void intel_i9xx_setup_flush(void)
1199 /* return if already configured */
1200 if (intel_private
.ifp_resource
.start
)
1203 /* setup a resource for this object */
1204 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1205 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1207 /* Setup chipset flush for 915 */
1208 if (IS_I965
|| IS_G33
|| IS_G4X
) {
1209 intel_i965_g33_setup_chipset_flush();
1211 intel_i915_setup_chipset_flush();
1214 if (intel_private
.ifp_resource
.start
) {
1215 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1216 if (!intel_private
.i9xx_flush_page
)
1217 dev_info(&intel_private
.pcidev
->dev
, "can't ioremap flush page - no chipset flushing");
1221 static int intel_i915_configure(void)
1223 struct aper_size_info_fixed
*current_size
;
1228 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
1230 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
, &temp
);
1232 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1234 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1235 gmch_ctrl
|= I830_GMCH_ENABLED
;
1236 pci_write_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, gmch_ctrl
);
1238 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
1239 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
1241 if (agp_bridge
->driver
->needs_scratch_page
) {
1242 for (i
= intel_private
.gtt_entries
; i
< intel_private
.gtt_total_size
; i
++) {
1243 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1245 readl(intel_private
.gtt
+i
-1); /* PCI Posting. */
1248 global_cache_flush();
1250 intel_i9xx_setup_flush();
1255 static void intel_i915_cleanup(void)
1257 if (intel_private
.i9xx_flush_page
)
1258 iounmap(intel_private
.i9xx_flush_page
);
1259 if (intel_private
.resource_valid
)
1260 release_resource(&intel_private
.ifp_resource
);
1261 intel_private
.ifp_resource
.start
= 0;
1262 intel_private
.resource_valid
= 0;
1263 iounmap(intel_private
.gtt
);
1264 iounmap(intel_private
.registers
);
1267 static void intel_i915_chipset_flush(struct agp_bridge_data
*bridge
)
1269 if (intel_private
.i9xx_flush_page
)
1270 writel(1, intel_private
.i9xx_flush_page
);
1273 static int intel_i915_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1281 if (mem
->page_count
== 0)
1284 temp
= agp_bridge
->current_size
;
1285 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1287 if (pg_start
< intel_private
.gtt_entries
) {
1288 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1289 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1290 pg_start
, intel_private
.gtt_entries
);
1292 dev_info(&intel_private
.pcidev
->dev
,
1293 "trying to insert into local/stolen memory\n");
1297 if ((pg_start
+ mem
->page_count
) > num_entries
)
1300 /* The i915 can't check the GTT for entries since it's read only;
1301 * depend on the caller to make the correct offset decisions.
1304 if (type
!= mem
->type
)
1307 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1309 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
1310 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1313 if (!mem
->is_flushed
)
1314 global_cache_flush();
1316 intel_agp_insert_sg_entries(mem
, pg_start
, mask_type
);
1317 agp_bridge
->driver
->tlb_flush(mem
);
1322 mem
->is_flushed
= true;
1326 static int intel_i915_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1331 if (mem
->page_count
== 0)
1334 if (pg_start
< intel_private
.gtt_entries
) {
1335 dev_info(&intel_private
.pcidev
->dev
,
1336 "trying to disable local/stolen memory\n");
1340 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++)
1341 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1343 readl(intel_private
.gtt
+i
-1);
1345 agp_bridge
->driver
->tlb_flush(mem
);
1349 /* Return the aperture size by just checking the resource length. The effect
1350 * described in the spec of the MSAC registers is just changing of the
1353 static int intel_i9xx_fetch_size(void)
1355 int num_sizes
= ARRAY_SIZE(intel_i830_sizes
);
1356 int aper_size
; /* size in megabytes */
1359 aper_size
= pci_resource_len(intel_private
.pcidev
, 2) / MB(1);
1361 for (i
= 0; i
< num_sizes
; i
++) {
1362 if (aper_size
== intel_i830_sizes
[i
].size
) {
1363 agp_bridge
->current_size
= intel_i830_sizes
+ i
;
1364 agp_bridge
->previous_size
= agp_bridge
->current_size
;
1372 /* The intel i915 automatically initializes the agp aperture during POST.
1373 * Use the memory already set aside for in the GTT.
1375 static int intel_i915_create_gatt_table(struct agp_bridge_data
*bridge
)
1378 struct aper_size_info_fixed
*size
;
1381 int gtt_map_size
= 256 * 1024;
1383 size
= agp_bridge
->current_size
;
1384 page_order
= size
->page_order
;
1385 num_entries
= size
->num_entries
;
1386 agp_bridge
->gatt_table_real
= NULL
;
1388 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1389 pci_read_config_dword(intel_private
.pcidev
, I915_PTEADDR
, &temp2
);
1392 gtt_map_size
= 1024 * 1024; /* 1M on G33 */
1393 intel_private
.gtt
= ioremap(temp2
, gtt_map_size
);
1394 if (!intel_private
.gtt
)
1397 intel_private
.gtt_total_size
= gtt_map_size
/ 4;
1401 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1402 if (!intel_private
.registers
) {
1403 iounmap(intel_private
.gtt
);
1407 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1408 global_cache_flush(); /* FIXME: ? */
1410 /* we have to call this as early as possible after the MMIO base address is known */
1411 intel_i830_init_gtt_entries();
1413 agp_bridge
->gatt_table
= NULL
;
1415 agp_bridge
->gatt_bus_addr
= temp
;
1421 * The i965 supports 36-bit physical addresses, but to keep
1422 * the format of the GTT the same, the bits that don't fit
1423 * in a 32-bit word are shifted down to bits 4..7.
1425 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1426 * is always zero on 32-bit architectures, so no need to make
1429 static unsigned long intel_i965_mask_memory(struct agp_bridge_data
*bridge
,
1430 dma_addr_t addr
, int type
)
1432 /* Shift high bits down */
1433 addr
|= (addr
>> 28) & 0xf0;
1435 /* Type checking must be done elsewhere */
1436 return addr
| bridge
->driver
->masks
[type
].mask
;
1439 static void intel_i965_get_gtt_range(int *gtt_offset
, int *gtt_size
)
1441 switch (agp_bridge
->dev
->device
) {
1442 case PCI_DEVICE_ID_INTEL_GM45_HB
:
1443 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
:
1444 case PCI_DEVICE_ID_INTEL_Q45_HB
:
1445 case PCI_DEVICE_ID_INTEL_G45_HB
:
1446 case PCI_DEVICE_ID_INTEL_G41_HB
:
1447 case PCI_DEVICE_ID_INTEL_B43_HB
:
1448 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
:
1449 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
:
1450 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
:
1451 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
:
1452 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
:
1453 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
:
1454 *gtt_offset
= *gtt_size
= MB(2);
1457 *gtt_offset
= *gtt_size
= KB(512);
1461 /* The intel i965 automatically initializes the agp aperture during POST.
1462 * Use the memory already set aside for in the GTT.
1464 static int intel_i965_create_gatt_table(struct agp_bridge_data
*bridge
)
1467 struct aper_size_info_fixed
*size
;
1470 int gtt_offset
, gtt_size
;
1472 size
= agp_bridge
->current_size
;
1473 page_order
= size
->page_order
;
1474 num_entries
= size
->num_entries
;
1475 agp_bridge
->gatt_table_real
= NULL
;
1477 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1481 intel_i965_get_gtt_range(>t_offset
, >t_size
);
1483 intel_private
.gtt
= ioremap((temp
+ gtt_offset
) , gtt_size
);
1485 if (!intel_private
.gtt
)
1488 intel_private
.gtt_total_size
= gtt_size
/ 4;
1490 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1491 if (!intel_private
.registers
) {
1492 iounmap(intel_private
.gtt
);
1496 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1497 global_cache_flush(); /* FIXME: ? */
1499 /* we have to call this as early as possible after the MMIO base address is known */
1500 intel_i830_init_gtt_entries();
1502 agp_bridge
->gatt_table
= NULL
;
1504 agp_bridge
->gatt_bus_addr
= temp
;
1510 static int intel_fetch_size(void)
1514 struct aper_size_info_16
*values
;
1516 pci_read_config_word(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1517 values
= A_SIZE_16(agp_bridge
->driver
->aperture_sizes
);
1519 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
1520 if (temp
== values
[i
].size_value
) {
1521 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) (values
+ i
);
1522 agp_bridge
->aperture_size_idx
= i
;
1523 return values
[i
].size
;
1530 static int __intel_8xx_fetch_size(u8 temp
)
1533 struct aper_size_info_8
*values
;
1535 values
= A_SIZE_8(agp_bridge
->driver
->aperture_sizes
);
1537 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
1538 if (temp
== values
[i
].size_value
) {
1539 agp_bridge
->previous_size
=
1540 agp_bridge
->current_size
= (void *) (values
+ i
);
1541 agp_bridge
->aperture_size_idx
= i
;
1542 return values
[i
].size
;
1548 static int intel_8xx_fetch_size(void)
1552 pci_read_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1553 return __intel_8xx_fetch_size(temp
);
1556 static int intel_815_fetch_size(void)
1560 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1561 * one non-reserved bit, so mask the others out ... */
1562 pci_read_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1565 return __intel_8xx_fetch_size(temp
);
1568 static void intel_tlbflush(struct agp_memory
*mem
)
1570 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2200);
1571 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2280);
1575 static void intel_8xx_tlbflush(struct agp_memory
*mem
)
1578 pci_read_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, &temp
);
1579 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, temp
& ~(1 << 7));
1580 pci_read_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, &temp
);
1581 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, temp
| (1 << 7));
1585 static void intel_cleanup(void)
1588 struct aper_size_info_16
*previous_size
;
1590 previous_size
= A_SIZE_16(agp_bridge
->previous_size
);
1591 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp
);
1592 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp
& ~(1 << 9));
1593 pci_write_config_word(agp_bridge
->dev
, INTEL_APSIZE
, previous_size
->size_value
);
1597 static void intel_8xx_cleanup(void)
1600 struct aper_size_info_8
*previous_size
;
1602 previous_size
= A_SIZE_8(agp_bridge
->previous_size
);
1603 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp
);
1604 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp
& ~(1 << 9));
1605 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, previous_size
->size_value
);
1609 static int intel_configure(void)
1613 struct aper_size_info_16
*current_size
;
1615 current_size
= A_SIZE_16(agp_bridge
->current_size
);
1618 pci_write_config_word(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1620 /* address to map to */
1621 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1622 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1624 /* attbase - aperture base */
1625 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1628 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2280);
1631 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp2
);
1632 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
,
1633 (temp2
& ~(1 << 10)) | (1 << 9));
1634 /* clear any possible error conditions */
1635 pci_write_config_byte(agp_bridge
->dev
, INTEL_ERRSTS
+ 1, 7);
1639 static int intel_815_configure(void)
1643 struct aper_size_info_8
*current_size
;
1645 /* attbase - aperture base */
1646 /* the Intel 815 chipset spec. says that bits 29-31 in the
1647 * ATTBASE register are reserved -> try not to write them */
1648 if (agp_bridge
->gatt_bus_addr
& INTEL_815_ATTBASE_MASK
) {
1649 dev_emerg(&agp_bridge
->dev
->dev
, "gatt bus addr too high");
1653 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1656 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
,
1657 current_size
->size_value
);
1659 /* address to map to */
1660 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1661 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1663 pci_read_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, &addr
);
1664 addr
&= INTEL_815_ATTBASE_MASK
;
1665 addr
|= agp_bridge
->gatt_bus_addr
;
1666 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, addr
);
1669 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1672 pci_read_config_byte(agp_bridge
->dev
, INTEL_815_APCONT
, &temp2
);
1673 pci_write_config_byte(agp_bridge
->dev
, INTEL_815_APCONT
, temp2
| (1 << 1));
1675 /* clear any possible error conditions */
1676 /* Oddness : this chipset seems to have no ERRSTS register ! */
1680 static void intel_820_tlbflush(struct agp_memory
*mem
)
1685 static void intel_820_cleanup(void)
1688 struct aper_size_info_8
*previous_size
;
1690 previous_size
= A_SIZE_8(agp_bridge
->previous_size
);
1691 pci_read_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, &temp
);
1692 pci_write_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
,
1694 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
,
1695 previous_size
->size_value
);
1699 static int intel_820_configure(void)
1703 struct aper_size_info_8
*current_size
;
1705 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1708 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1710 /* address to map to */
1711 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1712 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1714 /* attbase - aperture base */
1715 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1718 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1720 /* global enable aperture access */
1721 /* This flag is not accessed through MCHCFG register as in */
1723 pci_read_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, &temp2
);
1724 pci_write_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, temp2
| (1 << 1));
1725 /* clear any possible AGP-related error conditions */
1726 pci_write_config_word(agp_bridge
->dev
, INTEL_I820_ERRSTS
, 0x001c);
1730 static int intel_840_configure(void)
1734 struct aper_size_info_8
*current_size
;
1736 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1739 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1741 /* address to map to */
1742 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1743 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1745 /* attbase - aperture base */
1746 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1749 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1752 pci_read_config_word(agp_bridge
->dev
, INTEL_I840_MCHCFG
, &temp2
);
1753 pci_write_config_word(agp_bridge
->dev
, INTEL_I840_MCHCFG
, temp2
| (1 << 9));
1754 /* clear any possible error conditions */
1755 pci_write_config_word(agp_bridge
->dev
, INTEL_I840_ERRSTS
, 0xc000);
1759 static int intel_845_configure(void)
1763 struct aper_size_info_8
*current_size
;
1765 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1768 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1770 if (agp_bridge
->apbase_config
!= 0) {
1771 pci_write_config_dword(agp_bridge
->dev
, AGP_APBASE
,
1772 agp_bridge
->apbase_config
);
1774 /* address to map to */
1775 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1776 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1777 agp_bridge
->apbase_config
= temp
;
1780 /* attbase - aperture base */
1781 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1784 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1787 pci_read_config_byte(agp_bridge
->dev
, INTEL_I845_AGPM
, &temp2
);
1788 pci_write_config_byte(agp_bridge
->dev
, INTEL_I845_AGPM
, temp2
| (1 << 1));
1789 /* clear any possible error conditions */
1790 pci_write_config_word(agp_bridge
->dev
, INTEL_I845_ERRSTS
, 0x001c);
1792 intel_i830_setup_flush();
1796 static int intel_850_configure(void)
1800 struct aper_size_info_8
*current_size
;
1802 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1805 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1807 /* address to map to */
1808 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1809 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1811 /* attbase - aperture base */
1812 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1815 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1818 pci_read_config_word(agp_bridge
->dev
, INTEL_I850_MCHCFG
, &temp2
);
1819 pci_write_config_word(agp_bridge
->dev
, INTEL_I850_MCHCFG
, temp2
| (1 << 9));
1820 /* clear any possible AGP-related error conditions */
1821 pci_write_config_word(agp_bridge
->dev
, INTEL_I850_ERRSTS
, 0x001c);
1825 static int intel_860_configure(void)
1829 struct aper_size_info_8
*current_size
;
1831 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1834 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1836 /* address to map to */
1837 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1838 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1840 /* attbase - aperture base */
1841 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1844 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1847 pci_read_config_word(agp_bridge
->dev
, INTEL_I860_MCHCFG
, &temp2
);
1848 pci_write_config_word(agp_bridge
->dev
, INTEL_I860_MCHCFG
, temp2
| (1 << 9));
1849 /* clear any possible AGP-related error conditions */
1850 pci_write_config_word(agp_bridge
->dev
, INTEL_I860_ERRSTS
, 0xf700);
1854 static int intel_830mp_configure(void)
1858 struct aper_size_info_8
*current_size
;
1860 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1863 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1865 /* address to map to */
1866 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1867 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1869 /* attbase - aperture base */
1870 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1873 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1876 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp2
);
1877 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp2
| (1 << 9));
1878 /* clear any possible AGP-related error conditions */
1879 pci_write_config_word(agp_bridge
->dev
, INTEL_I830_ERRSTS
, 0x1c);
1883 static int intel_7505_configure(void)
1887 struct aper_size_info_8
*current_size
;
1889 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1892 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1894 /* address to map to */
1895 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1896 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1898 /* attbase - aperture base */
1899 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1902 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1905 pci_read_config_word(agp_bridge
->dev
, INTEL_I7505_MCHCFG
, &temp2
);
1906 pci_write_config_word(agp_bridge
->dev
, INTEL_I7505_MCHCFG
, temp2
| (1 << 9));
1911 /* Setup function */
1912 static const struct gatt_mask intel_generic_masks
[] =
1914 {.mask
= 0x00000017, .type
= 0}
1917 static const struct aper_size_info_8 intel_815_sizes
[2] =
1923 static const struct aper_size_info_8 intel_8xx_sizes
[7] =
1926 {128, 32768, 5, 32},
1934 static const struct aper_size_info_16 intel_generic_sizes
[7] =
1937 {128, 32768, 5, 32},
1945 static const struct aper_size_info_8 intel_830mp_sizes
[4] =
1948 {128, 32768, 5, 32},
1953 static const struct agp_bridge_driver intel_generic_driver
= {
1954 .owner
= THIS_MODULE
,
1955 .aperture_sizes
= intel_generic_sizes
,
1956 .size_type
= U16_APER_SIZE
,
1957 .num_aperture_sizes
= 7,
1958 .configure
= intel_configure
,
1959 .fetch_size
= intel_fetch_size
,
1960 .cleanup
= intel_cleanup
,
1961 .tlb_flush
= intel_tlbflush
,
1962 .mask_memory
= agp_generic_mask_memory
,
1963 .masks
= intel_generic_masks
,
1964 .agp_enable
= agp_generic_enable
,
1965 .cache_flush
= global_cache_flush
,
1966 .create_gatt_table
= agp_generic_create_gatt_table
,
1967 .free_gatt_table
= agp_generic_free_gatt_table
,
1968 .insert_memory
= agp_generic_insert_memory
,
1969 .remove_memory
= agp_generic_remove_memory
,
1970 .alloc_by_type
= agp_generic_alloc_by_type
,
1971 .free_by_type
= agp_generic_free_by_type
,
1972 .agp_alloc_page
= agp_generic_alloc_page
,
1973 .agp_alloc_pages
= agp_generic_alloc_pages
,
1974 .agp_destroy_page
= agp_generic_destroy_page
,
1975 .agp_destroy_pages
= agp_generic_destroy_pages
,
1976 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1979 static const struct agp_bridge_driver intel_810_driver
= {
1980 .owner
= THIS_MODULE
,
1981 .aperture_sizes
= intel_i810_sizes
,
1982 .size_type
= FIXED_APER_SIZE
,
1983 .num_aperture_sizes
= 2,
1984 .needs_scratch_page
= true,
1985 .configure
= intel_i810_configure
,
1986 .fetch_size
= intel_i810_fetch_size
,
1987 .cleanup
= intel_i810_cleanup
,
1988 .tlb_flush
= intel_i810_tlbflush
,
1989 .mask_memory
= intel_i810_mask_memory
,
1990 .masks
= intel_i810_masks
,
1991 .agp_enable
= intel_i810_agp_enable
,
1992 .cache_flush
= global_cache_flush
,
1993 .create_gatt_table
= agp_generic_create_gatt_table
,
1994 .free_gatt_table
= agp_generic_free_gatt_table
,
1995 .insert_memory
= intel_i810_insert_entries
,
1996 .remove_memory
= intel_i810_remove_entries
,
1997 .alloc_by_type
= intel_i810_alloc_by_type
,
1998 .free_by_type
= intel_i810_free_by_type
,
1999 .agp_alloc_page
= agp_generic_alloc_page
,
2000 .agp_alloc_pages
= agp_generic_alloc_pages
,
2001 .agp_destroy_page
= agp_generic_destroy_page
,
2002 .agp_destroy_pages
= agp_generic_destroy_pages
,
2003 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2006 static const struct agp_bridge_driver intel_815_driver
= {
2007 .owner
= THIS_MODULE
,
2008 .aperture_sizes
= intel_815_sizes
,
2009 .size_type
= U8_APER_SIZE
,
2010 .num_aperture_sizes
= 2,
2011 .configure
= intel_815_configure
,
2012 .fetch_size
= intel_815_fetch_size
,
2013 .cleanup
= intel_8xx_cleanup
,
2014 .tlb_flush
= intel_8xx_tlbflush
,
2015 .mask_memory
= agp_generic_mask_memory
,
2016 .masks
= intel_generic_masks
,
2017 .agp_enable
= agp_generic_enable
,
2018 .cache_flush
= global_cache_flush
,
2019 .create_gatt_table
= agp_generic_create_gatt_table
,
2020 .free_gatt_table
= agp_generic_free_gatt_table
,
2021 .insert_memory
= agp_generic_insert_memory
,
2022 .remove_memory
= agp_generic_remove_memory
,
2023 .alloc_by_type
= agp_generic_alloc_by_type
,
2024 .free_by_type
= agp_generic_free_by_type
,
2025 .agp_alloc_page
= agp_generic_alloc_page
,
2026 .agp_alloc_pages
= agp_generic_alloc_pages
,
2027 .agp_destroy_page
= agp_generic_destroy_page
,
2028 .agp_destroy_pages
= agp_generic_destroy_pages
,
2029 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2032 static const struct agp_bridge_driver intel_830_driver
= {
2033 .owner
= THIS_MODULE
,
2034 .aperture_sizes
= intel_i830_sizes
,
2035 .size_type
= FIXED_APER_SIZE
,
2036 .num_aperture_sizes
= 4,
2037 .needs_scratch_page
= true,
2038 .configure
= intel_i830_configure
,
2039 .fetch_size
= intel_i830_fetch_size
,
2040 .cleanup
= intel_i830_cleanup
,
2041 .tlb_flush
= intel_i810_tlbflush
,
2042 .mask_memory
= intel_i810_mask_memory
,
2043 .masks
= intel_i810_masks
,
2044 .agp_enable
= intel_i810_agp_enable
,
2045 .cache_flush
= global_cache_flush
,
2046 .create_gatt_table
= intel_i830_create_gatt_table
,
2047 .free_gatt_table
= intel_i830_free_gatt_table
,
2048 .insert_memory
= intel_i830_insert_entries
,
2049 .remove_memory
= intel_i830_remove_entries
,
2050 .alloc_by_type
= intel_i830_alloc_by_type
,
2051 .free_by_type
= intel_i810_free_by_type
,
2052 .agp_alloc_page
= agp_generic_alloc_page
,
2053 .agp_alloc_pages
= agp_generic_alloc_pages
,
2054 .agp_destroy_page
= agp_generic_destroy_page
,
2055 .agp_destroy_pages
= agp_generic_destroy_pages
,
2056 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2057 .chipset_flush
= intel_i830_chipset_flush
,
2060 static const struct agp_bridge_driver intel_820_driver
= {
2061 .owner
= THIS_MODULE
,
2062 .aperture_sizes
= intel_8xx_sizes
,
2063 .size_type
= U8_APER_SIZE
,
2064 .num_aperture_sizes
= 7,
2065 .configure
= intel_820_configure
,
2066 .fetch_size
= intel_8xx_fetch_size
,
2067 .cleanup
= intel_820_cleanup
,
2068 .tlb_flush
= intel_820_tlbflush
,
2069 .mask_memory
= agp_generic_mask_memory
,
2070 .masks
= intel_generic_masks
,
2071 .agp_enable
= agp_generic_enable
,
2072 .cache_flush
= global_cache_flush
,
2073 .create_gatt_table
= agp_generic_create_gatt_table
,
2074 .free_gatt_table
= agp_generic_free_gatt_table
,
2075 .insert_memory
= agp_generic_insert_memory
,
2076 .remove_memory
= agp_generic_remove_memory
,
2077 .alloc_by_type
= agp_generic_alloc_by_type
,
2078 .free_by_type
= agp_generic_free_by_type
,
2079 .agp_alloc_page
= agp_generic_alloc_page
,
2080 .agp_alloc_pages
= agp_generic_alloc_pages
,
2081 .agp_destroy_page
= agp_generic_destroy_page
,
2082 .agp_destroy_pages
= agp_generic_destroy_pages
,
2083 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2086 static const struct agp_bridge_driver intel_830mp_driver
= {
2087 .owner
= THIS_MODULE
,
2088 .aperture_sizes
= intel_830mp_sizes
,
2089 .size_type
= U8_APER_SIZE
,
2090 .num_aperture_sizes
= 4,
2091 .configure
= intel_830mp_configure
,
2092 .fetch_size
= intel_8xx_fetch_size
,
2093 .cleanup
= intel_8xx_cleanup
,
2094 .tlb_flush
= intel_8xx_tlbflush
,
2095 .mask_memory
= agp_generic_mask_memory
,
2096 .masks
= intel_generic_masks
,
2097 .agp_enable
= agp_generic_enable
,
2098 .cache_flush
= global_cache_flush
,
2099 .create_gatt_table
= agp_generic_create_gatt_table
,
2100 .free_gatt_table
= agp_generic_free_gatt_table
,
2101 .insert_memory
= agp_generic_insert_memory
,
2102 .remove_memory
= agp_generic_remove_memory
,
2103 .alloc_by_type
= agp_generic_alloc_by_type
,
2104 .free_by_type
= agp_generic_free_by_type
,
2105 .agp_alloc_page
= agp_generic_alloc_page
,
2106 .agp_alloc_pages
= agp_generic_alloc_pages
,
2107 .agp_destroy_page
= agp_generic_destroy_page
,
2108 .agp_destroy_pages
= agp_generic_destroy_pages
,
2109 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2112 static const struct agp_bridge_driver intel_840_driver
= {
2113 .owner
= THIS_MODULE
,
2114 .aperture_sizes
= intel_8xx_sizes
,
2115 .size_type
= U8_APER_SIZE
,
2116 .num_aperture_sizes
= 7,
2117 .configure
= intel_840_configure
,
2118 .fetch_size
= intel_8xx_fetch_size
,
2119 .cleanup
= intel_8xx_cleanup
,
2120 .tlb_flush
= intel_8xx_tlbflush
,
2121 .mask_memory
= agp_generic_mask_memory
,
2122 .masks
= intel_generic_masks
,
2123 .agp_enable
= agp_generic_enable
,
2124 .cache_flush
= global_cache_flush
,
2125 .create_gatt_table
= agp_generic_create_gatt_table
,
2126 .free_gatt_table
= agp_generic_free_gatt_table
,
2127 .insert_memory
= agp_generic_insert_memory
,
2128 .remove_memory
= agp_generic_remove_memory
,
2129 .alloc_by_type
= agp_generic_alloc_by_type
,
2130 .free_by_type
= agp_generic_free_by_type
,
2131 .agp_alloc_page
= agp_generic_alloc_page
,
2132 .agp_alloc_pages
= agp_generic_alloc_pages
,
2133 .agp_destroy_page
= agp_generic_destroy_page
,
2134 .agp_destroy_pages
= agp_generic_destroy_pages
,
2135 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2138 static const struct agp_bridge_driver intel_845_driver
= {
2139 .owner
= THIS_MODULE
,
2140 .aperture_sizes
= intel_8xx_sizes
,
2141 .size_type
= U8_APER_SIZE
,
2142 .num_aperture_sizes
= 7,
2143 .configure
= intel_845_configure
,
2144 .fetch_size
= intel_8xx_fetch_size
,
2145 .cleanup
= intel_8xx_cleanup
,
2146 .tlb_flush
= intel_8xx_tlbflush
,
2147 .mask_memory
= agp_generic_mask_memory
,
2148 .masks
= intel_generic_masks
,
2149 .agp_enable
= agp_generic_enable
,
2150 .cache_flush
= global_cache_flush
,
2151 .create_gatt_table
= agp_generic_create_gatt_table
,
2152 .free_gatt_table
= agp_generic_free_gatt_table
,
2153 .insert_memory
= agp_generic_insert_memory
,
2154 .remove_memory
= agp_generic_remove_memory
,
2155 .alloc_by_type
= agp_generic_alloc_by_type
,
2156 .free_by_type
= agp_generic_free_by_type
,
2157 .agp_alloc_page
= agp_generic_alloc_page
,
2158 .agp_alloc_pages
= agp_generic_alloc_pages
,
2159 .agp_destroy_page
= agp_generic_destroy_page
,
2160 .agp_destroy_pages
= agp_generic_destroy_pages
,
2161 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2162 .chipset_flush
= intel_i830_chipset_flush
,
2165 static const struct agp_bridge_driver intel_850_driver
= {
2166 .owner
= THIS_MODULE
,
2167 .aperture_sizes
= intel_8xx_sizes
,
2168 .size_type
= U8_APER_SIZE
,
2169 .num_aperture_sizes
= 7,
2170 .configure
= intel_850_configure
,
2171 .fetch_size
= intel_8xx_fetch_size
,
2172 .cleanup
= intel_8xx_cleanup
,
2173 .tlb_flush
= intel_8xx_tlbflush
,
2174 .mask_memory
= agp_generic_mask_memory
,
2175 .masks
= intel_generic_masks
,
2176 .agp_enable
= agp_generic_enable
,
2177 .cache_flush
= global_cache_flush
,
2178 .create_gatt_table
= agp_generic_create_gatt_table
,
2179 .free_gatt_table
= agp_generic_free_gatt_table
,
2180 .insert_memory
= agp_generic_insert_memory
,
2181 .remove_memory
= agp_generic_remove_memory
,
2182 .alloc_by_type
= agp_generic_alloc_by_type
,
2183 .free_by_type
= agp_generic_free_by_type
,
2184 .agp_alloc_page
= agp_generic_alloc_page
,
2185 .agp_alloc_pages
= agp_generic_alloc_pages
,
2186 .agp_destroy_page
= agp_generic_destroy_page
,
2187 .agp_destroy_pages
= agp_generic_destroy_pages
,
2188 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2191 static const struct agp_bridge_driver intel_860_driver
= {
2192 .owner
= THIS_MODULE
,
2193 .aperture_sizes
= intel_8xx_sizes
,
2194 .size_type
= U8_APER_SIZE
,
2195 .num_aperture_sizes
= 7,
2196 .configure
= intel_860_configure
,
2197 .fetch_size
= intel_8xx_fetch_size
,
2198 .cleanup
= intel_8xx_cleanup
,
2199 .tlb_flush
= intel_8xx_tlbflush
,
2200 .mask_memory
= agp_generic_mask_memory
,
2201 .masks
= intel_generic_masks
,
2202 .agp_enable
= agp_generic_enable
,
2203 .cache_flush
= global_cache_flush
,
2204 .create_gatt_table
= agp_generic_create_gatt_table
,
2205 .free_gatt_table
= agp_generic_free_gatt_table
,
2206 .insert_memory
= agp_generic_insert_memory
,
2207 .remove_memory
= agp_generic_remove_memory
,
2208 .alloc_by_type
= agp_generic_alloc_by_type
,
2209 .free_by_type
= agp_generic_free_by_type
,
2210 .agp_alloc_page
= agp_generic_alloc_page
,
2211 .agp_alloc_pages
= agp_generic_alloc_pages
,
2212 .agp_destroy_page
= agp_generic_destroy_page
,
2213 .agp_destroy_pages
= agp_generic_destroy_pages
,
2214 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2217 static const struct agp_bridge_driver intel_915_driver
= {
2218 .owner
= THIS_MODULE
,
2219 .aperture_sizes
= intel_i830_sizes
,
2220 .size_type
= FIXED_APER_SIZE
,
2221 .num_aperture_sizes
= 4,
2222 .needs_scratch_page
= true,
2223 .configure
= intel_i915_configure
,
2224 .fetch_size
= intel_i9xx_fetch_size
,
2225 .cleanup
= intel_i915_cleanup
,
2226 .tlb_flush
= intel_i810_tlbflush
,
2227 .mask_memory
= intel_i810_mask_memory
,
2228 .masks
= intel_i810_masks
,
2229 .agp_enable
= intel_i810_agp_enable
,
2230 .cache_flush
= global_cache_flush
,
2231 .create_gatt_table
= intel_i915_create_gatt_table
,
2232 .free_gatt_table
= intel_i830_free_gatt_table
,
2233 .insert_memory
= intel_i915_insert_entries
,
2234 .remove_memory
= intel_i915_remove_entries
,
2235 .alloc_by_type
= intel_i830_alloc_by_type
,
2236 .free_by_type
= intel_i810_free_by_type
,
2237 .agp_alloc_page
= agp_generic_alloc_page
,
2238 .agp_alloc_pages
= agp_generic_alloc_pages
,
2239 .agp_destroy_page
= agp_generic_destroy_page
,
2240 .agp_destroy_pages
= agp_generic_destroy_pages
,
2241 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2242 .chipset_flush
= intel_i915_chipset_flush
,
2243 #ifdef USE_PCI_DMA_API
2244 .agp_map_page
= intel_agp_map_page
,
2245 .agp_unmap_page
= intel_agp_unmap_page
,
2246 .agp_map_memory
= intel_agp_map_memory
,
2247 .agp_unmap_memory
= intel_agp_unmap_memory
,
2251 static const struct agp_bridge_driver intel_i965_driver
= {
2252 .owner
= THIS_MODULE
,
2253 .aperture_sizes
= intel_i830_sizes
,
2254 .size_type
= FIXED_APER_SIZE
,
2255 .num_aperture_sizes
= 4,
2256 .needs_scratch_page
= true,
2257 .configure
= intel_i915_configure
,
2258 .fetch_size
= intel_i9xx_fetch_size
,
2259 .cleanup
= intel_i915_cleanup
,
2260 .tlb_flush
= intel_i810_tlbflush
,
2261 .mask_memory
= intel_i965_mask_memory
,
2262 .masks
= intel_i810_masks
,
2263 .agp_enable
= intel_i810_agp_enable
,
2264 .cache_flush
= global_cache_flush
,
2265 .create_gatt_table
= intel_i965_create_gatt_table
,
2266 .free_gatt_table
= intel_i830_free_gatt_table
,
2267 .insert_memory
= intel_i915_insert_entries
,
2268 .remove_memory
= intel_i915_remove_entries
,
2269 .alloc_by_type
= intel_i830_alloc_by_type
,
2270 .free_by_type
= intel_i810_free_by_type
,
2271 .agp_alloc_page
= agp_generic_alloc_page
,
2272 .agp_alloc_pages
= agp_generic_alloc_pages
,
2273 .agp_destroy_page
= agp_generic_destroy_page
,
2274 .agp_destroy_pages
= agp_generic_destroy_pages
,
2275 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2276 .chipset_flush
= intel_i915_chipset_flush
,
2277 #ifdef USE_PCI_DMA_API
2278 .agp_map_page
= intel_agp_map_page
,
2279 .agp_unmap_page
= intel_agp_unmap_page
,
2280 .agp_map_memory
= intel_agp_map_memory
,
2281 .agp_unmap_memory
= intel_agp_unmap_memory
,
2285 static const struct agp_bridge_driver intel_7505_driver
= {
2286 .owner
= THIS_MODULE
,
2287 .aperture_sizes
= intel_8xx_sizes
,
2288 .size_type
= U8_APER_SIZE
,
2289 .num_aperture_sizes
= 7,
2290 .configure
= intel_7505_configure
,
2291 .fetch_size
= intel_8xx_fetch_size
,
2292 .cleanup
= intel_8xx_cleanup
,
2293 .tlb_flush
= intel_8xx_tlbflush
,
2294 .mask_memory
= agp_generic_mask_memory
,
2295 .masks
= intel_generic_masks
,
2296 .agp_enable
= agp_generic_enable
,
2297 .cache_flush
= global_cache_flush
,
2298 .create_gatt_table
= agp_generic_create_gatt_table
,
2299 .free_gatt_table
= agp_generic_free_gatt_table
,
2300 .insert_memory
= agp_generic_insert_memory
,
2301 .remove_memory
= agp_generic_remove_memory
,
2302 .alloc_by_type
= agp_generic_alloc_by_type
,
2303 .free_by_type
= agp_generic_free_by_type
,
2304 .agp_alloc_page
= agp_generic_alloc_page
,
2305 .agp_alloc_pages
= agp_generic_alloc_pages
,
2306 .agp_destroy_page
= agp_generic_destroy_page
,
2307 .agp_destroy_pages
= agp_generic_destroy_pages
,
2308 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2311 static const struct agp_bridge_driver intel_g33_driver
= {
2312 .owner
= THIS_MODULE
,
2313 .aperture_sizes
= intel_i830_sizes
,
2314 .size_type
= FIXED_APER_SIZE
,
2315 .num_aperture_sizes
= 4,
2316 .needs_scratch_page
= true,
2317 .configure
= intel_i915_configure
,
2318 .fetch_size
= intel_i9xx_fetch_size
,
2319 .cleanup
= intel_i915_cleanup
,
2320 .tlb_flush
= intel_i810_tlbflush
,
2321 .mask_memory
= intel_i965_mask_memory
,
2322 .masks
= intel_i810_masks
,
2323 .agp_enable
= intel_i810_agp_enable
,
2324 .cache_flush
= global_cache_flush
,
2325 .create_gatt_table
= intel_i915_create_gatt_table
,
2326 .free_gatt_table
= intel_i830_free_gatt_table
,
2327 .insert_memory
= intel_i915_insert_entries
,
2328 .remove_memory
= intel_i915_remove_entries
,
2329 .alloc_by_type
= intel_i830_alloc_by_type
,
2330 .free_by_type
= intel_i810_free_by_type
,
2331 .agp_alloc_page
= agp_generic_alloc_page
,
2332 .agp_alloc_pages
= agp_generic_alloc_pages
,
2333 .agp_destroy_page
= agp_generic_destroy_page
,
2334 .agp_destroy_pages
= agp_generic_destroy_pages
,
2335 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2336 .chipset_flush
= intel_i915_chipset_flush
,
2337 #ifdef USE_PCI_DMA_API
2338 .agp_map_page
= intel_agp_map_page
,
2339 .agp_unmap_page
= intel_agp_unmap_page
,
2340 .agp_map_memory
= intel_agp_map_memory
,
2341 .agp_unmap_memory
= intel_agp_unmap_memory
,
2345 static int find_gmch(u16 device
)
2347 struct pci_dev
*gmch_device
;
2349 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
2350 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
2351 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
2352 device
, gmch_device
);
2358 intel_private
.pcidev
= gmch_device
;
2362 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2363 * driver and gmch_driver must be non-null, and find_gmch will determine
2364 * which one should be used if a gmch_chip_id is present.
2366 static const struct intel_driver_description
{
2367 unsigned int chip_id
;
2368 unsigned int gmch_chip_id
;
2369 unsigned int multi_gmch_chip
; /* if we have more gfx chip type on this HB. */
2371 const struct agp_bridge_driver
*driver
;
2372 const struct agp_bridge_driver
*gmch_driver
;
2373 } intel_agp_chipsets
[] = {
2374 { PCI_DEVICE_ID_INTEL_82443LX_0
, 0, 0, "440LX", &intel_generic_driver
, NULL
},
2375 { PCI_DEVICE_ID_INTEL_82443BX_0
, 0, 0, "440BX", &intel_generic_driver
, NULL
},
2376 { PCI_DEVICE_ID_INTEL_82443GX_0
, 0, 0, "440GX", &intel_generic_driver
, NULL
},
2377 { PCI_DEVICE_ID_INTEL_82810_MC1
, PCI_DEVICE_ID_INTEL_82810_IG1
, 0, "i810",
2378 NULL
, &intel_810_driver
},
2379 { PCI_DEVICE_ID_INTEL_82810_MC3
, PCI_DEVICE_ID_INTEL_82810_IG3
, 0, "i810",
2380 NULL
, &intel_810_driver
},
2381 { PCI_DEVICE_ID_INTEL_82810E_MC
, PCI_DEVICE_ID_INTEL_82810E_IG
, 0, "i810",
2382 NULL
, &intel_810_driver
},
2383 { PCI_DEVICE_ID_INTEL_82815_MC
, PCI_DEVICE_ID_INTEL_82815_CGC
, 0, "i815",
2384 &intel_815_driver
, &intel_810_driver
},
2385 { PCI_DEVICE_ID_INTEL_82820_HB
, 0, 0, "i820", &intel_820_driver
, NULL
},
2386 { PCI_DEVICE_ID_INTEL_82820_UP_HB
, 0, 0, "i820", &intel_820_driver
, NULL
},
2387 { PCI_DEVICE_ID_INTEL_82830_HB
, PCI_DEVICE_ID_INTEL_82830_CGC
, 0, "830M",
2388 &intel_830mp_driver
, &intel_830_driver
},
2389 { PCI_DEVICE_ID_INTEL_82840_HB
, 0, 0, "i840", &intel_840_driver
, NULL
},
2390 { PCI_DEVICE_ID_INTEL_82845_HB
, 0, 0, "845G", &intel_845_driver
, NULL
},
2391 { PCI_DEVICE_ID_INTEL_82845G_HB
, PCI_DEVICE_ID_INTEL_82845G_IG
, 0, "830M",
2392 &intel_845_driver
, &intel_830_driver
},
2393 { PCI_DEVICE_ID_INTEL_82850_HB
, 0, 0, "i850", &intel_850_driver
, NULL
},
2394 { PCI_DEVICE_ID_INTEL_82854_HB
, PCI_DEVICE_ID_INTEL_82854_IG
, 0, "854",
2395 &intel_845_driver
, &intel_830_driver
},
2396 { PCI_DEVICE_ID_INTEL_82855PM_HB
, 0, 0, "855PM", &intel_845_driver
, NULL
},
2397 { PCI_DEVICE_ID_INTEL_82855GM_HB
, PCI_DEVICE_ID_INTEL_82855GM_IG
, 0, "855GM",
2398 &intel_845_driver
, &intel_830_driver
},
2399 { PCI_DEVICE_ID_INTEL_82860_HB
, 0, 0, "i860", &intel_860_driver
, NULL
},
2400 { PCI_DEVICE_ID_INTEL_82865_HB
, PCI_DEVICE_ID_INTEL_82865_IG
, 0, "865",
2401 &intel_845_driver
, &intel_830_driver
},
2402 { PCI_DEVICE_ID_INTEL_82875_HB
, 0, 0, "i875", &intel_845_driver
, NULL
},
2403 { PCI_DEVICE_ID_INTEL_E7221_HB
, PCI_DEVICE_ID_INTEL_E7221_IG
, 0, "E7221 (i915)",
2404 NULL
, &intel_915_driver
},
2405 { PCI_DEVICE_ID_INTEL_82915G_HB
, PCI_DEVICE_ID_INTEL_82915G_IG
, 0, "915G",
2406 NULL
, &intel_915_driver
},
2407 { PCI_DEVICE_ID_INTEL_82915GM_HB
, PCI_DEVICE_ID_INTEL_82915GM_IG
, 0, "915GM",
2408 NULL
, &intel_915_driver
},
2409 { PCI_DEVICE_ID_INTEL_82945G_HB
, PCI_DEVICE_ID_INTEL_82945G_IG
, 0, "945G",
2410 NULL
, &intel_915_driver
},
2411 { PCI_DEVICE_ID_INTEL_82945GM_HB
, PCI_DEVICE_ID_INTEL_82945GM_IG
, 0, "945GM",
2412 NULL
, &intel_915_driver
},
2413 { PCI_DEVICE_ID_INTEL_82945GME_HB
, PCI_DEVICE_ID_INTEL_82945GME_IG
, 0, "945GME",
2414 NULL
, &intel_915_driver
},
2415 { PCI_DEVICE_ID_INTEL_82946GZ_HB
, PCI_DEVICE_ID_INTEL_82946GZ_IG
, 0, "946GZ",
2416 NULL
, &intel_i965_driver
},
2417 { PCI_DEVICE_ID_INTEL_82G35_HB
, PCI_DEVICE_ID_INTEL_82G35_IG
, 0, "G35",
2418 NULL
, &intel_i965_driver
},
2419 { PCI_DEVICE_ID_INTEL_82965Q_HB
, PCI_DEVICE_ID_INTEL_82965Q_IG
, 0, "965Q",
2420 NULL
, &intel_i965_driver
},
2421 { PCI_DEVICE_ID_INTEL_82965G_HB
, PCI_DEVICE_ID_INTEL_82965G_IG
, 0, "965G",
2422 NULL
, &intel_i965_driver
},
2423 { PCI_DEVICE_ID_INTEL_82965GM_HB
, PCI_DEVICE_ID_INTEL_82965GM_IG
, 0, "965GM",
2424 NULL
, &intel_i965_driver
},
2425 { PCI_DEVICE_ID_INTEL_82965GME_HB
, PCI_DEVICE_ID_INTEL_82965GME_IG
, 0, "965GME/GLE",
2426 NULL
, &intel_i965_driver
},
2427 { PCI_DEVICE_ID_INTEL_7505_0
, 0, 0, "E7505", &intel_7505_driver
, NULL
},
2428 { PCI_DEVICE_ID_INTEL_7205_0
, 0, 0, "E7205", &intel_7505_driver
, NULL
},
2429 { PCI_DEVICE_ID_INTEL_G33_HB
, PCI_DEVICE_ID_INTEL_G33_IG
, 0, "G33",
2430 NULL
, &intel_g33_driver
},
2431 { PCI_DEVICE_ID_INTEL_Q35_HB
, PCI_DEVICE_ID_INTEL_Q35_IG
, 0, "Q35",
2432 NULL
, &intel_g33_driver
},
2433 { PCI_DEVICE_ID_INTEL_Q33_HB
, PCI_DEVICE_ID_INTEL_Q33_IG
, 0, "Q33",
2434 NULL
, &intel_g33_driver
},
2435 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB
, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, 0, "GMA3150",
2436 NULL
, &intel_g33_driver
},
2437 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB
, PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, 0, "GMA3150",
2438 NULL
, &intel_g33_driver
},
2439 { PCI_DEVICE_ID_INTEL_GM45_HB
, PCI_DEVICE_ID_INTEL_GM45_IG
, 0,
2440 "GM45", NULL
, &intel_i965_driver
},
2441 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, 0,
2442 "Eaglelake", NULL
, &intel_i965_driver
},
2443 { PCI_DEVICE_ID_INTEL_Q45_HB
, PCI_DEVICE_ID_INTEL_Q45_IG
, 0,
2444 "Q45/Q43", NULL
, &intel_i965_driver
},
2445 { PCI_DEVICE_ID_INTEL_G45_HB
, PCI_DEVICE_ID_INTEL_G45_IG
, 0,
2446 "G45/G43", NULL
, &intel_i965_driver
},
2447 { PCI_DEVICE_ID_INTEL_B43_HB
, PCI_DEVICE_ID_INTEL_B43_IG
, 0,
2448 "B43", NULL
, &intel_i965_driver
},
2449 { PCI_DEVICE_ID_INTEL_G41_HB
, PCI_DEVICE_ID_INTEL_G41_IG
, 0,
2450 "G41", NULL
, &intel_i965_driver
},
2451 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
, 0,
2452 "HD Graphics", NULL
, &intel_i965_driver
},
2453 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
, 0,
2454 "HD Graphics", NULL
, &intel_i965_driver
},
2455 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
, 0,
2456 "HD Graphics", NULL
, &intel_i965_driver
},
2457 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
, 0,
2458 "HD Graphics", NULL
, &intel_i965_driver
},
2459 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG
, 0,
2460 "Sandybridge", NULL
, &intel_i965_driver
},
2461 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG
, 0,
2462 "Sandybridge", NULL
, &intel_i965_driver
},
2463 { 0, 0, 0, NULL
, NULL
, NULL
}
2466 static int __devinit
agp_intel_probe(struct pci_dev
*pdev
,
2467 const struct pci_device_id
*ent
)
2469 struct agp_bridge_data
*bridge
;
2474 cap_ptr
= pci_find_capability(pdev
, PCI_CAP_ID_AGP
);
2476 bridge
= agp_alloc_bridge();
2480 for (i
= 0; intel_agp_chipsets
[i
].name
!= NULL
; i
++) {
2481 /* In case that multiple models of gfx chip may
2482 stand on same host bridge type, this can be
2483 sure we detect the right IGD. */
2484 if (pdev
->device
== intel_agp_chipsets
[i
].chip_id
) {
2485 if ((intel_agp_chipsets
[i
].gmch_chip_id
!= 0) &&
2486 find_gmch(intel_agp_chipsets
[i
].gmch_chip_id
)) {
2488 intel_agp_chipsets
[i
].gmch_driver
;
2490 } else if (intel_agp_chipsets
[i
].multi_gmch_chip
) {
2493 bridge
->driver
= intel_agp_chipsets
[i
].driver
;
2499 if (intel_agp_chipsets
[i
].name
== NULL
) {
2501 dev_warn(&pdev
->dev
, "unsupported Intel chipset [%04x/%04x]\n",
2502 pdev
->vendor
, pdev
->device
);
2503 agp_put_bridge(bridge
);
2507 if (bridge
->driver
== NULL
) {
2508 /* bridge has no AGP and no IGD detected */
2510 dev_warn(&pdev
->dev
, "can't find bridge device (chip_id: %04x)\n",
2511 intel_agp_chipsets
[i
].gmch_chip_id
);
2512 agp_put_bridge(bridge
);
2517 bridge
->capndx
= cap_ptr
;
2518 bridge
->dev_private_data
= &intel_private
;
2520 dev_info(&pdev
->dev
, "Intel %s Chipset\n", intel_agp_chipsets
[i
].name
);
2523 * The following fixes the case where the BIOS has "forgotten" to
2524 * provide an address range for the GART.
2525 * 20030610 - hamish@zot.org
2527 r
= &pdev
->resource
[0];
2528 if (!r
->start
&& r
->end
) {
2529 if (pci_assign_resource(pdev
, 0)) {
2530 dev_err(&pdev
->dev
, "can't assign resource 0\n");
2531 agp_put_bridge(bridge
);
2537 * If the device has not been properly setup, the following will catch
2538 * the problem and should stop the system from crashing.
2539 * 20030610 - hamish@zot.org
2541 if (pci_enable_device(pdev
)) {
2542 dev_err(&pdev
->dev
, "can't enable PCI device\n");
2543 agp_put_bridge(bridge
);
2547 /* Fill in the mode register */
2549 pci_read_config_dword(pdev
,
2550 bridge
->capndx
+PCI_AGP_STATUS
,
2554 if (bridge
->driver
->mask_memory
== intel_i965_mask_memory
) {
2555 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(36)))
2556 dev_err(&intel_private
.pcidev
->dev
,
2557 "set gfx device dma mask 36bit failed!\n");
2559 pci_set_consistent_dma_mask(intel_private
.pcidev
,
2563 pci_set_drvdata(pdev
, bridge
);
2564 err
= agp_add_bridge(bridge
);
2566 intel_agp_enabled
= 1;
2570 static void __devexit
agp_intel_remove(struct pci_dev
*pdev
)
2572 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
2574 agp_remove_bridge(bridge
);
2576 if (intel_private
.pcidev
)
2577 pci_dev_put(intel_private
.pcidev
);
2579 agp_put_bridge(bridge
);
2583 static int agp_intel_resume(struct pci_dev
*pdev
)
2585 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
2588 if (bridge
->driver
== &intel_generic_driver
)
2590 else if (bridge
->driver
== &intel_850_driver
)
2591 intel_850_configure();
2592 else if (bridge
->driver
== &intel_845_driver
)
2593 intel_845_configure();
2594 else if (bridge
->driver
== &intel_830mp_driver
)
2595 intel_830mp_configure();
2596 else if (bridge
->driver
== &intel_915_driver
)
2597 intel_i915_configure();
2598 else if (bridge
->driver
== &intel_830_driver
)
2599 intel_i830_configure();
2600 else if (bridge
->driver
== &intel_810_driver
)
2601 intel_i810_configure();
2602 else if (bridge
->driver
== &intel_i965_driver
)
2603 intel_i915_configure();
2605 ret_val
= agp_rebind_memory();
2613 static struct pci_device_id agp_intel_pci_table
[] = {
2616 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2618 .vendor = PCI_VENDOR_ID_INTEL, \
2620 .subvendor = PCI_ANY_ID, \
2621 .subdevice = PCI_ANY_ID, \
2623 ID(PCI_DEVICE_ID_INTEL_82443LX_0
),
2624 ID(PCI_DEVICE_ID_INTEL_82443BX_0
),
2625 ID(PCI_DEVICE_ID_INTEL_82443GX_0
),
2626 ID(PCI_DEVICE_ID_INTEL_82810_MC1
),
2627 ID(PCI_DEVICE_ID_INTEL_82810_MC3
),
2628 ID(PCI_DEVICE_ID_INTEL_82810E_MC
),
2629 ID(PCI_DEVICE_ID_INTEL_82815_MC
),
2630 ID(PCI_DEVICE_ID_INTEL_82820_HB
),
2631 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB
),
2632 ID(PCI_DEVICE_ID_INTEL_82830_HB
),
2633 ID(PCI_DEVICE_ID_INTEL_82840_HB
),
2634 ID(PCI_DEVICE_ID_INTEL_82845_HB
),
2635 ID(PCI_DEVICE_ID_INTEL_82845G_HB
),
2636 ID(PCI_DEVICE_ID_INTEL_82850_HB
),
2637 ID(PCI_DEVICE_ID_INTEL_82854_HB
),
2638 ID(PCI_DEVICE_ID_INTEL_82855PM_HB
),
2639 ID(PCI_DEVICE_ID_INTEL_82855GM_HB
),
2640 ID(PCI_DEVICE_ID_INTEL_82860_HB
),
2641 ID(PCI_DEVICE_ID_INTEL_82865_HB
),
2642 ID(PCI_DEVICE_ID_INTEL_82875_HB
),
2643 ID(PCI_DEVICE_ID_INTEL_7505_0
),
2644 ID(PCI_DEVICE_ID_INTEL_7205_0
),
2645 ID(PCI_DEVICE_ID_INTEL_E7221_HB
),
2646 ID(PCI_DEVICE_ID_INTEL_82915G_HB
),
2647 ID(PCI_DEVICE_ID_INTEL_82915GM_HB
),
2648 ID(PCI_DEVICE_ID_INTEL_82945G_HB
),
2649 ID(PCI_DEVICE_ID_INTEL_82945GM_HB
),
2650 ID(PCI_DEVICE_ID_INTEL_82945GME_HB
),
2651 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB
),
2652 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB
),
2653 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB
),
2654 ID(PCI_DEVICE_ID_INTEL_82G35_HB
),
2655 ID(PCI_DEVICE_ID_INTEL_82965Q_HB
),
2656 ID(PCI_DEVICE_ID_INTEL_82965G_HB
),
2657 ID(PCI_DEVICE_ID_INTEL_82965GM_HB
),
2658 ID(PCI_DEVICE_ID_INTEL_82965GME_HB
),
2659 ID(PCI_DEVICE_ID_INTEL_G33_HB
),
2660 ID(PCI_DEVICE_ID_INTEL_Q35_HB
),
2661 ID(PCI_DEVICE_ID_INTEL_Q33_HB
),
2662 ID(PCI_DEVICE_ID_INTEL_GM45_HB
),
2663 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
),
2664 ID(PCI_DEVICE_ID_INTEL_Q45_HB
),
2665 ID(PCI_DEVICE_ID_INTEL_G45_HB
),
2666 ID(PCI_DEVICE_ID_INTEL_G41_HB
),
2667 ID(PCI_DEVICE_ID_INTEL_B43_HB
),
2668 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
),
2669 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
),
2670 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
),
2671 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
),
2672 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
),
2673 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
),
2677 MODULE_DEVICE_TABLE(pci
, agp_intel_pci_table
);
2679 static struct pci_driver agp_intel_pci_driver
= {
2680 .name
= "agpgart-intel",
2681 .id_table
= agp_intel_pci_table
,
2682 .probe
= agp_intel_probe
,
2683 .remove
= __devexit_p(agp_intel_remove
),
2685 .resume
= agp_intel_resume
,
2689 static int __init
agp_intel_init(void)
2693 return pci_register_driver(&agp_intel_pci_driver
);
2696 static void __exit
agp_intel_cleanup(void)
2698 pci_unregister_driver(&agp_intel_pci_driver
);
2701 module_init(agp_intel_init
);
2702 module_exit(agp_intel_cleanup
);
2704 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2705 MODULE_LICENSE("GPL and additional rights");