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netxen: refactor firmware info code
[pohmelfs.git] / drivers / net / netxen / netxen_nic_hw.c
blob555bc4a7e8880228d5032805a094fe100992b19e
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33
34 #include <net/ip.h>
35
36 #define MASK(n) ((1ULL<<(n))-1)
37 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
38 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
39 #define MS_WIN(addr) (addr & 0x0ffc0000)
40
41 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
42
43 #define CRB_BLK(off) ((off >> 20) & 0x3f)
44 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
45 #define CRB_WINDOW_2M (0x130060)
46 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
47 #define CRB_INDIRECT_2M (0x1e0000UL)
48
49 #ifndef readq
50 static inline u64 readq(void __iomem *addr)
51 {
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
53 }
54 #endif
55
56 #ifndef writeq
57 static inline void writeq(u64 val, void __iomem *addr)
58 {
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
61 }
62 #endif
63
64 #define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
66
67 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
73
74 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
75 unsigned long off)
76 {
77 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
78 return PCI_OFFSET_FIRST_RANGE(adapter, off);
79
80 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
81 return PCI_OFFSET_SECOND_RANGE(adapter, off);
82
83 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
84 return PCI_OFFSET_THIRD_RANGE(adapter, off);
85
86 return NULL;
87 }
88
89 static crb_128M_2M_block_map_t
90 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
216 {{{0} } }, /* 35: */
217 {{{0} } }, /* 36: */
218 {{{0} } }, /* 37: */
219 {{{0} } }, /* 38: */
220 {{{0} } }, /* 39: */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
233 {{{0} } }, /* 52: */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
245 };
246
247 /*
248 * top 12 bits of crb internal address (hub, agent)
249 */
250 static unsigned crb_hub_agt[64] =
251 {
252 0,
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
287 0,
288 0,
289 0,
290 0,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
309 0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
313 0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
315 0,
316 };
317
318 /* PCI Windowing for DDR regions. */
319
320 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
321
322 #define NETXEN_PCIE_SEM_TIMEOUT 10000
323
324 int
325 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
326 {
327 int done = 0, timeout = 0;
328
329 while (!done) {
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
331 if (done == 1)
332 break;
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 return -1;
335 msleep(1);
336 }
337
338 if (id_reg)
339 NXWR32(adapter, id_reg, adapter->portnum);
340
341 return 0;
342 }
343
344 void
345 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
346 {
347 int val;
348 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
349 }
350
351 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
352 {
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
356 }
357
358 return 0;
359 }
360
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
363 {
364 __u32 mac_cfg;
365 u32 port = adapter->physical_port;
366
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
368 return 0;
369
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
371 return -EINVAL;
372
373 mac_cfg = 0;
374 if (NXWR32(adapter,
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
376 return -EIO;
377 return 0;
378 }
379
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
388
389 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
390 {
391 __u32 reg;
392 u32 port = adapter->physical_port;
393
394 if (port > NETXEN_NIU_MAX_XG_PORTS)
395 return -EINVAL;
396
397 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
398 if (mode == NETXEN_NIU_PROMISC_MODE)
399 reg = (reg | 0x2000UL);
400 else
401 reg = (reg & ~0x2000UL);
402
403 if (mode == NETXEN_NIU_ALLMULTI_MODE)
404 reg = (reg | 0x1000UL);
405 else
406 reg = (reg & ~0x1000UL);
407
408 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
409
410 return 0;
411 }
412
413 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
414 {
415 u32 mac_hi, mac_lo;
416 u32 reg_hi, reg_lo;
417
418 u8 phy = adapter->physical_port;
419
420 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
421 return -EINVAL;
422
423 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
424 mac_hi = addr[2] | ((u32)addr[3] << 8) |
425 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
426
427 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
428 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
429
430 /* write twice to flush */
431 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
432 return -EIO;
433 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
434 return -EIO;
435
436 return 0;
437 }
438
439 static int
440 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
441 {
442 u32 val = 0;
443 u16 port = adapter->physical_port;
444 u8 *addr = adapter->netdev->dev_addr;
445
446 if (adapter->mc_enabled)
447 return 0;
448
449 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
450 val |= (1UL << (28+port));
451 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
452
453 /* add broadcast addr to filter */
454 val = 0xffffff;
455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
456 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
457
458 /* add station addr to filter */
459 val = MAC_HI(addr);
460 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
461 val = MAC_LO(addr);
462 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
463
464 adapter->mc_enabled = 1;
465 return 0;
466 }
467
468 static int
469 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
470 {
471 u32 val = 0;
472 u16 port = adapter->physical_port;
473 u8 *addr = adapter->netdev->dev_addr;
474
475 if (!adapter->mc_enabled)
476 return 0;
477
478 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
479 val &= ~(1UL << (28+port));
480 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
481
482 val = MAC_HI(addr);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
484 val = MAC_LO(addr);
485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
486
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
489
490 adapter->mc_enabled = 0;
491 return 0;
492 }
493
494 static int
495 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
496 int index, u8 *addr)
497 {
498 u32 hi = 0, lo = 0;
499 u16 port = adapter->physical_port;
500
501 lo = MAC_LO(addr);
502 hi = MAC_HI(addr);
503
504 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
505 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
506
507 return 0;
508 }
509
510 void netxen_p2_nic_set_multi(struct net_device *netdev)
511 {
512 struct netxen_adapter *adapter = netdev_priv(netdev);
513 struct dev_mc_list *mc_ptr;
514 u8 null_addr[6];
515 int index = 0;
516
517 memset(null_addr, 0, 6);
518
519 if (netdev->flags & IFF_PROMISC) {
520
521 adapter->set_promisc(adapter,
522 NETXEN_NIU_PROMISC_MODE);
523
524 /* Full promiscuous mode */
525 netxen_nic_disable_mcast_filter(adapter);
526
527 return;
528 }
529
530 if (netdev->mc_count == 0) {
531 adapter->set_promisc(adapter,
532 NETXEN_NIU_NON_PROMISC_MODE);
533 netxen_nic_disable_mcast_filter(adapter);
534 return;
535 }
536
537 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
538 if (netdev->flags & IFF_ALLMULTI ||
539 netdev->mc_count > adapter->max_mc_count) {
540 netxen_nic_disable_mcast_filter(adapter);
541 return;
542 }
543
544 netxen_nic_enable_mcast_filter(adapter);
545
546 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
547 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
548
549 if (index != netdev->mc_count)
550 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
551 netxen_nic_driver_name, netdev->name);
552
553 /* Clear out remaining addresses */
554 for (; index < adapter->max_mc_count; index++)
555 netxen_nic_set_mcast_addr(adapter, index, null_addr);
556 }
557
558 static int
559 netxen_send_cmd_descs(struct netxen_adapter *adapter,
560 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
561 {
562 u32 i, producer, consumer;
563 struct netxen_cmd_buffer *pbuf;
564 struct cmd_desc_type0 *cmd_desc;
565 struct nx_host_tx_ring *tx_ring;
566
567 i = 0;
568
569 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
570 return -EIO;
571
572 tx_ring = adapter->tx_ring;
573 __netif_tx_lock_bh(tx_ring->txq);
574
575 producer = tx_ring->producer;
576 consumer = tx_ring->sw_consumer;
577
578 if (nr_desc >= netxen_tx_avail(tx_ring)) {
579 netif_tx_stop_queue(tx_ring->txq);
580 __netif_tx_unlock_bh(tx_ring->txq);
581 return -EBUSY;
582 }
583
584 do {
585 cmd_desc = &cmd_desc_arr[i];
586
587 pbuf = &tx_ring->cmd_buf_arr[producer];
588 pbuf->skb = NULL;
589 pbuf->frag_count = 0;
590
591 memcpy(&tx_ring->desc_head[producer],
592 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
593
594 producer = get_next_index(producer, tx_ring->num_desc);
595 i++;
596
597 } while (i != nr_desc);
598
599 tx_ring->producer = producer;
600
601 netxen_nic_update_cmd_producer(adapter, tx_ring);
602
603 __netif_tx_unlock_bh(tx_ring->txq);
604
605 return 0;
606 }
607
608 static int
609 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
610 {
611 nx_nic_req_t req;
612 nx_mac_req_t *mac_req;
613 u64 word;
614
615 memset(&req, 0, sizeof(nx_nic_req_t));
616 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
617
618 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
619 req.req_hdr = cpu_to_le64(word);
620
621 mac_req = (nx_mac_req_t *)&req.words[0];
622 mac_req->op = op;
623 memcpy(mac_req->mac_addr, addr, 6);
624
625 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
626 }
627
628 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
629 u8 *addr, struct list_head *del_list)
630 {
631 struct list_head *head;
632 nx_mac_list_t *cur;
633
634 /* look up if already exists */
635 list_for_each(head, del_list) {
636 cur = list_entry(head, nx_mac_list_t, list);
637
638 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
639 list_move_tail(head, &adapter->mac_list);
640 return 0;
641 }
642 }
643
644 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
645 if (cur == NULL) {
646 printk(KERN_ERR "%s: failed to add mac address filter\n",
647 adapter->netdev->name);
648 return -ENOMEM;
649 }
650 memcpy(cur->mac_addr, addr, ETH_ALEN);
651 list_add_tail(&cur->list, &adapter->mac_list);
652 return nx_p3_sre_macaddr_change(adapter,
653 cur->mac_addr, NETXEN_MAC_ADD);
654 }
655
656 void netxen_p3_nic_set_multi(struct net_device *netdev)
657 {
658 struct netxen_adapter *adapter = netdev_priv(netdev);
659 struct dev_mc_list *mc_ptr;
660 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
661 u32 mode = VPORT_MISS_MODE_DROP;
662 LIST_HEAD(del_list);
663 struct list_head *head;
664 nx_mac_list_t *cur;
665
666 list_splice_tail_init(&adapter->mac_list, &del_list);
667
668 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
669 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
670
671 if (netdev->flags & IFF_PROMISC) {
672 mode = VPORT_MISS_MODE_ACCEPT_ALL;
673 goto send_fw_cmd;
674 }
675
676 if ((netdev->flags & IFF_ALLMULTI) ||
677 (netdev->mc_count > adapter->max_mc_count)) {
678 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
679 goto send_fw_cmd;
680 }
681
682 if (netdev->mc_count > 0) {
683 for (mc_ptr = netdev->mc_list; mc_ptr;
684 mc_ptr = mc_ptr->next) {
685 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
686 }
687 }
688
689 send_fw_cmd:
690 adapter->set_promisc(adapter, mode);
691 head = &del_list;
692 while (!list_empty(head)) {
693 cur = list_entry(head->next, nx_mac_list_t, list);
694
695 nx_p3_sre_macaddr_change(adapter,
696 cur->mac_addr, NETXEN_MAC_DEL);
697 list_del(&cur->list);
698 kfree(cur);
699 }
700 }
701
702 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
703 {
704 nx_nic_req_t req;
705 u64 word;
706
707 memset(&req, 0, sizeof(nx_nic_req_t));
708
709 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
710
711 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
712 ((u64)adapter->portnum << 16);
713 req.req_hdr = cpu_to_le64(word);
714
715 req.words[0] = cpu_to_le64(mode);
716
717 return netxen_send_cmd_descs(adapter,
718 (struct cmd_desc_type0 *)&req, 1);
719 }
720
721 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
722 {
723 nx_mac_list_t *cur;
724 struct list_head *head = &adapter->mac_list;
725
726 while (!list_empty(head)) {
727 cur = list_entry(head->next, nx_mac_list_t, list);
728 nx_p3_sre_macaddr_change(adapter,
729 cur->mac_addr, NETXEN_MAC_DEL);
730 list_del(&cur->list);
731 kfree(cur);
732 }
733 }
734
735 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
736 {
737 /* assuming caller has already copied new addr to netdev */
738 netxen_p3_nic_set_multi(adapter->netdev);
739 return 0;
740 }
741
742 #define NETXEN_CONFIG_INTR_COALESCE 3
743
744 /*
745 * Send the interrupt coalescing parameter set by ethtool to the card.
746 */
747 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
748 {
749 nx_nic_req_t req;
750 u64 word;
751 int rv;
752
753 memset(&req, 0, sizeof(nx_nic_req_t));
754
755 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
756
757 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
758 req.req_hdr = cpu_to_le64(word);
759
760 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
761
762 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
763 if (rv != 0) {
764 printk(KERN_ERR "ERROR. Could not send "
765 "interrupt coalescing parameters\n");
766 }
767
768 return rv;
769 }
770
771 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
772 {
773 nx_nic_req_t req;
774 u64 word;
775 int rv = 0;
776
777 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
778 return 0;
779
780 memset(&req, 0, sizeof(nx_nic_req_t));
781
782 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
783
784 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
785 req.req_hdr = cpu_to_le64(word);
786
787 req.words[0] = cpu_to_le64(enable);
788
789 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
790 if (rv != 0) {
791 printk(KERN_ERR "ERROR. Could not send "
792 "configure hw lro request\n");
793 }
794
795 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
796
797 return rv;
798 }
799
800 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
801 {
802 nx_nic_req_t req;
803 u64 word;
804 int rv = 0;
805
806 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
807 return rv;
808
809 memset(&req, 0, sizeof(nx_nic_req_t));
810
811 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
812
813 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
814 ((u64)adapter->portnum << 16);
815 req.req_hdr = cpu_to_le64(word);
816
817 req.words[0] = cpu_to_le64(enable);
818
819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
820 if (rv != 0) {
821 printk(KERN_ERR "ERROR. Could not send "
822 "configure bridge mode request\n");
823 }
824
825 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
826
827 return rv;
828 }
829
830
831 #define RSS_HASHTYPE_IP_TCP 0x3
832
833 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
834 {
835 nx_nic_req_t req;
836 u64 word;
837 int i, rv;
838
839 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
840 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
841 0x255b0ec26d5a56daULL };
842
843
844 memset(&req, 0, sizeof(nx_nic_req_t));
845 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
846
847 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
848 req.req_hdr = cpu_to_le64(word);
849
850 /*
851 * RSS request:
852 * bits 3-0: hash_method
853 * 5-4: hash_type_ipv4
854 * 7-6: hash_type_ipv6
855 * 8: enable
856 * 9: use indirection table
857 * 47-10: reserved
858 * 63-48: indirection table mask
859 */
860 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
861 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
862 ((u64)(enable & 0x1) << 8) |
863 ((0x7ULL) << 48);
864 req.words[0] = cpu_to_le64(word);
865 for (i = 0; i < 5; i++)
866 req.words[i+1] = cpu_to_le64(key[i]);
867
868
869 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
870 if (rv != 0) {
871 printk(KERN_ERR "%s: could not configure RSS\n",
872 adapter->netdev->name);
873 }
874
875 return rv;
876 }
877
878 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
879 {
880 nx_nic_req_t req;
881 u64 word;
882 int rv;
883
884 memset(&req, 0, sizeof(nx_nic_req_t));
885 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
886
887 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
888 req.req_hdr = cpu_to_le64(word);
889
890 req.words[0] = cpu_to_le64(cmd);
891 req.words[1] = cpu_to_le64(ip);
892
893 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
894 if (rv != 0) {
895 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
896 adapter->netdev->name,
897 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
898 }
899 return rv;
900 }
901
902 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
903 {
904 nx_nic_req_t req;
905 u64 word;
906 int rv;
907
908 memset(&req, 0, sizeof(nx_nic_req_t));
909 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
910
911 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
912 req.req_hdr = cpu_to_le64(word);
913 req.words[0] = cpu_to_le64(enable | (enable << 8));
914
915 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
916 if (rv != 0) {
917 printk(KERN_ERR "%s: could not configure link notification\n",
918 adapter->netdev->name);
919 }
920
921 return rv;
922 }
923
924 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
925 {
926 nx_nic_req_t req;
927 u64 word;
928 int rv;
929
930 memset(&req, 0, sizeof(nx_nic_req_t));
931 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
932
933 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
934 ((u64)adapter->portnum << 16) |
935 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
936
937 req.req_hdr = cpu_to_le64(word);
938
939 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
940 if (rv != 0) {
941 printk(KERN_ERR "%s: could not cleanup lro flows\n",
942 adapter->netdev->name);
943 }
944 return rv;
945 }
946
947 /*
948 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
949 * @returns 0 on success, negative on failure
950 */
951
952 #define MTU_FUDGE_FACTOR 100
953
954 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
955 {
956 struct netxen_adapter *adapter = netdev_priv(netdev);
957 int max_mtu;
958 int rc = 0;
959
960 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
961 max_mtu = P3_MAX_MTU;
962 else
963 max_mtu = P2_MAX_MTU;
964
965 if (mtu > max_mtu) {
966 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
967 netdev->name, max_mtu);
968 return -EINVAL;
969 }
970
971 if (adapter->set_mtu)
972 rc = adapter->set_mtu(adapter, mtu);
973
974 if (!rc)
975 netdev->mtu = mtu;
976
977 return rc;
978 }
979
980 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
981 int size, __le32 * buf)
982 {
983 int i, v, addr;
984 __le32 *ptr32;
985
986 addr = base;
987 ptr32 = buf;
988 for (i = 0; i < size / sizeof(u32); i++) {
989 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
990 return -1;
991 *ptr32 = cpu_to_le32(v);
992 ptr32++;
993 addr += sizeof(u32);
994 }
995 if ((char *)buf + size > (char *)ptr32) {
996 __le32 local;
997 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
998 return -1;
999 local = cpu_to_le32(v);
1000 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1001 }
1002
1003 return 0;
1004 }
1005
1006 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1007 {
1008 __le32 *pmac = (__le32 *) mac;
1009 u32 offset;
1010
1011 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1012
1013 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1014 return -1;
1015
1016 if (*mac == cpu_to_le64(~0ULL)) {
1017
1018 offset = NX_OLD_MAC_ADDR_OFFSET +
1019 (adapter->portnum * sizeof(u64));
1020
1021 if (netxen_get_flash_block(adapter,
1022 offset, sizeof(u64), pmac) == -1)
1023 return -1;
1024
1025 if (*mac == cpu_to_le64(~0ULL))
1026 return -1;
1027 }
1028 return 0;
1029 }
1030
1031 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1032 {
1033 uint32_t crbaddr, mac_hi, mac_lo;
1034 int pci_func = adapter->ahw.pci_func;
1035
1036 crbaddr = CRB_MAC_BLOCK_START +
1037 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1038
1039 mac_lo = NXRD32(adapter, crbaddr);
1040 mac_hi = NXRD32(adapter, crbaddr+4);
1041
1042 if (pci_func & 1)
1043 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1044 else
1045 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1046
1047 return 0;
1048 }
1049
1050 /*
1051 * Changes the CRB window to the specified window.
1052 */
1053 static void
1054 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
1055 {
1056 void __iomem *offset;
1057 u32 tmp;
1058 int count = 0;
1059 uint8_t func = adapter->ahw.pci_func;
1060
1061 if (adapter->curr_window == wndw)
1062 return;
1063 /*
1064 * Move the CRB window.
1065 * We need to write to the "direct access" region of PCI
1066 * to avoid a race condition where the window register has
1067 * not been successfully written across CRB before the target
1068 * register address is received by PCI. The direct region bypasses
1069 * the CRB bus.
1070 */
1071 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1072 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1073
1074 if (wndw & 0x1)
1075 wndw = NETXEN_WINDOW_ONE;
1076
1077 writel(wndw, offset);
1078
1079 /* MUST make sure window is set before we forge on... */
1080 while ((tmp = readl(offset)) != wndw) {
1081 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1082 "registered properly: 0x%08x.\n",
1083 netxen_nic_driver_name, __func__, tmp);
1084 mdelay(1);
1085 if (count >= 10)
1086 break;
1087 count++;
1088 }
1089
1090 if (wndw == NETXEN_WINDOW_ONE)
1091 adapter->curr_window = 1;
1092 else
1093 adapter->curr_window = 0;
1094 }
1095
1096 /*
1097 * Return -1 if off is not valid,
1098 * 1 if window access is needed. 'off' is set to offset from
1099 * CRB space in 128M pci map
1100 * 0 if no window access is needed. 'off' is set to 2M addr
1101 * In: 'off' is offset from base in 128M pci map
1102 */
1103 static int
1104 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1105 {
1106 crb_128M_2M_sub_block_map_t *m;
1107
1108
1109 if (*off >= NETXEN_CRB_MAX)
1110 return -1;
1111
1112 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1113 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1114 (ulong)adapter->ahw.pci_base0;
1115 return 0;
1116 }
1117
1118 if (*off < NETXEN_PCI_CRBSPACE)
1119 return -1;
1120
1121 *off -= NETXEN_PCI_CRBSPACE;
1122
1123 /*
1124 * Try direct map
1125 */
1126 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1127
1128 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1129 *off = *off + m->start_2M - m->start_128M +
1130 (ulong)adapter->ahw.pci_base0;
1131 return 0;
1132 }
1133
1134 /*
1135 * Not in direct map, use crb window
1136 */
1137 return 1;
1138 }
1139
1140 /*
1141 * In: 'off' is offset from CRB space in 128M pci map
1142 * Out: 'off' is 2M pci map addr
1143 * side effect: lock crb window
1144 */
1145 static void
1146 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1147 {
1148 u32 win_read;
1149
1150 adapter->crb_win = CRB_HI(*off);
1151 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1152 /*
1153 * Read back value to make sure write has gone through before trying
1154 * to use it.
1155 */
1156 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1157 if (win_read != adapter->crb_win) {
1158 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1159 "Read crbwin (0x%x), off=0x%lx\n",
1160 __func__, adapter->crb_win, win_read, *off);
1161 }
1162 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1163 (ulong)adapter->ahw.pci_base0;
1164 }
1165
1166 static int
1167 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1168 {
1169 unsigned long flags;
1170 void __iomem *addr;
1171
1172 if (ADDR_IN_WINDOW1(off))
1173 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1174 else
1175 addr = pci_base_offset(adapter, off);
1176
1177 BUG_ON(!addr);
1178
1179 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1180 read_lock(&adapter->adapter_lock);
1181 writel(data, addr);
1182 read_unlock(&adapter->adapter_lock);
1183 } else { /* Window 0 */
1184 write_lock_irqsave(&adapter->adapter_lock, flags);
1185 addr = pci_base_offset(adapter, off);
1186 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1187 writel(data, addr);
1188 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1189 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1190 }
1191
1192 return 0;
1193 }
1194
1195 static u32
1196 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1197 {
1198 unsigned long flags;
1199 void __iomem *addr;
1200 u32 data;
1201
1202 if (ADDR_IN_WINDOW1(off))
1203 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1204 else
1205 addr = pci_base_offset(adapter, off);
1206
1207 BUG_ON(!addr);
1208
1209 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1210 read_lock(&adapter->adapter_lock);
1211 data = readl(addr);
1212 read_unlock(&adapter->adapter_lock);
1213 } else { /* Window 0 */
1214 write_lock_irqsave(&adapter->adapter_lock, flags);
1215 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1216 data = readl(addr);
1217 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1218 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1219 }
1220
1221 return data;
1222 }
1223
1224 static int
1225 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1226 {
1227 unsigned long flags;
1228 int rv;
1229
1230 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1231
1232 if (rv == -1) {
1233 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1234 __func__, off);
1235 dump_stack();
1236 return -1;
1237 }
1238
1239 if (rv == 1) {
1240 write_lock_irqsave(&adapter->adapter_lock, flags);
1241 crb_win_lock(adapter);
1242 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1243 writel(data, (void __iomem *)off);
1244 crb_win_unlock(adapter);
1245 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1246 } else
1247 writel(data, (void __iomem *)off);
1248
1249
1250 return 0;
1251 }
1252
1253 static u32
1254 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1255 {
1256 unsigned long flags;
1257 int rv;
1258 u32 data;
1259
1260 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1261
1262 if (rv == -1) {
1263 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1264 __func__, off);
1265 dump_stack();
1266 return -1;
1267 }
1268
1269 if (rv == 1) {
1270 write_lock_irqsave(&adapter->adapter_lock, flags);
1271 crb_win_lock(adapter);
1272 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1273 data = readl((void __iomem *)off);
1274 crb_win_unlock(adapter);
1275 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1276 } else
1277 data = readl((void __iomem *)off);
1278
1279 return data;
1280 }
1281
1282 /*
1283 * check memory access boundary.
1284 * used by test agent. support ddr access only for now
1285 */
1286 static unsigned long
1287 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1288 unsigned long long addr, int size)
1289 {
1290 if (!ADDR_IN_RANGE(addr,
1291 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1292 !ADDR_IN_RANGE(addr+size-1,
1293 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1294 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1295 return 0;
1296 }
1297
1298 return 1;
1299 }
1300
1301 static int netxen_pci_set_window_warning_count;
1302
1303 static unsigned long
1304 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1305 unsigned long long addr)
1306 {
1307 void __iomem *offset;
1308 int window;
1309 unsigned long long qdr_max;
1310 uint8_t func = adapter->ahw.pci_func;
1311
1312 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1313 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1314 } else {
1315 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1316 }
1317
1318 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1319 /* DDR network side */
1320 addr -= NETXEN_ADDR_DDR_NET;
1321 window = (addr >> 25) & 0x3ff;
1322 if (adapter->ahw.ddr_mn_window != window) {
1323 adapter->ahw.ddr_mn_window = window;
1324 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1325 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1326 writel(window, offset);
1327 /* MUST make sure window is set before we forge on... */
1328 readl(offset);
1329 }
1330 addr -= (window * NETXEN_WINDOW_ONE);
1331 addr += NETXEN_PCI_DDR_NET;
1332 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1333 addr -= NETXEN_ADDR_OCM0;
1334 addr += NETXEN_PCI_OCM0;
1335 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1336 addr -= NETXEN_ADDR_OCM1;
1337 addr += NETXEN_PCI_OCM1;
1338 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1339 /* QDR network side */
1340 addr -= NETXEN_ADDR_QDR_NET;
1341 window = (addr >> 22) & 0x3f;
1342 if (adapter->ahw.qdr_sn_window != window) {
1343 adapter->ahw.qdr_sn_window = window;
1344 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1345 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1346 writel((window << 22), offset);
1347 /* MUST make sure window is set before we forge on... */
1348 readl(offset);
1349 }
1350 addr -= (window * 0x400000);
1351 addr += NETXEN_PCI_QDR_NET;
1352 } else {
1353 /*
1354 * peg gdb frequently accesses memory that doesn't exist,
1355 * this limits the chit chat so debugging isn't slowed down.
1356 */
1357 if ((netxen_pci_set_window_warning_count++ < 8)
1358 || (netxen_pci_set_window_warning_count % 64 == 0))
1359 printk("%s: Warning:netxen_nic_pci_set_window()"
1360 " Unknown address range!\n",
1361 netxen_nic_driver_name);
1362 addr = -1UL;
1363 }
1364 return addr;
1365 }
1366
1367 /* window 1 registers only */
1368 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1369 void __iomem *addr, u32 data)
1370 {
1371 read_lock(&adapter->adapter_lock);
1372 writel(data, addr);
1373 read_unlock(&adapter->adapter_lock);
1374 }
1375
1376 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1377 void __iomem *addr)
1378 {
1379 u32 val;
1380
1381 read_lock(&adapter->adapter_lock);
1382 val = readl(addr);
1383 read_unlock(&adapter->adapter_lock);
1384
1385 return val;
1386 }
1387
1388 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1389 void __iomem *addr, u32 data)
1390 {
1391 writel(data, addr);
1392 }
1393
1394 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1395 void __iomem *addr)
1396 {
1397 return readl(addr);
1398 }
1399
1400 void __iomem *
1401 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1402 {
1403 ulong off = offset;
1404
1405 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1406 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1407 offset > NETXEN_CRB_PCIX_HOST)
1408 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1409 return NETXEN_CRB_NORMALIZE(adapter, offset);
1410 }
1411
1412 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1413 return (void __iomem *)off;
1414 }
1415
1416 static unsigned long
1417 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1418 unsigned long long addr)
1419 {
1420 int window;
1421 u32 win_read;
1422
1423 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1424 /* DDR network side */
1425 window = MN_WIN(addr);
1426 adapter->ahw.ddr_mn_window = window;
1427 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1428 window);
1429 win_read = NXRD32(adapter,
1430 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1431 if ((win_read << 17) != window) {
1432 printk(KERN_INFO "Written MNwin (0x%x) != "
1433 "Read MNwin (0x%x)\n", window, win_read);
1434 }
1435 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1436 } else if (ADDR_IN_RANGE(addr,
1437 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1438 if ((addr & 0x00ff800) == 0xff800) {
1439 printk("%s: QM access not handled.\n", __func__);
1440 addr = -1UL;
1441 }
1442
1443 window = OCM_WIN(addr);
1444 adapter->ahw.ddr_mn_window = window;
1445 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1446 window);
1447 win_read = NXRD32(adapter,
1448 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1449 if ((win_read >> 7) != window) {
1450 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1451 "Read OCMwin (0x%x)\n",
1452 __func__, window, win_read);
1453 }
1454 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1455
1456 } else if (ADDR_IN_RANGE(addr,
1457 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1458 /* QDR network side */
1459 window = MS_WIN(addr);
1460 adapter->ahw.qdr_sn_window = window;
1461 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1462 window);
1463 win_read = NXRD32(adapter,
1464 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1465 if (win_read != window) {
1466 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1467 "Read MSwin (0x%x)\n",
1468 __func__, window, win_read);
1469 }
1470 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1471
1472 } else {
1473 /*
1474 * peg gdb frequently accesses memory that doesn't exist,
1475 * this limits the chit chat so debugging isn't slowed down.
1476 */
1477 if ((netxen_pci_set_window_warning_count++ < 8)
1478 || (netxen_pci_set_window_warning_count%64 == 0)) {
1479 printk("%s: Warning:%s Unknown address range!\n",
1480 __func__, netxen_nic_driver_name);
1481 }
1482 addr = -1UL;
1483 }
1484 return addr;
1485 }
1486
1487 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1488 unsigned long long addr)
1489 {
1490 int window;
1491 unsigned long long qdr_max;
1492
1493 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1494 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1495 else
1496 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1497
1498 if (ADDR_IN_RANGE(addr,
1499 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1500 /* DDR network side */
1501 BUG(); /* MN access can not come here */
1502 } else if (ADDR_IN_RANGE(addr,
1503 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1504 return 1;
1505 } else if (ADDR_IN_RANGE(addr,
1506 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1507 return 1;
1508 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1509 /* QDR network side */
1510 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1511 if (adapter->ahw.qdr_sn_window == window)
1512 return 1;
1513 }
1514
1515 return 0;
1516 }
1517
1518 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1519 u64 off, void *data, int size)
1520 {
1521 unsigned long flags;
1522 void __iomem *addr, *mem_ptr = NULL;
1523 int ret = 0;
1524 u64 start;
1525 unsigned long mem_base;
1526 unsigned long mem_page;
1527
1528 write_lock_irqsave(&adapter->adapter_lock, flags);
1529
1530 /*
1531 * If attempting to access unknown address or straddle hw windows,
1532 * do not access.
1533 */
1534 start = adapter->pci_set_window(adapter, off);
1535 if ((start == -1UL) ||
1536 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1537 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1538 printk(KERN_ERR "%s out of bound pci memory access. "
1539 "offset is 0x%llx\n", netxen_nic_driver_name,
1540 (unsigned long long)off);
1541 return -1;
1542 }
1543
1544 addr = pci_base_offset(adapter, start);
1545 if (!addr) {
1546 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1547 mem_base = pci_resource_start(adapter->pdev, 0);
1548 mem_page = start & PAGE_MASK;
1549 /* Map two pages whenever user tries to access addresses in two
1550 consecutive pages.
1551 */
1552 if (mem_page != ((start + size - 1) & PAGE_MASK))
1553 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1554 else
1555 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1556 if (mem_ptr == NULL) {
1557 *(uint8_t *)data = 0;
1558 return -1;
1559 }
1560 addr = mem_ptr;
1561 addr += start & (PAGE_SIZE - 1);
1562 write_lock_irqsave(&adapter->adapter_lock, flags);
1563 }
1564
1565 switch (size) {
1566 case 1:
1567 *(uint8_t *)data = readb(addr);
1568 break;
1569 case 2:
1570 *(uint16_t *)data = readw(addr);
1571 break;
1572 case 4:
1573 *(uint32_t *)data = readl(addr);
1574 break;
1575 case 8:
1576 *(uint64_t *)data = readq(addr);
1577 break;
1578 default:
1579 ret = -1;
1580 break;
1581 }
1582 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1583
1584 if (mem_ptr)
1585 iounmap(mem_ptr);
1586 return ret;
1587 }
1588
1589 static int
1590 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1591 void *data, int size)
1592 {
1593 unsigned long flags;
1594 void __iomem *addr, *mem_ptr = NULL;
1595 int ret = 0;
1596 u64 start;
1597 unsigned long mem_base;
1598 unsigned long mem_page;
1599
1600 write_lock_irqsave(&adapter->adapter_lock, flags);
1601
1602 /*
1603 * If attempting to access unknown address or straddle hw windows,
1604 * do not access.
1605 */
1606 start = adapter->pci_set_window(adapter, off);
1607 if ((start == -1UL) ||
1608 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1609 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1610 printk(KERN_ERR "%s out of bound pci memory access. "
1611 "offset is 0x%llx\n", netxen_nic_driver_name,
1612 (unsigned long long)off);
1613 return -1;
1614 }
1615
1616 addr = pci_base_offset(adapter, start);
1617 if (!addr) {
1618 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1619 mem_base = pci_resource_start(adapter->pdev, 0);
1620 mem_page = start & PAGE_MASK;
1621 /* Map two pages whenever user tries to access addresses in two
1622 * consecutive pages.
1623 */
1624 if (mem_page != ((start + size - 1) & PAGE_MASK))
1625 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1626 else
1627 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1628 if (mem_ptr == NULL)
1629 return -1;
1630 addr = mem_ptr;
1631 addr += start & (PAGE_SIZE - 1);
1632 write_lock_irqsave(&adapter->adapter_lock, flags);
1633 }
1634
1635 switch (size) {
1636 case 1:
1637 writeb(*(uint8_t *)data, addr);
1638 break;
1639 case 2:
1640 writew(*(uint16_t *)data, addr);
1641 break;
1642 case 4:
1643 writel(*(uint32_t *)data, addr);
1644 break;
1645 case 8:
1646 writeq(*(uint64_t *)data, addr);
1647 break;
1648 default:
1649 ret = -1;
1650 break;
1651 }
1652 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1653 if (mem_ptr)
1654 iounmap(mem_ptr);
1655 return ret;
1656 }
1657
1658 #define MAX_CTL_CHECK 1000
1659
1660 static int
1661 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1662 u64 off, void *data, int size)
1663 {
1664 unsigned long flags;
1665 int i, j, ret = 0, loop, sz[2], off0;
1666 uint32_t temp;
1667 uint64_t off8, tmpw, word[2] = {0, 0};
1668 void __iomem *mem_crb;
1669
1670 /*
1671 * If not MN, go check for MS or invalid.
1672 */
1673 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1674 return netxen_nic_pci_mem_write_direct(adapter,
1675 off, data, size);
1676
1677 off8 = off & 0xfffffff8;
1678 off0 = off & 0x7;
1679 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1680 sz[1] = size - sz[0];
1681 loop = ((off0 + size - 1) >> 3) + 1;
1682 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1683
1684 if ((size != 8) || (off0 != 0)) {
1685 for (i = 0; i < loop; i++) {
1686 if (adapter->pci_mem_read(adapter,
1687 off8 + (i << 3), &word[i], 8))
1688 return -1;
1689 }
1690 }
1691
1692 switch (size) {
1693 case 1:
1694 tmpw = *((uint8_t *)data);
1695 break;
1696 case 2:
1697 tmpw = *((uint16_t *)data);
1698 break;
1699 case 4:
1700 tmpw = *((uint32_t *)data);
1701 break;
1702 case 8:
1703 default:
1704 tmpw = *((uint64_t *)data);
1705 break;
1706 }
1707 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1708 word[0] |= tmpw << (off0 * 8);
1709
1710 if (loop == 2) {
1711 word[1] &= ~(~0ULL << (sz[1] * 8));
1712 word[1] |= tmpw >> (sz[0] * 8);
1713 }
1714
1715 write_lock_irqsave(&adapter->adapter_lock, flags);
1716 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1717
1718 for (i = 0; i < loop; i++) {
1719 writel((uint32_t)(off8 + (i << 3)),
1720 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1721 writel(0,
1722 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1723 writel(word[i] & 0xffffffff,
1724 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1725 writel((word[i] >> 32) & 0xffffffff,
1726 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1727 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1728 (mem_crb+MIU_TEST_AGT_CTRL));
1729 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1730 (mem_crb+MIU_TEST_AGT_CTRL));
1731
1732 for (j = 0; j < MAX_CTL_CHECK; j++) {
1733 temp = readl(
1734 (mem_crb+MIU_TEST_AGT_CTRL));
1735 if ((temp & MIU_TA_CTL_BUSY) == 0)
1736 break;
1737 }
1738
1739 if (j >= MAX_CTL_CHECK) {
1740 if (printk_ratelimit())
1741 dev_err(&adapter->pdev->dev,
1742 "failed to write through agent\n");
1743 ret = -1;
1744 break;
1745 }
1746 }
1747
1748 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1749 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1750 return ret;
1751 }
1752
1753 static int
1754 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1755 u64 off, void *data, int size)
1756 {
1757 unsigned long flags;
1758 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1759 uint32_t temp;
1760 uint64_t off8, val, word[2] = {0, 0};
1761 void __iomem *mem_crb;
1762
1763
1764 /*
1765 * If not MN, go check for MS or invalid.
1766 */
1767 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1768 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1769
1770 off8 = off & 0xfffffff8;
1771 off0[0] = off & 0x7;
1772 off0[1] = 0;
1773 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1774 sz[1] = size - sz[0];
1775 loop = ((off0[0] + size - 1) >> 3) + 1;
1776 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1777
1778 write_lock_irqsave(&adapter->adapter_lock, flags);
1779 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1780
1781 for (i = 0; i < loop; i++) {
1782 writel((uint32_t)(off8 + (i << 3)),
1783 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1784 writel(0,
1785 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1786 writel(MIU_TA_CTL_ENABLE,
1787 (mem_crb+MIU_TEST_AGT_CTRL));
1788 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1789 (mem_crb+MIU_TEST_AGT_CTRL));
1790
1791 for (j = 0; j < MAX_CTL_CHECK; j++) {
1792 temp = readl(
1793 (mem_crb+MIU_TEST_AGT_CTRL));
1794 if ((temp & MIU_TA_CTL_BUSY) == 0)
1795 break;
1796 }
1797
1798 if (j >= MAX_CTL_CHECK) {
1799 if (printk_ratelimit())
1800 dev_err(&adapter->pdev->dev,
1801 "failed to read through agent\n");
1802 break;
1803 }
1804
1805 start = off0[i] >> 2;
1806 end = (off0[i] + sz[i] - 1) >> 2;
1807 for (k = start; k <= end; k++) {
1808 word[i] |= ((uint64_t) readl(
1809 (mem_crb +
1810 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1811 }
1812 }
1813
1814 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1815 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1816
1817 if (j >= MAX_CTL_CHECK)
1818 return -1;
1819
1820 if (sz[0] == 8) {
1821 val = word[0];
1822 } else {
1823 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1824 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1825 }
1826
1827 switch (size) {
1828 case 1:
1829 *(uint8_t *)data = val;
1830 break;
1831 case 2:
1832 *(uint16_t *)data = val;
1833 break;
1834 case 4:
1835 *(uint32_t *)data = val;
1836 break;
1837 case 8:
1838 *(uint64_t *)data = val;
1839 break;
1840 }
1841 return 0;
1842 }
1843
1844 static int
1845 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1846 u64 off, void *data, int size)
1847 {
1848 int i, j, ret = 0, loop, sz[2], off0;
1849 uint32_t temp;
1850 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1851
1852 /*
1853 * If not MN, go check for MS or invalid.
1854 */
1855 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1856 mem_crb = NETXEN_CRB_QDR_NET;
1857 else {
1858 mem_crb = NETXEN_CRB_DDR_NET;
1859 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1860 return netxen_nic_pci_mem_write_direct(adapter,
1861 off, data, size);
1862 }
1863
1864 off8 = off & 0xfffffff8;
1865 off0 = off & 0x7;
1866 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1867 sz[1] = size - sz[0];
1868 loop = ((off0 + size - 1) >> 3) + 1;
1869
1870 if ((size != 8) || (off0 != 0)) {
1871 for (i = 0; i < loop; i++) {
1872 if (adapter->pci_mem_read(adapter,
1873 off8 + (i << 3), &word[i], 8))
1874 return -1;
1875 }
1876 }
1877
1878 switch (size) {
1879 case 1:
1880 tmpw = *((uint8_t *)data);
1881 break;
1882 case 2:
1883 tmpw = *((uint16_t *)data);
1884 break;
1885 case 4:
1886 tmpw = *((uint32_t *)data);
1887 break;
1888 case 8:
1889 default:
1890 tmpw = *((uint64_t *)data);
1891 break;
1892 }
1893
1894 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1895 word[0] |= tmpw << (off0 * 8);
1896
1897 if (loop == 2) {
1898 word[1] &= ~(~0ULL << (sz[1] * 8));
1899 word[1] |= tmpw >> (sz[0] * 8);
1900 }
1901
1902 /*
1903 * don't lock here - write_wx gets the lock if each time
1904 * write_lock_irqsave(&adapter->adapter_lock, flags);
1905 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1906 */
1907
1908 for (i = 0; i < loop; i++) {
1909 temp = off8 + (i << 3);
1910 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1911 temp = 0;
1912 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1913 temp = word[i] & 0xffffffff;
1914 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1915 temp = (word[i] >> 32) & 0xffffffff;
1916 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1917 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1918 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1919 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1920 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1921
1922 for (j = 0; j < MAX_CTL_CHECK; j++) {
1923 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1924 if ((temp & MIU_TA_CTL_BUSY) == 0)
1925 break;
1926 }
1927
1928 if (j >= MAX_CTL_CHECK) {
1929 if (printk_ratelimit())
1930 dev_err(&adapter->pdev->dev,
1931 "failed to write through agent\n");
1932 ret = -1;
1933 break;
1934 }
1935 }
1936
1937 /*
1938 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1939 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1940 */
1941 return ret;
1942 }
1943
1944 static int
1945 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1946 u64 off, void *data, int size)
1947 {
1948 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1949 uint32_t temp;
1950 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1951
1952 /*
1953 * If not MN, go check for MS or invalid.
1954 */
1955
1956 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1957 mem_crb = NETXEN_CRB_QDR_NET;
1958 else {
1959 mem_crb = NETXEN_CRB_DDR_NET;
1960 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1961 return netxen_nic_pci_mem_read_direct(adapter,
1962 off, data, size);
1963 }
1964
1965 off8 = off & 0xfffffff8;
1966 off0[0] = off & 0x7;
1967 off0[1] = 0;
1968 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1969 sz[1] = size - sz[0];
1970 loop = ((off0[0] + size - 1) >> 3) + 1;
1971
1972 /*
1973 * don't lock here - write_wx gets the lock if each time
1974 * write_lock_irqsave(&adapter->adapter_lock, flags);
1975 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1976 */
1977
1978 for (i = 0; i < loop; i++) {
1979 temp = off8 + (i << 3);
1980 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1981 temp = 0;
1982 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1983 temp = MIU_TA_CTL_ENABLE;
1984 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1985 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1986 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1987
1988 for (j = 0; j < MAX_CTL_CHECK; j++) {
1989 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1990 if ((temp & MIU_TA_CTL_BUSY) == 0)
1991 break;
1992 }
1993
1994 if (j >= MAX_CTL_CHECK) {
1995 if (printk_ratelimit())
1996 dev_err(&adapter->pdev->dev,
1997 "failed to read through agent\n");
1998 break;
1999 }
2000
2001 start = off0[i] >> 2;
2002 end = (off0[i] + sz[i] - 1) >> 2;
2003 for (k = start; k <= end; k++) {
2004 temp = NXRD32(adapter,
2005 mem_crb + MIU_TEST_AGT_RDDATA(k));
2006 word[i] |= ((uint64_t)temp << (32 * k));
2007 }
2008 }
2009
2010 /*
2011 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2012 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2013 */
2014
2015 if (j >= MAX_CTL_CHECK)
2016 return -1;
2017
2018 if (sz[0] == 8) {
2019 val = word[0];
2020 } else {
2021 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2022 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2023 }
2024
2025 switch (size) {
2026 case 1:
2027 *(uint8_t *)data = val;
2028 break;
2029 case 2:
2030 *(uint16_t *)data = val;
2031 break;
2032 case 4:
2033 *(uint32_t *)data = val;
2034 break;
2035 case 8:
2036 *(uint64_t *)data = val;
2037 break;
2038 }
2039 return 0;
2040 }
2041
2042 void
2043 netxen_setup_hwops(struct netxen_adapter *adapter)
2044 {
2045 adapter->init_port = netxen_niu_xg_init_port;
2046 adapter->stop_port = netxen_niu_disable_xg_port;
2047
2048 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
2049 adapter->crb_read = netxen_nic_hw_read_wx_128M,
2050 adapter->crb_write = netxen_nic_hw_write_wx_128M,
2051 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
2052 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
2053 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
2054 adapter->io_read = netxen_nic_io_read_128M,
2055 adapter->io_write = netxen_nic_io_write_128M,
2056
2057 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
2058 adapter->set_multi = netxen_p2_nic_set_multi;
2059 adapter->set_mtu = netxen_nic_set_mtu_xgb;
2060 adapter->set_promisc = netxen_p2_nic_set_promisc;
2061
2062 } else {
2063 adapter->crb_read = netxen_nic_hw_read_wx_2M,
2064 adapter->crb_write = netxen_nic_hw_write_wx_2M,
2065 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
2066 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
2067 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
2068 adapter->io_read = netxen_nic_io_read_2M,
2069 adapter->io_write = netxen_nic_io_write_2M,
2070
2071 adapter->set_mtu = nx_fw_cmd_set_mtu;
2072 adapter->set_promisc = netxen_p3_nic_set_promisc;
2073 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
2074 adapter->set_multi = netxen_p3_nic_set_multi;
2075
2076 adapter->phy_read = nx_fw_cmd_query_phy;
2077 adapter->phy_write = nx_fw_cmd_set_phy;
2078 }
2079 }
2080
2081 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2082 {
2083 int offset, board_type, magic, header_version;
2084 struct pci_dev *pdev = adapter->pdev;
2085
2086 offset = NX_FW_MAGIC_OFFSET;
2087 if (netxen_rom_fast_read(adapter, offset, &magic))
2088 return -EIO;
2089
2090 offset = NX_HDR_VERSION_OFFSET;
2091 if (netxen_rom_fast_read(adapter, offset, &header_version))
2092 return -EIO;
2093
2094 if (magic != NETXEN_BDINFO_MAGIC ||
2095 header_version != NETXEN_BDINFO_VERSION) {
2096 dev_err(&pdev->dev,
2097 "invalid board config, magic=%08x, version=%08x\n",
2098 magic, header_version);
2099 return -EIO;
2100 }
2101
2102 offset = NX_BRDTYPE_OFFSET;
2103 if (netxen_rom_fast_read(adapter, offset, &board_type))
2104 return -EIO;
2105
2106 adapter->ahw.board_type = board_type;
2107
2108 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2109 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2110 if ((gpio & 0x8000) == 0)
2111 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2112 }
2113
2114 switch (board_type) {
2115 case NETXEN_BRDTYPE_P2_SB35_4G:
2116 adapter->ahw.port_type = NETXEN_NIC_GBE;
2117 break;
2118 case NETXEN_BRDTYPE_P2_SB31_10G:
2119 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2120 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2121 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2122 case NETXEN_BRDTYPE_P3_HMEZ:
2123 case NETXEN_BRDTYPE_P3_XG_LOM:
2124 case NETXEN_BRDTYPE_P3_10G_CX4:
2125 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2126 case NETXEN_BRDTYPE_P3_IMEZ:
2127 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2128 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2129 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2130 case NETXEN_BRDTYPE_P3_10G_XFP:
2131 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2132 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2133 break;
2134 case NETXEN_BRDTYPE_P1_BD:
2135 case NETXEN_BRDTYPE_P1_SB:
2136 case NETXEN_BRDTYPE_P1_SMAX:
2137 case NETXEN_BRDTYPE_P1_SOCK:
2138 case NETXEN_BRDTYPE_P3_REF_QG:
2139 case NETXEN_BRDTYPE_P3_4_GB:
2140 case NETXEN_BRDTYPE_P3_4_GB_MM:
2141 adapter->ahw.port_type = NETXEN_NIC_GBE;
2142 break;
2143 case NETXEN_BRDTYPE_P3_10G_TP:
2144 adapter->ahw.port_type = (adapter->portnum < 2) ?
2145 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2146 break;
2147 default:
2148 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2149 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2150 break;
2151 }
2152
2153 return 0;
2154 }
2155
2156 /* NIU access sections */
2157
2158 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2159 {
2160 new_mtu += MTU_FUDGE_FACTOR;
2161 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2162 new_mtu);
2163 return 0;
2164 }
2165
2166 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2167 {
2168 new_mtu += MTU_FUDGE_FACTOR;
2169 if (adapter->physical_port == 0)
2170 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2171 else
2172 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2173 return 0;
2174 }
2175
2176 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2177 {
2178 __u32 status;
2179 __u32 autoneg;
2180 __u32 port_mode;
2181
2182 if (!netif_carrier_ok(adapter->netdev)) {
2183 adapter->link_speed = 0;
2184 adapter->link_duplex = -1;
2185 adapter->link_autoneg = AUTONEG_ENABLE;
2186 return;
2187 }
2188
2189 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2190 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2191 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2192 adapter->link_speed = SPEED_1000;
2193 adapter->link_duplex = DUPLEX_FULL;
2194 adapter->link_autoneg = AUTONEG_DISABLE;
2195 return;
2196 }
2197
2198 if (adapter->phy_read
2199 && adapter->phy_read(adapter,
2200 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2201 &status) == 0) {
2202 if (netxen_get_phy_link(status)) {
2203 switch (netxen_get_phy_speed(status)) {
2204 case 0:
2205 adapter->link_speed = SPEED_10;
2206 break;
2207 case 1:
2208 adapter->link_speed = SPEED_100;
2209 break;
2210 case 2:
2211 adapter->link_speed = SPEED_1000;
2212 break;
2213 default:
2214 adapter->link_speed = 0;
2215 break;
2216 }
2217 switch (netxen_get_phy_duplex(status)) {
2218 case 0:
2219 adapter->link_duplex = DUPLEX_HALF;
2220 break;
2221 case 1:
2222 adapter->link_duplex = DUPLEX_FULL;
2223 break;
2224 default:
2225 adapter->link_duplex = -1;
2226 break;
2227 }
2228 if (adapter->phy_read
2229 && adapter->phy_read(adapter,
2230 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2231 &autoneg) != 0)
2232 adapter->link_autoneg = autoneg;
2233 } else
2234 goto link_down;
2235 } else {
2236 link_down:
2237 adapter->link_speed = 0;
2238 adapter->link_duplex = -1;
2239 }
2240 }
2241 }
2242
2243 int
2244 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2245 {
2246 u32 wol_cfg;
2247
2248 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2249 return 0;
2250
2251 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2252 if (wol_cfg & (1UL << adapter->portnum)) {
2253 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2254 if (wol_cfg & (1 << adapter->portnum))
2255 return 1;
2256 }
2257
2258 return 0;
2259 }