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xtensa: use the new byteorder headers
[pohmelfs.git] / drivers / net / smc91x.h
bloba07cc9351c6bfd7568fe3502f5242cb3034e9b19
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_ARCH_VIPER)
48
49 #include <asm/mach-types.h>
50
51 /* Now the bus width is specified in the platform data
52 * pretend here to support all I/O access types
53 */
54 #define SMC_CAN_USE_8BIT 1
55 #define SMC_CAN_USE_16BIT 1
56 #define SMC_CAN_USE_32BIT 1
57 #define SMC_NOWAIT 1
58
59 #define SMC_IO_SHIFT (lp->io_shift)
60
61 #define SMC_inb(a, r) readb((a) + (r))
62 #define SMC_inw(a, r) readw((a) + (r))
63 #define SMC_inl(a, r) readl((a) + (r))
64 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
65 #define SMC_outl(v, a, r) writel(v, (a) + (r))
66 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
67 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
68 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
69 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
70 #define SMC_IRQ_FLAGS (-1) /* from resource */
71
72 /* We actually can't write halfwords properly if not word aligned */
73 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
74 {
75 if (machine_is_mainstone() && reg & 2) {
76 unsigned int v = val << 16;
77 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
78 writel(v, ioaddr + (reg & ~2));
79 } else {
80 writew(val, ioaddr + reg);
81 }
82 }
83
84 #elif defined(CONFIG_BLACKFIN)
85
86 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
87 #define RPC_LSA_DEFAULT RPC_LED_100_10
88 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
89
90 # if defined (CONFIG_BFIN561_EZKIT)
91 #define SMC_CAN_USE_8BIT 0
92 #define SMC_CAN_USE_16BIT 1
93 #define SMC_CAN_USE_32BIT 1
94 #define SMC_IO_SHIFT 0
95 #define SMC_NOWAIT 1
96 #define SMC_USE_BFIN_DMA 0
97
98
99 #define SMC_inw(a, r) readw((a) + (r))
100 #define SMC_outw(v, a, r) writew(v, (a) + (r))
101 #define SMC_inl(a, r) readl((a) + (r))
102 #define SMC_outl(v, a, r) writel(v, (a) + (r))
103 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
104 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
105 # else
106 #define SMC_CAN_USE_8BIT 0
107 #define SMC_CAN_USE_16BIT 1
108 #define SMC_CAN_USE_32BIT 0
109 #define SMC_IO_SHIFT 0
110 #define SMC_NOWAIT 1
111 #define SMC_USE_BFIN_DMA 0
112
113
114 #define SMC_inw(a, r) readw((a) + (r))
115 #define SMC_outw(v, a, r) writew(v, (a) + (r))
116 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
117 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
118 # endif
119 /* check if the mac in reg is valid */
120 #define SMC_GET_MAC_ADDR(lp, addr) \
121 do { \
122 unsigned int __v; \
123 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
124 addr[0] = __v; addr[1] = __v >> 8; \
125 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
126 addr[2] = __v; addr[3] = __v >> 8; \
127 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
128 addr[4] = __v; addr[5] = __v >> 8; \
129 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
130 random_ether_addr(addr); \
131 } \
132 } while (0)
133 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
134
135 /* We can only do 16-bit reads and writes in the static memory space. */
136 #define SMC_CAN_USE_8BIT 0
137 #define SMC_CAN_USE_16BIT 1
138 #define SMC_CAN_USE_32BIT 0
139 #define SMC_NOWAIT 1
140
141 #define SMC_IO_SHIFT 0
142
143 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
144 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
145 #define SMC_insw(a, r, p, l) \
146 do { \
147 unsigned long __port = (a) + (r); \
148 u16 *__p = (u16 *)(p); \
149 int __l = (l); \
150 insw(__port, __p, __l); \
151 while (__l > 0) { \
152 *__p = swab16(*__p); \
153 __p++; \
154 __l--; \
155 } \
156 } while (0)
157 #define SMC_outsw(a, r, p, l) \
158 do { \
159 unsigned long __port = (a) + (r); \
160 u16 *__p = (u16 *)(p); \
161 int __l = (l); \
162 while (__l > 0) { \
163 /* Believe it or not, the swab isn't needed. */ \
164 outw( /* swab16 */ (*__p++), __port); \
165 __l--; \
166 } \
167 } while (0)
168 #define SMC_IRQ_FLAGS (0)
169
170 #elif defined(CONFIG_SA1100_PLEB)
171 /* We can only do 16-bit reads and writes in the static memory space. */
172 #define SMC_CAN_USE_8BIT 1
173 #define SMC_CAN_USE_16BIT 1
174 #define SMC_CAN_USE_32BIT 0
175 #define SMC_IO_SHIFT 0
176 #define SMC_NOWAIT 1
177
178 #define SMC_inb(a, r) readb((a) + (r))
179 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
180 #define SMC_inw(a, r) readw((a) + (r))
181 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
182 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
183 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
184 #define SMC_outw(v, a, r) writew(v, (a) + (r))
185 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
186
187 #define SMC_IRQ_FLAGS (-1)
188
189 #elif defined(CONFIG_SA1100_ASSABET)
190
191 #include <mach/neponset.h>
192
193 /* We can only do 8-bit reads and writes in the static memory space. */
194 #define SMC_CAN_USE_8BIT 1
195 #define SMC_CAN_USE_16BIT 0
196 #define SMC_CAN_USE_32BIT 0
197 #define SMC_NOWAIT 1
198
199 /* The first two address lines aren't connected... */
200 #define SMC_IO_SHIFT 2
201
202 #define SMC_inb(a, r) readb((a) + (r))
203 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
204 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
205 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
206 #define SMC_IRQ_FLAGS (-1) /* from resource */
207
208 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
209
210 #define SMC_CAN_USE_8BIT 0
211 #define SMC_CAN_USE_16BIT 1
212 #define SMC_CAN_USE_32BIT 0
213 #define SMC_IO_SHIFT 0
214 #define SMC_NOWAIT 1
215
216 #define SMC_inw(a, r) readw((a) + (r))
217 #define SMC_outw(v, a, r) writew(v, (a) + (r))
218 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
219 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
220
221 #elif defined(CONFIG_ARCH_INNOKOM) || \
222 defined(CONFIG_ARCH_PXA_IDP) || \
223 defined(CONFIG_ARCH_RAMSES) || \
224 defined(CONFIG_ARCH_PCM027)
225
226 #define SMC_CAN_USE_8BIT 1
227 #define SMC_CAN_USE_16BIT 1
228 #define SMC_CAN_USE_32BIT 1
229 #define SMC_IO_SHIFT 0
230 #define SMC_NOWAIT 1
231 #define SMC_USE_PXA_DMA 1
232
233 #define SMC_inb(a, r) readb((a) + (r))
234 #define SMC_inw(a, r) readw((a) + (r))
235 #define SMC_inl(a, r) readl((a) + (r))
236 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
237 #define SMC_outl(v, a, r) writel(v, (a) + (r))
238 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
239 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
240 #define SMC_IRQ_FLAGS (-1) /* from resource */
241
242 /* We actually can't write halfwords properly if not word aligned */
243 static inline void
244 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
245 {
246 if (reg & 2) {
247 unsigned int v = val << 16;
248 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
249 writel(v, ioaddr + (reg & ~2));
250 } else {
251 writew(val, ioaddr + reg);
252 }
253 }
254
255 #elif defined(CONFIG_ARCH_OMAP)
256
257 /* We can only do 16-bit reads and writes in the static memory space. */
258 #define SMC_CAN_USE_8BIT 0
259 #define SMC_CAN_USE_16BIT 1
260 #define SMC_CAN_USE_32BIT 0
261 #define SMC_IO_SHIFT 0
262 #define SMC_NOWAIT 1
263
264 #define SMC_inw(a, r) readw((a) + (r))
265 #define SMC_outw(v, a, r) writew(v, (a) + (r))
266 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
267 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
268 #define SMC_IRQ_FLAGS (-1) /* from resource */
269
270 #elif defined(CONFIG_SH_SH4202_MICRODEV)
271
272 #define SMC_CAN_USE_8BIT 0
273 #define SMC_CAN_USE_16BIT 1
274 #define SMC_CAN_USE_32BIT 0
275
276 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
277 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
278 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
279 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
280 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
281 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
282 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
283 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
284 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
285 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
286
287 #define SMC_IRQ_FLAGS (0)
288
289 #elif defined(CONFIG_ISA)
290
291 #define SMC_CAN_USE_8BIT 1
292 #define SMC_CAN_USE_16BIT 1
293 #define SMC_CAN_USE_32BIT 0
294
295 #define SMC_inb(a, r) inb((a) + (r))
296 #define SMC_inw(a, r) inw((a) + (r))
297 #define SMC_outb(v, a, r) outb(v, (a) + (r))
298 #define SMC_outw(v, a, r) outw(v, (a) + (r))
299 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
300 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
301
302 #elif defined(CONFIG_M32R)
303
304 #define SMC_CAN_USE_8BIT 0
305 #define SMC_CAN_USE_16BIT 1
306 #define SMC_CAN_USE_32BIT 0
307
308 #define SMC_inb(a, r) inb(((u32)a) + (r))
309 #define SMC_inw(a, r) inw(((u32)a) + (r))
310 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
311 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
312 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
313 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
314
315 #define SMC_IRQ_FLAGS (0)
316
317 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
318 #define RPC_LSB_DEFAULT RPC_LED_100_10
319
320 #elif defined(CONFIG_MACH_LPD79520) \
321 || defined(CONFIG_MACH_LPD7A400) \
322 || defined(CONFIG_MACH_LPD7A404)
323
324 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
325 * way that the CPU handles chip selects and the way that the SMC chip
326 * expects the chip select to operate. Refer to
327 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
328 * IOBARRIER is a byte, in order that we read the least-common
329 * denominator. It would be wasteful to read 32 bits from an 8-bit
330 * accessible region.
331 *
332 * There is no explicit protection against interrupts intervening
333 * between the writew and the IOBARRIER. In SMC ISR there is a
334 * preamble that performs an IOBARRIER in the extremely unlikely event
335 * that the driver interrupts itself between a writew to the chip an
336 * the IOBARRIER that follows *and* the cache is large enough that the
337 * first off-chip access while handing the interrupt is to the SMC
338 * chip. Other devices in the same address space as the SMC chip must
339 * be aware of the potential for trouble and perform a similar
340 * IOBARRIER on entry to their ISR.
341 */
342
343 #include <mach/constants.h> /* IOBARRIER_VIRT */
344
345 #define SMC_CAN_USE_8BIT 0
346 #define SMC_CAN_USE_16BIT 1
347 #define SMC_CAN_USE_32BIT 0
348 #define SMC_NOWAIT 0
349 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
350
351 #define SMC_inw(a,r)\
352 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
353 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
354
355 #define SMC_insw LPD7_SMC_insw
356 static inline void LPD7_SMC_insw (unsigned char* a, int r,
357 unsigned char* p, int l)
358 {
359 unsigned short* ps = (unsigned short*) p;
360 while (l-- > 0) {
361 *ps++ = readw (a + r);
362 LPD7X_IOBARRIER;
363 }
364 }
365
366 #define SMC_outsw LPD7_SMC_outsw
367 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
368 unsigned char* p, int l)
369 {
370 unsigned short* ps = (unsigned short*) p;
371 while (l-- > 0) {
372 writew (*ps++, a + r);
373 LPD7X_IOBARRIER;
374 }
375 }
376
377 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
378
379 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
380 #define RPC_LSB_DEFAULT RPC_LED_100_10
381
382 #elif defined(CONFIG_SOC_AU1X00)
383
384 #include <au1xxx.h>
385
386 /* We can only do 16-bit reads and writes in the static memory space. */
387 #define SMC_CAN_USE_8BIT 0
388 #define SMC_CAN_USE_16BIT 1
389 #define SMC_CAN_USE_32BIT 0
390 #define SMC_IO_SHIFT 0
391 #define SMC_NOWAIT 1
392
393 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
394 #define SMC_insw(a, r, p, l) \
395 do { \
396 unsigned long _a = (unsigned long)((a) + (r)); \
397 int _l = (l); \
398 u16 *_p = (u16 *)(p); \
399 while (_l-- > 0) \
400 *_p++ = au_readw(_a); \
401 } while(0)
402 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
403 #define SMC_outsw(a, r, p, l) \
404 do { \
405 unsigned long _a = (unsigned long)((a) + (r)); \
406 int _l = (l); \
407 const u16 *_p = (const u16 *)(p); \
408 while (_l-- > 0) \
409 au_writew(*_p++ , _a); \
410 } while(0)
411
412 #define SMC_IRQ_FLAGS (0)
413
414 #elif defined(CONFIG_ARCH_VERSATILE)
415
416 #define SMC_CAN_USE_8BIT 1
417 #define SMC_CAN_USE_16BIT 1
418 #define SMC_CAN_USE_32BIT 1
419 #define SMC_NOWAIT 1
420
421 #define SMC_inb(a, r) readb((a) + (r))
422 #define SMC_inw(a, r) readw((a) + (r))
423 #define SMC_inl(a, r) readl((a) + (r))
424 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
425 #define SMC_outw(v, a, r) writew(v, (a) + (r))
426 #define SMC_outl(v, a, r) writel(v, (a) + (r))
427 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
428 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
429 #define SMC_IRQ_FLAGS (-1) /* from resource */
430
431 #elif defined(CONFIG_MN10300)
432
433 /*
434 * MN10300/AM33 configuration
435 */
436
437 #include <asm/unit/smc91111.h>
438
439 #else
440
441 /*
442 * Default configuration
443 */
444
445 #define SMC_CAN_USE_8BIT 1
446 #define SMC_CAN_USE_16BIT 1
447 #define SMC_CAN_USE_32BIT 1
448 #define SMC_NOWAIT 1
449
450 #define SMC_IO_SHIFT (lp->io_shift)
451
452 #define SMC_inb(a, r) readb((a) + (r))
453 #define SMC_inw(a, r) readw((a) + (r))
454 #define SMC_inl(a, r) readl((a) + (r))
455 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
456 #define SMC_outw(v, a, r) writew(v, (a) + (r))
457 #define SMC_outl(v, a, r) writel(v, (a) + (r))
458 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
459 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
460 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
461 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
462
463 #define RPC_LSA_DEFAULT RPC_LED_100_10
464 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
465
466 #endif
467
468
469 /* store this information for the driver.. */
470 struct smc_local {
471 /*
472 * If I have to wait until memory is available to send a
473 * packet, I will store the skbuff here, until I get the
474 * desired memory. Then, I'll send it out and free it.
475 */
476 struct sk_buff *pending_tx_skb;
477 struct tasklet_struct tx_task;
478
479 /* version/revision of the SMC91x chip */
480 int version;
481
482 /* Contains the current active transmission mode */
483 int tcr_cur_mode;
484
485 /* Contains the current active receive mode */
486 int rcr_cur_mode;
487
488 /* Contains the current active receive/phy mode */
489 int rpc_cur_mode;
490 int ctl_rfduplx;
491 int ctl_rspeed;
492
493 u32 msg_enable;
494 u32 phy_type;
495 struct mii_if_info mii;
496
497 /* work queue */
498 struct work_struct phy_configure;
499 struct net_device *dev;
500 int work_pending;
501
502 spinlock_t lock;
503
504 #ifdef CONFIG_ARCH_PXA
505 /* DMA needs the physical address of the chip */
506 u_long physaddr;
507 struct device *device;
508 #endif
509 void __iomem *base;
510 void __iomem *datacs;
511
512 /* the low address lines on some platforms aren't connected... */
513 int io_shift;
514
515 struct smc91x_platdata cfg;
516 };
517
518 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
519 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
520 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
521
522 #ifdef CONFIG_ARCH_PXA
523 /*
524 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
525 * always happening in irq context so no need to worry about races. TX is
526 * different and probably not worth it for that reason, and not as critical
527 * as RX which can overrun memory and lose packets.
528 */
529 #include <linux/dma-mapping.h>
530 #include <asm/dma.h>
531 #include <mach/pxa-regs.h>
532
533 #ifdef SMC_insl
534 #undef SMC_insl
535 #define SMC_insl(a, r, p, l) \
536 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
537 static inline void
538 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
539 u_char *buf, int len)
540 {
541 u_long physaddr = lp->physaddr;
542 dma_addr_t dmabuf;
543
544 /* fallback if no DMA available */
545 if (dma == (unsigned char)-1) {
546 readsl(ioaddr + reg, buf, len);
547 return;
548 }
549
550 /* 64 bit alignment is required for memory to memory DMA */
551 if ((long)buf & 4) {
552 *((u32 *)buf) = SMC_inl(ioaddr, reg);
553 buf += 4;
554 len--;
555 }
556
557 len *= 4;
558 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
559 DCSR(dma) = DCSR_NODESC;
560 DTADR(dma) = dmabuf;
561 DSADR(dma) = physaddr + reg;
562 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
563 DCMD_WIDTH4 | (DCMD_LENGTH & len));
564 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
565 while (!(DCSR(dma) & DCSR_STOPSTATE))
566 cpu_relax();
567 DCSR(dma) = 0;
568 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
569 }
570 #endif
571
572 #ifdef SMC_insw
573 #undef SMC_insw
574 #define SMC_insw(a, r, p, l) \
575 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
576 static inline void
577 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
578 u_char *buf, int len)
579 {
580 u_long physaddr = lp->physaddr;
581 dma_addr_t dmabuf;
582
583 /* fallback if no DMA available */
584 if (dma == (unsigned char)-1) {
585 readsw(ioaddr + reg, buf, len);
586 return;
587 }
588
589 /* 64 bit alignment is required for memory to memory DMA */
590 while ((long)buf & 6) {
591 *((u16 *)buf) = SMC_inw(ioaddr, reg);
592 buf += 2;
593 len--;
594 }
595
596 len *= 2;
597 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
598 DCSR(dma) = DCSR_NODESC;
599 DTADR(dma) = dmabuf;
600 DSADR(dma) = physaddr + reg;
601 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
602 DCMD_WIDTH2 | (DCMD_LENGTH & len));
603 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
604 while (!(DCSR(dma) & DCSR_STOPSTATE))
605 cpu_relax();
606 DCSR(dma) = 0;
607 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
608 }
609 #endif
610
611 static void
612 smc_pxa_dma_irq(int dma, void *dummy)
613 {
614 DCSR(dma) = 0;
615 }
616 #endif /* CONFIG_ARCH_PXA */
617
618
619 /*
620 * Everything a particular hardware setup needs should have been defined
621 * at this point. Add stubs for the undefined cases, mainly to avoid
622 * compilation warnings since they'll be optimized away, or to prevent buggy
623 * use of them.
624 */
625
626 #if ! SMC_CAN_USE_32BIT
627 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
628 #define SMC_outl(x, ioaddr, reg) BUG()
629 #define SMC_insl(a, r, p, l) BUG()
630 #define SMC_outsl(a, r, p, l) BUG()
631 #endif
632
633 #if !defined(SMC_insl) || !defined(SMC_outsl)
634 #define SMC_insl(a, r, p, l) BUG()
635 #define SMC_outsl(a, r, p, l) BUG()
636 #endif
637
638 #if ! SMC_CAN_USE_16BIT
639
640 /*
641 * Any 16-bit access is performed with two 8-bit accesses if the hardware
642 * can't do it directly. Most registers are 16-bit so those are mandatory.
643 */
644 #define SMC_outw(x, ioaddr, reg) \
645 do { \
646 unsigned int __val16 = (x); \
647 SMC_outb( __val16, ioaddr, reg ); \
648 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
649 } while (0)
650 #define SMC_inw(ioaddr, reg) \
651 ({ \
652 unsigned int __val16; \
653 __val16 = SMC_inb( ioaddr, reg ); \
654 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
655 __val16; \
656 })
657
658 #define SMC_insw(a, r, p, l) BUG()
659 #define SMC_outsw(a, r, p, l) BUG()
660
661 #endif
662
663 #if !defined(SMC_insw) || !defined(SMC_outsw)
664 #define SMC_insw(a, r, p, l) BUG()
665 #define SMC_outsw(a, r, p, l) BUG()
666 #endif
667
668 #if ! SMC_CAN_USE_8BIT
669 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
670 #define SMC_outb(x, ioaddr, reg) BUG()
671 #define SMC_insb(a, r, p, l) BUG()
672 #define SMC_outsb(a, r, p, l) BUG()
673 #endif
674
675 #if !defined(SMC_insb) || !defined(SMC_outsb)
676 #define SMC_insb(a, r, p, l) BUG()
677 #define SMC_outsb(a, r, p, l) BUG()
678 #endif
679
680 #ifndef SMC_CAN_USE_DATACS
681 #define SMC_CAN_USE_DATACS 0
682 #endif
683
684 #ifndef SMC_IO_SHIFT
685 #define SMC_IO_SHIFT 0
686 #endif
687
688 #ifndef SMC_IRQ_FLAGS
689 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
690 #endif
691
692 #ifndef SMC_INTERRUPT_PREAMBLE
693 #define SMC_INTERRUPT_PREAMBLE
694 #endif
695
696
697 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
698 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
699 #define SMC_DATA_EXTENT (4)
700
701 /*
702 . Bank Select Register:
703 .
704 . yyyy yyyy 0000 00xx
705 . xx = bank number
706 . yyyy yyyy = 0x33, for identification purposes.
707 */
708 #define BANK_SELECT (14 << SMC_IO_SHIFT)
709
710
711 // Transmit Control Register
712 /* BANK 0 */
713 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
714 #define TCR_ENABLE 0x0001 // When 1 we can transmit
715 #define TCR_LOOP 0x0002 // Controls output pin LBK
716 #define TCR_FORCOL 0x0004 // When 1 will force a collision
717 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
718 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
719 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
720 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
721 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
722 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
723 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
724
725 #define TCR_CLEAR 0 /* do NOTHING */
726 /* the default settings for the TCR register : */
727 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
728
729
730 // EPH Status Register
731 /* BANK 0 */
732 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
733 #define ES_TX_SUC 0x0001 // Last TX was successful
734 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
735 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
736 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
737 #define ES_16COL 0x0010 // 16 Collisions Reached
738 #define ES_SQET 0x0020 // Signal Quality Error Test
739 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
740 #define ES_TXDEFR 0x0080 // Transmit Deferred
741 #define ES_LATCOL 0x0200 // Late collision detected on last tx
742 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
743 #define ES_EXC_DEF 0x0800 // Excessive Deferral
744 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
745 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
746 #define ES_TXUNRN 0x8000 // Tx Underrun
747
748
749 // Receive Control Register
750 /* BANK 0 */
751 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
752 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
753 #define RCR_PRMS 0x0002 // Enable promiscuous mode
754 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
755 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
756 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
757 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
758 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
759 #define RCR_SOFTRST 0x8000 // resets the chip
760
761 /* the normal settings for the RCR register : */
762 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
763 #define RCR_CLEAR 0x0 // set it to a base state
764
765
766 // Counter Register
767 /* BANK 0 */
768 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
769
770
771 // Memory Information Register
772 /* BANK 0 */
773 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
774
775
776 // Receive/Phy Control Register
777 /* BANK 0 */
778 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
779 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
780 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
781 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
782 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
783 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
784
785 #ifndef RPC_LSA_DEFAULT
786 #define RPC_LSA_DEFAULT RPC_LED_100
787 #endif
788 #ifndef RPC_LSB_DEFAULT
789 #define RPC_LSB_DEFAULT RPC_LED_FD
790 #endif
791
792 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
793
794
795 /* Bank 0 0x0C is reserved */
796
797 // Bank Select Register
798 /* All Banks */
799 #define BSR_REG 0x000E
800
801
802 // Configuration Reg
803 /* BANK 1 */
804 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
805 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
806 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
807 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
808 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
809
810 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
811 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
812
813
814 // Base Address Register
815 /* BANK 1 */
816 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
817
818
819 // Individual Address Registers
820 /* BANK 1 */
821 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
822 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
823 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
824
825
826 // General Purpose Register
827 /* BANK 1 */
828 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
829
830
831 // Control Register
832 /* BANK 1 */
833 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
834 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
835 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
836 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
837 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
838 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
839 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
840 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
841 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
842
843
844 // MMU Command Register
845 /* BANK 2 */
846 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
847 #define MC_BUSY 1 // When 1 the last release has not completed
848 #define MC_NOP (0<<5) // No Op
849 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
850 #define MC_RESET (2<<5) // Reset MMU to initial state
851 #define MC_REMOVE (3<<5) // Remove the current rx packet
852 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
853 #define MC_FREEPKT (5<<5) // Release packet in PNR register
854 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
855 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
856
857
858 // Packet Number Register
859 /* BANK 2 */
860 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
861
862
863 // Allocation Result Register
864 /* BANK 2 */
865 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
866 #define AR_FAILED 0x80 // Alocation Failed
867
868
869 // TX FIFO Ports Register
870 /* BANK 2 */
871 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
872 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
873
874 // RX FIFO Ports Register
875 /* BANK 2 */
876 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
877 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
878
879 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
880
881 // Pointer Register
882 /* BANK 2 */
883 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
884 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
885 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
886 #define PTR_READ 0x2000 // When 1 the operation is a read
887
888
889 // Data Register
890 /* BANK 2 */
891 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
892
893
894 // Interrupt Status/Acknowledge Register
895 /* BANK 2 */
896 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
897
898
899 // Interrupt Mask Register
900 /* BANK 2 */
901 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
902 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
903 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
904 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
905 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
906 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
907 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
908 #define IM_TX_INT 0x02 // Transmit Interrupt
909 #define IM_RCV_INT 0x01 // Receive Interrupt
910
911
912 // Multicast Table Registers
913 /* BANK 3 */
914 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
915 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
916 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
917 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
918
919
920 // Management Interface Register (MII)
921 /* BANK 3 */
922 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
923 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
924 #define MII_MDOE 0x0008 // MII Output Enable
925 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
926 #define MII_MDI 0x0002 // MII Input, pin MDI
927 #define MII_MDO 0x0001 // MII Output, pin MDO
928
929
930 // Revision Register
931 /* BANK 3 */
932 /* ( hi: chip id low: rev # ) */
933 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
934
935
936 // Early RCV Register
937 /* BANK 3 */
938 /* this is NOT on SMC9192 */
939 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
940 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
941 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
942
943
944 // External Register
945 /* BANK 7 */
946 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
947
948
949 #define CHIP_9192 3
950 #define CHIP_9194 4
951 #define CHIP_9195 5
952 #define CHIP_9196 6
953 #define CHIP_91100 7
954 #define CHIP_91100FD 8
955 #define CHIP_91111FD 9
956
957 static const char * chip_ids[ 16 ] = {
958 NULL, NULL, NULL,
959 /* 3 */ "SMC91C90/91C92",
960 /* 4 */ "SMC91C94",
961 /* 5 */ "SMC91C95",
962 /* 6 */ "SMC91C96",
963 /* 7 */ "SMC91C100",
964 /* 8 */ "SMC91C100FD",
965 /* 9 */ "SMC91C11xFD",
966 NULL, NULL, NULL,
967 NULL, NULL, NULL};
968
969
970 /*
971 . Receive status bits
972 */
973 #define RS_ALGNERR 0x8000
974 #define RS_BRODCAST 0x4000
975 #define RS_BADCRC 0x2000
976 #define RS_ODDFRAME 0x1000
977 #define RS_TOOLONG 0x0800
978 #define RS_TOOSHORT 0x0400
979 #define RS_MULTICAST 0x0001
980 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
981
982
983 /*
984 * PHY IDs
985 * LAN83C183 == LAN91C111 Internal PHY
986 */
987 #define PHY_LAN83C183 0x0016f840
988 #define PHY_LAN83C180 0x02821c50
989
990 /*
991 * PHY Register Addresses (LAN91C111 Internal PHY)
992 *
993 * Generic PHY registers can be found in <linux/mii.h>
994 *
995 * These phy registers are specific to our on-board phy.
996 */
997
998 // PHY Configuration Register 1
999 #define PHY_CFG1_REG 0x10
1000 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1001 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1002 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1003 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1004 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1005 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1006 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1007 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1008 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1009 #define PHY_CFG1_TLVL_MASK 0x003C
1010 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1011
1012
1013 // PHY Configuration Register 2
1014 #define PHY_CFG2_REG 0x11
1015 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1016 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1017 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1018 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1019
1020 // PHY Status Output (and Interrupt status) Register
1021 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1022 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1023 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1024 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1025 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1026 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1027 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1028 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1029 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1030 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1031 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1032
1033 // PHY Interrupt/Status Mask Register
1034 #define PHY_MASK_REG 0x13 // Interrupt Mask
1035 // Uses the same bit definitions as PHY_INT_REG
1036
1037
1038 /*
1039 * SMC91C96 ethernet config and status registers.
1040 * These are in the "attribute" space.
1041 */
1042 #define ECOR 0x8000
1043 #define ECOR_RESET 0x80
1044 #define ECOR_LEVEL_IRQ 0x40
1045 #define ECOR_WR_ATTRIB 0x04
1046 #define ECOR_ENABLE 0x01
1047
1048 #define ECSR 0x8002
1049 #define ECSR_IOIS8 0x20
1050 #define ECSR_PWRDWN 0x04
1051 #define ECSR_INT 0x02
1052
1053 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1054
1055
1056 /*
1057 * Macros to abstract register access according to the data bus
1058 * capabilities. Please use those and not the in/out primitives.
1059 * Note: the following macros do *not* select the bank -- this must
1060 * be done separately as needed in the main code. The SMC_REG() macro
1061 * only uses the bank argument for debugging purposes (when enabled).
1062 *
1063 * Note: despite inline functions being safer, everything leading to this
1064 * should preferably be macros to let BUG() display the line number in
1065 * the core source code since we're interested in the top call site
1066 * not in any inline function location.
1067 */
1068
1069 #if SMC_DEBUG > 0
1070 #define SMC_REG(lp, reg, bank) \
1071 ({ \
1072 int __b = SMC_CURRENT_BANK(lp); \
1073 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1074 printk( "%s: bank reg screwed (0x%04x)\n", \
1075 CARDNAME, __b ); \
1076 BUG(); \
1077 } \
1078 reg<<SMC_IO_SHIFT; \
1079 })
1080 #else
1081 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1082 #endif
1083
1084 /*
1085 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1086 * aligned to a 32 bit boundary. I tell you that does exist!
1087 * Fortunately the affected register accesses can be easily worked around
1088 * since we can write zeroes to the preceeding 16 bits without adverse
1089 * effects and use a 32-bit access.
1090 *
1091 * Enforce it on any 32-bit capable setup for now.
1092 */
1093 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1094
1095 #define SMC_GET_PN(lp) \
1096 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1097 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1098
1099 #define SMC_SET_PN(lp, x) \
1100 do { \
1101 if (SMC_MUST_ALIGN_WRITE(lp)) \
1102 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1103 else if (SMC_8BIT(lp)) \
1104 SMC_outb(x, ioaddr, PN_REG(lp)); \
1105 else \
1106 SMC_outw(x, ioaddr, PN_REG(lp)); \
1107 } while (0)
1108
1109 #define SMC_GET_AR(lp) \
1110 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1111 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1112
1113 #define SMC_GET_TXFIFO(lp) \
1114 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1115 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1116
1117 #define SMC_GET_RXFIFO(lp) \
1118 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1119 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1120
1121 #define SMC_GET_INT(lp) \
1122 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1123 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1124
1125 #define SMC_ACK_INT(lp, x) \
1126 do { \
1127 if (SMC_8BIT(lp)) \
1128 SMC_outb(x, ioaddr, INT_REG(lp)); \
1129 else { \
1130 unsigned long __flags; \
1131 int __mask; \
1132 local_irq_save(__flags); \
1133 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1134 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1135 local_irq_restore(__flags); \
1136 } \
1137 } while (0)
1138
1139 #define SMC_GET_INT_MASK(lp) \
1140 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1141 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1142
1143 #define SMC_SET_INT_MASK(lp, x) \
1144 do { \
1145 if (SMC_8BIT(lp)) \
1146 SMC_outb(x, ioaddr, IM_REG(lp)); \
1147 else \
1148 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1149 } while (0)
1150
1151 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1152
1153 #define SMC_SELECT_BANK(lp, x) \
1154 do { \
1155 if (SMC_MUST_ALIGN_WRITE(lp)) \
1156 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1157 else \
1158 SMC_outw(x, ioaddr, BANK_SELECT); \
1159 } while (0)
1160
1161 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1162
1163 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1164
1165 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1166
1167 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1168
1169 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1170
1171 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1172
1173 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1174
1175 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1176
1177 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1178
1179 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1180
1181 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1182
1183 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1184
1185 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1186
1187 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1188
1189 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1190
1191 #define SMC_SET_PTR(lp, x) \
1192 do { \
1193 if (SMC_MUST_ALIGN_WRITE(lp)) \
1194 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1195 else \
1196 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1197 } while (0)
1198
1199 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1200
1201 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1202
1203 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1204
1205 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1206
1207 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1208
1209 #define SMC_SET_RPC(lp, x) \
1210 do { \
1211 if (SMC_MUST_ALIGN_WRITE(lp)) \
1212 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1213 else \
1214 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1215 } while (0)
1216
1217 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1218
1219 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1220
1221 #ifndef SMC_GET_MAC_ADDR
1222 #define SMC_GET_MAC_ADDR(lp, addr) \
1223 do { \
1224 unsigned int __v; \
1225 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1226 addr[0] = __v; addr[1] = __v >> 8; \
1227 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1228 addr[2] = __v; addr[3] = __v >> 8; \
1229 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1230 addr[4] = __v; addr[5] = __v >> 8; \
1231 } while (0)
1232 #endif
1233
1234 #define SMC_SET_MAC_ADDR(lp, addr) \
1235 do { \
1236 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1237 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1238 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1239 } while (0)
1240
1241 #define SMC_SET_MCAST(lp, x) \
1242 do { \
1243 const unsigned char *mt = (x); \
1244 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1245 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1246 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1247 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1248 } while (0)
1249
1250 #define SMC_PUT_PKT_HDR(lp, status, length) \
1251 do { \
1252 if (SMC_32BIT(lp)) \
1253 SMC_outl((status) | (length)<<16, ioaddr, \
1254 DATA_REG(lp)); \
1255 else { \
1256 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1257 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1258 } \
1259 } while (0)
1260
1261 #define SMC_GET_PKT_HDR(lp, status, length) \
1262 do { \
1263 if (SMC_32BIT(lp)) { \
1264 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1265 (status) = __val & 0xffff; \
1266 (length) = __val >> 16; \
1267 } else { \
1268 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1269 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1270 } \
1271 } while (0)
1272
1273 #define SMC_PUSH_DATA(lp, p, l) \
1274 do { \
1275 if (SMC_32BIT(lp)) { \
1276 void *__ptr = (p); \
1277 int __len = (l); \
1278 void __iomem *__ioaddr = ioaddr; \
1279 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1280 __len -= 2; \
1281 SMC_outw(*(u16 *)__ptr, ioaddr, \
1282 DATA_REG(lp)); \
1283 __ptr += 2; \
1284 } \
1285 if (SMC_CAN_USE_DATACS && lp->datacs) \
1286 __ioaddr = lp->datacs; \
1287 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1288 if (__len & 2) { \
1289 __ptr += (__len & ~3); \
1290 SMC_outw(*((u16 *)__ptr), ioaddr, \
1291 DATA_REG(lp)); \
1292 } \
1293 } else if (SMC_16BIT(lp)) \
1294 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1295 else if (SMC_8BIT(lp)) \
1296 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1297 } while (0)
1298
1299 #define SMC_PULL_DATA(lp, p, l) \
1300 do { \
1301 if (SMC_32BIT(lp)) { \
1302 void *__ptr = (p); \
1303 int __len = (l); \
1304 void __iomem *__ioaddr = ioaddr; \
1305 if ((unsigned long)__ptr & 2) { \
1306 /* \
1307 * We want 32bit alignment here. \
1308 * Since some buses perform a full \
1309 * 32bit fetch even for 16bit data \
1310 * we can't use SMC_inw() here. \
1311 * Back both source (on-chip) and \
1312 * destination pointers of 2 bytes. \
1313 * This is possible since the call to \
1314 * SMC_GET_PKT_HDR() already advanced \
1315 * the source pointer of 4 bytes, and \
1316 * the skb_reserve(skb, 2) advanced \
1317 * the destination pointer of 2 bytes. \
1318 */ \
1319 __ptr -= 2; \
1320 __len += 2; \
1321 SMC_SET_PTR(lp, \
1322 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1323 } \
1324 if (SMC_CAN_USE_DATACS && lp->datacs) \
1325 __ioaddr = lp->datacs; \
1326 __len += 2; \
1327 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1328 } else if (SMC_16BIT(lp)) \
1329 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1330 else if (SMC_8BIT(lp)) \
1331 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1332 } while (0)
1333
1334 #endif /* _SMC91X_H_ */