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xtensa: use the new byteorder headers
[pohmelfs.git] / drivers / net / epic100.c
blob76118ddd104272f82f194746739ceacbb102c017
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
23
24 ---------------------------------------------------------------------
25
26 */
27
28 #define DRV_NAME "epic100"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sept 11, 2006"
31
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37 /* Used to pass the full-duplex flag, etc. */
38 #define MAX_UNITS 8 /* More are supported, limit only on options */
39 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44 static int rx_copybreak;
45
46 /* Operational parameters that are set at compile time. */
47
48 /* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53 #define TX_RING_SIZE 256
54 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55 #define RX_RING_SIZE 256
56 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59 /* Operational parameters that usually are not changed. */
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (2*HZ)
62
63 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65 /* Bytes transferred to chip before transmission starts. */
66 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67 #define TX_FIFO_THRESH 256
68 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/slab.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/delay.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/spinlock.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89 #include <asm/io.h>
90 #include <asm/uaccess.h>
91
92 /* These identify the driver base version and may not be removed. */
93 static char version[] __devinitdata =
94 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95 static char version2[] __devinitdata =
96 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100 MODULE_LICENSE("GPL");
101
102 module_param(debug, int, 0);
103 module_param(rx_copybreak, int, 0);
104 module_param_array(options, int, NULL, 0);
105 module_param_array(full_duplex, int, NULL, 0);
106 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111 /*
112 Theory of Operation
113
114 I. Board Compatibility
115
116 This device driver is designed for the SMC "EPIC/100", the SMC
117 single-chip Ethernet controllers for PCI. This chip is used on
118 the SMC EtherPower II boards.
119
120 II. Board-specific settings
121
122 PCI bus devices are configured by the system at boot time, so no jumpers
123 need to be set on the board. The system BIOS will assign the
124 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126 interrupt lines.
127
128 III. Driver operation
129
130 IIIa. Ring buffers
131
132 IVb. References
133
134 http://www.smsc.com/main/tools/discontinued/83c171.pdf
135 http://www.smsc.com/main/tools/discontinued/83c175.pdf
136 http://scyld.com/expert/NWay.html
137 http://www.national.com/pf/DP/DP83840A.html
138
139 IVc. Errata
140
141 */
142
143
144 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146 #define EPIC_TOTAL_SIZE 0x100
147 #define USE_IO_OPS 1
148
149 typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153 } chip_t;
154
155
156 struct epic_chip_info {
157 const char *name;
158 int drv_flags; /* Driver use, intended as capability flags. */
159 };
160
161
162 /* indexed by chip_t */
163 static const struct epic_chip_info pci_id_tbl[] = {
164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
167 };
168
169
170 static struct pci_device_id epic_pci_tbl[] = {
171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176 };
177 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
179
180 #ifndef USE_IO_OPS
181 #undef inb
182 #undef inw
183 #undef inl
184 #undef outb
185 #undef outw
186 #undef outl
187 #define inb readb
188 #define inw readw
189 #define inl readl
190 #define outb writeb
191 #define outw writew
192 #define outl writel
193 #endif
194
195 /* Offsets to registers, using the (ugh) SMC names. */
196 enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205 };
206
207 /* Interrupt register bits, using my own meaningful names. */
208 enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214 };
215 enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218 };
219
220 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222 #define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
226 static const u16 media2miictl[16] = {
227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
230 /*
231 * The EPIC100 Rx and Tx buffer descriptors. Note that these
232 * really ARE host-endian; it's not a misannotation. We tell
233 * the card to byteswap them internally on big-endian hosts -
234 * look for #ifdef CONFIG_BIG_ENDIAN in epic_open().
235 */
236
237 struct epic_tx_desc {
238 u32 txstatus;
239 u32 bufaddr;
240 u32 buflength;
241 u32 next;
242 };
243
244 struct epic_rx_desc {
245 u32 rxstatus;
246 u32 bufaddr;
247 u32 buflength;
248 u32 next;
249 };
250
251 enum desc_status_bits {
252 DescOwn=0x8000,
253 };
254
255 #define PRIV_ALIGN 15 /* Required alignment mask */
256 struct epic_private {
257 struct epic_rx_desc *rx_ring;
258 struct epic_tx_desc *tx_ring;
259 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
260 struct sk_buff* tx_skbuff[TX_RING_SIZE];
261 /* The addresses of receive-in-place skbuffs. */
262 struct sk_buff* rx_skbuff[RX_RING_SIZE];
263
264 dma_addr_t tx_ring_dma;
265 dma_addr_t rx_ring_dma;
266
267 /* Ring pointers. */
268 spinlock_t lock; /* Group with Tx control cache line. */
269 spinlock_t napi_lock;
270 struct napi_struct napi;
271 unsigned int reschedule_in_poll;
272 unsigned int cur_tx, dirty_tx;
273
274 unsigned int cur_rx, dirty_rx;
275 u32 irq_mask;
276 unsigned int rx_buf_sz; /* Based on MTU+slack. */
277
278 struct pci_dev *pci_dev; /* PCI bus location. */
279 int chip_id, chip_flags;
280
281 struct net_device_stats stats;
282 struct timer_list timer; /* Media selection timer. */
283 int tx_threshold;
284 unsigned char mc_filter[8];
285 signed char phys[4]; /* MII device addresses. */
286 u16 advertising; /* NWay media advertisement */
287 int mii_phy_cnt;
288 struct mii_if_info mii;
289 unsigned int tx_full:1; /* The Tx queue is full. */
290 unsigned int default_port:4; /* Last dev->if_port value. */
291 };
292
293 static int epic_open(struct net_device *dev);
294 static int read_eeprom(long ioaddr, int location);
295 static int mdio_read(struct net_device *dev, int phy_id, int location);
296 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
297 static void epic_restart(struct net_device *dev);
298 static void epic_timer(unsigned long data);
299 static void epic_tx_timeout(struct net_device *dev);
300 static void epic_init_ring(struct net_device *dev);
301 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
302 static int epic_rx(struct net_device *dev, int budget);
303 static int epic_poll(struct napi_struct *napi, int budget);
304 static irqreturn_t epic_interrupt(int irq, void *dev_instance);
305 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
306 static const struct ethtool_ops netdev_ethtool_ops;
307 static int epic_close(struct net_device *dev);
308 static struct net_device_stats *epic_get_stats(struct net_device *dev);
309 static void set_rx_mode(struct net_device *dev);
310
311
312
313 static int __devinit epic_init_one (struct pci_dev *pdev,
314 const struct pci_device_id *ent)
315 {
316 static int card_idx = -1;
317 long ioaddr;
318 int chip_idx = (int) ent->driver_data;
319 int irq;
320 struct net_device *dev;
321 struct epic_private *ep;
322 int i, ret, option = 0, duplex = 0;
323 void *ring_space;
324 dma_addr_t ring_dma;
325 DECLARE_MAC_BUF(mac);
326
327 /* when built into the kernel, we only print version if device is found */
328 #ifndef MODULE
329 static int printed_version;
330 if (!printed_version++)
331 printk (KERN_INFO "%s" KERN_INFO "%s",
332 version, version2);
333 #endif
334
335 card_idx++;
336
337 ret = pci_enable_device(pdev);
338 if (ret)
339 goto out;
340 irq = pdev->irq;
341
342 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
343 dev_err(&pdev->dev, "no PCI region space\n");
344 ret = -ENODEV;
345 goto err_out_disable;
346 }
347
348 pci_set_master(pdev);
349
350 ret = pci_request_regions(pdev, DRV_NAME);
351 if (ret < 0)
352 goto err_out_disable;
353
354 ret = -ENOMEM;
355
356 dev = alloc_etherdev(sizeof (*ep));
357 if (!dev) {
358 dev_err(&pdev->dev, "no memory for eth device\n");
359 goto err_out_free_res;
360 }
361 SET_NETDEV_DEV(dev, &pdev->dev);
362
363 #ifdef USE_IO_OPS
364 ioaddr = pci_resource_start (pdev, 0);
365 #else
366 ioaddr = pci_resource_start (pdev, 1);
367 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
368 if (!ioaddr) {
369 dev_err(&pdev->dev, "ioremap failed\n");
370 goto err_out_free_netdev;
371 }
372 #endif
373
374 pci_set_drvdata(pdev, dev);
375 ep = dev->priv;
376 ep->mii.dev = dev;
377 ep->mii.mdio_read = mdio_read;
378 ep->mii.mdio_write = mdio_write;
379 ep->mii.phy_id_mask = 0x1f;
380 ep->mii.reg_num_mask = 0x1f;
381
382 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
383 if (!ring_space)
384 goto err_out_iounmap;
385 ep->tx_ring = (struct epic_tx_desc *)ring_space;
386 ep->tx_ring_dma = ring_dma;
387
388 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
389 if (!ring_space)
390 goto err_out_unmap_tx;
391 ep->rx_ring = (struct epic_rx_desc *)ring_space;
392 ep->rx_ring_dma = ring_dma;
393
394 if (dev->mem_start) {
395 option = dev->mem_start;
396 duplex = (dev->mem_start & 16) ? 1 : 0;
397 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
398 if (options[card_idx] >= 0)
399 option = options[card_idx];
400 if (full_duplex[card_idx] >= 0)
401 duplex = full_duplex[card_idx];
402 }
403
404 dev->base_addr = ioaddr;
405 dev->irq = irq;
406
407 spin_lock_init(&ep->lock);
408 spin_lock_init(&ep->napi_lock);
409 ep->reschedule_in_poll = 0;
410
411 /* Bring the chip out of low-power mode. */
412 outl(0x4200, ioaddr + GENCTL);
413 /* Magic?! If we don't set this bit the MII interface won't work. */
414 /* This magic is documented in SMSC app note 7.15 */
415 for (i = 16; i > 0; i--)
416 outl(0x0008, ioaddr + TEST1);
417
418 /* Turn on the MII transceiver. */
419 outl(0x12, ioaddr + MIICfg);
420 if (chip_idx == 1)
421 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
422 outl(0x0200, ioaddr + GENCTL);
423
424 /* Note: the '175 does not have a serial EEPROM. */
425 for (i = 0; i < 3; i++)
426 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4));
427
428 if (debug > 2) {
429 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
430 for (i = 0; i < 64; i++)
431 printk(" %4.4x%s", read_eeprom(ioaddr, i),
432 i % 16 == 15 ? "\n" : "");
433 }
434
435 ep->pci_dev = pdev;
436 ep->chip_id = chip_idx;
437 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
438 ep->irq_mask =
439 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
440 | CntFull | TxUnderrun | EpicNapiEvent;
441
442 /* Find the connected MII xcvrs.
443 Doing this in open() would allow detecting external xcvrs later, but
444 takes much time and no cards have external MII. */
445 {
446 int phy, phy_idx = 0;
447 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
448 int mii_status = mdio_read(dev, phy, MII_BMSR);
449 if (mii_status != 0xffff && mii_status != 0x0000) {
450 ep->phys[phy_idx++] = phy;
451 dev_info(&pdev->dev,
452 "MII transceiver #%d control "
453 "%4.4x status %4.4x.\n",
454 phy, mdio_read(dev, phy, 0), mii_status);
455 }
456 }
457 ep->mii_phy_cnt = phy_idx;
458 if (phy_idx != 0) {
459 phy = ep->phys[0];
460 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
461 dev_info(&pdev->dev,
462 "Autonegotiation advertising %4.4x link "
463 "partner %4.4x.\n",
464 ep->mii.advertising, mdio_read(dev, phy, 5));
465 } else if ( ! (ep->chip_flags & NO_MII)) {
466 dev_warn(&pdev->dev,
467 "***WARNING***: No MII transceiver found!\n");
468 /* Use the known PHY address of the EPII. */
469 ep->phys[0] = 3;
470 }
471 ep->mii.phy_id = ep->phys[0];
472 }
473
474 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
475 if (ep->chip_flags & MII_PWRDWN)
476 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
477 outl(0x0008, ioaddr + GENCTL);
478
479 /* The lower four bits are the media type. */
480 if (duplex) {
481 ep->mii.force_media = ep->mii.full_duplex = 1;
482 dev_info(&pdev->dev, "Forced full duplex requested.\n");
483 }
484 dev->if_port = ep->default_port = option;
485
486 /* The Epic-specific entries in the device structure. */
487 dev->open = &epic_open;
488 dev->hard_start_xmit = &epic_start_xmit;
489 dev->stop = &epic_close;
490 dev->get_stats = &epic_get_stats;
491 dev->set_multicast_list = &set_rx_mode;
492 dev->do_ioctl = &netdev_ioctl;
493 dev->ethtool_ops = &netdev_ethtool_ops;
494 dev->watchdog_timeo = TX_TIMEOUT;
495 dev->tx_timeout = &epic_tx_timeout;
496 netif_napi_add(dev, &ep->napi, epic_poll, 64);
497
498 ret = register_netdev(dev);
499 if (ret < 0)
500 goto err_out_unmap_rx;
501
502 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %s\n",
503 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
504 print_mac(mac, dev->dev_addr));
505
506 out:
507 return ret;
508
509 err_out_unmap_rx:
510 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
511 err_out_unmap_tx:
512 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
513 err_out_iounmap:
514 #ifndef USE_IO_OPS
515 iounmap(ioaddr);
516 err_out_free_netdev:
517 #endif
518 free_netdev(dev);
519 err_out_free_res:
520 pci_release_regions(pdev);
521 err_out_disable:
522 pci_disable_device(pdev);
523 goto out;
524 }
525
526 /* Serial EEPROM section. */
527
528 /* EEPROM_Ctrl bits. */
529 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
530 #define EE_CS 0x02 /* EEPROM chip select. */
531 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
532 #define EE_WRITE_0 0x01
533 #define EE_WRITE_1 0x09
534 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
535 #define EE_ENB (0x0001 | EE_CS)
536
537 /* Delay between EEPROM clock transitions.
538 This serves to flush the operation to the PCI bus.
539 */
540
541 #define eeprom_delay() inl(ee_addr)
542
543 /* The EEPROM commands include the alway-set leading bit. */
544 #define EE_WRITE_CMD (5 << 6)
545 #define EE_READ64_CMD (6 << 6)
546 #define EE_READ256_CMD (6 << 8)
547 #define EE_ERASE_CMD (7 << 6)
548
549 static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
550 {
551 long ioaddr = dev->base_addr;
552
553 outl(0x00000000, ioaddr + INTMASK);
554 }
555
556 static inline void __epic_pci_commit(long ioaddr)
557 {
558 #ifndef USE_IO_OPS
559 inl(ioaddr + INTMASK);
560 #endif
561 }
562
563 static inline void epic_napi_irq_off(struct net_device *dev,
564 struct epic_private *ep)
565 {
566 long ioaddr = dev->base_addr;
567
568 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
569 __epic_pci_commit(ioaddr);
570 }
571
572 static inline void epic_napi_irq_on(struct net_device *dev,
573 struct epic_private *ep)
574 {
575 long ioaddr = dev->base_addr;
576
577 /* No need to commit possible posted write */
578 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
579 }
580
581 static int __devinit read_eeprom(long ioaddr, int location)
582 {
583 int i;
584 int retval = 0;
585 long ee_addr = ioaddr + EECTL;
586 int read_cmd = location |
587 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
588
589 outl(EE_ENB & ~EE_CS, ee_addr);
590 outl(EE_ENB, ee_addr);
591
592 /* Shift the read command bits out. */
593 for (i = 12; i >= 0; i--) {
594 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
595 outl(EE_ENB | dataval, ee_addr);
596 eeprom_delay();
597 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
598 eeprom_delay();
599 }
600 outl(EE_ENB, ee_addr);
601
602 for (i = 16; i > 0; i--) {
603 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
604 eeprom_delay();
605 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
606 outl(EE_ENB, ee_addr);
607 eeprom_delay();
608 }
609
610 /* Terminate the EEPROM access. */
611 outl(EE_ENB & ~EE_CS, ee_addr);
612 return retval;
613 }
614
615 #define MII_READOP 1
616 #define MII_WRITEOP 2
617 static int mdio_read(struct net_device *dev, int phy_id, int location)
618 {
619 long ioaddr = dev->base_addr;
620 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
621 int i;
622
623 outl(read_cmd, ioaddr + MIICtrl);
624 /* Typical operation takes 25 loops. */
625 for (i = 400; i > 0; i--) {
626 barrier();
627 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
628 /* Work around read failure bug. */
629 if (phy_id == 1 && location < 6
630 && inw(ioaddr + MIIData) == 0xffff) {
631 outl(read_cmd, ioaddr + MIICtrl);
632 continue;
633 }
634 return inw(ioaddr + MIIData);
635 }
636 }
637 return 0xffff;
638 }
639
640 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
641 {
642 long ioaddr = dev->base_addr;
643 int i;
644
645 outw(value, ioaddr + MIIData);
646 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
647 for (i = 10000; i > 0; i--) {
648 barrier();
649 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
650 break;
651 }
652 return;
653 }
654
655
656 static int epic_open(struct net_device *dev)
657 {
658 struct epic_private *ep = dev->priv;
659 long ioaddr = dev->base_addr;
660 int i;
661 int retval;
662
663 /* Soft reset the chip. */
664 outl(0x4001, ioaddr + GENCTL);
665
666 napi_enable(&ep->napi);
667 if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev))) {
668 napi_disable(&ep->napi);
669 return retval;
670 }
671
672 epic_init_ring(dev);
673
674 outl(0x4000, ioaddr + GENCTL);
675 /* This magic is documented in SMSC app note 7.15 */
676 for (i = 16; i > 0; i--)
677 outl(0x0008, ioaddr + TEST1);
678
679 /* Pull the chip out of low-power mode, enable interrupts, and set for
680 PCI read multiple. The MIIcfg setting and strange write order are
681 required by the details of which bits are reset and the transceiver
682 wiring on the Ositech CardBus card.
683 */
684 #if 0
685 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
686 #endif
687 if (ep->chip_flags & MII_PWRDWN)
688 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
689
690 /* Tell the chip to byteswap descriptors on big-endian hosts */
691 #ifdef CONFIG_BIG_ENDIAN
692 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
693 inl(ioaddr + GENCTL);
694 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
695 #else
696 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
697 inl(ioaddr + GENCTL);
698 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
699 #endif
700
701 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
702
703 for (i = 0; i < 3; i++)
704 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
705
706 ep->tx_threshold = TX_FIFO_THRESH;
707 outl(ep->tx_threshold, ioaddr + TxThresh);
708
709 if (media2miictl[dev->if_port & 15]) {
710 if (ep->mii_phy_cnt)
711 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
712 if (dev->if_port == 1) {
713 if (debug > 1)
714 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
715 "status %4.4x.\n",
716 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
717 }
718 } else {
719 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
720 if (mii_lpa != 0xffff) {
721 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
722 ep->mii.full_duplex = 1;
723 else if (! (mii_lpa & LPA_LPACK))
724 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
725 if (debug > 1)
726 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
727 " register read of %4.4x.\n", dev->name,
728 ep->mii.full_duplex ? "full" : "half",
729 ep->phys[0], mii_lpa);
730 }
731 }
732
733 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
734 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
735 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
736
737 /* Start the chip's Rx process. */
738 set_rx_mode(dev);
739 outl(StartRx | RxQueued, ioaddr + COMMAND);
740
741 netif_start_queue(dev);
742
743 /* Enable interrupts by setting the interrupt mask. */
744 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
745 | CntFull | TxUnderrun
746 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
747
748 if (debug > 1)
749 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
750 "%s-duplex.\n",
751 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
752 ep->mii.full_duplex ? "full" : "half");
753
754 /* Set the timer to switch to check for link beat and perhaps switch
755 to an alternate media type. */
756 init_timer(&ep->timer);
757 ep->timer.expires = jiffies + 3*HZ;
758 ep->timer.data = (unsigned long)dev;
759 ep->timer.function = &epic_timer; /* timer handler */
760 add_timer(&ep->timer);
761
762 return 0;
763 }
764
765 /* Reset the chip to recover from a PCI transaction error.
766 This may occur at interrupt time. */
767 static void epic_pause(struct net_device *dev)
768 {
769 long ioaddr = dev->base_addr;
770 struct epic_private *ep = dev->priv;
771
772 netif_stop_queue (dev);
773
774 /* Disable interrupts by clearing the interrupt mask. */
775 outl(0x00000000, ioaddr + INTMASK);
776 /* Stop the chip's Tx and Rx DMA processes. */
777 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
778
779 /* Update the error counts. */
780 if (inw(ioaddr + COMMAND) != 0xffff) {
781 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
782 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
783 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
784 }
785
786 /* Remove the packets on the Rx queue. */
787 epic_rx(dev, RX_RING_SIZE);
788 }
789
790 static void epic_restart(struct net_device *dev)
791 {
792 long ioaddr = dev->base_addr;
793 struct epic_private *ep = dev->priv;
794 int i;
795
796 /* Soft reset the chip. */
797 outl(0x4001, ioaddr + GENCTL);
798
799 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
800 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
801 udelay(1);
802
803 /* This magic is documented in SMSC app note 7.15 */
804 for (i = 16; i > 0; i--)
805 outl(0x0008, ioaddr + TEST1);
806
807 #ifdef CONFIG_BIG_ENDIAN
808 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
809 #else
810 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
811 #endif
812 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
813 if (ep->chip_flags & MII_PWRDWN)
814 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
815
816 for (i = 0; i < 3; i++)
817 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
818
819 ep->tx_threshold = TX_FIFO_THRESH;
820 outl(ep->tx_threshold, ioaddr + TxThresh);
821 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
822 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
823 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
824 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
825 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
826
827 /* Start the chip's Rx process. */
828 set_rx_mode(dev);
829 outl(StartRx | RxQueued, ioaddr + COMMAND);
830
831 /* Enable interrupts by setting the interrupt mask. */
832 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
833 | CntFull | TxUnderrun
834 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
835
836 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
837 " interrupt %4.4x.\n",
838 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
839 (int)inl(ioaddr + INTSTAT));
840 return;
841 }
842
843 static void check_media(struct net_device *dev)
844 {
845 struct epic_private *ep = dev->priv;
846 long ioaddr = dev->base_addr;
847 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
848 int negotiated = mii_lpa & ep->mii.advertising;
849 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
850
851 if (ep->mii.force_media)
852 return;
853 if (mii_lpa == 0xffff) /* Bogus read */
854 return;
855 if (ep->mii.full_duplex != duplex) {
856 ep->mii.full_duplex = duplex;
857 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
858 " partner capability of %4.4x.\n", dev->name,
859 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
860 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
861 }
862 }
863
864 static void epic_timer(unsigned long data)
865 {
866 struct net_device *dev = (struct net_device *)data;
867 struct epic_private *ep = dev->priv;
868 long ioaddr = dev->base_addr;
869 int next_tick = 5*HZ;
870
871 if (debug > 3) {
872 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
873 dev->name, (int)inl(ioaddr + TxSTAT));
874 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
875 "IntStatus %4.4x RxStatus %4.4x.\n",
876 dev->name, (int)inl(ioaddr + INTMASK),
877 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
878 }
879
880 check_media(dev);
881
882 ep->timer.expires = jiffies + next_tick;
883 add_timer(&ep->timer);
884 }
885
886 static void epic_tx_timeout(struct net_device *dev)
887 {
888 struct epic_private *ep = dev->priv;
889 long ioaddr = dev->base_addr;
890
891 if (debug > 0) {
892 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
893 "Tx status %4.4x.\n",
894 dev->name, (int)inw(ioaddr + TxSTAT));
895 if (debug > 1) {
896 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
897 dev->name, ep->dirty_tx, ep->cur_tx);
898 }
899 }
900 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
901 ep->stats.tx_fifo_errors++;
902 outl(RestartTx, ioaddr + COMMAND);
903 } else {
904 epic_restart(dev);
905 outl(TxQueued, dev->base_addr + COMMAND);
906 }
907
908 dev->trans_start = jiffies;
909 ep->stats.tx_errors++;
910 if (!ep->tx_full)
911 netif_wake_queue(dev);
912 }
913
914 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
915 static void epic_init_ring(struct net_device *dev)
916 {
917 struct epic_private *ep = dev->priv;
918 int i;
919
920 ep->tx_full = 0;
921 ep->dirty_tx = ep->cur_tx = 0;
922 ep->cur_rx = ep->dirty_rx = 0;
923 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
924
925 /* Initialize all Rx descriptors. */
926 for (i = 0; i < RX_RING_SIZE; i++) {
927 ep->rx_ring[i].rxstatus = 0;
928 ep->rx_ring[i].buflength = ep->rx_buf_sz;
929 ep->rx_ring[i].next = ep->rx_ring_dma +
930 (i+1)*sizeof(struct epic_rx_desc);
931 ep->rx_skbuff[i] = NULL;
932 }
933 /* Mark the last entry as wrapping the ring. */
934 ep->rx_ring[i-1].next = ep->rx_ring_dma;
935
936 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
937 for (i = 0; i < RX_RING_SIZE; i++) {
938 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
939 ep->rx_skbuff[i] = skb;
940 if (skb == NULL)
941 break;
942 skb_reserve(skb, 2); /* 16 byte align the IP header. */
943 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
944 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
945 ep->rx_ring[i].rxstatus = DescOwn;
946 }
947 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
948
949 /* The Tx buffer descriptor is filled in as needed, but we
950 do need to clear the ownership bit. */
951 for (i = 0; i < TX_RING_SIZE; i++) {
952 ep->tx_skbuff[i] = NULL;
953 ep->tx_ring[i].txstatus = 0x0000;
954 ep->tx_ring[i].next = ep->tx_ring_dma +
955 (i+1)*sizeof(struct epic_tx_desc);
956 }
957 ep->tx_ring[i-1].next = ep->tx_ring_dma;
958 return;
959 }
960
961 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
962 {
963 struct epic_private *ep = dev->priv;
964 int entry, free_count;
965 u32 ctrl_word;
966 unsigned long flags;
967
968 if (skb_padto(skb, ETH_ZLEN))
969 return 0;
970
971 /* Caution: the write order is important here, set the field with the
972 "ownership" bit last. */
973
974 /* Calculate the next Tx descriptor entry. */
975 spin_lock_irqsave(&ep->lock, flags);
976 free_count = ep->cur_tx - ep->dirty_tx;
977 entry = ep->cur_tx % TX_RING_SIZE;
978
979 ep->tx_skbuff[entry] = skb;
980 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
981 skb->len, PCI_DMA_TODEVICE);
982 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
983 ctrl_word = 0x100000; /* No interrupt */
984 } else if (free_count == TX_QUEUE_LEN/2) {
985 ctrl_word = 0x140000; /* Tx-done intr. */
986 } else if (free_count < TX_QUEUE_LEN - 1) {
987 ctrl_word = 0x100000; /* No Tx-done intr. */
988 } else {
989 /* Leave room for an additional entry. */
990 ctrl_word = 0x140000; /* Tx-done intr. */
991 ep->tx_full = 1;
992 }
993 ep->tx_ring[entry].buflength = ctrl_word | skb->len;
994 ep->tx_ring[entry].txstatus =
995 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
996 | DescOwn;
997
998 ep->cur_tx++;
999 if (ep->tx_full)
1000 netif_stop_queue(dev);
1001
1002 spin_unlock_irqrestore(&ep->lock, flags);
1003 /* Trigger an immediate transmit demand. */
1004 outl(TxQueued, dev->base_addr + COMMAND);
1005
1006 dev->trans_start = jiffies;
1007 if (debug > 4)
1008 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1009 "flag %2.2x Tx status %8.8x.\n",
1010 dev->name, (int)skb->len, entry, ctrl_word,
1011 (int)inl(dev->base_addr + TxSTAT));
1012
1013 return 0;
1014 }
1015
1016 static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1017 int status)
1018 {
1019 struct net_device_stats *stats = &ep->stats;
1020
1021 #ifndef final_version
1022 /* There was an major error, log it. */
1023 if (debug > 1)
1024 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1025 dev->name, status);
1026 #endif
1027 stats->tx_errors++;
1028 if (status & 0x1050)
1029 stats->tx_aborted_errors++;
1030 if (status & 0x0008)
1031 stats->tx_carrier_errors++;
1032 if (status & 0x0040)
1033 stats->tx_window_errors++;
1034 if (status & 0x0010)
1035 stats->tx_fifo_errors++;
1036 }
1037
1038 static void epic_tx(struct net_device *dev, struct epic_private *ep)
1039 {
1040 unsigned int dirty_tx, cur_tx;
1041
1042 /*
1043 * Note: if this lock becomes a problem we can narrow the locked
1044 * region at the cost of occasionally grabbing the lock more times.
1045 */
1046 cur_tx = ep->cur_tx;
1047 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1048 struct sk_buff *skb;
1049 int entry = dirty_tx % TX_RING_SIZE;
1050 int txstatus = ep->tx_ring[entry].txstatus;
1051
1052 if (txstatus & DescOwn)
1053 break; /* It still hasn't been Txed */
1054
1055 if (likely(txstatus & 0x0001)) {
1056 ep->stats.collisions += (txstatus >> 8) & 15;
1057 ep->stats.tx_packets++;
1058 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1059 } else
1060 epic_tx_error(dev, ep, txstatus);
1061
1062 /* Free the original skb. */
1063 skb = ep->tx_skbuff[entry];
1064 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1065 skb->len, PCI_DMA_TODEVICE);
1066 dev_kfree_skb_irq(skb);
1067 ep->tx_skbuff[entry] = NULL;
1068 }
1069
1070 #ifndef final_version
1071 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1072 printk(KERN_WARNING
1073 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1074 dev->name, dirty_tx, cur_tx, ep->tx_full);
1075 dirty_tx += TX_RING_SIZE;
1076 }
1077 #endif
1078 ep->dirty_tx = dirty_tx;
1079 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1080 /* The ring is no longer full, allow new TX entries. */
1081 ep->tx_full = 0;
1082 netif_wake_queue(dev);
1083 }
1084 }
1085
1086 /* The interrupt handler does all of the Rx thread work and cleans up
1087 after the Tx thread. */
1088 static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1089 {
1090 struct net_device *dev = dev_instance;
1091 struct epic_private *ep = dev->priv;
1092 long ioaddr = dev->base_addr;
1093 unsigned int handled = 0;
1094 int status;
1095
1096 status = inl(ioaddr + INTSTAT);
1097 /* Acknowledge all of the current interrupt sources ASAP. */
1098 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1099
1100 if (debug > 4) {
1101 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1102 "intstat=%#8.8x.\n", dev->name, status,
1103 (int)inl(ioaddr + INTSTAT));
1104 }
1105
1106 if ((status & IntrSummary) == 0)
1107 goto out;
1108
1109 handled = 1;
1110
1111 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1112 spin_lock(&ep->napi_lock);
1113 if (netif_rx_schedule_prep(dev, &ep->napi)) {
1114 epic_napi_irq_off(dev, ep);
1115 __netif_rx_schedule(dev, &ep->napi);
1116 } else
1117 ep->reschedule_in_poll++;
1118 spin_unlock(&ep->napi_lock);
1119 }
1120 status &= ~EpicNapiEvent;
1121
1122 /* Check uncommon events all at once. */
1123 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1124 if (status == EpicRemoved)
1125 goto out;
1126
1127 /* Always update the error counts to avoid overhead later. */
1128 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1129 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1130 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1131
1132 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1133 ep->stats.tx_fifo_errors++;
1134 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1135 /* Restart the transmit process. */
1136 outl(RestartTx, ioaddr + COMMAND);
1137 }
1138 if (status & PCIBusErr170) {
1139 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1140 dev->name, status);
1141 epic_pause(dev);
1142 epic_restart(dev);
1143 }
1144 /* Clear all error sources. */
1145 outl(status & 0x7f18, ioaddr + INTSTAT);
1146 }
1147
1148 out:
1149 if (debug > 3) {
1150 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1151 dev->name, status);
1152 }
1153
1154 return IRQ_RETVAL(handled);
1155 }
1156
1157 static int epic_rx(struct net_device *dev, int budget)
1158 {
1159 struct epic_private *ep = dev->priv;
1160 int entry = ep->cur_rx % RX_RING_SIZE;
1161 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1162 int work_done = 0;
1163
1164 if (debug > 4)
1165 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1166 ep->rx_ring[entry].rxstatus);
1167
1168 if (rx_work_limit > budget)
1169 rx_work_limit = budget;
1170
1171 /* If we own the next entry, it's a new packet. Send it up. */
1172 while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
1173 int status = ep->rx_ring[entry].rxstatus;
1174
1175 if (debug > 4)
1176 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1177 if (--rx_work_limit < 0)
1178 break;
1179 if (status & 0x2006) {
1180 if (debug > 2)
1181 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1182 dev->name, status);
1183 if (status & 0x2000) {
1184 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1185 "multiple buffers, status %4.4x!\n", dev->name, status);
1186 ep->stats.rx_length_errors++;
1187 } else if (status & 0x0006)
1188 /* Rx Frame errors are counted in hardware. */
1189 ep->stats.rx_errors++;
1190 } else {
1191 /* Malloc up new buffer, compatible with net-2e. */
1192 /* Omit the four octet CRC from the length. */
1193 short pkt_len = (status >> 16) - 4;
1194 struct sk_buff *skb;
1195
1196 if (pkt_len > PKT_BUF_SZ - 4) {
1197 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1198 "%d bytes.\n",
1199 dev->name, status, pkt_len);
1200 pkt_len = 1514;
1201 }
1202 /* Check if the packet is long enough to accept without copying
1203 to a minimally-sized skbuff. */
1204 if (pkt_len < rx_copybreak
1205 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1206 skb_reserve(skb, 2); /* 16 byte align the IP header */
1207 pci_dma_sync_single_for_cpu(ep->pci_dev,
1208 ep->rx_ring[entry].bufaddr,
1209 ep->rx_buf_sz,
1210 PCI_DMA_FROMDEVICE);
1211 skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1212 skb_put(skb, pkt_len);
1213 pci_dma_sync_single_for_device(ep->pci_dev,
1214 ep->rx_ring[entry].bufaddr,
1215 ep->rx_buf_sz,
1216 PCI_DMA_FROMDEVICE);
1217 } else {
1218 pci_unmap_single(ep->pci_dev,
1219 ep->rx_ring[entry].bufaddr,
1220 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1221 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1222 ep->rx_skbuff[entry] = NULL;
1223 }
1224 skb->protocol = eth_type_trans(skb, dev);
1225 netif_receive_skb(skb);
1226 dev->last_rx = jiffies;
1227 ep->stats.rx_packets++;
1228 ep->stats.rx_bytes += pkt_len;
1229 }
1230 work_done++;
1231 entry = (++ep->cur_rx) % RX_RING_SIZE;
1232 }
1233
1234 /* Refill the Rx ring buffers. */
1235 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1236 entry = ep->dirty_rx % RX_RING_SIZE;
1237 if (ep->rx_skbuff[entry] == NULL) {
1238 struct sk_buff *skb;
1239 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1240 if (skb == NULL)
1241 break;
1242 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1243 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1244 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1245 work_done++;
1246 }
1247 /* AV: shouldn't we add a barrier here? */
1248 ep->rx_ring[entry].rxstatus = DescOwn;
1249 }
1250 return work_done;
1251 }
1252
1253 static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1254 {
1255 long ioaddr = dev->base_addr;
1256 int status;
1257
1258 status = inl(ioaddr + INTSTAT);
1259
1260 if (status == EpicRemoved)
1261 return;
1262 if (status & RxOverflow) /* Missed a Rx frame. */
1263 ep->stats.rx_errors++;
1264 if (status & (RxOverflow | RxFull))
1265 outw(RxQueued, ioaddr + COMMAND);
1266 }
1267
1268 static int epic_poll(struct napi_struct *napi, int budget)
1269 {
1270 struct epic_private *ep = container_of(napi, struct epic_private, napi);
1271 struct net_device *dev = ep->mii.dev;
1272 int work_done = 0;
1273 long ioaddr = dev->base_addr;
1274
1275 rx_action:
1276
1277 epic_tx(dev, ep);
1278
1279 work_done += epic_rx(dev, budget);
1280
1281 epic_rx_err(dev, ep);
1282
1283 if (work_done < budget) {
1284 unsigned long flags;
1285 int more;
1286
1287 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1288
1289 spin_lock_irqsave(&ep->napi_lock, flags);
1290
1291 more = ep->reschedule_in_poll;
1292 if (!more) {
1293 __netif_rx_complete(dev, napi);
1294 outl(EpicNapiEvent, ioaddr + INTSTAT);
1295 epic_napi_irq_on(dev, ep);
1296 } else
1297 ep->reschedule_in_poll--;
1298
1299 spin_unlock_irqrestore(&ep->napi_lock, flags);
1300
1301 if (more)
1302 goto rx_action;
1303 }
1304
1305 return work_done;
1306 }
1307
1308 static int epic_close(struct net_device *dev)
1309 {
1310 long ioaddr = dev->base_addr;
1311 struct epic_private *ep = dev->priv;
1312 struct sk_buff *skb;
1313 int i;
1314
1315 netif_stop_queue(dev);
1316 napi_disable(&ep->napi);
1317
1318 if (debug > 1)
1319 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1320 dev->name, (int)inl(ioaddr + INTSTAT));
1321
1322 del_timer_sync(&ep->timer);
1323
1324 epic_disable_int(dev, ep);
1325
1326 free_irq(dev->irq, dev);
1327
1328 epic_pause(dev);
1329
1330 /* Free all the skbuffs in the Rx queue. */
1331 for (i = 0; i < RX_RING_SIZE; i++) {
1332 skb = ep->rx_skbuff[i];
1333 ep->rx_skbuff[i] = NULL;
1334 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1335 ep->rx_ring[i].buflength = 0;
1336 if (skb) {
1337 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1338 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1339 dev_kfree_skb(skb);
1340 }
1341 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1342 }
1343 for (i = 0; i < TX_RING_SIZE; i++) {
1344 skb = ep->tx_skbuff[i];
1345 ep->tx_skbuff[i] = NULL;
1346 if (!skb)
1347 continue;
1348 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1349 skb->len, PCI_DMA_TODEVICE);
1350 dev_kfree_skb(skb);
1351 }
1352
1353 /* Green! Leave the chip in low-power mode. */
1354 outl(0x0008, ioaddr + GENCTL);
1355
1356 return 0;
1357 }
1358
1359 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1360 {
1361 struct epic_private *ep = dev->priv;
1362 long ioaddr = dev->base_addr;
1363
1364 if (netif_running(dev)) {
1365 /* Update the error counts. */
1366 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1367 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1368 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1369 }
1370
1371 return &ep->stats;
1372 }
1373
1374 /* Set or clear the multicast filter for this adaptor.
1375 Note that we only use exclusion around actually queueing the
1376 new frame, not around filling ep->setup_frame. This is non-deterministic
1377 when re-entered but still correct. */
1378
1379 static void set_rx_mode(struct net_device *dev)
1380 {
1381 long ioaddr = dev->base_addr;
1382 struct epic_private *ep = dev->priv;
1383 unsigned char mc_filter[8]; /* Multicast hash filter */
1384 int i;
1385
1386 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1387 outl(0x002C, ioaddr + RxCtrl);
1388 /* Unconditionally log net taps. */
1389 memset(mc_filter, 0xff, sizeof(mc_filter));
1390 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1391 /* There is apparently a chip bug, so the multicast filter
1392 is never enabled. */
1393 /* Too many to filter perfectly -- accept all multicasts. */
1394 memset(mc_filter, 0xff, sizeof(mc_filter));
1395 outl(0x000C, ioaddr + RxCtrl);
1396 } else if (dev->mc_count == 0) {
1397 outl(0x0004, ioaddr + RxCtrl);
1398 return;
1399 } else { /* Never executed, for now. */
1400 struct dev_mc_list *mclist;
1401
1402 memset(mc_filter, 0, sizeof(mc_filter));
1403 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1404 i++, mclist = mclist->next) {
1405 unsigned int bit_nr =
1406 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1407 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1408 }
1409 }
1410 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1411 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1412 for (i = 0; i < 4; i++)
1413 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1414 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1415 }
1416 return;
1417 }
1418
1419 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1420 {
1421 struct epic_private *np = dev->priv;
1422
1423 strcpy (info->driver, DRV_NAME);
1424 strcpy (info->version, DRV_VERSION);
1425 strcpy (info->bus_info, pci_name(np->pci_dev));
1426 }
1427
1428 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1429 {
1430 struct epic_private *np = dev->priv;
1431 int rc;
1432
1433 spin_lock_irq(&np->lock);
1434 rc = mii_ethtool_gset(&np->mii, cmd);
1435 spin_unlock_irq(&np->lock);
1436
1437 return rc;
1438 }
1439
1440 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1441 {
1442 struct epic_private *np = dev->priv;
1443 int rc;
1444
1445 spin_lock_irq(&np->lock);
1446 rc = mii_ethtool_sset(&np->mii, cmd);
1447 spin_unlock_irq(&np->lock);
1448
1449 return rc;
1450 }
1451
1452 static int netdev_nway_reset(struct net_device *dev)
1453 {
1454 struct epic_private *np = dev->priv;
1455 return mii_nway_restart(&np->mii);
1456 }
1457
1458 static u32 netdev_get_link(struct net_device *dev)
1459 {
1460 struct epic_private *np = dev->priv;
1461 return mii_link_ok(&np->mii);
1462 }
1463
1464 static u32 netdev_get_msglevel(struct net_device *dev)
1465 {
1466 return debug;
1467 }
1468
1469 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1470 {
1471 debug = value;
1472 }
1473
1474 static int ethtool_begin(struct net_device *dev)
1475 {
1476 unsigned long ioaddr = dev->base_addr;
1477 /* power-up, if interface is down */
1478 if (! netif_running(dev)) {
1479 outl(0x0200, ioaddr + GENCTL);
1480 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1481 }
1482 return 0;
1483 }
1484
1485 static void ethtool_complete(struct net_device *dev)
1486 {
1487 unsigned long ioaddr = dev->base_addr;
1488 /* power-down, if interface is down */
1489 if (! netif_running(dev)) {
1490 outl(0x0008, ioaddr + GENCTL);
1491 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1492 }
1493 }
1494
1495 static const struct ethtool_ops netdev_ethtool_ops = {
1496 .get_drvinfo = netdev_get_drvinfo,
1497 .get_settings = netdev_get_settings,
1498 .set_settings = netdev_set_settings,
1499 .nway_reset = netdev_nway_reset,
1500 .get_link = netdev_get_link,
1501 .get_msglevel = netdev_get_msglevel,
1502 .set_msglevel = netdev_set_msglevel,
1503 .begin = ethtool_begin,
1504 .complete = ethtool_complete
1505 };
1506
1507 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1508 {
1509 struct epic_private *np = dev->priv;
1510 long ioaddr = dev->base_addr;
1511 struct mii_ioctl_data *data = if_mii(rq);
1512 int rc;
1513
1514 /* power-up, if interface is down */
1515 if (! netif_running(dev)) {
1516 outl(0x0200, ioaddr + GENCTL);
1517 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1518 }
1519
1520 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1521 spin_lock_irq(&np->lock);
1522 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1523 spin_unlock_irq(&np->lock);
1524
1525 /* power-down, if interface is down */
1526 if (! netif_running(dev)) {
1527 outl(0x0008, ioaddr + GENCTL);
1528 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1529 }
1530 return rc;
1531 }
1532
1533
1534 static void __devexit epic_remove_one (struct pci_dev *pdev)
1535 {
1536 struct net_device *dev = pci_get_drvdata(pdev);
1537 struct epic_private *ep = dev->priv;
1538
1539 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1540 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1541 unregister_netdev(dev);
1542 #ifndef USE_IO_OPS
1543 iounmap((void*) dev->base_addr);
1544 #endif
1545 pci_release_regions(pdev);
1546 free_netdev(dev);
1547 pci_disable_device(pdev);
1548 pci_set_drvdata(pdev, NULL);
1549 /* pci_power_off(pdev, -1); */
1550 }
1551
1552
1553 #ifdef CONFIG_PM
1554
1555 static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1556 {
1557 struct net_device *dev = pci_get_drvdata(pdev);
1558 long ioaddr = dev->base_addr;
1559
1560 if (!netif_running(dev))
1561 return 0;
1562 epic_pause(dev);
1563 /* Put the chip into low-power mode. */
1564 outl(0x0008, ioaddr + GENCTL);
1565 /* pci_power_off(pdev, -1); */
1566 return 0;
1567 }
1568
1569
1570 static int epic_resume (struct pci_dev *pdev)
1571 {
1572 struct net_device *dev = pci_get_drvdata(pdev);
1573
1574 if (!netif_running(dev))
1575 return 0;
1576 epic_restart(dev);
1577 /* pci_power_on(pdev); */
1578 return 0;
1579 }
1580
1581 #endif /* CONFIG_PM */
1582
1583
1584 static struct pci_driver epic_driver = {
1585 .name = DRV_NAME,
1586 .id_table = epic_pci_tbl,
1587 .probe = epic_init_one,
1588 .remove = __devexit_p(epic_remove_one),
1589 #ifdef CONFIG_PM
1590 .suspend = epic_suspend,
1591 .resume = epic_resume,
1592 #endif /* CONFIG_PM */
1593 };
1594
1595
1596 static int __init epic_init (void)
1597 {
1598 /* when a module, this is printed whether or not devices are found in probe */
1599 #ifdef MODULE
1600 printk (KERN_INFO "%s" KERN_INFO "%s",
1601 version, version2);
1602 #endif
1603
1604 return pci_register_driver(&epic_driver);
1605 }
1606
1607
1608 static void __exit epic_cleanup (void)
1609 {
1610 pci_unregister_driver (&epic_driver);
1611 }
1612
1613
1614 module_init(epic_init);
1615 module_exit(epic_cleanup);