usr/src/uts/common/sys/pcie_impl.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _SYS_PCIE_IMPL_H
  27 #define _SYS_PCIE_IMPL_H
  28
  29 #ifdef  __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 #include <sys/pcie.h>
  34
  35 #define PCI_GET_BDF(dip)        \
  36         PCIE_DIP2BUS(dip)->bus_bdf
  37 #define PCI_GET_SEC_BUS(dip)    \
  38         PCIE_DIP2BUS(dip)->bus_bdg_secbus
  39 #define PCI_GET_PCIE2PCI_SECBUS(dip) \
  40         PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus
  41
  42 #define DEVI_PORT_TYPE_PCI \
  43         ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \
  44         PCI_BRIDGE_PCI_IF_PCI2PCI)
  45
  46 #define PCIE_DIP2BUS(dip) \
  47         (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \
  48         PCIE_DIP2UPBUS(dip) : \
  49         ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \
  50         PCIE_DIP2DOWNBUS(dip) : NULL)
  51
  52 #define PCIE_DIP2UPBUS(dip) \
  53         ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE))
  54 #define PCIE_DIP2DOWNBUS(dip) \
  55         ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE))
  56 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd
  57 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p
  58 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip
  59 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip
  60 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p))
  61
  62 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off)
  63 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off)
  64 #define PCIE_IS_PCI(bus_p) \
  65         (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV)
  66 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off)
  67 /* IS_ROOT = is RC or RP */
  68 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p))
  69 /*
  70  * This is a pseudo pcie "device type", but it's needed to explain describe
  71  * nodes such as PX and NPE, which aren't really PCI devices but do control or
  72  * interaction with PCI error handling.
  73  */
  74 #define PCIE_IS_RC(bus_p) \
  75         (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO)
  76 #define PCIE_IS_RP(bus_p) \
  77         ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \
  78             PCIE_IS_PCIE(bus_p))
  79 #define PCIE_IS_SW(bus_p) \
  80         ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) || \
  81             (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN))
  82 #define PCIE_IS_BDG(bus_p)  (bus_p->bus_hdr_type == PCI_HEADER_ONE)
  83 #define PCIE_IS_PCI_BDG(bus_p) \
  84         ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV) && \
  85             PCIE_IS_BDG(bus_p))
  86 #define PCIE_IS_PCIE_BDG(bus_p) \
  87         (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI)
  88 #define PCIE_IS_PCI2PCIE(bus_p) \
  89         (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)
  90 #define PCIE_IS_PCIE_SEC(bus_p) \
  91         (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p))
  92 #define PCIX_ECC_VERSION_CHECK(bus_p) \
  93         ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \
  94             (bus_p->bus_ecc_ver == PCI_PCIX_VER_2))
  95
  96 #define PCIE_VENID(bus_p)       (bus_p->bus_dev_ven_id & 0xffff)
  97 #define PCIE_DEVID(bus_p)       ((bus_p->bus_dev_ven_id >> 16) & 0xffff)
  98
  99 /* PCIE Cap/AER shortcuts */
 100 #define PCIE_GET(sz, bus_p, off) \
 101         pci_config_get ## sz(bus_p->bus_cfg_hdl, off)
 102 #define PCIE_PUT(sz, bus_p, off, val) \
 103         pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val)
 104 #define PCIE_CAP_GET(sz, bus_p, off) \
 105         PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off)
 106 #define PCIE_CAP_PUT(sz, bus_p, off, val) \
 107         PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \
 108             val)
 109 #define PCIE_AER_GET(sz, bus_p, off) \
 110         PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off)
 111 #define PCIE_AER_PUT(sz, bus_p, off, val) \
 112         PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \
 113             val)
 114 #define PCIX_CAP_GET(sz, bus_p, off) \
 115         PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off)
 116 #define PCIX_CAP_PUT(sz, bus_p, off, val) \
 117         PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \
 118             val)
 119
 120 /* Translate PF error return values to DDI_FM values */
 121 #define PF_ERR2DDIFM_ERR(sts) \
 122         (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL :      \
 123         (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL))
 124
 125 /*
 126  * The following flag is used for Broadcom 5714/5715 bridge prefetch issue.
 127  * This flag will be used both by px and px_pci nexus drivers.
 128  */
 129 #define PX_DMAI_FLAGS_MAP_BUFZONE       0x40000
 130
 131 /*
 132  * PCI(e/-X) structures used to to gather and report errors detected by
 133  * PCI(e/-X) compliant devices.  These registers only contain "dynamic" data.
 134  * Static data such as Capability Offsets and Version #s is saved in the parent
 135  * private data.
 136  */
 137 #define PCI_ERR_REG(pfd_p)         pfd_p->pe_pci_regs
 138 #define PCI_BDG_ERR_REG(pfd_p)     PCI_ERR_REG(pfd_p)->pci_bdg_regs
 139 #define PCIX_ERR_REG(pfd_p)        pfd_p->pe_ext.pe_pcix_regs
 140 #define PCIX_ECC_REG(pfd_p)        PCIX_ERR_REG(pfd_p)->pcix_ecc_regs
 141 #define PCIX_BDG_ERR_REG(pfd_p)    pfd_p->pe_pcix_bdg_regs
 142 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n]
 143 #define PCIE_ERR_REG(pfd_p)        pfd_p->pe_ext.pe_pcie_regs
 144 #define PCIE_RP_REG(pfd_p)         PCIE_ERR_REG(pfd_p)->pcie_rp_regs
 145 #define PCIE_ROOT_FAULT(pfd_p)     pfd_p->pe_root_fault
 146 #define PCIE_ADV_REG(pfd_p)        PCIE_ERR_REG(pfd_p)->pcie_adv_regs
 147 #define PCIE_ADV_HDR(pfd_p, n)     PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n]
 148 #define PCIE_ADV_BDG_REG(pfd_p) \
 149         PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs
 150 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n]
 151 #define PCIE_ADV_RP_REG(pfd_p) \
 152         PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs
 153 #define PFD_IS_ROOT(pfd_p)         PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p))
 154 #define PFD_IS_RC(pfd_p)           PCIE_IS_RC(PCIE_PFD2BUS(pfd_p))
 155 #define PFD_IS_RP(pfd_p)           PCIE_IS_RP(PCIE_PFD2BUS(pfd_p))
 156
 157 typedef struct pf_pci_bdg_err_regs {
 158         uint16_t pci_bdg_sec_stat;      /* PCI secondary status reg */
 159         uint16_t pci_bdg_ctrl;          /* PCI bridge control reg */
 160 } pf_pci_bdg_err_regs_t;
 161
 162 typedef struct pf_pci_err_regs {
 163         uint16_t pci_err_status;        /* pci status register */
 164         uint16_t pci_cfg_comm;          /* pci command register */
 165         pf_pci_bdg_err_regs_t *pci_bdg_regs;
 166 } pf_pci_err_regs_t;
 167
 168 typedef struct pf_pcix_ecc_regs {
 169         uint32_t pcix_ecc_ctlstat;      /* pcix ecc control status reg */
 170         uint32_t pcix_ecc_fstaddr;      /* pcix ecc first address reg */
 171         uint32_t pcix_ecc_secaddr;      /* pcix ecc second address reg */
 172         uint32_t pcix_ecc_attr;         /* pcix ecc attributes reg */
 173 } pf_pcix_ecc_regs_t;
 174
 175 typedef struct pf_pcix_err_regs {
 176         uint16_t pcix_command;          /* pcix command register */
 177         uint32_t pcix_status;           /* pcix status register */
 178         pf_pcix_ecc_regs_t *pcix_ecc_regs;      /* pcix ecc registers */
 179 } pf_pcix_err_regs_t;
 180
 181 typedef struct pf_pcix_bdg_err_regs {
 182         uint16_t pcix_bdg_sec_stat;     /* pcix bridge secondary status reg */
 183         uint32_t pcix_bdg_stat;         /* pcix bridge status reg */
 184         pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2];       /* pcix ecc registers */
 185 } pf_pcix_bdg_err_regs_t;
 186
 187 typedef struct pf_pcie_adv_bdg_err_regs {
 188         uint32_t pcie_sue_ctl;          /* pcie bridge secondary ue control */
 189         uint32_t pcie_sue_status;       /* pcie bridge secondary ue status */
 190         uint32_t pcie_sue_mask;         /* pcie bridge secondary ue mask */
 191         uint32_t pcie_sue_sev;          /* pcie bridge secondary ue severity */
 192         uint32_t pcie_sue_hdr[4];       /* pcie bridge secondary ue hdr log */
 193         uint32_t pcie_sue_tgt_trans;    /* Fault trans type from SAER Logs */
 194         uint64_t pcie_sue_tgt_addr;     /* Fault addr from SAER Logs */
 195         pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */
 196 } pf_pcie_adv_bdg_err_regs_t;
 197
 198 typedef struct pf_pcie_adv_rp_err_regs {
 199         uint32_t pcie_rp_err_status;    /* pcie root complex error status reg */
 200         uint32_t pcie_rp_err_cmd;       /* pcie root complex error cmd reg */
 201         uint16_t pcie_rp_ce_src_id;     /* pcie root complex ce sourpe id */
 202         uint16_t pcie_rp_ue_src_id;     /* pcie root complex ue sourpe id */
 203 } pf_pcie_adv_rp_err_regs_t;
 204
 205 typedef struct pf_pcie_adv_err_regs {
 206         uint32_t pcie_adv_ctl;          /* pcie advanced control reg */
 207         uint32_t pcie_ue_status;        /* pcie ue error status reg */
 208         uint32_t pcie_ue_mask;          /* pcie ue error mask reg */
 209         uint32_t pcie_ue_sev;           /* pcie ue error severity reg */
 210         uint32_t pcie_ue_hdr[4];        /* pcie ue header log */
 211         uint32_t pcie_ce_status;        /* pcie ce error status reg */
 212         uint32_t pcie_ce_mask;          /* pcie ce error mask reg */
 213         union {
 214                 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */
 215                 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs;     /* rp regs */
 216         } pcie_ext;
 217         uint32_t pcie_ue_tgt_trans;     /* Fault trans type from AER Logs */
 218         uint64_t pcie_ue_tgt_addr;      /* Fault addr from AER Logs */
 219         pcie_req_id_t pcie_ue_tgt_bdf;  /* Fault bdf from SAER Logs */
 220 } pf_pcie_adv_err_regs_t;
 221
 222 typedef struct pf_pcie_rp_err_regs {
 223         uint32_t pcie_rp_status;        /* root complex status register */
 224         uint16_t pcie_rp_ctl;           /* root complex control register */
 225 } pf_pcie_rp_err_regs_t;
 226
 227 typedef struct pf_pcie_err_regs {
 228         uint16_t pcie_err_status;       /* pcie device status register */
 229         uint16_t pcie_err_ctl;          /* pcie error control register */
 230         uint32_t pcie_dev_cap;          /* pcie device capabilities register */
 231         pf_pcie_rp_err_regs_t *pcie_rp_regs;     /* pcie root complex regs */
 232         pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */
 233 } pf_pcie_err_regs_t;
 234
 235 typedef struct pf_root_fault {
 236         pcie_req_id_t   fault_bdf;      /* Fault BDF of error */
 237         uint64_t        fault_addr;     /* Fault Addr of error */
 238         boolean_t       full_scan;      /* Option to do a full scan */
 239 } pf_root_fault_t;
 240
 241 typedef struct pf_data pf_data_t;
 242
 243 typedef struct pcie_bus {
 244         /* Needed for PCI/PCIe fabric error handling */
 245         dev_info_t      *bus_dip;
 246         dev_info_t      *bus_rp_dip;
 247         ddi_acc_handle_t bus_cfg_hdl;           /* error handling acc handle */
 248         uint_t          bus_fm_flags;
 249
 250         /* Static PCI/PCIe information */
 251         pcie_req_id_t   bus_bdf;
 252         pcie_req_id_t   bus_rp_bdf;             /* BDF of device's Root Port */
 253         uint32_t        bus_dev_ven_id;         /* device/vendor ID */
 254         uint8_t         bus_rev_id;             /* revision ID */
 255         uint8_t         bus_hdr_type;           /* pci header type, see pci.h */
 256         pcie_req_id_t   bus_pcie2pci_secbus;    /* PCIe2PCI Bridge secbus num */
 257         uint16_t        bus_dev_type;           /* PCI-E dev type, see pcie.h */
 258         uint8_t         bus_bdg_secbus;         /* Bridge secondary bus num */
 259         uint16_t        bus_pcie_off;           /* PCIe Capability Offset */
 260         uint16_t        bus_aer_off;            /* PCIe Advanced Error Offset */
 261         uint16_t        bus_pcix_off;           /* PCIx Capability Offset */
 262         uint16_t        bus_ecc_ver;            /* PCIX ecc version */
 263         pci_bus_range_t bus_bus_range;          /* pci bus-range property */
 264         ppb_ranges_t    *bus_addr_ranges;       /* pci range property */
 265         int             bus_addr_entries;       /* number of range prop */
 266         pci_regspec_t   *bus_assigned_addr;     /* "assigned-address" prop */
 267         int             bus_assigned_entries;   /* number of prop entries */
 268
 269         /* Cache of last fault data */
 270         pf_data_t       *bus_pfd;
 271
 272         int             bus_mps;                /* Maximum Payload Size */
 273 } pcie_bus_t;
 274
 275 struct pf_data {
 276         boolean_t               pe_lock;
 277         boolean_t               pe_valid;
 278         uint32_t                pe_severity_flags;      /* Severity of error */
 279         pcie_bus_t              *pe_bus_p;
 280         pf_root_fault_t         *pe_root_fault; /* Only valid for RC and RP */
 281         pf_pci_err_regs_t       *pe_pci_regs;   /* PCI error reg */
 282         union {
 283                 pf_pcix_err_regs_t      *pe_pcix_regs;  /* PCI-X error reg */
 284                 pf_pcie_err_regs_t      *pe_pcie_regs;  /* PCIe error reg */
 285         } pe_ext;
 286         pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */
 287         pf_data_t               *pe_prev;       /* Next error in queue */
 288         pf_data_t               *pe_next;       /* Next error in queue */
 289         boolean_t               pe_rber_fatal;
 290 };
 291
 292 /* Information used while handling errors in the fabric. */
 293 typedef struct pf_impl {
 294         ddi_fm_error_t  *pf_derr;
 295         pf_root_fault_t *pf_fault;      /* captured fault bdf/addr to scan */
 296         pf_data_t       *pf_dq_head_p;  /* ptr to fault data queue */
 297         pf_data_t       *pf_dq_tail_p;  /* ptr pt last fault data q */
 298         uint32_t        pf_total;       /* total non RC pf_datas */
 299 } pf_impl_t;
 300
 301 /* bus_fm_flags field */
 302 #define PF_FM_READY             (1 << 0)        /* bus_fm_lock initialized */
 303 #define PF_FM_IS_NH             (1 << 1)        /* known as non-hardened */
 304
 305 /*
 306  * PCIe fabric handle lookup address flags.  Used to define what type of
 307  * transaction the address is for.  These same value are defined again in
 308  * fabric-xlate FM module.  Do not modify these variables, without modifying
 309  * those.
 310  */
 311 #define PF_ADDR_DMA             (1 << 0)
 312 #define PF_ADDR_PIO             (1 << 1)
 313 #define PF_ADDR_CFG             (1 << 2)
 314
 315 /* PCIe fabric error scanning status flags */
 316 #define PF_SCAN_SUCCESS         (1 << 0)
 317 #define PF_SCAN_CB_FAILURE      (1 << 1) /* hardened device callback failure */
 318 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */
 319 #define PF_SCAN_IN_DQ           (1 << 3) /* already present in the faultq */
 320 #define PF_SCAN_DEADLOCK        (1 << 4) /* deadlock detected */
 321 #define PF_SCAN_BAD_RESPONSE    (1 << 5) /* Incorrect device response */
 322
 323 /* PCIe fabric error handling severity return flags */
 324 #define PF_ERR_NO_ERROR         (1 << 0) /* No error seen */
 325 #define PF_ERR_CE               (1 << 1) /* Correctable Error */
 326 #define PF_ERR_NO_PANIC         (1 << 2) /* Error should not panic sys */
 327 #define PF_ERR_MATCHED_DEVICE   (1 << 3) /* Error Handled By Device */
 328 #define PF_ERR_MATCHED_RC       (1 << 4) /* Error Handled By RC */
 329 #define PF_ERR_MATCHED_PARENT   (1 << 5) /* Error Handled By Parent */
 330 #define PF_ERR_PANIC            (1 << 6) /* Error should panic system */
 331 #define PF_ERR_PANIC_DEADLOCK   (1 << 7) /* deadlock detected */
 332
 333 #define PF_ERR_FATAL_FLAGS      (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK)
 334
 335 #define PF_HDL_FOUND            1
 336 #define PF_HDL_NOTFOUND         2
 337
 338 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100
 339
 340 typedef struct {
 341         dev_info_t      *dip;
 342         int             highest_common_mps;
 343 } pcie_max_supported_t;
 344
 345 /* PCIe Friendly Functions */
 346 extern void pcie_init_root_port_mps(dev_info_t *dip);
 347 extern int pcie_initchild(dev_info_t *dip);
 348 extern void pcie_uninitchild(dev_info_t *dip);
 349 extern void pcie_clear_errors(dev_info_t *dip);
 350 extern int pcie_postattach_child(dev_info_t *dip);
 351 extern void pcie_enable_errors(dev_info_t *dip);
 352 extern void pcie_disable_errors(dev_info_t *dip);
 353 extern int pcie_enable_ce(dev_info_t *dip);
 354 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *);
 355
 356 extern pcie_bus_t *pcie_init_bus(dev_info_t *cdip);
 357 extern void pcie_fini_bus(dev_info_t *cdip);
 358 extern void pcie_rc_init_bus(dev_info_t *dip);
 359 extern void pcie_rc_fini_bus(dev_info_t *dip);
 360 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd);
 361 extern void pcie_rc_fini_pfd(pf_data_t *pfd);
 362 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip);
 363 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf);
 364 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
 365 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip);
 366 extern int pcie_dev(dev_info_t *dip);
 367 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip,
 368         int *max_supported);
 369 extern int pcie_root_port(dev_info_t *dip);
 370 extern int pcie_initchild_mps(dev_info_t *dip);
 371 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val);
 372 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip);
 373
 374 extern uint32_t pcie_get_aer_uce_mask();
 375 extern uint32_t pcie_get_aer_ce_mask();
 376 extern uint32_t pcie_get_aer_suce_mask();
 377 extern uint32_t pcie_get_serr_mask();
 378 extern void pcie_set_aer_uce_mask(uint32_t mask);
 379 extern void pcie_set_aer_ce_mask(uint32_t mask);
 380 extern void pcie_set_aer_suce_mask(uint32_t mask);
 381 extern void pcie_set_serr_mask(uint32_t mask);
 382
 383 /* PCIe error handling functions */
 384 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr,
 385     pf_data_t *root_pfd_p);
 386 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t);
 387 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t);
 388 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t,
 389     pcie_req_id_t);
 390 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *);
 391
 392 #ifdef  __cplusplus
 393 }
 394 #endif
 395
 396 #endif  /* _SYS_PCIE_IMPL_H */