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target: simplify register get/set ops
[openocd/ztw.git] / src / target / arm11.c
blob936edd818fc23a5dc22aa88b0b1ef9181f99bfce
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "etm.h"
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
36 #include "register.h"
37
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 #if 0
44 #define FNC_INFO LOG_DEBUG("-")
45 #else
46 #define FNC_INFO
47 #endif
48
49 #if 1
50 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
51 #else
52 #define FNC_INFO_NOTIMPLEMENTED
53 #endif
54
55 static bool arm11_config_memwrite_burst = true;
56 static bool arm11_config_memwrite_error_fatal = true;
57 static uint32_t arm11_vcr = 0;
58 static bool arm11_config_step_irq_enable = false;
59 static bool arm11_config_hardware_step = false;
60
61 enum arm11_regtype
62 {
63 ARM11_REGISTER_CORE,
64 ARM11_REGISTER_CPSR,
65
66 ARM11_REGISTER_FX,
67 ARM11_REGISTER_FPS,
68
69 ARM11_REGISTER_FIQ,
70 ARM11_REGISTER_SVC,
71 ARM11_REGISTER_ABT,
72 ARM11_REGISTER_IRQ,
73 ARM11_REGISTER_UND,
74 ARM11_REGISTER_MON,
75
76 ARM11_REGISTER_SPSR_FIQ,
77 ARM11_REGISTER_SPSR_SVC,
78 ARM11_REGISTER_SPSR_ABT,
79 ARM11_REGISTER_SPSR_IRQ,
80 ARM11_REGISTER_SPSR_UND,
81 ARM11_REGISTER_SPSR_MON,
82
83 /* debug regs */
84 ARM11_REGISTER_DSCR,
85 ARM11_REGISTER_WDTR,
86 ARM11_REGISTER_RDTR,
87 };
88
89
90 struct arm11_reg_defs
91 {
92 char * name;
93 uint32_t num;
94 int gdb_num;
95 enum arm11_regtype type;
96 };
97
98 /* update arm11_regcache_ids when changing this */
99 static const struct arm11_reg_defs arm11_reg_defs[] =
100 {
101 {"r0", 0, 0, ARM11_REGISTER_CORE},
102 {"r1", 1, 1, ARM11_REGISTER_CORE},
103 {"r2", 2, 2, ARM11_REGISTER_CORE},
104 {"r3", 3, 3, ARM11_REGISTER_CORE},
105 {"r4", 4, 4, ARM11_REGISTER_CORE},
106 {"r5", 5, 5, ARM11_REGISTER_CORE},
107 {"r6", 6, 6, ARM11_REGISTER_CORE},
108 {"r7", 7, 7, ARM11_REGISTER_CORE},
109 {"r8", 8, 8, ARM11_REGISTER_CORE},
110 {"r9", 9, 9, ARM11_REGISTER_CORE},
111 {"r10", 10, 10, ARM11_REGISTER_CORE},
112 {"r11", 11, 11, ARM11_REGISTER_CORE},
113 {"r12", 12, 12, ARM11_REGISTER_CORE},
114 {"sp", 13, 13, ARM11_REGISTER_CORE},
115 {"lr", 14, 14, ARM11_REGISTER_CORE},
116 {"pc", 15, 15, ARM11_REGISTER_CORE},
117
118 #if ARM11_REGCACHE_FREGS
119 {"f0", 0, 16, ARM11_REGISTER_FX},
120 {"f1", 1, 17, ARM11_REGISTER_FX},
121 {"f2", 2, 18, ARM11_REGISTER_FX},
122 {"f3", 3, 19, ARM11_REGISTER_FX},
123 {"f4", 4, 20, ARM11_REGISTER_FX},
124 {"f5", 5, 21, ARM11_REGISTER_FX},
125 {"f6", 6, 22, ARM11_REGISTER_FX},
126 {"f7", 7, 23, ARM11_REGISTER_FX},
127 {"fps", 0, 24, ARM11_REGISTER_FPS},
128 #endif
129
130 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
131
132 #if ARM11_REGCACHE_MODEREGS
133 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
134 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
135 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
136 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
137 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
138 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
139 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
140 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
141
142 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
143 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
144 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
145
146 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
147 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
148 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
149
150 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
151 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
152 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
153
154 {"r13_und", 13, -1, ARM11_REGISTER_UND},
155 {"r14_und", 14, -1, ARM11_REGISTER_UND},
156 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
157
158 /* ARM1176 only */
159 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
160 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
161 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
162 #endif
163
164 /* Debug Registers */
165 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
166 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
167 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
168 };
169
170 enum arm11_regcache_ids
171 {
172 ARM11_RC_R0,
173 ARM11_RC_RX = ARM11_RC_R0,
174
175 ARM11_RC_R1,
176 ARM11_RC_R2,
177 ARM11_RC_R3,
178 ARM11_RC_R4,
179 ARM11_RC_R5,
180 ARM11_RC_R6,
181 ARM11_RC_R7,
182 ARM11_RC_R8,
183 ARM11_RC_R9,
184 ARM11_RC_R10,
185 ARM11_RC_R11,
186 ARM11_RC_R12,
187 ARM11_RC_R13,
188 ARM11_RC_SP = ARM11_RC_R13,
189 ARM11_RC_R14,
190 ARM11_RC_LR = ARM11_RC_R14,
191 ARM11_RC_R15,
192 ARM11_RC_PC = ARM11_RC_R15,
193
194 #if ARM11_REGCACHE_FREGS
195 ARM11_RC_F0,
196 ARM11_RC_FX = ARM11_RC_F0,
197 ARM11_RC_F1,
198 ARM11_RC_F2,
199 ARM11_RC_F3,
200 ARM11_RC_F4,
201 ARM11_RC_F5,
202 ARM11_RC_F6,
203 ARM11_RC_F7,
204 ARM11_RC_FPS,
205 #endif
206
207 ARM11_RC_CPSR,
208
209 #if ARM11_REGCACHE_MODEREGS
210 ARM11_RC_R8_FIQ,
211 ARM11_RC_R9_FIQ,
212 ARM11_RC_R10_FIQ,
213 ARM11_RC_R11_FIQ,
214 ARM11_RC_R12_FIQ,
215 ARM11_RC_R13_FIQ,
216 ARM11_RC_R14_FIQ,
217 ARM11_RC_SPSR_FIQ,
218
219 ARM11_RC_R13_SVC,
220 ARM11_RC_R14_SVC,
221 ARM11_RC_SPSR_SVC,
222
223 ARM11_RC_R13_ABT,
224 ARM11_RC_R14_ABT,
225 ARM11_RC_SPSR_ABT,
226
227 ARM11_RC_R13_IRQ,
228 ARM11_RC_R14_IRQ,
229 ARM11_RC_SPSR_IRQ,
230
231 ARM11_RC_R13_UND,
232 ARM11_RC_R14_UND,
233 ARM11_RC_SPSR_UND,
234
235 ARM11_RC_R13_MON,
236 ARM11_RC_R14_MON,
237 ARM11_RC_SPSR_MON,
238 #endif
239
240 ARM11_RC_DSCR,
241 ARM11_RC_WDTR,
242 ARM11_RC_RDTR,
243
244 ARM11_RC_MAX,
245 };
246
247 #define ARM11_GDB_REGISTER_COUNT 26
248
249 /* FIXME these are *identical* to the ARMv4_5 dummies ... except
250 * for their names, and being static vs global, and having different
251 * addresses. Ditto ARMv7a and ARMv7m dummies.
252 */
253
254 static uint8_t arm11_gdb_dummy_fp_value[12];
255
256 static struct reg arm11_gdb_dummy_fp_reg =
257 {
258 .name = "GDB dummy floating-point register",
259 .value = arm11_gdb_dummy_fp_value,
260 .dirty = 0,
261 .valid = 1,
262 .size = 96,
263 .arch_info = NULL,
264 };
265
266 static uint8_t arm11_gdb_dummy_fps_value[4];
267
268 static struct reg arm11_gdb_dummy_fps_reg =
269 {
270 .name = "GDB dummy floating-point status register",
271 .value = arm11_gdb_dummy_fps_value,
272 .dirty = 0,
273 .valid = 1,
274 .size = 32,
275 .arch_info = NULL,
276 };
277
278
279 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
280 static int arm11_step(struct target *target, int current,
281 uint32_t address, int handle_breakpoints);
282 /* helpers */
283 static int arm11_build_reg_cache(struct target *target);
284 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
285 static int arm11_get_reg(struct reg *reg);
286
287 static void arm11_record_register_history(struct arm11_common * arm11);
288 static void arm11_dump_reg_changes(struct arm11_common * arm11);
289
290
291 /** Check and if necessary take control of the system
292 *
293 * \param arm11 Target state variable.
294 * \param dscr If the current DSCR content is
295 * available a pointer to a word holding the
296 * DSCR can be passed. Otherwise use NULL.
297 */
298 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
299 {
300 FNC_INFO;
301
302 uint32_t dscr_local_tmp_copy;
303
304 if (!dscr)
305 {
306 dscr = &dscr_local_tmp_copy;
307
308 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
309 }
310
311 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
312 {
313 LOG_DEBUG("Bringing target into debug mode");
314
315 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
316 arm11_write_DSCR(arm11, *dscr);
317
318 /* add further reset initialization here */
319
320 arm11->simulate_reset_on_next_halt = true;
321
322 if (*dscr & ARM11_DSCR_CORE_HALTED)
323 {
324 /** \todo TODO: this needs further scrutiny because
325 * arm11_on_enter_debug_state() never gets properly called.
326 * As a result we don't read the actual register states from
327 * the target.
328 */
329
330 arm11->target->state = TARGET_HALTED;
331 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
332 }
333 else
334 {
335 arm11->target->state = TARGET_RUNNING;
336 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
337 }
338
339 arm11_sc7_clear_vbw(arm11);
340 }
341
342 return ERROR_OK;
343 }
344
345
346
347 #define R(x) \
348 (arm11->reg_values[ARM11_RC_##x])
349
350 /** Save processor state.
351 *
352 * This is called when the HALT instruction has succeeded
353 * or on other occasions that stop the processor.
354 *
355 */
356 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
357 {
358 int retval;
359 FNC_INFO;
360
361 for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
362 {
363 arm11->reg_list[i].valid = 1;
364 arm11->reg_list[i].dirty = 0;
365 }
366
367 /* Save DSCR */
368 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
369
370 /* Save wDTR */
371
372 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
373 {
374 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
375
376 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
377
378 struct scan_field chain5_fields[3];
379
380 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
381 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
382 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
383
384 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
385 }
386 else
387 {
388 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
389 }
390
391
392 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
393 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
394 ARM1136 seems to require this to issue ITR's as well */
395
396 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
397
398 /* this executes JTAG queue: */
399
400 arm11_write_DSCR(arm11, new_dscr);
401
402
403 /* From the spec:
404 Before executing any instruction in debug state you have to drain the write buffer.
405 This ensures that no imprecise Data Aborts can return at a later point:*/
406
407 /** \todo TODO: Test drain write buffer. */
408
409 #if 0
410 while (1)
411 {
412 /* MRC p14,0,R0,c5,c10,0 */
413 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
414
415 /* mcr 15, 0, r0, cr7, cr10, {4} */
416 arm11_run_instr_no_data1(arm11, 0xee070f9a);
417
418 uint32_t dscr = arm11_read_DSCR(arm11);
419
420 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
421
422 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
423 {
424 arm11_run_instr_no_data1(arm11, 0xe320f000);
425
426 dscr = arm11_read_DSCR(arm11);
427
428 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
429
430 break;
431 }
432 }
433 #endif
434
435 retval = arm11_run_instr_data_prepare(arm11);
436 if (retval != ERROR_OK)
437 return retval;
438
439 /* save r0 - r14 */
440
441 /** \todo TODO: handle other mode registers */
442
443 for (size_t i = 0; i < 15; i++)
444 {
445 /* MCR p14,0,R?,c0,c5,0 */
446 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
447 if (retval != ERROR_OK)
448 return retval;
449 }
450
451 /* save rDTR */
452
453 /* check rDTRfull in DSCR */
454
455 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
456 {
457 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
458 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
459 if (retval != ERROR_OK)
460 return retval;
461 }
462 else
463 {
464 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
465 }
466
467 /* save CPSR */
468
469 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
470 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
471 if (retval != ERROR_OK)
472 return retval;
473
474 /* save PC */
475
476 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
477 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
478 if (retval != ERROR_OK)
479 return retval;
480
481 /* adjust PC depending on ARM state */
482
483 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
484 {
485 arm11->reg_values[ARM11_RC_PC] -= 0;
486 }
487 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
488 {
489 arm11->reg_values[ARM11_RC_PC] -= 4;
490 }
491 else /* ARM state */
492 {
493 arm11->reg_values[ARM11_RC_PC] -= 8;
494 }
495
496 if (arm11->simulate_reset_on_next_halt)
497 {
498 arm11->simulate_reset_on_next_halt = false;
499
500 LOG_DEBUG("Reset c1 Control Register");
501
502 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
503
504 /* MCR p15,0,R0,c1,c0,0 */
505 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
506 if (retval != ERROR_OK)
507 return retval;
508
509 }
510
511 retval = arm11_run_instr_data_finish(arm11);
512 if (retval != ERROR_OK)
513 return retval;
514
515 arm11_dump_reg_changes(arm11);
516
517 return ERROR_OK;
518 }
519
520 void arm11_dump_reg_changes(struct arm11_common * arm11)
521 {
522
523 if (!(debug_level >= LOG_LVL_DEBUG))
524 {
525 return;
526 }
527
528 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
529 {
530 if (!arm11->reg_list[i].valid)
531 {
532 if (arm11->reg_history[i].valid)
533 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
534 }
535 else
536 {
537 if (arm11->reg_history[i].valid)
538 {
539 if (arm11->reg_history[i].value != arm11->reg_values[i])
540 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
541 }
542 else
543 {
544 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
545 }
546 }
547 }
548 }
549
550 /** Restore processor state
551 *
552 * This is called in preparation for the RESTART function.
553 *
554 */
555 static int arm11_leave_debug_state(struct arm11_common *arm11)
556 {
557 FNC_INFO;
558 int retval;
559
560 retval = arm11_run_instr_data_prepare(arm11);
561 if (retval != ERROR_OK)
562 return retval;
563
564 /** \todo TODO: handle other mode registers */
565
566 /* restore R1 - R14 */
567
568 for (size_t i = 1; i < 15; i++)
569 {
570 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
571 continue;
572
573 /* MRC p14,0,r?,c0,c5,0 */
574 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
575
576 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
577 }
578
579 retval = arm11_run_instr_data_finish(arm11);
580 if (retval != ERROR_OK)
581 return retval;
582
583 /* spec says clear wDTR and rDTR; we assume they are clear as
584 otherwise our programming would be sloppy */
585 {
586 uint32_t DSCR;
587
588 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
589
590 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
591 {
592 /*
593 The wDTR/rDTR two registers that are used to send/receive data to/from
594 the core in tandem with corresponding instruction codes that are
595 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
596 registers hold data that was written by one side (CPU or JTAG) and not
597 read out by the other side.
598 */
599 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
600 return ERROR_FAIL;
601 }
602 }
603
604 retval = arm11_run_instr_data_prepare(arm11);
605 if (retval != ERROR_OK)
606 return retval;
607
608 /* restore original wDTR */
609
610 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
611 {
612 /* MCR p14,0,R0,c0,c5,0 */
613 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
614 if (retval != ERROR_OK)
615 return retval;
616 }
617
618 /* restore CPSR */
619
620 /* MSR CPSR,R0*/
621 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
622 if (retval != ERROR_OK)
623 return retval;
624
625
626 /* restore PC */
627
628 /* MOV PC,R0 */
629 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
630 if (retval != ERROR_OK)
631 return retval;
632
633
634 /* restore R0 */
635
636 /* MRC p14,0,r0,c0,c5,0 */
637 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
638
639 retval = arm11_run_instr_data_finish(arm11);
640 if (retval != ERROR_OK)
641 return retval;
642
643 /* restore DSCR */
644
645 arm11_write_DSCR(arm11, R(DSCR));
646
647 /* restore rDTR */
648
649 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
650 {
651 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
652
653 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
654
655 struct scan_field chain5_fields[3];
656
657 uint8_t Ready = 0; /* ignored */
658 uint8_t Valid = 0; /* ignored */
659
660 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
661 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
662 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
663
664 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
665 }
666
667 arm11_record_register_history(arm11);
668
669 return ERROR_OK;
670 }
671
672 static void arm11_record_register_history(struct arm11_common *arm11)
673 {
674 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
675 {
676 arm11->reg_history[i].value = arm11->reg_values[i];
677 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
678
679 arm11->reg_list[i].valid = 0;
680 arm11->reg_list[i].dirty = 0;
681 }
682 }
683
684
685 /* poll current target status */
686 static int arm11_poll(struct target *target)
687 {
688 FNC_INFO;
689 int retval;
690 struct arm11_common *arm11 = target_to_arm11(target);
691 uint32_t dscr;
692
693 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
694
695 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
696
697 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
698
699 if (dscr & ARM11_DSCR_CORE_HALTED)
700 {
701 if (target->state != TARGET_HALTED)
702 {
703 enum target_state old_state = target->state;
704
705 LOG_DEBUG("enter TARGET_HALTED");
706 target->state = TARGET_HALTED;
707 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
708 retval = arm11_on_enter_debug_state(arm11);
709 if (retval != ERROR_OK)
710 return retval;
711
712 target_call_event_callbacks(target,
713 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
714 }
715 }
716 else
717 {
718 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
719 {
720 LOG_DEBUG("enter TARGET_RUNNING");
721 target->state = TARGET_RUNNING;
722 target->debug_reason = DBG_REASON_NOTHALTED;
723 }
724 }
725
726 return ERROR_OK;
727 }
728 /* architecture specific status reply */
729 static int arm11_arch_state(struct target *target)
730 {
731 struct arm11_common *arm11 = target_to_arm11(target);
732
733 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
734 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
735 R(CPSR),
736 R(PC));
737
738 return ERROR_OK;
739 }
740
741 /* target request support */
742 static int arm11_target_request_data(struct target *target,
743 uint32_t size, uint8_t *buffer)
744 {
745 FNC_INFO_NOTIMPLEMENTED;
746
747 return ERROR_OK;
748 }
749
750 /* target execution control */
751 static int arm11_halt(struct target *target)
752 {
753 FNC_INFO;
754 struct arm11_common *arm11 = target_to_arm11(target);
755
756 LOG_DEBUG("target->state: %s",
757 target_state_name(target));
758
759 if (target->state == TARGET_UNKNOWN)
760 {
761 arm11->simulate_reset_on_next_halt = true;
762 }
763
764 if (target->state == TARGET_HALTED)
765 {
766 LOG_DEBUG("target was already halted");
767 return ERROR_OK;
768 }
769
770 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
771
772 CHECK_RETVAL(jtag_execute_queue());
773
774 uint32_t dscr;
775
776 int i = 0;
777 while (1)
778 {
779 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
780
781 if (dscr & ARM11_DSCR_CORE_HALTED)
782 break;
783
784
785 long long then = 0;
786 if (i == 1000)
787 {
788 then = timeval_ms();
789 }
790 if (i >= 1000)
791 {
792 if ((timeval_ms()-then) > 1000)
793 {
794 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
795 return ERROR_FAIL;
796 }
797 }
798 i++;
799 }
800
801 arm11_on_enter_debug_state(arm11);
802
803 enum target_state old_state = target->state;
804
805 target->state = TARGET_HALTED;
806 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
807
808 CHECK_RETVAL(
809 target_call_event_callbacks(target,
810 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
811
812 return ERROR_OK;
813 }
814
815 static int arm11_resume(struct target *target, int current,
816 uint32_t address, int handle_breakpoints, int debug_execution)
817 {
818 FNC_INFO;
819
820 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
821 // current, address, handle_breakpoints, debug_execution);
822
823 struct arm11_common *arm11 = target_to_arm11(target);
824
825 LOG_DEBUG("target->state: %s",
826 target_state_name(target));
827
828
829 if (target->state != TARGET_HALTED)
830 {
831 LOG_ERROR("Target not halted");
832 return ERROR_TARGET_NOT_HALTED;
833 }
834
835 if (!current)
836 R(PC) = address;
837
838 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
839
840 /* clear breakpoints/watchpoints and VCR*/
841 arm11_sc7_clear_vbw(arm11);
842
843 /* Set up breakpoints */
844 if (!debug_execution)
845 {
846 /* check if one matches PC and step over it if necessary */
847
848 struct breakpoint * bp;
849
850 for (bp = target->breakpoints; bp; bp = bp->next)
851 {
852 if (bp->address == R(PC))
853 {
854 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
855 arm11_step(target, 1, 0, 0);
856 break;
857 }
858 }
859
860 /* set all breakpoints */
861
862 size_t brp_num = 0;
863
864 for (bp = target->breakpoints; bp; bp = bp->next)
865 {
866 struct arm11_sc7_action brp[2];
867
868 brp[0].write = 1;
869 brp[0].address = ARM11_SC7_BVR0 + brp_num;
870 brp[0].value = bp->address;
871 brp[1].write = 1;
872 brp[1].address = ARM11_SC7_BCR0 + brp_num;
873 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
874
875 arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
876
877 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
878
879 brp_num++;
880 }
881
882 arm11_sc7_set_vcr(arm11, arm11_vcr);
883 }
884
885 arm11_leave_debug_state(arm11);
886
887 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
888
889 CHECK_RETVAL(jtag_execute_queue());
890
891 int i = 0;
892 while (1)
893 {
894 uint32_t dscr;
895
896 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
897
898 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
899
900 if (dscr & ARM11_DSCR_CORE_RESTARTED)
901 break;
902
903
904 long long then = 0;
905 if (i == 1000)
906 {
907 then = timeval_ms();
908 }
909 if (i >= 1000)
910 {
911 if ((timeval_ms()-then) > 1000)
912 {
913 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
914 return ERROR_FAIL;
915 }
916 }
917 i++;
918 }
919
920 if (!debug_execution)
921 {
922 target->state = TARGET_RUNNING;
923 target->debug_reason = DBG_REASON_NOTHALTED;
924
925 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
926 }
927 else
928 {
929 target->state = TARGET_DEBUG_RUNNING;
930 target->debug_reason = DBG_REASON_NOTHALTED;
931
932 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
933 }
934
935 return ERROR_OK;
936 }
937
938
939 static int armv4_5_to_arm11(int reg)
940 {
941 if (reg < 16)
942 return reg;
943 switch (reg)
944 {
945 case ARMV4_5_CPSR:
946 return ARM11_RC_CPSR;
947 case 16:
948 /* FIX!!! handle thumb better! */
949 return ARM11_RC_CPSR;
950 default:
951 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
952 exit(-1);
953 }
954 }
955
956
957 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
958 {
959 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
960
961 reg=armv4_5_to_arm11(reg);
962
963 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
964 }
965
966 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
967 int reg, uint32_t value)
968 {
969 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
970
971 reg=armv4_5_to_arm11(reg);
972
973 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
974 }
975
976 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
977 int pos, int bits)
978 {
979 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
980
981 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
982 }
983
984 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
985 {
986 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
987
988 /* FIX!!!! we should implement thumb for arm11 */
989 return ARMV4_5_STATE_ARM;
990 }
991
992 static void arm11_sim_set_state(struct arm_sim_interface *sim,
993 enum armv4_5_state mode)
994 {
995 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
996
997 /* FIX!!!! we should implement thumb for arm11 */
998 LOG_ERROR("Not implemetned!");
999 }
1000
1001
1002 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1003 {
1004 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1005
1006 /* FIX!!!! we should implement something that returns the current mode here!!! */
1007 return ARMV4_5_MODE_USR;
1008 }
1009
1010 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
1011 {
1012 struct arm_sim_interface sim;
1013
1014 sim.user_data=target->arch_info;
1015 sim.get_reg=&arm11_sim_get_reg;
1016 sim.set_reg=&arm11_sim_set_reg;
1017 sim.get_reg_mode=&arm11_sim_get_reg;
1018 sim.set_reg_mode=&arm11_sim_set_reg;
1019 sim.get_cpsr=&arm11_sim_get_cpsr;
1020 sim.get_mode=&arm11_sim_get_mode;
1021 sim.get_state=&arm11_sim_get_state;
1022 sim.set_state=&arm11_sim_set_state;
1023
1024 return arm_simulate_step_core(target, dry_run_pc, &sim);
1025
1026 }
1027
1028 static int arm11_step(struct target *target, int current,
1029 uint32_t address, int handle_breakpoints)
1030 {
1031 FNC_INFO;
1032
1033 LOG_DEBUG("target->state: %s",
1034 target_state_name(target));
1035
1036 if (target->state != TARGET_HALTED)
1037 {
1038 LOG_WARNING("target was not halted");
1039 return ERROR_TARGET_NOT_HALTED;
1040 }
1041
1042 struct arm11_common *arm11 = target_to_arm11(target);
1043
1044 if (!current)
1045 R(PC) = address;
1046
1047 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1048
1049
1050 /** \todo TODO: Thumb not supported here */
1051
1052 uint32_t next_instruction;
1053
1054 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1055
1056 /* skip over BKPT */
1057 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1058 {
1059 R(PC) += 4;
1060 arm11->reg_list[ARM11_RC_PC].valid = 1;
1061 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1062 LOG_DEBUG("Skipping BKPT");
1063 }
1064 /* skip over Wait for interrupt / Standby */
1065 /* mcr 15, 0, r?, cr7, cr0, {4} */
1066 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1067 {
1068 R(PC) += 4;
1069 arm11->reg_list[ARM11_RC_PC].valid = 1;
1070 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1071 LOG_DEBUG("Skipping WFI");
1072 }
1073 /* ignore B to self */
1074 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1075 {
1076 LOG_DEBUG("Not stepping jump to self");
1077 }
1078 else
1079 {
1080 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1081 * with this. */
1082
1083 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1084 * the VCR might be something worth looking into. */
1085
1086
1087 /* Set up breakpoint for stepping */
1088
1089 struct arm11_sc7_action brp[2];
1090
1091 brp[0].write = 1;
1092 brp[0].address = ARM11_SC7_BVR0;
1093 brp[1].write = 1;
1094 brp[1].address = ARM11_SC7_BCR0;
1095
1096 if (arm11_config_hardware_step)
1097 {
1098 /* hardware single stepping be used if possible or is it better to
1099 * always use the same code path? Hardware single stepping is not supported
1100 * on all hardware
1101 */
1102 brp[0].value = R(PC);
1103 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1104 } else
1105 {
1106 /* sets a breakpoint on the next PC(calculated by simulation),
1107 */
1108 uint32_t next_pc;
1109 int retval;
1110 retval = arm11_simulate_step(target, &next_pc);
1111 if (retval != ERROR_OK)
1112 return retval;
1113
1114 brp[0].value = next_pc;
1115 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1116 }
1117
1118 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
1119
1120 /* resume */
1121
1122
1123 if (arm11_config_step_irq_enable)
1124 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1125 else
1126 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1127
1128
1129 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1130
1131 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1132
1133 CHECK_RETVAL(jtag_execute_queue());
1134
1135 /* wait for halt */
1136 int i = 0;
1137 while (1)
1138 {
1139 uint32_t dscr;
1140
1141 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1142
1143 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1144
1145 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1146 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1147 break;
1148
1149 long long then = 0;
1150 if (i == 1000)
1151 {
1152 then = timeval_ms();
1153 }
1154 if (i >= 1000)
1155 {
1156 if ((timeval_ms()-then) > 1000)
1157 {
1158 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1159 return ERROR_FAIL;
1160 }
1161 }
1162 i++;
1163 }
1164
1165 /* clear breakpoint */
1166 arm11_sc7_clear_vbw(arm11);
1167
1168 /* save state */
1169 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1170
1171 /* restore default state */
1172 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1173
1174 }
1175
1176 // target->state = TARGET_HALTED;
1177 target->debug_reason = DBG_REASON_SINGLESTEP;
1178
1179 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1180
1181 return ERROR_OK;
1182 }
1183
1184 static int arm11_assert_reset(struct target *target)
1185 {
1186 FNC_INFO;
1187 int retval;
1188 struct arm11_common *arm11 = target_to_arm11(target);
1189
1190 retval = arm11_check_init(arm11, NULL);
1191 if (retval != ERROR_OK)
1192 return retval;
1193
1194 target->state = TARGET_UNKNOWN;
1195
1196 /* we would very much like to reset into the halted, state,
1197 * but resetting and halting is second best... */
1198 if (target->reset_halt)
1199 {
1200 CHECK_RETVAL(target_halt(target));
1201 }
1202
1203
1204 /* srst is funny. We can not do *anything* else while it's asserted
1205 * and it has unkonwn side effects. Make sure no other code runs
1206 * meanwhile.
1207 *
1208 * Code below assumes srst:
1209 *
1210 * - Causes power-on-reset (but of what parts of the system?). Bug
1211 * in arm11?
1212 *
1213 * - Messes us TAP state without asserting trst.
1214 *
1215 * - There is another bug in the arm11 core. When you generate an access to
1216 * external logic (for example ddr controller via AHB bus) and that block
1217 * is not configured (perhaps it is still held in reset), that transaction
1218 * will never complete. This will hang arm11 core but it will also hang
1219 * JTAG controller. Nothing, short of srst assertion will bring it out of
1220 * this.
1221 *
1222 * Mysteries:
1223 *
1224 * - What should the PC be after an srst reset when starting in the halted
1225 * state?
1226 */
1227
1228 jtag_add_reset(0, 1);
1229 jtag_add_reset(0, 0);
1230
1231 /* How long do we have to wait? */
1232 jtag_add_sleep(5000);
1233
1234 /* un-mess up TAP state */
1235 jtag_add_tlr();
1236
1237 retval = jtag_execute_queue();
1238 if (retval != ERROR_OK)
1239 {
1240 return retval;
1241 }
1242
1243 return ERROR_OK;
1244 }
1245
1246 static int arm11_deassert_reset(struct target *target)
1247 {
1248 return ERROR_OK;
1249 }
1250
1251 static int arm11_soft_reset_halt(struct target *target)
1252 {
1253 FNC_INFO_NOTIMPLEMENTED;
1254
1255 return ERROR_OK;
1256 }
1257
1258 /* target register access for gdb */
1259 static int arm11_get_gdb_reg_list(struct target *target,
1260 struct reg **reg_list[], int *reg_list_size)
1261 {
1262 FNC_INFO;
1263 struct arm11_common *arm11 = target_to_arm11(target);
1264
1265 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1266 *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
1267
1268 for (size_t i = 16; i < 24; i++)
1269 {
1270 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1271 }
1272
1273 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1274
1275 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1276 {
1277 if (arm11_reg_defs[i].gdb_num == -1)
1278 continue;
1279
1280 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1281 }
1282
1283 return ERROR_OK;
1284 }
1285
1286 /* target memory access
1287 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1288 * count: number of items of <size>
1289 *
1290 * arm11_config_memrw_no_increment - in the future we may want to be able
1291 * to read/write a range of data to a "port". a "port" is an action on
1292 * read memory address for some peripheral.
1293 */
1294 static int arm11_read_memory_inner(struct target *target,
1295 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1296 bool arm11_config_memrw_no_increment)
1297 {
1298 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1299 int retval;
1300
1301 FNC_INFO;
1302
1303 if (target->state != TARGET_HALTED)
1304 {
1305 LOG_WARNING("target was not halted");
1306 return ERROR_TARGET_NOT_HALTED;
1307 }
1308
1309 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1310
1311 struct arm11_common *arm11 = target_to_arm11(target);
1312
1313 retval = arm11_run_instr_data_prepare(arm11);
1314 if (retval != ERROR_OK)
1315 return retval;
1316
1317 /* MRC p14,0,r0,c0,c5,0 */
1318 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1319 if (retval != ERROR_OK)
1320 return retval;
1321
1322 switch (size)
1323 {
1324 case 1:
1325 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1326 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1327
1328 for (size_t i = 0; i < count; i++)
1329 {
1330 /* ldrb r1, [r0], #1 */
1331 /* ldrb r1, [r0] */
1332 arm11_run_instr_no_data1(arm11,
1333 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1334
1335 uint32_t res;
1336 /* MCR p14,0,R1,c0,c5,0 */
1337 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1338
1339 *buffer++ = res;
1340 }
1341
1342 break;
1343
1344 case 2:
1345 {
1346 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1347
1348 for (size_t i = 0; i < count; i++)
1349 {
1350 /* ldrh r1, [r0], #2 */
1351 arm11_run_instr_no_data1(arm11,
1352 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1353
1354 uint32_t res;
1355
1356 /* MCR p14,0,R1,c0,c5,0 */
1357 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1358
1359 uint16_t svalue = res;
1360 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1361 }
1362
1363 break;
1364 }
1365
1366 case 4:
1367 {
1368 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1369 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1370 uint32_t *words = (uint32_t *)buffer;
1371
1372 /* LDC p14,c5,[R0],#4 */
1373 /* LDC p14,c5,[R0] */
1374 arm11_run_instr_data_from_core(arm11, instr, words, count);
1375 break;
1376 }
1377 }
1378
1379 return arm11_run_instr_data_finish(arm11);
1380 }
1381
1382 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1383 {
1384 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1385 }
1386
1387 /*
1388 * arm11_config_memrw_no_increment - in the future we may want to be able
1389 * to read/write a range of data to a "port". a "port" is an action on
1390 * read memory address for some peripheral.
1391 */
1392 static int arm11_write_memory_inner(struct target *target,
1393 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1394 bool arm11_config_memrw_no_increment)
1395 {
1396 int retval;
1397 FNC_INFO;
1398
1399 if (target->state != TARGET_HALTED)
1400 {
1401 LOG_WARNING("target was not halted");
1402 return ERROR_TARGET_NOT_HALTED;
1403 }
1404
1405 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1406
1407 struct arm11_common *arm11 = target_to_arm11(target);
1408
1409 retval = arm11_run_instr_data_prepare(arm11);
1410 if (retval != ERROR_OK)
1411 return retval;
1412
1413 /* MRC p14,0,r0,c0,c5,0 */
1414 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1415 if (retval != ERROR_OK)
1416 return retval;
1417
1418 /* burst writes are not used for single words as those may well be
1419 * reset init script writes.
1420 *
1421 * The other advantage is that as burst writes are default, we'll
1422 * now exercise both burst and non-burst code paths with the
1423 * default settings, increasing code coverage.
1424 */
1425 bool burst = arm11_config_memwrite_burst && (count > 1);
1426
1427 switch (size)
1428 {
1429 case 1:
1430 {
1431 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1432
1433 for (size_t i = 0; i < count; i++)
1434 {
1435 /* MRC p14,0,r1,c0,c5,0 */
1436 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1437 if (retval != ERROR_OK)
1438 return retval;
1439
1440 /* strb r1, [r0], #1 */
1441 /* strb r1, [r0] */
1442 retval = arm11_run_instr_no_data1(arm11,
1443 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1444 if (retval != ERROR_OK)
1445 return retval;
1446 }
1447
1448 break;
1449 }
1450
1451 case 2:
1452 {
1453 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1454
1455 for (size_t i = 0; i < count; i++)
1456 {
1457 uint16_t value;
1458 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1459
1460 /* MRC p14,0,r1,c0,c5,0 */
1461 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1462 if (retval != ERROR_OK)
1463 return retval;
1464
1465 /* strh r1, [r0], #2 */
1466 /* strh r1, [r0] */
1467 retval = arm11_run_instr_no_data1(arm11,
1468 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1469 if (retval != ERROR_OK)
1470 return retval;
1471 }
1472
1473 break;
1474 }
1475
1476 case 4: {
1477 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1478
1479 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1480 uint32_t *words = (uint32_t*)buffer;
1481
1482 if (!burst)
1483 {
1484 /* STC p14,c5,[R0],#4 */
1485 /* STC p14,c5,[R0]*/
1486 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1487 if (retval != ERROR_OK)
1488 return retval;
1489 }
1490 else
1491 {
1492 /* STC p14,c5,[R0],#4 */
1493 /* STC p14,c5,[R0]*/
1494 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1495 if (retval != ERROR_OK)
1496 return retval;
1497 }
1498
1499 break;
1500 }
1501 }
1502
1503 /* r0 verification */
1504 if (!arm11_config_memrw_no_increment)
1505 {
1506 uint32_t r0;
1507
1508 /* MCR p14,0,R0,c0,c5,0 */
1509 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1510 if (retval != ERROR_OK)
1511 return retval;
1512
1513 if (address + size * count != r0)
1514 {
1515 LOG_ERROR("Data transfer failed. Expected end "
1516 "address 0x%08x, got 0x%08x",
1517 (unsigned) (address + size * count),
1518 (unsigned) r0);
1519
1520 if (burst)
1521 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1522
1523 if (arm11_config_memwrite_error_fatal)
1524 return ERROR_FAIL;
1525 }
1526 }
1527
1528 return arm11_run_instr_data_finish(arm11);
1529 }
1530
1531 static int arm11_write_memory(struct target *target,
1532 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1533 {
1534 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1535 }
1536
1537 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1538 static int arm11_bulk_write_memory(struct target *target,
1539 uint32_t address, uint32_t count, uint8_t *buffer)
1540 {
1541 FNC_INFO;
1542
1543 if (target->state != TARGET_HALTED)
1544 {
1545 LOG_WARNING("target was not halted");
1546 return ERROR_TARGET_NOT_HALTED;
1547 }
1548
1549 return arm11_write_memory(target, address, 4, count, buffer);
1550 }
1551
1552 /* target break-/watchpoint control
1553 * rw: 0 = write, 1 = read, 2 = access
1554 */
1555 static int arm11_add_breakpoint(struct target *target,
1556 struct breakpoint *breakpoint)
1557 {
1558 FNC_INFO;
1559 struct arm11_common *arm11 = target_to_arm11(target);
1560
1561 #if 0
1562 if (breakpoint->type == BKPT_SOFT)
1563 {
1564 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1565 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1566 }
1567 #endif
1568
1569 if (!arm11->free_brps)
1570 {
1571 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1572 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1573 }
1574
1575 if (breakpoint->length != 4)
1576 {
1577 LOG_DEBUG("only breakpoints of four bytes length supported");
1578 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1579 }
1580
1581 arm11->free_brps--;
1582
1583 return ERROR_OK;
1584 }
1585
1586 static int arm11_remove_breakpoint(struct target *target,
1587 struct breakpoint *breakpoint)
1588 {
1589 FNC_INFO;
1590 struct arm11_common *arm11 = target_to_arm11(target);
1591
1592 arm11->free_brps++;
1593
1594 return ERROR_OK;
1595 }
1596
1597 static int arm11_add_watchpoint(struct target *target,
1598 struct watchpoint *watchpoint)
1599 {
1600 FNC_INFO_NOTIMPLEMENTED;
1601
1602 return ERROR_OK;
1603 }
1604
1605 static int arm11_remove_watchpoint(struct target *target,
1606 struct watchpoint *watchpoint)
1607 {
1608 FNC_INFO_NOTIMPLEMENTED;
1609
1610 return ERROR_OK;
1611 }
1612
1613 // HACKHACKHACK - FIXME mode/state
1614 /* target algorithm support */
1615 static int arm11_run_algorithm(struct target *target,
1616 int num_mem_params, struct mem_param *mem_params,
1617 int num_reg_params, struct reg_param *reg_params,
1618 uint32_t entry_point, uint32_t exit_point,
1619 int timeout_ms, void *arch_info)
1620 {
1621 struct arm11_common *arm11 = target_to_arm11(target);
1622 // enum armv4_5_state core_state = arm11->core_state;
1623 // enum armv4_5_mode core_mode = arm11->core_mode;
1624 uint32_t context[16];
1625 uint32_t cpsr;
1626 int exit_breakpoint_size = 0;
1627 int retval = ERROR_OK;
1628 LOG_DEBUG("Running algorithm");
1629
1630
1631 if (target->state != TARGET_HALTED)
1632 {
1633 LOG_WARNING("target not halted");
1634 return ERROR_TARGET_NOT_HALTED;
1635 }
1636
1637 // FIXME
1638 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1639 // return ERROR_FAIL;
1640
1641 // Save regs
1642 for (unsigned i = 0; i < 16; i++)
1643 {
1644 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1645 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1646 }
1647
1648 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1649 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1650
1651 for (int i = 0; i < num_mem_params; i++)
1652 {
1653 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1654 }
1655
1656 // Set register parameters
1657 for (int i = 0; i < num_reg_params; i++)
1658 {
1659 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1660 if (!reg)
1661 {
1662 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1663 return ERROR_INVALID_ARGUMENTS;
1664 }
1665
1666 if (reg->size != reg_params[i].size)
1667 {
1668 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1669 return ERROR_INVALID_ARGUMENTS;
1670 }
1671 arm11_set_reg(reg,reg_params[i].value);
1672 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1673 }
1674
1675 exit_breakpoint_size = 4;
1676
1677 /* arm11->core_state = arm11_algorithm_info->core_state;
1678 if (arm11->core_state == ARMV4_5_STATE_ARM)
1679 exit_breakpoint_size = 4;
1680 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1681 exit_breakpoint_size = 2;
1682 else
1683 {
1684 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1685 exit(-1);
1686 }
1687 */
1688
1689
1690 /* arm11 at this point only supports ARM not THUMB mode
1691 however if this test needs to be reactivated the current state can be read back
1692 from CPSR */
1693 #if 0
1694 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1695 {
1696 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1697 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1698 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1699 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1700 }
1701 #endif
1702
1703 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1704 {
1705 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1706 retval = ERROR_TARGET_FAILURE;
1707 goto restore;
1708 }
1709
1710 // no debug, otherwise breakpoint is not set
1711 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1712
1713 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1714
1715 if (target->state != TARGET_HALTED)
1716 {
1717 CHECK_RETVAL(target_halt(target));
1718
1719 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1720
1721 retval = ERROR_TARGET_TIMEOUT;
1722
1723 goto del_breakpoint;
1724 }
1725
1726 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1727 {
1728 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1729 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1730 retval = ERROR_TARGET_TIMEOUT;
1731 goto del_breakpoint;
1732 }
1733
1734 for (int i = 0; i < num_mem_params; i++)
1735 {
1736 if (mem_params[i].direction != PARAM_OUT)
1737 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1738 }
1739
1740 for (int i = 0; i < num_reg_params; i++)
1741 {
1742 if (reg_params[i].direction != PARAM_OUT)
1743 {
1744 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1745 if (!reg)
1746 {
1747 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1748 retval = ERROR_INVALID_ARGUMENTS;
1749 goto del_breakpoint;
1750 }
1751
1752 if (reg->size != reg_params[i].size)
1753 {
1754 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1755 retval = ERROR_INVALID_ARGUMENTS;
1756 goto del_breakpoint;
1757 }
1758
1759 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1760 }
1761 }
1762
1763 del_breakpoint:
1764 breakpoint_remove(target, exit_point);
1765
1766 restore:
1767 // Restore context
1768 for (size_t i = 0; i < 16; i++)
1769 {
1770 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1771 arm11->reg_list[i].name, context[i]);
1772 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1773 }
1774 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1775 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1776
1777 // arm11->core_state = core_state;
1778 // arm11->core_mode = core_mode;
1779
1780 return retval;
1781 }
1782
1783 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1784 {
1785 FNC_INFO;
1786
1787 NEW(struct arm11_common, arm11, 1);
1788
1789 arm11->target = target;
1790
1791 if (target->tap == NULL)
1792 return ERROR_FAIL;
1793
1794 if (target->tap->ir_length != 5)
1795 {
1796 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1797 return ERROR_COMMAND_SYNTAX_ERROR;
1798 }
1799
1800 armv4_5_init_arch_info(target, &arm11->arm);
1801
1802 arm11->jtag_info.tap = target->tap;
1803 arm11->jtag_info.scann_size = 5;
1804 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1805 /* cur_scan_chain == 0 */
1806 arm11->jtag_info.intest_instr = ARM11_INTEST;
1807
1808 return ERROR_OK;
1809 }
1810
1811 static int arm11_init_target(struct command_context *cmd_ctx,
1812 struct target *target)
1813 {
1814 /* Initialize anything we can set up without talking to the target */
1815 return arm11_build_reg_cache(target);
1816 }
1817
1818 /* talk to the target and set things up */
1819 static int arm11_examine(struct target *target)
1820 {
1821 int retval;
1822
1823 FNC_INFO;
1824 struct arm11_common *arm11 = target_to_arm11(target);
1825
1826 /* check IDCODE */
1827
1828 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1829
1830 struct scan_field idcode_field;
1831
1832 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1833
1834 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1835
1836 /* check DIDR */
1837
1838 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1839
1840 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1841
1842 struct scan_field chain0_fields[2];
1843
1844 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1845 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1846
1847 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1848
1849 CHECK_RETVAL(jtag_execute_queue());
1850
1851 switch (arm11->device_id & 0x0FFFF000)
1852 {
1853 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1854 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1855 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1856 default:
1857 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1858 return ERROR_FAIL;
1859 }
1860
1861 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1862
1863 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1864 arm11->debug_version != ARM11_DEBUG_V61)
1865 {
1866 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1867 return ERROR_FAIL;
1868 }
1869
1870 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1871 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1872
1873 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1874 arm11->free_brps = arm11->brp;
1875 arm11->free_wrps = arm11->wrp;
1876
1877 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1878 arm11->device_id,
1879 (int)(arm11->implementor),
1880 arm11->didr);
1881
1882 /* as a side-effect this reads DSCR and thus
1883 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1884 * as suggested by the spec.
1885 */
1886
1887 retval = arm11_check_init(arm11, NULL);
1888 if (retval != ERROR_OK)
1889 return retval;
1890
1891 /* ETM on ARM11 still uses original scanchain 6 access mode */
1892 if (arm11->arm.etm && !target_was_examined(target)) {
1893 *register_get_last_cache_p(&target->reg_cache) =
1894 etm_build_reg_cache(target, &arm11->jtag_info,
1895 arm11->arm.etm);
1896 retval = etm_setup(target);
1897 }
1898
1899 target_set_examined(target);
1900
1901 return ERROR_OK;
1902 }
1903
1904
1905 /** Load a register that is marked !valid in the register cache */
1906 static int arm11_get_reg(struct reg *reg)
1907 {
1908 FNC_INFO;
1909
1910 struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1911
1912 if (target->state != TARGET_HALTED)
1913 {
1914 LOG_WARNING("target was not halted");
1915 return ERROR_TARGET_NOT_HALTED;
1916 }
1917
1918 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1919
1920 #if 0
1921 struct arm11_common *arm11 = target_to_arm11(target);
1922 const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1923 #endif
1924
1925 return ERROR_OK;
1926 }
1927
1928 /** Change a value in the register cache */
1929 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1930 {
1931 FNC_INFO;
1932
1933 struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
1934 struct arm11_common *arm11 = target_to_arm11(target);
1935 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1936
1937 arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1938 reg->valid = 1;
1939 reg->dirty = 1;
1940
1941 return ERROR_OK;
1942 }
1943
1944 static const struct reg_arch_type arm11_reg_type = {
1945 .get = arm11_get_reg,
1946 .set = arm11_set_reg,
1947 };
1948
1949 static int arm11_build_reg_cache(struct target *target)
1950 {
1951 struct arm11_common *arm11 = target_to_arm11(target);
1952
1953 NEW(struct reg_cache, cache, 1);
1954 NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
1955 NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
1956
1957 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1958 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1959
1960 arm11->reg_list = reg_list;
1961
1962 /* Build the process context cache */
1963 cache->name = "arm11 registers";
1964 cache->next = NULL;
1965 cache->reg_list = reg_list;
1966 cache->num_regs = ARM11_REGCACHE_COUNT;
1967
1968 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1969 (*cache_p) = cache;
1970
1971 arm11->core_cache = cache;
1972 // armv7m->process_context = cache;
1973
1974 size_t i;
1975
1976 /* Not very elegant assertion */
1977 if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1978 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1979 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1980 {
1981 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX);
1982 exit(-1);
1983 }
1984
1985 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1986 {
1987 struct reg * r = reg_list + i;
1988 const struct arm11_reg_defs * rd = arm11_reg_defs + i;
1989 struct arm11_reg_state * rs = arm11_reg_states + i;
1990
1991 r->name = rd->name;
1992 r->size = 32;
1993 r->value = (uint8_t *)(arm11->reg_values + i);
1994 r->dirty = 0;
1995 r->valid = 0;
1996 r->type = &arm11_reg_type;
1997 r->arch_info = rs;
1998
1999 rs->def_index = i;
2000 rs->target = target;
2001 }
2002
2003 return ERROR_OK;
2004 }
2005
2006 static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
2007 {
2008 if (argc == 0)
2009 {
2010 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
2011 return ERROR_OK;
2012 }
2013
2014 if (argc != 1)
2015 return ERROR_COMMAND_SYNTAX_ERROR;
2016
2017 switch (args[0][0])
2018 {
2019 case '0': /* 0 */
2020 case 'f': /* false */
2021 case 'F':
2022 case 'd': /* disable */
2023 case 'D':
2024 *var = false;
2025 break;
2026
2027 case '1': /* 1 */
2028 case 't': /* true */
2029 case 'T':
2030 case 'e': /* enable */
2031 case 'E':
2032 *var = true;
2033 break;
2034 }
2035
2036 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2037
2038 return ERROR_OK;
2039 }
2040
2041 #define BOOL_WRAPPER(name, print_name) \
2042 COMMAND_HANDLER(arm11_handle_bool_##name) \
2043 { \
2044 return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2045 &arm11_config_##name, print_name); \
2046 }
2047
2048 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2049 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2050 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2051 BOOL_WRAPPER(hardware_step, "hardware single step")
2052
2053 COMMAND_HANDLER(arm11_handle_vcr)
2054 {
2055 switch (argc) {
2056 case 0:
2057 break;
2058 case 1:
2059 COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
2060 break;
2061 default:
2062 return ERROR_COMMAND_SYNTAX_ERROR;
2063 }
2064
2065 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2066 return ERROR_OK;
2067 }
2068
2069 static const uint32_t arm11_coproc_instruction_limits[] =
2070 {
2071 15, /* coprocessor */
2072 7, /* opcode 1 */
2073 15, /* CRn */
2074 15, /* CRm */
2075 7, /* opcode 2 */
2076 0xFFFFFFFF, /* value */
2077 };
2078
2079 static int arm11_mrc_inner(struct target *target, int cpnum,
2080 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
2081 uint32_t *value, bool read)
2082 {
2083 int retval;
2084 struct arm11_common *arm11 = target_to_arm11(target);
2085
2086 if (target->state != TARGET_HALTED)
2087 {
2088 LOG_ERROR("Target not halted");
2089 return ERROR_FAIL;
2090 }
2091
2092 uint32_t instr = 0xEE000010 |
2093 (cpnum << 8) |
2094 (op1 << 21) |
2095 (CRn << 16) |
2096 (CRm << 0) |
2097 (op2 << 5);
2098
2099 if (read)
2100 instr |= 0x00100000;
2101
2102 retval = arm11_run_instr_data_prepare(arm11);
2103 if (retval != ERROR_OK)
2104 return retval;
2105
2106 if (read)
2107 {
2108 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2109 if (retval != ERROR_OK)
2110 return retval;
2111 }
2112 else
2113 {
2114 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2115 if (retval != ERROR_OK)
2116 return retval;
2117 }
2118
2119 return arm11_run_instr_data_finish(arm11);
2120 }
2121
2122 static int arm11_mrc(struct target *target, int cpnum,
2123 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2124 {
2125 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2126 }
2127
2128 static int arm11_mcr(struct target *target, int cpnum,
2129 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2130 {
2131 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2132 }
2133
2134 static int arm11_register_commands(struct command_context *cmd_ctx)
2135 {
2136 FNC_INFO;
2137
2138 struct command *top_cmd, *mw_cmd;
2139
2140 armv4_5_register_commands(cmd_ctx);
2141
2142 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2143 NULL, COMMAND_ANY, NULL);
2144
2145 /* "hardware_step" is only here to check if the default
2146 * simulate + breakpoint implementation is broken.
2147 * TEMPORARY! NOT DOCUMENTED!
2148 */
2149 register_command(cmd_ctx, top_cmd, "hardware_step",
2150 arm11_handle_bool_hardware_step, COMMAND_ANY,
2151 "DEBUG ONLY - Hardware single stepping"
2152 " (default: disabled)");
2153
2154 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2155 NULL, COMMAND_ANY, NULL);
2156 register_command(cmd_ctx, mw_cmd, "burst",
2157 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2158 "Enable/Disable non-standard but fast burst mode"
2159 " (default: enabled)");
2160 register_command(cmd_ctx, mw_cmd, "error_fatal",
2161 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2162 "Terminate program if transfer error was found"
2163 " (default: enabled)");
2164
2165 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2166 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2167 "Enable interrupts while stepping"
2168 " (default: disabled)");
2169 register_command(cmd_ctx, top_cmd, "vcr",
2170 arm11_handle_vcr, COMMAND_ANY,
2171 "Control (Interrupt) Vector Catch Register");
2172
2173 return etm_register_commands(cmd_ctx);
2174 }
2175
2176 /** Holds methods for ARM11xx targets. */
2177 struct target_type arm11_target = {
2178 .name = "arm11",
2179
2180 .poll = arm11_poll,
2181 .arch_state = arm11_arch_state,
2182
2183 .target_request_data = arm11_target_request_data,
2184
2185 .halt = arm11_halt,
2186 .resume = arm11_resume,
2187 .step = arm11_step,
2188
2189 .assert_reset = arm11_assert_reset,
2190 .deassert_reset = arm11_deassert_reset,
2191 .soft_reset_halt = arm11_soft_reset_halt,
2192
2193 .get_gdb_reg_list = arm11_get_gdb_reg_list,
2194
2195 .read_memory = arm11_read_memory,
2196 .write_memory = arm11_write_memory,
2197
2198 .bulk_write_memory = arm11_bulk_write_memory,
2199
2200 .checksum_memory = arm_checksum_memory,
2201 .blank_check_memory = arm_blank_check_memory,
2202
2203 .add_breakpoint = arm11_add_breakpoint,
2204 .remove_breakpoint = arm11_remove_breakpoint,
2205 .add_watchpoint = arm11_add_watchpoint,
2206 .remove_watchpoint = arm11_remove_watchpoint,
2207
2208 .run_algorithm = arm11_run_algorithm,
2209
2210 .register_commands = arm11_register_commands,
2211 .target_create = arm11_target_create,
2212 .init_target = arm11_init_target,
2213 .examine = arm11_examine,
2214
2215 .mrc = arm11_mrc,
2216 .mcr = arm11_mcr,
2217 };
Zach's Unofficial Testing Repository