1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
22 #include <target/arm_adi_v5.h>
23 #include <target/armv4_5.h>
24 #include <target/armv4_5_mmu.h>
25 #include <target/armv4_5_cache.h>
26 #include <target/arm_dpm.h>
35 #define ARMV7_COMMON_MAGIC 0x0A450999
37 /* VA to PA translation operations opc2 values*/
49 struct arm armv4_5_common
;
51 struct reg_cache
*core_cache
;
53 /* arm adp debug port */
54 struct swjdp_common swjdp_info
;
62 /* Cache and Memory Management Unit */
63 struct armv4_5_mmu_common armv4_5_mmu
;
65 int (*examine_debug_reason
)(struct target
*target
);
66 void (*post_debug_entry
)(struct target
*target
);
68 void (*pre_restore_context
)(struct target
*target
);
69 void (*post_restore_context
)(struct target
*target
);
73 static inline struct armv7a_common
*
74 target_to_armv7a(struct target
*target
)
76 return container_of(target
->arch_info
, struct armv7a_common
,
80 /* register offsets from armv7a.debug_base */
82 /* See ARMv7a arch spec section C10.2 */
83 #define CPUDBG_DIDR 0x000
85 /* See ARMv7a arch spec section C10.3 */
86 #define CPUDBG_WFAR 0x018
87 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
88 #define CPUDBG_DSCR 0x088
89 #define CPUDBG_DRCR 0x090
90 #define CPUDBG_PRCR 0x310
91 #define CPUDBG_PRSR 0x314
93 /* See ARMv7a arch spec section C10.4 */
94 #define CPUDBG_DTRRX 0x080
95 #define CPUDBG_ITR 0x084
96 #define CPUDBG_DTRTX 0x08c
98 /* See ARMv7a arch spec section C10.5 */
99 #define CPUDBG_BVR_BASE 0x100
100 #define CPUDBG_BCR_BASE 0x140
101 #define CPUDBG_WVR_BASE 0x180
102 #define CPUDBG_WCR_BASE 0x1C0
103 #define CPUDBG_VCR 0x01C
105 /* See ARMv7a arch spec section C10.6 */
106 #define CPUDBG_OSLAR 0x300
107 #define CPUDBG_OSLSR 0x304
108 #define CPUDBG_OSSRR 0x308
109 #define CPUDBG_ECR 0x024
111 /* See ARMv7a arch spec section C10.7 */
112 #define CPUDBG_DSCCR 0x028
114 /* See ARMv7a arch spec section C10.8 */
115 #define CPUDBG_AUTHSTATUS 0xFB8
117 struct armv7a_algorithm
121 enum armv4_5_mode core_mode
;
122 enum armv4_5_state core_state
;
125 struct armv7a_core_reg
128 enum armv4_5_mode mode
;
129 struct target
*target
;
130 struct armv7a_common
*armv7a_common
;
133 int armv7a_arch_state(struct target
*target
);
134 struct reg_cache
*armv7a_build_reg_cache(struct target
*target
,
135 struct armv7a_common
*armv7a_common
);
136 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
);
138 extern const struct command_registration armv7a_command_handlers
[];
140 #endif /* ARMV4_5_H */