src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "target.h"
  30
  31 typedef enum armv4_5_mode
  32 {
  33         ARMV4_5_MODE_USR = 16,
  34         ARMV4_5_MODE_FIQ = 17,
  35         ARMV4_5_MODE_IRQ = 18,
  36         ARMV4_5_MODE_SVC = 19,
  37         ARMV4_5_MODE_ABT = 23,
  38         ARMV4_5_MODE_UND = 27,
  39         ARMV4_5_MODE_SYS = 31,
  40         ARMV4_5_MODE_ANY = -1
  41 } armv4_5_mode_t;
  42
  43 int armv4_5_mode_to_number(enum armv4_5_mode mode);
  44 enum armv4_5_mode armv4_5_number_to_mode(int number);
  45
  46 extern const char **armv4_5_mode_strings;
  47
  48 typedef enum armv4_5_state
  49 {
  50         ARMV4_5_STATE_ARM,
  51         ARMV4_5_STATE_THUMB,
  52         ARMV4_5_STATE_JAZELLE,
  53 } armv4_5_state_t;
  54
  55 extern char* armv4_5_state_strings[];
  56
  57 extern int armv4_5_core_reg_map[7][17];
  58
  59 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  60                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  61 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  62                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  63
  64 /* offsets into armv4_5 core register cache */
  65 enum
  66 {
  67         ARMV4_5_CPSR = 31,
  68         ARMV4_5_SPSR_FIQ = 32,
  69         ARMV4_5_SPSR_IRQ = 33,
  70         ARMV4_5_SPSR_SVC = 34,
  71         ARMV4_5_SPSR_ABT = 35,
  72         ARMV4_5_SPSR_UND = 36
  73 };
  74
  75 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  76
  77 /* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
  78 #define armv4_5_common_s arm
  79
  80 /**
  81  * Represents a generic ARM core, with standard application registers.
  82  *
  83  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  84  * Cortex-M series cores do not support as many core states or shadowed
  85  * registers as traditional ARM cores, and only support Thumb2 instructions.
  86  */
  87 struct arm
  88 {
  89         int common_magic;
  90         struct reg_cache *core_cache;
  91
  92         int /* armv4_5_mode */ core_mode;
  93         enum armv4_5_state core_state;
  94
  95         /** Flag reporting unavailability of the BKPT instruction. */
  96         bool is_armv4;
  97
  98         /** Handle for the Embedded Trace Module, if one is present. */
  99         struct etm_context *etm;
 100
 101         int (*full_context)(struct target *target);
 102         int (*read_core_reg)(struct target *target,
 103                         int num, enum armv4_5_mode mode);
 104         int (*write_core_reg)(struct target *target,
 105                         int num, enum armv4_5_mode mode, uint32_t value);
 106         void *arch_info;
 107 };
 108
 109 #define target_to_armv4_5 target_to_arm
 110
 111 /** Convert target handle to generic ARM target state handle. */
 112 static inline struct arm *target_to_arm(struct target *target)
 113 {
 114         return target->arch_info;
 115 }
 116
 117 static inline bool is_arm(struct arm *arm)
 118 {
 119         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 120 }
 121
 122 struct armv4_5_algorithm
 123 {
 124         int common_magic;
 125
 126         enum armv4_5_mode core_mode;
 127         enum armv4_5_state core_state;
 128 };
 129
 130 struct armv4_5_core_reg
 131 {
 132         int num;
 133         enum armv4_5_mode mode;
 134         struct target *target;
 135         struct arm *armv4_5_common;
 136 };
 137
 138 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 139                 struct arm *armv4_5_common);
 140
 141 int armv4_5_arch_state(struct target *target);
 142 int armv4_5_get_gdb_reg_list(struct target *target,
 143                 struct reg **reg_list[], int *reg_list_size);
 144
 145 int armv4_5_register_commands(struct command_context *cmd_ctx);
 146 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 147
 148 int armv4_5_run_algorithm(struct target *target,
 149                 int num_mem_params, struct mem_param *mem_params,
 150                 int num_reg_params, struct reg_param *reg_params,
 151                 uint32_t entry_point, uint32_t exit_point,
 152                 int timeout_ms, void *arch_info);
 153
 154 int armv4_5_invalidate_core_regs(struct target *target);
 155
 156 int arm_checksum_memory(struct target *target,
 157                 uint32_t address, uint32_t count, uint32_t *checksum);
 158 int arm_blank_check_memory(struct target *target,
 159                 uint32_t address, uint32_t count, uint32_t *blank);
 160
 161 extern struct reg arm_gdb_dummy_fp_reg;
 162 extern struct reg arm_gdb_dummy_fps_reg;
 163
 164 /* ARM mode instructions
 165  */
 166
 167 /* Store multiple increment after
 168  * Rn: base register
 169  * List: for each bit in list: store register
 170  * S: in priviledged mode: store user-mode registers
 171  * W = 1: update the base register. W = 0: leave the base register untouched
 172  */
 173 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 174
 175 /* Load multiple increment after
 176  * Rn: base register
 177  * List: for each bit in list: store register
 178  * S: in priviledged mode: store user-mode registers
 179  * W = 1: update the base register. W = 0: leave the base register untouched
 180  */
 181 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 182
 183 /* MOV r8, r8 */
 184 #define ARMV4_5_NOP                                     (0xe1a08008)
 185
 186 /* Move PSR to general purpose register
 187  * R = 1: SPSR R = 0: CPSR
 188  * Rn: target register
 189  */
 190 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 191
 192 /* Store register
 193  * Rd: register to store
 194  * Rn: base register
 195  */
 196 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 197
 198 /* Load register
 199  * Rd: register to load
 200  * Rn: base register
 201  */
 202 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 203
 204 /* Move general purpose register to PSR
 205  * R = 1: SPSR R = 0: CPSR
 206  * Field: Field mask
 207  * 1: control field 2: extension field 4: status field 8: flags field
 208  * Rm: source register
 209  */
 210 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 211 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 212
 213 /* Load Register Halfword Immediate Post-Index
 214  * Rd: register to load
 215  * Rn: base register
 216  */
 217 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 218
 219 /* Load Register Byte Immediate Post-Index
 220  * Rd: register to load
 221  * Rn: base register
 222  */
 223 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 224
 225 /* Store register Halfword Immediate Post-Index
 226  * Rd: register to store
 227  * Rn: base register
 228  */
 229 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 230
 231 /* Store register Byte Immediate Post-Index
 232  * Rd: register to store
 233  * Rn: base register
 234  */
 235 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 236
 237 /* Branch (and Link)
 238  * Im: Branch target (left-shifted by 2 bits, added to PC)
 239  * L: 1: branch and link 0: branch only
 240  */
 241 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 242
 243 /* Branch and exchange (ARM state)
 244  * Rm: register holding branch target address
 245  */
 246 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 247
 248 /* Move to ARM register from coprocessor
 249  * CP: Coprocessor number
 250  * op1: Coprocessor opcode
 251  * Rd: destination register
 252  * CRn: first coprocessor operand
 253  * CRm: second coprocessor operand
 254  * op2: Second coprocessor opcode
 255  */
 256 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 257
 258 /* Move to coprocessor from ARM register
 259  * CP: Coprocessor number
 260  * op1: Coprocessor opcode
 261  * Rd: destination register
 262  * CRn: first coprocessor operand
 263  * CRm: second coprocessor operand
 264  * op2: Second coprocessor opcode
 265  */
 266 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 267
 268 /* Breakpoint instruction (ARMv5)
 269  * Im: 16-bit immediate
 270  */
 271 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 272
 273
 274 /* Thumb mode instructions
 275  */
 276
 277 /* Store register (Thumb mode)
 278  * Rd: source register
 279  * Rn: base register
 280  */
 281 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 282
 283 /* Load register (Thumb state)
 284  * Rd: destination register
 285  * Rn: base register
 286  */
 287 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 288
 289 /* Load multiple (Thumb state)
 290  * Rn: base register
 291  * List: for each bit in list: store register
 292  */
 293 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 294
 295 /* Load register with PC relative addressing
 296  * Rd: register to load
 297  */
 298 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 299
 300 /* Move hi register (Thumb mode)
 301  * Rd: destination register
 302  * Rm: source register
 303  */
 304 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 305
 306 /* No operation (Thumb mode)
 307  */
 308 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 309
 310 /* Move immediate to register (Thumb state)
 311  * Rd: destination register
 312  * Im: 8-bit immediate value
 313  */
 314 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 315
 316 /* Branch and Exchange
 317  * Rm: register containing branch target
 318  */
 319 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 320
 321 /* Branch (Thumb state)
 322  * Imm: Branch target
 323  */
 324 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 325
 326 /* Breakpoint instruction (ARMv5) (Thumb state)
 327  * Im: 8-bit immediate
 328  */
 329 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 330
 331 /* build basic mrc/mcr opcode */
 332
 333 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 334 {
 335         uint32_t t = 0;
 336         t|=op1<<21;
 337         t|=op2<<5;
 338         t|=CRn<<16;
 339         t|=CRm<<0;
 340         return t;
 341 }
 342
 343 #endif /* ARMV4_5_H */