1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
32 char* mips32_core_reg_list
[] =
34 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
35 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
36 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
37 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
38 "status", "lo", "hi", "badvaddr", "cause", "pc"
41 struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
84 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
85 * we also add 18 unknown registers to handle gdb requests */
87 #define MIPS32NUMFPREGS 34 + 18
89 uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
91 struct reg mips32_gdb_dummy_fp_reg
=
93 .name
= "GDB dummy floating-point register",
94 .value
= mips32_gdb_dummy_fp_value
,
102 int mips32_core_reg_arch_type
= -1;
104 int mips32_get_core_reg(struct reg
*reg
)
107 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
108 struct target
*target
= mips32_reg
->target
;
109 struct mips32_common
*mips32_target
= target
->arch_info
;
111 if (target
->state
!= TARGET_HALTED
)
113 return ERROR_TARGET_NOT_HALTED
;
116 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
121 int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
123 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
124 struct target
*target
= mips32_reg
->target
;
125 uint32_t value
= buf_get_u32(buf
, 0, 32);
127 if (target
->state
!= TARGET_HALTED
)
129 return ERROR_TARGET_NOT_HALTED
;
132 buf_set_u32(reg
->value
, 0, 32, value
);
139 int mips32_read_core_reg(struct target
*target
, int num
)
142 struct mips32_core_reg
*mips_core_reg
;
144 /* get pointers to arch-specific information */
145 struct mips32_common
*mips32
= target
->arch_info
;
147 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
148 return ERROR_INVALID_ARGUMENTS
;
150 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
151 reg_value
= mips32
->core_regs
[num
];
152 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
153 mips32
->core_cache
->reg_list
[num
].valid
= 1;
154 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
159 int mips32_write_core_reg(struct target
*target
, int num
)
162 struct mips32_core_reg
*mips_core_reg
;
164 /* get pointers to arch-specific information */
165 struct mips32_common
*mips32
= target
->arch_info
;
167 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
168 return ERROR_INVALID_ARGUMENTS
;
170 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
171 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
172 mips32
->core_regs
[num
] = reg_value
;
173 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
174 mips32
->core_cache
->reg_list
[num
].valid
= 1;
175 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
180 int mips32_invalidate_core_regs(struct target
*target
)
182 /* get pointers to arch-specific information */
183 struct mips32_common
*mips32
= target
->arch_info
;
186 for (i
= 0; i
< mips32
->core_cache
->num_regs
; i
++)
188 mips32
->core_cache
->reg_list
[i
].valid
= 0;
189 mips32
->core_cache
->reg_list
[i
].dirty
= 0;
195 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
197 /* get pointers to arch-specific information */
198 struct mips32_common
*mips32
= target
->arch_info
;
201 /* include floating point registers */
202 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
203 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
205 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
207 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
210 /* add dummy floating points regs */
211 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
213 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
219 int mips32_save_context(struct target
*target
)
223 /* get pointers to arch-specific information */
224 struct mips32_common
*mips32
= target
->arch_info
;
225 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
227 /* read core registers */
228 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
230 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
232 if (!mips32
->core_cache
->reg_list
[i
].valid
)
234 mips32
->read_core_reg(target
, i
);
241 int mips32_restore_context(struct target
*target
)
245 /* get pointers to arch-specific information */
246 struct mips32_common
*mips32
= target
->arch_info
;
247 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
249 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
251 if (mips32
->core_cache
->reg_list
[i
].dirty
)
253 mips32
->write_core_reg(target
, i
);
257 /* write core regs */
258 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
263 int mips32_arch_state(struct target
*target
)
265 struct mips32_common
*mips32
= target
->arch_info
;
267 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
269 LOG_ERROR("BUG: called for a non-MIPS32 target");
273 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32
"",
274 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
275 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
280 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
282 /* get pointers to arch-specific information */
283 struct mips32_common
*mips32
= target
->arch_info
;
285 int num_regs
= MIPS32NUMCOREREGS
;
286 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
287 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
288 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
289 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
292 if (mips32_core_reg_arch_type
== -1)
293 mips32_core_reg_arch_type
= register_reg_arch_type(mips32_get_core_reg
, mips32_set_core_reg
);
295 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
297 /* Build the process context cache */
298 cache
->name
= "mips32 registers";
300 cache
->reg_list
= reg_list
;
301 cache
->num_regs
= num_regs
;
303 mips32
->core_cache
= cache
;
305 for (i
= 0; i
< num_regs
; i
++)
307 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
308 arch_info
[i
].target
= target
;
309 arch_info
[i
].mips32_common
= mips32
;
310 reg_list
[i
].name
= mips32_core_reg_list
[i
];
311 reg_list
[i
].size
= 32;
312 reg_list
[i
].value
= calloc(1, 4);
313 reg_list
[i
].dirty
= 0;
314 reg_list
[i
].valid
= 0;
315 reg_list
[i
].arch_type
= mips32_core_reg_arch_type
;
316 reg_list
[i
].arch_info
= &arch_info
[i
];
322 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
324 target
->arch_info
= mips32
;
325 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
327 /* has breakpoint/watchpint unit been scanned */
328 mips32
->bp_scanned
= 0;
329 mips32
->data_break_list
= NULL
;
331 mips32
->ejtag_info
.tap
= tap
;
332 mips32
->read_core_reg
= mips32_read_core_reg
;
333 mips32
->write_core_reg
= mips32_write_core_reg
;
338 int mips32_register_commands(struct command_context
*cmd_ctx
)
343 int mips32_run_algorithm(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
349 int mips32_examine(struct target
*target
)
351 struct mips32_common
*mips32
= target
->arch_info
;
353 if (!target_was_examined(target
))
355 target_set_examined(target
);
357 /* we will configure later */
358 mips32
->bp_scanned
= 0;
359 mips32
->num_inst_bpoints
= 0;
360 mips32
->num_data_bpoints
= 0;
361 mips32
->num_inst_bpoints_avail
= 0;
362 mips32
->num_data_bpoints_avail
= 0;
368 int mips32_configure_break_unit(struct target
*target
)
370 /* get pointers to arch-specific information */
371 struct mips32_common
*mips32
= target
->arch_info
;
373 uint32_t dcr
, bpinfo
;
376 if (mips32
->bp_scanned
)
379 /* get info about breakpoint support */
380 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
385 /* get number of inst breakpoints */
386 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
389 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
390 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
391 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
392 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
394 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
398 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
404 /* get number of data breakpoints */
405 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
408 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
409 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
410 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
411 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
413 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
417 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
421 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
423 mips32
->bp_scanned
= 1;
428 int mips32_enable_interrupts(struct target
*target
, int enable
)
434 /* read debug control register */
435 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
440 if (!(dcr
& (1 << 4)))
442 /* enable interrupts */
451 /* disable interrupts */
459 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)