src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "target.h"
  30
  31 typedef enum armv4_5_mode
  32 {
  33         ARMV4_5_MODE_USR = 16,
  34         ARMV4_5_MODE_FIQ = 17,
  35         ARMV4_5_MODE_IRQ = 18,
  36         ARMV4_5_MODE_SVC = 19,
  37         ARMV4_5_MODE_ABT = 23,
  38         ARM_MODE_MON = 26,
  39         ARMV4_5_MODE_UND = 27,
  40         ARMV4_5_MODE_SYS = 31,
  41         ARMV4_5_MODE_ANY = -1
  42 } armv4_5_mode_t;
  43
  44 const char *arm_mode_name(unsigned psr_mode);
  45 bool is_arm_mode(unsigned psr_mode);
  46
  47 int armv4_5_mode_to_number(enum armv4_5_mode mode);
  48 enum armv4_5_mode armv4_5_number_to_mode(int number);
  49
  50 typedef enum armv4_5_state
  51 {
  52         ARMV4_5_STATE_ARM,
  53         ARMV4_5_STATE_THUMB,
  54         ARMV4_5_STATE_JAZELLE,
  55         ARM_STATE_THUMB_EE,
  56 } armv4_5_state_t;
  57
  58 extern char* armv4_5_state_strings[];
  59
  60 extern const int armv4_5_core_reg_map[8][17];
  61
  62 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  63                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  64
  65 /* offsets into armv4_5 core register cache */
  66 enum
  67 {
  68         ARMV4_5_CPSR = 31,
  69         ARMV4_5_SPSR_FIQ = 32,
  70         ARMV4_5_SPSR_IRQ = 33,
  71         ARMV4_5_SPSR_SVC = 34,
  72         ARMV4_5_SPSR_ABT = 35,
  73         ARMV4_5_SPSR_UND = 36,
  74         ARM_SPSR_MON = 39,
  75 };
  76
  77 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  78
  79 /* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
  80 #define armv4_5_common_s arm
  81
  82 /**
  83  * Represents a generic ARM core, with standard application registers.
  84  *
  85  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  86  * Cortex-M series cores do not support as many core states or shadowed
  87  * registers as traditional ARM cores, and only support Thumb2 instructions.
  88  */
  89 struct arm
  90 {
  91         int common_magic;
  92         struct reg_cache *core_cache;
  93
  94         /**
  95          * Indicates what registers are in the ARM state core register set.
  96          * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
  97          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
  98          * more registers are shadowed, for "Secure Monitor" mode.
  99          */
 100         enum armv4_5_mode core_type;
 101
 102         enum armv4_5_mode core_mode;
 103         enum armv4_5_state core_state;
 104
 105         /** Flag reporting unavailability of the BKPT instruction. */
 106         bool is_armv4;
 107
 108         /** Handle for the Embedded Trace Module, if one is present. */
 109         struct etm_context *etm;
 110
 111         int (*full_context)(struct target *target);
 112         int (*read_core_reg)(struct target *target,
 113                         int num, enum armv4_5_mode mode);
 114         int (*write_core_reg)(struct target *target,
 115                         int num, enum armv4_5_mode mode, uint32_t value);
 116         void *arch_info;
 117 };
 118
 119 #define target_to_armv4_5 target_to_arm
 120
 121 /** Convert target handle to generic ARM target state handle. */
 122 static inline struct arm *target_to_arm(struct target *target)
 123 {
 124         return target->arch_info;
 125 }
 126
 127 static inline bool is_arm(struct arm *arm)
 128 {
 129         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 130 }
 131
 132 struct armv4_5_algorithm
 133 {
 134         int common_magic;
 135
 136         enum armv4_5_mode core_mode;
 137         enum armv4_5_state core_state;
 138 };
 139
 140 struct armv4_5_core_reg
 141 {
 142         int num;
 143         enum armv4_5_mode mode;
 144         struct target *target;
 145         struct arm *armv4_5_common;
 146         uint32_t value;
 147 };
 148
 149 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 150                 struct arm *armv4_5_common);
 151
 152 int armv4_5_arch_state(struct target *target);
 153 int armv4_5_get_gdb_reg_list(struct target *target,
 154                 struct reg **reg_list[], int *reg_list_size);
 155
 156 int armv4_5_register_commands(struct command_context *cmd_ctx);
 157 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 158
 159 int armv4_5_run_algorithm(struct target *target,
 160                 int num_mem_params, struct mem_param *mem_params,
 161                 int num_reg_params, struct reg_param *reg_params,
 162                 uint32_t entry_point, uint32_t exit_point,
 163                 int timeout_ms, void *arch_info);
 164
 165 int armv4_5_invalidate_core_regs(struct target *target);
 166
 167 int arm_checksum_memory(struct target *target,
 168                 uint32_t address, uint32_t count, uint32_t *checksum);
 169 int arm_blank_check_memory(struct target *target,
 170                 uint32_t address, uint32_t count, uint32_t *blank);
 171
 172 extern struct reg arm_gdb_dummy_fp_reg;
 173 extern struct reg arm_gdb_dummy_fps_reg;
 174
 175 /* ARM mode instructions
 176  */
 177
 178 /* Store multiple increment after
 179  * Rn: base register
 180  * List: for each bit in list: store register
 181  * S: in priviledged mode: store user-mode registers
 182  * W = 1: update the base register. W = 0: leave the base register untouched
 183  */
 184 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 185
 186 /* Load multiple increment after
 187  * Rn: base register
 188  * List: for each bit in list: store register
 189  * S: in priviledged mode: store user-mode registers
 190  * W = 1: update the base register. W = 0: leave the base register untouched
 191  */
 192 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 193
 194 /* MOV r8, r8 */
 195 #define ARMV4_5_NOP                                     (0xe1a08008)
 196
 197 /* Move PSR to general purpose register
 198  * R = 1: SPSR R = 0: CPSR
 199  * Rn: target register
 200  */
 201 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 202
 203 /* Store register
 204  * Rd: register to store
 205  * Rn: base register
 206  */
 207 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 208
 209 /* Load register
 210  * Rd: register to load
 211  * Rn: base register
 212  */
 213 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 214
 215 /* Move general purpose register to PSR
 216  * R = 1: SPSR R = 0: CPSR
 217  * Field: Field mask
 218  * 1: control field 2: extension field 4: status field 8: flags field
 219  * Rm: source register
 220  */
 221 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 222 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 223
 224 /* Load Register Halfword Immediate Post-Index
 225  * Rd: register to load
 226  * Rn: base register
 227  */
 228 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 229
 230 /* Load Register Byte Immediate Post-Index
 231  * Rd: register to load
 232  * Rn: base register
 233  */
 234 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 235
 236 /* Store register Halfword Immediate Post-Index
 237  * Rd: register to store
 238  * Rn: base register
 239  */
 240 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 241
 242 /* Store register Byte Immediate Post-Index
 243  * Rd: register to store
 244  * Rn: base register
 245  */
 246 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 247
 248 /* Branch (and Link)
 249  * Im: Branch target (left-shifted by 2 bits, added to PC)
 250  * L: 1: branch and link 0: branch only
 251  */
 252 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 253
 254 /* Branch and exchange (ARM state)
 255  * Rm: register holding branch target address
 256  */
 257 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 258
 259 /* Move to ARM register from coprocessor
 260  * CP: Coprocessor number
 261  * op1: Coprocessor opcode
 262  * Rd: destination register
 263  * CRn: first coprocessor operand
 264  * CRm: second coprocessor operand
 265  * op2: Second coprocessor opcode
 266  */
 267 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 268
 269 /* Move to coprocessor from ARM register
 270  * CP: Coprocessor number
 271  * op1: Coprocessor opcode
 272  * Rd: destination register
 273  * CRn: first coprocessor operand
 274  * CRm: second coprocessor operand
 275  * op2: Second coprocessor opcode
 276  */
 277 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 278
 279 /* Breakpoint instruction (ARMv5)
 280  * Im: 16-bit immediate
 281  */
 282 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 283
 284
 285 /* Thumb mode instructions
 286  */
 287
 288 /* Store register (Thumb mode)
 289  * Rd: source register
 290  * Rn: base register
 291  */
 292 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 293
 294 /* Load register (Thumb state)
 295  * Rd: destination register
 296  * Rn: base register
 297  */
 298 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 299
 300 /* Load multiple (Thumb state)
 301  * Rn: base register
 302  * List: for each bit in list: store register
 303  */
 304 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 305
 306 /* Load register with PC relative addressing
 307  * Rd: register to load
 308  */
 309 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 310
 311 /* Move hi register (Thumb mode)
 312  * Rd: destination register
 313  * Rm: source register
 314  */
 315 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 316
 317 /* No operation (Thumb mode)
 318  */
 319 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 320
 321 /* Move immediate to register (Thumb state)
 322  * Rd: destination register
 323  * Im: 8-bit immediate value
 324  */
 325 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 326
 327 /* Branch and Exchange
 328  * Rm: register containing branch target
 329  */
 330 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 331
 332 /* Branch (Thumb state)
 333  * Imm: Branch target
 334  */
 335 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 336
 337 /* Breakpoint instruction (ARMv5) (Thumb state)
 338  * Im: 8-bit immediate
 339  */
 340 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 341
 342 /* build basic mrc/mcr opcode */
 343
 344 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 345 {
 346         uint32_t t = 0;
 347         t|=op1<<21;
 348         t|=op2<<5;
 349         t|=CRn<<16;
 350         t|=CRm<<0;
 351         return t;
 352 }
 353
 354 #endif /* ARMV4_5_H */